/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_INTERFACE_H__
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#define __HALBB_INTERFACE_H__
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/*@--------------------------[Define] ---------------------------------------*/
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/*[IO Reg]*/
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#define HALBB_SET_CR_CMN(bb, cr, val, phy_idx) halbb_set_reg_cmn(bb, cr, cr##_M, val, phy_idx);
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#define HALBB_SET_CR(bb, cr, val) halbb_set_reg(bb, cr, cr##_M, val);
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#define HALBB_GET_CR_CMN(bb, cr, val, phy_idx) halbb_get_reg_cmn(bb, cr, cr##_M, phy_idx);
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#define HALBB_GET_CR(bb, cr) halbb_get_reg(bb, cr, cr##_M);
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#if 1
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#define halbb_get_32(bb, addr) hal_read32((bb)->hal_com, addr)
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//#define halbb_get_16(bb, addr) hal_read16((bb)->hal_com, addr)
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//#define halbb_get_8(bb, addr) hal_read8((bb)->hal_com, addr)
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#define halbb_set_32(bb, addr, val) hal_write32((bb)->hal_com, addr, val)
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//#define halbb_set_16(bb, addr, val) hal_write16((bb)->hal_com, addr, val)
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//#define halbb_set_8(bb, addr, val) hal_write8((bb)->hal_com, addr, val)
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#endif
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#define halbb_read_mem(bb, addr, cnt, pmem) hal_read_mem((bb)->hal_com, addr, cnt, pmem)
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/*[Delay]*/
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#define halbb_delay_ms(bb, ms) _os_delay_ms(bb->hal_com->drv_priv, ms)
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//#define halbb_delay_us(bb, us) _os_delay_us(bb->hal_com->drv_priv, us)
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/*[Memory Access]*/
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#define halbb_mem_alloc(bb, buf_sz) hal_mem_alloc(bb->hal_com, buf_sz)
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#define halbb_mem_free(bb, buf, buf_sz) hal_mem_free(bb->hal_com, (void *)buf, buf_sz)
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#define halbb_mem_set(bb, buf, value, size) _os_mem_set(bb->hal_com->drv_priv, (void *)buf, value, size)
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#define halbb_mem_cpy(bb, dest, src, size) _os_mem_cpy(bb->hal_com->drv_priv, (void *)dest, (void *)src, size)
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#define halbb_mem_cmp(bb, dest, src, size) _os_mem_cmp(bb->hal_com->drv_priv, (void *)dest, (void *)src, size)
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/*[Timer]*/
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#ifdef HALBB_TIMER_SUPPORT
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#define halbb_timer_list _os_timer
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#define halbb_init_timer(bb, timer, call_back_func, context, sz_id) _os_init_timer(bb->hal_com->drv_priv, timer, call_back_func, context, sz_id)
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#define halbb_set_timer(bb, timer, ms_delay) _os_set_timer(bb->hal_com->drv_priv, timer, ms_delay)
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#define halbb_cancel_timer(bb, timer) _os_cancel_timer(bb->hal_com->drv_priv, timer)
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#define halbb_release_timer(bb, timer) _os_release_timer(bb->hal_com->drv_priv, timer)
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#else
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#define halbb_timer_list u8
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#define halbb_init_timer(bb, timer, call_back_func, context, sz_id)
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#define halbb_set_timer(bb, timer, ms_delay)
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#define halbb_cancel_timer(bb, timer)
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#define halbb_release_timer(bb, timer)
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#endif
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/*[Efuse]*/
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#ifndef RTW_FLASH_98D
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#define halbb_efuse_get_info(bb, info_type, value, size) rtw_hal_efuse_get_info(bb->hal_com, info_type, (void *)value, size)
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#else
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#define halbb_efuse_get_info(bb, info_type, value, size) rtw_hal_flash_get_info(bb->hal_com, info_type, (void *)value, size)
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#endif
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#define halbb_phy_efuse_get_info(bb, addr, size, value) rtw_hal_mac_read_phy_efuse(bb->hal_com, addr, size, value)
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/*[String]*/
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#define halbb_snprintf _os_snprintf
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/*[PwrTable]*/
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#define PWR_TBL_NUM 32
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#define NUM_HE_MCS 12
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#define NUM_DCM_MCS 4
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/*@--------------------------[Enum]------------------------------------------*/
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enum bb_timer_cfg_t {
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BB_INIT_TIMER = 0,
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BB_CANCEL_TIMER = 1,
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BB_RELEASE_TIMER = 2,
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BB_SET_TIMER = 3
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};
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enum halbb_h2c_ra_cmdid {
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RA_H2C_MACIDCFG = 0x0,
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RA_H2C_RSSISETTING = 0x1,
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RA_H2C_GET_TXSTS = 0x2,
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RA_H2C_RA_ADJUST = 0x3,
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RA_H2C_ADJUST_RA_MASK = 0x4,
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RA_H2C_RA_D_O_TIMER = 0x5,
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RA_H2C_RA_CLS = 0x6,
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RA_H2C_RA_SHIFT_DARF_TC = 0x7,
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RA_H2C_RA_TX_INFO = 0x8,
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RA_H2C_MUCFG = 0x10,
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RA_MAX_H2CCMD
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};
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enum halbb_h2c_rua_cmdid {
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RUA_H2C_TABLE = 0x0,
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RUA_H2C_SWGRP = 0x1,
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RUA_H2C_DL_MACID = 0x2,
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RUA_H2C_UL_MACID = 0x3,
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RUA_H2C_CSIINFO = 0x4,
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RUA_H2C_CQI = 0x5,
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RUA_H2C_BBINFO = 0x6,
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RUA_H2C_SEN_TBL = 0x7,
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RUA_H2C_PWR_TBL = 0x8,
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RUA_H2C_DBG = 0x9,
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RUA_H2C_DBG_W = 0x10,
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RUA_H2C_MACID_INIT = 0x11,
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RUA_H2C_RA_MASK = 0x12,
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RUA_MAX_H2CCMD
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};
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enum halbb_h2c_classid {
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HALBB_H2C_RUA = 0x0,
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HALBB_H2C_RA = 0x1,
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HALBB_H2C_DM = 0x2,
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HALBB_MAX_H2CCMD
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};
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enum halbb_h2c_dm_cmdid {
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DM_H2C_FWTRACE = 0x0,
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DM_H2C_FW_TRIG_TX = 0x1,
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DM_H2C_FW_H2C_TEST = 0x2,
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DM_H2C_FW_EHTSIG_SIGB = 0x3,
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DM_H2C_FW_EDCCA = 0x4,
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DM_H2C_FW_CMW = 0x5,
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DM_H2C_FW_MCC = 0x6,
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DM_H2C_FW_L6M_WA = 0x7,
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DM_H2C_FW_ENV_MNTR = 0x8,
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DM_H2C_FW_LPS_INFO = 0x9,
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DM_H2C_FW_LPS_CH_INFO = 0xb,
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DM_MAX_H2CCMD
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};
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enum halbb_c2h_classid {
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HALBB_C2H_RUA = 0x0,
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HALBB_C2H_RA = 0x1,
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HALBB_C2H_DM = 0x2,
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HALBB_MAX_C2HCMD
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};
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enum halbb_c2h_ra_cmdid {
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HALBB_C2HRA_STS_RPT = 0x0,
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HALBB_C2HRA_MU_GPTBL_RPT = 0x1,
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HALBB_C2HRA_TXSTS = 0x2,
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HALBB_C2HRA_TX_DBG_INFO = 0x3,
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HALBB_MAX_C2HRACMD
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};
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enum halbb_c2h_rua_cmdid {
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HALBB_C2HRUA_DBG = 0x0,
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HALBB_MAX_C2HRUACMD
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};
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enum halbb_c2h_dm_cmdid {
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DM_C2H_FW_TEST = 0x0,
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DM_C2H_FW_TRIG_TX_RPT = 0x1,
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DM_C2H_SIGB = 0x2,
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DM_C2H_LOWRT_RTY = 0x3,
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DM_C2H_MCC_DIG = 0x4,
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DM_C2H_FW_ENV_MNTR = 0x5,
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DM_C2H_DBG = 0x6,
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DM_C2H_EHTSIG =0x7,
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HALBB_MAX_C2HDMCMD
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};
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enum halbb_event_idx_t {
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/*timer*/
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BB_EVENT_TIMER_DIG = 0,
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BB_EVENT_TIMER_CFO = 1,
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BB_EVENT_TIMER_ANTDIV = 2,
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BB_EVENT_TIMER_TDMA_CR = 3,
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BB_EVENT_TIMER_LA = 4,
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BB_EVENT_TIMER_DTR = 5
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};
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enum halbb_timer_state_t {
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/*timer*/
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BB_TIMER_IDLE = 0,
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BB_TIMER_RUN = 1,
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BB_TIMER_RELEASE = 0xff,
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct halbb_timer_info {
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halbb_timer_list timer_list;
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u32 cb_time; /*callback time (ms)*/
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enum halbb_event_idx_t event_idx;
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enum halbb_timer_state_t timer_state;
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};
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struct halbb_pwr_by_rate_tbl {
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u8 pwr_by_rate[PWR_TBL_NUM*2];
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};
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struct halbb_lps_chb {
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u8 pri_ch;
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u8 c_ch;
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u8 bw;
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u8 band;
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};
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struct halbb_lsp_ch_info {
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struct halbb_lps_chb bw_ch_i[HW_PHY_MAX];
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u32 mlo_dbcc_mode_lps;
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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struct bb_info;
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void halbb_cfg_timers(struct bb_info *bb, enum bb_timer_cfg_t cfg,
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struct halbb_timer_info *timer);
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u32 halbb_get_sys_time(struct bb_info *bb);
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u32 halbb_phy0_to_phy1_ofst(struct bb_info *bb, u32 addr, enum phl_phy_idx phy_idx);
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void halbb_delay_us(struct bb_info *bb, u32 us);
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void halbb_set_bb_wrap_reg_cmn(struct bb_info* bb, enum phl_phy_idx bb_phy_idx, u32 addr, u32 val);
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void halbb_set_cr(struct bb_info *bb, u32 addr, u32 mask, u32 val);
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u32 halbb_get_cr(struct bb_info *bb, u32 addr, u32 mask);
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void halbb_set_reg_curr_phy(struct bb_info *bb, u32 addr, u32 mask, u32 val);
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void halbb_set_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 val);
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u32 halbb_get_reg_curr_phy(struct bb_info *bb, u32 addr, u32 mask);
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u32 halbb_get_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 *val_1);
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bool halbb_fill_h2c_cmd(struct bb_info *bb, u16 cmdlen, u8 cmdid,
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u8 classid, u32 *pval);
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bool halbb_test_h2c_c2h_flow(struct bb_info *bb);
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bool halbb_check_fw_ofld(struct bb_info *bb);
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bool halbb_fw_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val, u8 lst_cmd);
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bool halbb_fw_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val,
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enum phl_phy_idx phy_idx, u8 lst_cmd);
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bool halbb_fw_set_rf_reg(struct bb_info *bb, enum rf_path path,
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u32 reg_addr, u32 bit_mask, u32 data);
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enum rtw_hal_status
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halbb_config_cmac_tbl_ax(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i,
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void *cmac_ctrl,
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void *cmac_ctrl_mask);
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enum rtw_hal_status
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halbb_config_cmac_tbl_be(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i,
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void *cmac_ctrl,
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void *cmac_ctrl_mask);
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#endif
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