/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "halbb_precomp.h"
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void halbb_cfg_timers(struct bb_info *bb, enum bb_timer_cfg_t cfg,
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struct halbb_timer_info *timer)
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{
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BB_DBG(bb, DBG_INIT, "[%s] %s timer, event=%d\n", __func__,
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((cfg == BB_SET_TIMER) ? "SET" : ((cfg == BB_CANCEL_TIMER) ? "CANCEL" : ("RLS"))),
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timer->event_idx);
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if (cfg == BB_INIT_TIMER) {
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BB_WARNING("[%s]\n", __func__);
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return;
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}
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if (cfg == BB_SET_TIMER) {
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if (timer->timer_state != BB_TIMER_IDLE) {
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BB_WARNING("[%s] state=%d\n", __func__, timer->timer_state);
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return;
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}
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timer->timer_state = BB_TIMER_RUN;
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halbb_set_timer(bb, &timer->timer_list, timer->cb_time);
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} else if (cfg == BB_CANCEL_TIMER) {
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halbb_cancel_timer(bb, &timer->timer_list);
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timer->timer_state = BB_TIMER_IDLE;
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} else if (cfg == BB_RELEASE_TIMER) {
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halbb_release_timer(bb, &timer->timer_list);
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timer->timer_state = BB_TIMER_RELEASE;
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}
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}
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u32 halbb_get_sys_time(struct bb_info *bb)
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{
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return 0;
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}
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u32 halbb_phy0_to_phy1_ofst(struct bb_info *bb, u32 addr, enum phl_phy_idx phy_idx)
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{
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u32 ofst = 0;
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if (phy_idx == HW_PHY_0)
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return 0;
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if (!bb->bb_cmn_hooker->ic_dual_phy_support && !bb->hal_com->dbcc_en)
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return 0;
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switch (bb->ic_type) {
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#ifdef BB_8852A_2_SUPPORT
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case BB_RTL8852A:
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ofst = halbb_phy0_to_phy1_ofst_8852a_2(bb, addr);
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break;
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#endif
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#ifdef BB_8852C_SUPPORT
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case BB_RTL8852C:
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ofst = halbb_phy0_to_phy1_ofst_8852c(bb, addr);
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break;
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#endif
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#ifdef BB_1115_SUPPORT
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case BB_RLE1115:
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ofst = (addr < 0x10000) ? 0x20000 : 0;
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break;
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#endif
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#if (HLABB_CODE_BASE_NUM >= 33) //will be removed when (022+032) branch phase out
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#ifdef BB_8922A_SUPPORT
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case BB_RTL8922A:
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ofst = halbb_phy0_to_phy1_ofst_8922a(bb, addr);
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break;
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#endif
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#endif
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default:
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break;
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}
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return ofst;
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}
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void halbb_delay_us(struct bb_info *bb, u32 us)
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{
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bool ret = true;
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#ifdef HALBB_FW_OFLD_SUPPORT
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if (halbb_check_fw_ofld(bb)) {
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if (bb->bb_cmn_hooker->bbcr_fwofld_state || bb->bb_cmn_hooker->bb_fwofld_in_progress) {
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ret = halbb_fw_delay(bb, us);
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BB_DBG(bb, DBG_FW_INFO, "[OK:%d][O:%d,N:%d] halbb fwofld delay = %d\n",
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ret,
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bb->bb_cmn_hooker->bbcr_fwofld_state,
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bb->bb_cmn_hooker->bb_fwofld_in_progress,
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us);
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return;
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}
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}
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#endif
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_os_delay_us(bb->hal_com->drv_priv, us);
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}
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void halbb_set_bb_wrap_reg_cmn(struct bb_info* bb, enum phl_phy_idx bb_phy_idx, u32 addr, u32 val)
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{
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rtw_hal_mac_set_pwr_reg(bb->hal_com, (u8)bb_phy_idx, addr, val);
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}
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void halbb_set_cr(struct bb_info *bb, u32 addr, u32 mask, u32 val)
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{
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u8 mask_lsb = 0, mask_msb = 0;
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if (bb->bb_dbg_i.cr_recorder_en) {
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BB_TRACE("[W] 0x%04x = 0x%08x\n", addr, val);
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} else if (bb->bb_dbg_i.cr_mp_recorder_en) {
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if ((addr != 0xF9) && (addr != 0xFA) && (addr != 0xFB) && (addr != 0xFD) && (addr != 0xFE)) {
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mask_lsb = halbb_bitmask_lsb(bb, mask);
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mask_msb = halbb_bitmask_msb(bb, mask);
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if (halbb_ones_num_in_bitmap(mask, 32) == 1)
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BB_TRACE("[MP] op 0x%x[%d] 0x%x\n", addr, mask_lsb, ((val & mask) >> mask_lsb));
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else if (mask == MASKDWORD)
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BB_TRACE("[MP] od 0x%x 0x%x\n", addr, val);
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else
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BB_TRACE("[MP] op 0x%x[%d:%d] 0x%x\n", addr, mask_msb, mask_lsb, ((val & mask) >> mask_lsb));
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} else {
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if ((addr == 0xF9) || (addr == 0xFA) || (addr == 0xFB)) // Delay log (1ms)
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BB_TRACE("[MP] delay 1\n"); // Smallest resolusion of MP script is 1ms
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else if (addr == 0xFD) // Delay log (5ms)
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BB_TRACE("[MP] delay 5\n");
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else if (addr == 0xFE) // Delay log (50ms)
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BB_TRACE("[MP] delay 50\n");
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}
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}
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hal_write32(bb->hal_com, (addr + bb->bb0_cr_offset), val);
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#if 0
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if (bb->bb0_cr_offset != 0x10000)
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BB_WARNING("[W] bb0_ofst=0x%x, 0x%04x = 0x%08x\n", bb->bb0_cr_offset, addr, val);
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#endif
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}
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u32 halbb_get_cr(struct bb_info *bb, u32 addr, u32 mask)
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{
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u32 val = hal_read32(bb->hal_com, (addr + bb->bb0_cr_offset));
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u8 mask_lsb = 0, mask_msb = 0;
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if (bb->bb_dbg_i.cr_recorder_en)
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BB_TRACE("[R] 0x%04x = 0x%08x\n", addr, val);
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#if 0
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if (bb->bb_dbg_i.cr_mp_recorder_en) {
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mask_lsb = halbb_bitmask_lsb(bb, mask);
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mask_msb = halbb_bitmask_msb(bb, mask);
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if (mask_lsb == mask_msb)
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BB_TRACE("[MP] id 0x%x[%d]\n", addr, mask_lsb);
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else if ((mask_lsb == 0) && (mask_msb == 31))
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BB_TRACE("[MP] id 0x%x\n", addr);
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else
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BB_TRACE("[MP] id 0x%x[%d:%d]\n", addr, mask_msb, mask_lsb);
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}
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#endif
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#if 0
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if (bb->bb0_cr_offset != 0x10000)
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BB_WARNING("[R] bb0_ofst=0x%x, 0x%04x = 0x%08x\n", bb->bb0_cr_offset, addr, val);
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#endif
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return val;
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}
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void halbb_set_reg(struct bb_info *bb, u32 addr, u32 mask, u32 val)
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{
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u32 ori_val = 0;
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u32 shift;
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#ifdef HALBB_FW_OFLD_SUPPORT
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bool ret = true;
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#endif
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#ifdef HALBB_DBCC_SUPPORT
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if (bb->hal_com->dbcc_en && bb->bb_phy_idx == HW_PHY_1)
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addr += halbb_phy0_to_phy1_ofst(bb, addr, HW_PHY_1);
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#endif
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#ifdef HALBB_FW_OFLD_SUPPORT
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if (halbb_check_fw_ofld(bb)) {
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if (bb->bb_cmn_hooker->bbcr_fwofld_state || bb->bb_cmn_hooker->bb_fwofld_in_progress) {
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ret = halbb_fw_set_reg(bb, addr, mask, val, 0);
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BB_DBG(bb, DBG_FW_INFO, "[OK:%d][O:%d,N:%d] Reg_0x%08x = 0x%08x\n",
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ret,
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bb->bb_cmn_hooker->bbcr_fwofld_state,
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bb->bb_cmn_hooker->bb_fwofld_in_progress,
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addr, val);
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return;
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}
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}
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#endif
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if (mask != MASKDWORD) {
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ori_val = halbb_get_cr(bb, addr, mask);
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shift = halbb_cal_bit_shift(mask);
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val = ((ori_val) & (~mask)) | (((val << shift)) & mask);
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}
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halbb_set_cr(bb, addr, mask, val);
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}
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void halbb_set_reg_curr_phy(struct bb_info *bb, u32 addr, u32 mask, u32 val)
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{
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enum phl_phy_idx phy_idx = bb->bb_phy_idx;
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/*u32 ori_val, shift;
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u32 val_mod = val;
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addr += halbb_phy0_to_phy1_ofst(bb, addr, phy_idx);
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if (mask != MASKDWORD) {
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shift = halbb_cal_bit_shift(mask);
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ori_val = halbb_get_cr(bb, addr, mask);
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val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask);
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}
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halbb_set_cr(bb, addr, mask, val_mod);*/
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halbb_set_reg_cmn(bb, addr, mask, val, phy_idx);
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}
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void halbb_set_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, u32 val, enum phl_phy_idx phy_idx)
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{
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u32 ori_val, shift;
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u32 val_mod = val;
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#ifdef HALBB_FW_OFLD_SUPPORT
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bool ret = true;
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if (bb->bb_cmn_hooker->bbcr_fwofld_state || bb->bb_cmn_hooker->bb_fwofld_in_progress) {
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ret = halbb_fw_set_reg_cmn(bb, addr, mask, val, phy_idx, 0);
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return;
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}
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#endif
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addr += halbb_phy0_to_phy1_ofst(bb, addr, phy_idx);
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if (mask != MASKDWORD) {
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shift = halbb_cal_bit_shift(mask);
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ori_val = halbb_get_cr(bb, addr, mask);
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val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask);
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}
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halbb_set_cr(bb, addr, mask, val_mod);
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}
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void halbb_set_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 val)
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{
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/*u32 ori_val = 0, shift = 0;
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u32 val_mod = val;*/
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u32 ofst_val = 0;
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/*if (mask != MASKDWORD) {
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shift = halbb_cal_bit_shift(mask);
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ori_val = halbb_get_cr(bb, addr, mask);
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val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask);
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}
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halbb_set_cr(bb, addr, mask, val_mod);*/
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halbb_set_reg(bb, addr, mask, val);
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ofst_val = halbb_phy0_to_phy1_ofst(bb, addr, HW_PHY_1);
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if (ofst_val == 0)
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return;
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addr += ofst_val;
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/*if (mask != MASKDWORD) {
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ori_val = halbb_get_cr(bb, addr, mask);
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val_mod = ((ori_val) & (~mask)) | (((val << shift)) & mask);
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}
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halbb_set_cr(bb, addr, mask, val_mod);*/
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halbb_set_reg(bb, addr, mask, val);
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}
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u32 halbb_get_reg(struct bb_info *bb, u32 addr, u32 mask)
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{
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u32 val_0 = 0;
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#ifdef HALBB_DBCC_SUPPORT
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if (bb->hal_com->dbcc_en && bb->bb_phy_idx == HW_PHY_1)
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addr += halbb_phy0_to_phy1_ofst(bb, addr, HW_PHY_1);
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#endif
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val_0 = (halbb_get_cr(bb, addr, mask) & mask) >> halbb_cal_bit_shift(mask);
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return val_0;
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}
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u32 halbb_get_reg_curr_phy(struct bb_info *bb, u32 addr, u32 mask)
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{
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enum phl_phy_idx phy_idx = bb->bb_phy_idx;
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u32 val_0 = 0;
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addr += halbb_phy0_to_phy1_ofst(bb, addr, phy_idx);
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val_0 = (halbb_get_cr(bb, addr, mask) & mask) >> halbb_cal_bit_shift(mask);
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return val_0;
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}
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u32 halbb_get_reg_cmn(struct bb_info *bb, u32 addr, u32 mask, enum phl_phy_idx phy_idx)
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{
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u32 val_0 = 0;
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u32 shift_val = 0;
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addr += halbb_phy0_to_phy1_ofst(bb, addr, phy_idx);
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shift_val = halbb_cal_bit_shift(mask);
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shift_val = (shift_val >= 31) ? 31 : shift_val;
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val_0 = (halbb_get_cr(bb, addr, mask) & mask) >> shift_val;
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return val_0;
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}
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u32 halbb_get_reg_phy0_1(struct bb_info *bb, u32 addr, u32 mask, u32 *val_1)
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{
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u32 val_0 = 0;
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u32 shift = halbb_cal_bit_shift(mask);
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u32 ofst_val;
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val_0 = (halbb_get_cr(bb, addr, mask) & mask) >> shift;
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ofst_val = halbb_phy0_to_phy1_ofst(bb, addr, HW_PHY_1);
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if (ofst_val == 0) {
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*val_1 = val_0;
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return val_0;
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}
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addr += ofst_val;
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*val_1 = (halbb_get_cr(bb, addr, mask) & mask) >> shift;
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return val_0;
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}
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bool halbb_fill_h2c_cmd(struct bb_info *bb, u16 cmdlen, u8 cmdid,
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u8 classid, u32 *pval)
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{
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u32 rt_val = 0;
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struct rtw_g6_h2c_hdr hdr = {0};
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struct rtw_hal_com_t *hal_com = NULL;
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hdr.h2c_class = classid;
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hdr.h2c_func = cmdid;
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hdr.content_len = cmdlen;
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hdr.type = H2CB_TYPE_LONG_DATA;
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hdr.rec_ack = 0;
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hdr.done_ack = 0;
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hal_com = bb->hal_com;
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BB_DBG(bb, DBG_FW_INFO, "H2C: %x %x %x\n", classid, cmdid, cmdlen);
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rt_val = rtw_hal_mac_send_h2c(hal_com, &hdr, pval);
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if (cmdlen % 4) {
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BB_WARNING("[%s] cmdlen = %d\n", __func__, cmdlen);
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}
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if (rt_val != 0) {
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BB_WARNING("Error H2C CLASS=%d, ID=%d, Rt_v = %d\n", classid, cmdid, rt_val);
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return false;
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} else {
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return true;
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}
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}
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bool halbb_test_h2c_c2h_flow(struct bb_info *bb)
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{
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u32 rt_val = 0;
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u32 *bb_h2c;
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u8 h2ctest[4] = {1, 0, 0, 0};
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bb_h2c = (u32 *) &h2ctest;
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rt_val = halbb_fill_h2c_cmd(bb, 1, DM_H2C_FW_H2C_TEST, HALBB_H2C_DM, bb_h2c);
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if (rt_val != 0) {
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BB_WARNING("Error H2C TEST\n");
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return false;
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} else {
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return true;
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}
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}
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u32 halbb_c2h_mu_gptbl_rpt(struct bb_info *bb, u16 len, u8 *c2h)
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{
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/* Set MU grouping table and return value */
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u32 val = 0;
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u8 i = 0;
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u8 j = 0;
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u8 k = 0;
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/*u8 mask = 0x03;*/
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struct hal_mu_score_tbl *mu_sc_tbl = &bb->hal_com->bb_mu_score_tbl;
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u16 mu_score = 0;
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/*
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Need to do MU protect to prevent error c2h sending
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this function will be return to prevent error c2h
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*/
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/*return val;*/
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mu_sc_tbl->mu_ctrl.mu_sc_thr = 1;
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mu_sc_tbl->mu_ctrl.mu_opt = 0;
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for (i = 0; i < HAL_MAX_MU_STA_NUM; i++) {
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k = (i << 1);
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mu_score = (c2h[k] | c2h[k + 1] << 8); /*check endian*/
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for (j = 0; j < (HAL_MAX_MU_STA_NUM - 1); j++) {
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mu_sc_tbl->mu_score[i].score[j] = (mu_score & 3);
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mu_score >>= 2;
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}
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}
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#if 0
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for (i = 0; i < HAL_MAX_MU_STA_NUM; i++)
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for (j = 0; j < HAL_MAX_MU_SCORE_SIZE; j++) {
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if (mask == 0x03) {
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mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask);
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mask = mask <<2;
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} else if (mask == 0x0c) {
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mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>2;
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mask = mask <<2;
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} else if (mask == 0x30) {
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mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>4;
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mask = mask <<2;
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} else { /*(mask == 0xc0) */
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mu_sc_tbl->mu_score[i].score[j] = (c2h[k]&mask)>>6;
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mask = 0x03;
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k++;
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}
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}
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#endif
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return val;
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}
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#ifdef HALBB_DYN_L2H_SUPPORT
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u32 halbb_c2h_lowrt_rty(struct bb_info *bb, u16 len, u8 *c2h)
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{
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u32 c2h_rty_cnt = 0;
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struct bb_dyn_l2h_info *dyn_l2h_i = &bb->bb_dyn_l2h_i;
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c2h_rty_cnt = (*c2h) + ((*(c2h+1))<<8);
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dyn_l2h_i->low_rate_rty_cnt += c2h_rty_cnt;
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return 0;
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}
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void halbb_fw_ctrl_rtyrpt(struct bb_info *bb, u8 rpt_rtycnt, u8 en_fw_rpt)
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{
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struct bb_fw_dbg_cmn_info *fwmn_i = &bb->bb_fwdbg_i;
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u32 *bb_h2c = (u32 *) fwmn_i;
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u8 cmdlen = sizeof(struct bb_fw_dbg_cmn_info);
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bool ret_val = false;
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fwmn_i->fw_cmn_info |= (en_fw_rpt & 0x01);
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fwmn_i->fw_rty_rpt_ctrl = rpt_rtycnt;
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BB_DBG(bb, DBG_FW_INFO, "FW CTRL RTYRPT: %d %d\n", fwmn_i->fw_cmn_info, fwmn_i->fw_rty_rpt_ctrl);
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BB_DBG(bb, DBG_FW_INFO, "FW CMN CTRL: %x %x\n", bb_h2c[0], bb_h2c[1]);
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ret_val = halbb_fill_h2c_cmd(bb, cmdlen, DM_H2C_FWTRACE, HALBB_H2C_DM, bb_h2c);
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}
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#endif
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/* Remove after 8852A B cut */
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/*
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u32 halbb_c2h_fw_trig_tx_rpt(struct bb_info *bb, u16 len, u8 *c2h)
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{
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struct bb_c2h_fw_tx_rpt *fw_tx_i = &bb->bb_fwtx_c2h_i;
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bool tx_stat = c2h[0] & BIT(0);
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u32 val = (u32)false;
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if (tx_stat) {
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BB_DBG(bb, DBG_FW_INFO, "[FW][C2H] Tx done\n");
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} else {
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BB_DBG(bb, DBG_FW_INFO, "[FW][C2H] Tx fail\n");
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}
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// PD hit enable
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halbb_set_reg(bb, 0xa3c, BIT(9), 0);
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halbb_set_reg(bb, 0xabc, BIT(9), 0);
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fw_tx_i->tx_done = tx_stat;
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val = (u32)true;
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return val;
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}*/
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u32 halbb_c2h_fw_h2c_test(struct bb_info *bb, u16 len, u8 *c2h)
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{
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u16 i;
|
u32 val = (u32)false;
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for (i = 0; i < len; i++) {
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BB_DBG(bb, DBG_FW_INFO, "FW H2C and C2H test: %d\n", c2h[i]);
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}
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return val;
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}
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u32 halbb_c2h_ra_parsing(struct bb_info *bb, u8 cmdid, u16 len, u8 *c2h)
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{
|
u32 val = 0;
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u16 i;
|
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BB_DBG(bb, DBG_FW_INFO, "FW C2H RA parsing: cmdid:%d len:%d\n", cmdid, len);
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BB_DBG(bb, DBG_FW_INFO, "FW C2H RA parsing: content ==>");
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for (i = 0; i < len; i++)
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BB_DBG(bb, DBG_FW_INFO, "%x", c2h[i]);
|
BB_DBG(bb, DBG_FW_INFO, "<== \n ");
|
switch(cmdid) {
|
case HALBB_C2HRA_STS_RPT:
|
val = halbb_get_fw_ra_rpt(bb, len, c2h);
|
break;
|
case HALBB_C2HRA_MU_GPTBL_RPT:
|
val = halbb_c2h_mu_gptbl_rpt(bb, len, c2h);
|
break;
|
case HALBB_C2HRA_TXSTS:
|
val = halbb_get_txsts_rpt(bb, len, c2h);
|
break;
|
case HALBB_C2HRA_TX_DBG_INFO:
|
val = halbb_get_fw_ra_dbgrpt_wifi7(bb, len, c2h);
|
break;
|
default:
|
break;
|
}
|
return val;
|
}
|
|
u32 halbb_c2h_dm_parsing(struct bb_info *bb, u8 cmdid, u16 len, u8 *c2h)
|
{
|
u32 val = 0;
|
u16 i;
|
|
BB_DBG(bb, DBG_FW_INFO, "FW C2H DM parsing: cmdid:%d len:%d\n", cmdid, len);
|
BB_DBG(bb, DBG_FW_INFO, "FW C2H DM parsing: content ==>");
|
for (i = 0; i < len; i++)
|
BB_DBG(bb, DBG_FW_INFO, "%x", c2h[i]);
|
BB_DBG(bb, DBG_FW_INFO, "<== \n ");
|
switch(cmdid) {
|
case DM_C2H_FW_TEST:
|
val = halbb_c2h_fw_h2c_test(bb, len, c2h);
|
break;
|
case DM_C2H_FW_TRIG_TX_RPT: /* Remove after 8852A B cut */
|
break;
|
#ifdef HALBB_DYN_L2H_SUPPORT
|
case DM_C2H_LOWRT_RTY:
|
val = halbb_c2h_lowrt_rty(bb, len, c2h);
|
break;
|
#endif
|
#ifdef HALBB_DIG_MCC_SUPPORT
|
case DM_C2H_MCC_DIG:
|
val = halbb_c2h_mccdm_check(bb, len, c2h);
|
break;
|
#endif
|
#ifdef HALBB_PMAC_TX_SUPPORT
|
case DM_C2H_EHTSIG:
|
val = halbb_c2h_ehtsig_rpt(bb, len, c2h);
|
break;
|
#endif
|
case DM_C2H_DBG:
|
val = halbb_c2h_fw_dbg(bb, len, c2h);
|
default:
|
break;
|
}
|
return val;
|
}
|
|
u32 halbb_c2h_rua_parsing(struct bb_info *bb, u8 cmdid, u16 len, u8 *c2h)
|
{
|
u32 val = 0;
|
u8 *printaddr = c2h;
|
int i = 0;
|
int len_s = len - 4;
|
BB_DBG(bb, DBG_RUA_TBL,"FW C2H RUA parsing: cmdid:%d len:%d\n", cmdid, len);
|
BB_DBG(bb, DBG_RUA_TBL,"print len=%x, content==>\n", len);
|
|
for (i = 0; i < len; i = i+4) {
|
if(i > len_s)
|
break;
|
BB_DBG(bb, DBG_RUA_TBL,"%02x: %02x%02x%02x%02x\n", i, printaddr[i+3], printaddr[i+2], printaddr[i+1], printaddr[i]);
|
}
|
|
switch(cmdid) {
|
case HALBB_C2HRUA_DBG:
|
val = 1;
|
break;
|
default:
|
break;
|
}
|
return val;
|
}
|
|
u32 rtw_halbb_c2h_parsing(struct bb_info *bb, u8 classid, u8 cmdid, u16 len, u8 *c2h)
|
{
|
u32 val = 0;
|
switch(classid) {
|
case HALBB_C2H_RUA:
|
val = halbb_c2h_rua_parsing(bb, cmdid, len, c2h);
|
break;
|
case HALBB_C2H_RA:
|
val = halbb_c2h_ra_parsing(bb, cmdid, len, c2h);
|
break;
|
case HALBB_C2H_DM:
|
val = halbb_c2h_dm_parsing(bb, cmdid, len, c2h);
|
break;
|
default:
|
break;
|
}
|
return val;
|
}
|
|
enum rf_path halbb_config_path(struct bb_info *bb, enum phl_band_idx band_idx,
|
u8 rf_num)
|
{
|
enum rf_path path_set = RF_PATH_A;
|
|
if (bb->num_rf_path == 1)
|
path_set = RF_PATH_A;
|
else if (bb->num_rf_path == 2)
|
path_set = RF_PATH_AB;
|
else if (bb->num_rf_path == 3)
|
path_set = RF_PATH_ABC;
|
else
|
path_set = RF_PATH_ABCD;
|
if (rf_num == 1) {
|
if (bb->ic_type == BB_RTL8851B)
|
path_set = RF_PATH_A;
|
else
|
path_set = RF_PATH_B;
|
}
|
#ifdef HALBB_DBCC_SUPPORT
|
/* While DBCC enable, PHY0 should set path_en = 0,
|
PHY1 should set path_en = 1, and PHY0 Txpath_map_a should set 0, others
|
will be config by HW
|
*/
|
|
if (bb->hal_com->dbcc_en) {
|
if (band_idx == HW_BAND_0)
|
path_set = RF_PATH_A;
|
else
|
path_set = RF_PATH_B;
|
}
|
#endif
|
return path_set;
|
}
|
|
enum rtw_hal_status
|
halbb_config_cmac_tbl_be(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i,
|
void *cmac_ctrl,
|
void *cmac_ctrl_mask)
|
{
|
enum rtw_hal_status ret = RTW_HAL_STATUS_FAILURE;
|
/* tbd */
|
ret = RTW_HAL_STATUS_SUCCESS;
|
return ret;
|
}
|
|
enum rtw_hal_status
|
halbb_config_cmac_tbl_ax(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i,
|
void *cmac_ctrl,
|
void *cmac_ctrl_mask)
|
{
|
struct rtw_hal_mac_ax_cctl_info * cctrl = (struct rtw_hal_mac_ax_cctl_info *)cmac_ctrl;
|
struct rtw_hal_mac_ax_cctl_info *cctl_info_mask = (struct rtw_hal_mac_ax_cctl_info *)cmac_ctrl_mask;
|
enum rtw_hal_status ret = RTW_HAL_STATUS_FAILURE;
|
enum rf_path path_set = RF_PATH_A;
|
u16 cfg;
|
u16 macid = 0;
|
u8 rf_num = 0;
|
bool dbcc_en = false;
|
enum phl_band_idx band_idx = HW_BAND_0;
|
|
if (NULL == phl_sta_i)
|
return ret;
|
|
band_idx = phl_sta_i->rlink->hw_band;
|
rf_num = bb->phl_com->phy_cap[band_idx].tx_path_num;
|
|
/* BB related mask */
|
cctl_info_mask->txpwr_mode = 0x7;
|
cctl_info_mask->ntx_path_en = 0xf;
|
cctl_info_mask->path_map_a = 0x3;
|
cctl_info_mask->path_map_b = 0x3;
|
cctl_info_mask->path_map_c = 0x3;
|
cctl_info_mask->path_map_d = 0x3;
|
cctl_info_mask->antsel_a = 0x1;
|
cctl_info_mask->antsel_b = 0x1;
|
cctl_info_mask->antsel_c = 0x1;
|
cctl_info_mask->antsel_d = 0x1;
|
cctl_info_mask->doppler_ctrl = 0x3;
|
cctl_info_mask->txpwr_tolerence = 0xf;
|
|
/* BB related cmac tbl */
|
path_set = halbb_config_path(bb, band_idx, rf_num);
|
cctrl->txpwr_mode = 0; /* txpwr ctrl */
|
cfg = halbb_cfg_cmac_tx_ant(bb, path_set);
|
cctrl->ntx_path_en = cfg & 0x0f;
|
cctrl->path_map_a = ((cfg>>4) & 0x03);
|
cctrl->path_map_b = ((cfg>>6) & 0x03);
|
cctrl->path_map_c = ((cfg>>8) & 0x03);
|
cctrl->path_map_d = ((cfg>>10) & 0x03);
|
cctrl->antsel_a = 0x0;
|
cctrl->antsel_b = 0x0;
|
cctrl->antsel_c = 0x0;
|
cctrl->antsel_d = 0x0;
|
cctrl->doppler_ctrl = 0;
|
cctrl->txpwr_tolerence = 0;
|
ret = RTW_HAL_STATUS_SUCCESS;
|
BB_DBG(bb, DBG_FW_INFO, "HALBB CMAC tbl config: path = %x\n", cfg);
|
return ret;
|
}
|
|
|
|
u8 halbb_set_cmac_txpwr_mode(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
/* power by macid */
|
return 0;
|
}
|
|
u8 halbb_set_cmac_ntx_en(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 1;
|
}
|
|
u8 halbb_set_cmac_path_map_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 0;
|
}
|
|
u8 halbb_set_cmac_path_map_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 1;
|
}
|
|
u8 halbb_set_cmac_path_map_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 2;
|
}
|
|
u8 halbb_set_cmac_path_map_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 3;
|
}
|
|
u8 halbb_set_cmac_antsel_a(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
/* antenna selection*/
|
return 0;
|
}
|
|
u8 halbb_set_cmac_antsel_b(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 0;
|
}
|
|
u8 halbb_set_cmac_antsel_c(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 0;
|
}
|
|
u8 halbb_set_cmac_antsel_d(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 0;
|
}
|
|
u8 halbb_set_cmac_pwr_tol(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
return 0;
|
}
|
|
u8 halbb_set_cmac_databw_er(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
/* 0: RU242, 1:RU106*/
|
return 0;
|
}
|
|
bool halbb_set_pwr_by_rate_tbl(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_i)
|
{
|
struct halbb_pwr_by_rate_tbl pwr_t = {{0}};
|
u8 i = 0;
|
enum rtw_data_rate ru_pwr_rate[PWR_TBL_NUM] = {RTW_DATA_RATE_HE_NSS1_MCS0,
|
RTW_DATA_RATE_HE_NSS1_MCS1, RTW_DATA_RATE_HE_NSS1_MCS2,
|
RTW_DATA_RATE_HE_NSS1_MCS3, RTW_DATA_RATE_HE_NSS1_MCS4,
|
RTW_DATA_RATE_HE_NSS1_MCS5, RTW_DATA_RATE_HE_NSS1_MCS6,
|
RTW_DATA_RATE_HE_NSS1_MCS7, RTW_DATA_RATE_HE_NSS1_MCS8,
|
RTW_DATA_RATE_HE_NSS1_MCS9, RTW_DATA_RATE_HE_NSS1_MCS10,
|
RTW_DATA_RATE_HE_NSS1_MCS11, RTW_DATA_RATE_HE_NSS2_MCS0,
|
RTW_DATA_RATE_HE_NSS2_MCS1, RTW_DATA_RATE_HE_NSS2_MCS2,
|
RTW_DATA_RATE_HE_NSS2_MCS3, RTW_DATA_RATE_HE_NSS2_MCS4,
|
RTW_DATA_RATE_HE_NSS2_MCS5, RTW_DATA_RATE_HE_NSS2_MCS6,
|
RTW_DATA_RATE_HE_NSS2_MCS7, RTW_DATA_RATE_HE_NSS2_MCS8,
|
RTW_DATA_RATE_HE_NSS2_MCS9, RTW_DATA_RATE_HE_NSS2_MCS10,
|
RTW_DATA_RATE_HE_NSS2_MCS11, RTW_DATA_RATE_HE_NSS1_MCS0,
|
RTW_DATA_RATE_HE_NSS1_MCS1, RTW_DATA_RATE_HE_NSS1_MCS3,
|
RTW_DATA_RATE_HE_NSS1_MCS4, RTW_DATA_RATE_HE_NSS2_MCS0,
|
RTW_DATA_RATE_HE_NSS2_MCS1, RTW_DATA_RATE_HE_NSS2_MCS3,
|
RTW_DATA_RATE_HE_NSS2_MCS4};
|
u32 *pval = (u32 *)&pwr_t;
|
u8 cmdlen = sizeof(pwr_t);
|
u8 dcm = 0;
|
enum rtw_data_rate rate;
|
enum channel_width bw = phl_sta_i->chandef.bw;
|
u8 channel = phl_sta_i->chandef.center_ch;
|
s16 pwr_db = 0;
|
|
|
for (i = 0; i < PWR_TBL_NUM; i++) {
|
rate = ru_pwr_rate[i];
|
if (i >=24)
|
dcm = 1;
|
/*rtw_hal_rf_read_pwr_table(bb->hal_com, 0, rate, bw, channel, 0, dcm, 0, &pwr_db);*/
|
pwr_t.pwr_by_rate[i*2] = (u8)(pwr_db&0xff);
|
pwr_t.pwr_by_rate[i*2+1] = (u8)((pwr_db>>8)&0xff);
|
}
|
/* Get pwr by rate tbl from halrf */
|
halbb_fill_h2c_cmd(bb, cmdlen, RUA_H2C_PWR_TBL, HALBB_H2C_RUA, pval);
|
return false;
|
}
|
