/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_EX_H__
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#define __HALBB_EX_H__
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#include "halbb_ic_hw_info.h"
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/*@--------------------------[Define] ---------------------------------------*/
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/*@--------------------------[Enum]------------------------------------------*/
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enum halbb_pause_type {
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HALBB_PAUSE = 1, /*Pause & Set new value*/
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HALBB_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/
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HALBB_RESUME = 3,
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HALBB_RESUME_NO_RECOVERY = 4,
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};
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enum halbb_pause_lv_type {
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HALBB_PAUSE_RELEASE = -1,
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HALBB_PAUSE_LV_0 = 0, /* @Low Priority function */
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HALBB_PAUSE_LV_1 = 1, /* @Middle Priority function */
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HALBB_PAUSE_LV_2 = 2, /* @High priority function (ex: Check hang function) */
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HALBB_PAUSE_LV_3 = 3, /* @Debug function (the highest priority) */
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HALBB_PAUSE_MAX_NUM = 4
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};
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enum halbb_pause_rpt {
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PAUSE_FAIL = 0,
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PAUSE_SUCCESS = 1
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};
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/*---[BB Components]---*/
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enum habb_fun_t {
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F_RA = 0,
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F_FA_CNT = 1,
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HALBB_FUN_RSVD_2 = 2,
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F_DFS = 3,
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F_EDCCA = 4,
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F_ENV_MNTR = 5,
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F_CFO_TRK = 6,
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F_PWR_CTRL = 7,
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F_RUA_TBL = 8,
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F_AUTO_DBG = 9,
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F_ANT_DIV = 10,
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F_DIG = 11,
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F_PATH_DIV = 12,
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F_UL_TB_CTRL = 13,
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F_DCR = 31,
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F_DEFAULT = 0xff
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};
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enum bb_watchdog_mode_t {
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BB_WATCHDOG_NORMAL = 0,
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BB_WATCHDOG_LOW_IO = 1,
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BB_WATCHDOG_NON_IO = 2,
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};
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struct halbb_func_info {
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char name[16];
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u8 id;
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};
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static const struct halbb_func_info halbb_func_i[] = {
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{"ra", F_RA}, /*@do not move this element to other position*/
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{"fa_cnt", F_FA_CNT}, /*@do not move this element to other position*/
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{"rsvd2", HALBB_FUN_RSVD_2},
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{"dfs", F_DFS},
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{"edcca", F_EDCCA},
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{"env_mntr", F_ENV_MNTR},
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{"cfo_trk", F_CFO_TRK},
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{"pwr_ctrl", F_PWR_CTRL},
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{"rua_tbl", F_RUA_TBL},
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{"auto_dbg", F_AUTO_DBG},
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{"ant_div", F_ANT_DIV},
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{"dig", F_DIG},
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{"path_div", F_PATH_DIV},
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{"ul_tb", F_UL_TB_CTRL},
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};
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/*@=[HALBB supportability]=======================================*/
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enum habb_supportability_t {
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BB_RA = BIT(F_RA),
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BB_FA_CNT = BIT(F_FA_CNT),
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BB_FUN_RSVD_2 = BIT(HALBB_FUN_RSVD_2),
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BB_DFS = BIT(F_DFS),
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BB_EDCCA = BIT(F_EDCCA),
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BB_ENVMNTR = BIT(F_ENV_MNTR),
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BB_CFO_TRK = BIT(F_CFO_TRK),
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BB_PWR_CTRL = BIT(F_PWR_CTRL),
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BB_RUA_TBL = BIT(F_RUA_TBL),
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BB_AUTO_DBG = BIT(F_AUTO_DBG),
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BB_ANT_DIV = BIT(F_ANT_DIV),
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BB_DIG = BIT(F_DIG),
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BB_PATH_DIV = BIT(F_PATH_DIV),
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BB_UL_TB_CTRL = BIT(F_UL_TB_CTRL),
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BB_DCR = BIT(F_DCR)
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};
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/*@=[HALBB Debug Component]=====================================*/
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enum halbb_dbg_comp_t {
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/*=== [DM Part] ==========================*/
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DBG_RA = BIT(F_RA),
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DBG_FA_CNT = BIT(F_FA_CNT),
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DBG_HALBB_FUN_RSVD_2 = BIT(HALBB_FUN_RSVD_2),
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DBG_DFS = BIT(F_DFS),
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DBG_EDCCA = BIT(F_EDCCA),
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DBG_ENV_MNTR = BIT(F_ENV_MNTR),
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DBG_CFO_TRK = BIT(F_CFO_TRK),
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DBG_PWR_CTRL = BIT(F_PWR_CTRL),
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DBG_RUA_TBL = BIT(F_RUA_TBL),
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DBG_AUTO_DBG = BIT(F_AUTO_DBG),
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DBG_ANT_DIV = BIT(F_ANT_DIV),
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DBG_DIG = BIT(F_DIG),
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DBG_PATH_DIV = BIT(F_PATH_DIV),
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DBG_UL_TB_CTRL = BIT(F_UL_TB_CTRL),
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/*=== [Non-DM Part] ======================*/
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DBG_BIT14 = BIT(14),
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DBG_FW_DBG = BIT(15),
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DBG_PHY_CONFIG_BE = BIT(16),
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DBG_BIT17 = BIT(17),
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DBG_SNIFFER = BIT(18),
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DBG_CH_INFO = BIT(19),
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DBG_PHY_STS = BIT(20),
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DBG_CONNECT = BIT(21),
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DBG_FW_INFO = BIT(22),
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DBG_COMMON_FLOW = BIT(23),
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DBG_IC_API = BIT(24),
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DBG_DBG_API = BIT(25),
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DBG_DBCC = BIT(26),
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DBG_DM_SUMMARY = BIT(27),
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DBG_PHY_CONFIG = BIT(28),
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DBG_INIT = BIT(29),
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DBG_CMN = BIT(30),
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DBG_DCR = BIT(F_DCR)
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};
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/*@--------------------------[Structure]-------------------------------------*/
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#if 0
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/*For development use only, and will move to "struct rtw_rssi_info" in near furture*/
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struct bb_rssi_info{
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u8 rssi; /*avg RSSI among all RF path, dbm = RSSI - 110*/
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u16 rssi_acc; /*U(16,4) version of rssi*/
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u8 rssi_cck; /*instance value of CCK RSSI*/
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u8 rssi_ofdm; /*instance value of OFDM RSSI*/
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};
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#endif
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struct bb_sta_info {
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u8 sta_status_tmp;
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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struct bb_info;
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bool halbb_sta_info_init(struct bb_info *bb,
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struct rtw_phl_stainfo_t *phl_sta_info);
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bool halbb_sta_info_deinit(struct bb_info *bb,
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struct rtw_phl_stainfo_t *phl_sta_info);
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bool halbb_sta_info_add_entry(struct bb_info *bb, struct rtw_phl_stainfo_t *phl_sta_info);
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bool halbb_sta_info_delete_entry(struct bb_info *bb,
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struct rtw_phl_stainfo_t *phl_sta_info);
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void halbb_media_status_update(struct bb_info *bb,
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struct rtw_phl_stainfo_t *phl_sta_info,
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bool is_connected);
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void halbb_watchdog_reset(struct bb_info *bb);
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void halbb_watchdog(struct bb_info *bb, enum bb_watchdog_mode_t mode,
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enum phl_phy_idx phy_idx);
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u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx);
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void halbb_bb_cmd_notify(struct bb_info *bb, void *bb_cmd, enum phl_phy_idx phy_idx);
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u8 halbb_pause_func(struct bb_info *bb, enum habb_fun_t pause_func,
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enum halbb_pause_type pause_type,
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enum halbb_pause_lv_type lv,
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u8 val_lehgth,
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u32 *val_buf, enum phl_phy_idx phy_idx);
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#endif
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