/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_EDCCA_H__
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#define __HALBB_EDCCA_H__
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/*@--------------------------[Define] ---------------------------------------*/
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#define EDCCA_HL_DIFF_ADPTVTY 7
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#define EDCCA_HL_DIFF_NORMAL 8
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// EDCCA
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#define CBP_6G 53 /*@-68 dB to avoid cross-band loss*/
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#define EDCCA_5G 63 /*@-62 dBm -3 dB margin*/
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#define EDCCA_2G 68 /*@-57 dBm -3 dB margin*/
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#define CARRIER_SENSE 75 /*@-50dBm -3 dB margin*/
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#define EDCCA_MAX 249 /*@ 127dBm for normal mode*/
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#define EDCCA_TH_L2H_LB 66 /*@ -62 dBm from IEEE*/
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#define EDCCA_PWDB_EXCLU_TX 128 /*128 - 256 = -128dBm when Tx*/
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#define EDCCA_PWDB_TO_RSSI(pwdb) ((pwdb + 110) < 0 ? 0 : (pwdb + 110))
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#define EDCCA_PWROFST_DEFAULT 18 /*2dB is phyUD default value. Note that the loss from adc to snd is actually 0.5dB*/
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#define EDCCA_TH_REF 3
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// Collision T2R/R2T TH
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#define COLLOSION_TH_LOW 0
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#define COLLOSION_TH_HIGH 31
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#define COLLOSION_TH_RSSI2VAL 50
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#define COLLOSION_TH_OFST 0
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// FW EDCCA
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#define EDCCA_5G_TH 70 // -62
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#define EDCCA_2p4G_TH 65// -57
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#define CARRIER_SENSE_TH 58 // -50
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/*@--------------------------[Enum]------------------------------------------*/
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/*@--------------------------[Structure]-------------------------------------*/
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struct bb_h2c_fw_edcca {
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u8 mode;
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u8 band;
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u8 pwr_th_5g;
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u8 pwr_th_2p4;
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u8 pwr_th_cs;
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u8 enable;
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u8 rsvd1;
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u8 rsvd2;
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};
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struct bb_edcca_cr_info {
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u32 r_snd_en;
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u32 r_snd_en_m;
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u32 r_snd_en_s80_1;
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u32 r_snd_en_s80_1_m;
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u32 r_snd_en_s80_2;
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u32 r_snd_en_s80_2_m;
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u32 r_snd_en_s80_3;
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u32 r_snd_en_s80_3_m;
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u32 r_dwn_level;
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u32 r_dwn_level_m;
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u32 r_dwn_level_s80_1;
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u32 r_dwn_level_s80_1_m;
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u32 r_dwn_level_s80_2;
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u32 r_dwn_level_s80_2_m;
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u32 r_dwn_level_s80_3;
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u32 r_dwn_level_s80_3_m;
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u32 r_edcca_level;
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u32 r_edcca_level_m;
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u32 r_edcca_level_p;
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u32 r_edcca_level_p_m;
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u32 r_edcca_level_s80_1;
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u32 r_edcca_level_s80_1_m;
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u32 r_edcca_level_s80_1_p;
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u32 r_edcca_level_s80_1_p_m;
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u32 r_edcca_level_s80_2;
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u32 r_edcca_level_s80_2_m;
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u32 r_edcca_level_s80_2_p;
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u32 r_edcca_level_s80_2_p_m;
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u32 r_edcca_level_s80_3;
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u32 r_edcca_level_s80_3_m;
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u32 r_edcca_level_s80_3_p;
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u32 r_edcca_level_s80_3_p_m;
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u32 r_edcca_rpt_a;
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u32 r_edcca_rpt_a_m;
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u32 r_edcca_rpt_b;
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u32 r_edcca_rpt_b_m;
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u32 r_edcca_rpt_a_p1;
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u32 r_edcca_rpt_a_p1_m;
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u32 r_edcca_rpt_b_p1;
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u32 r_edcca_rpt_b_p1_m;
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u32 r_edcca_rpt_sel;
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u32 r_edcca_rpt_sel_m;
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u32 r_edcca_rpt_sel_p1;
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u32 r_edcca_rpt_sel_p1_m;
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u32 r_edcca_rptreg_sel_be_dd;
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u32 r_edcca_rptreg_sel_be_dd_m;
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u32 r_ppdu_level;
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u32 r_ppdu_level_m;
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u32 r_ppdu_level_p;
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u32 r_ppdu_level_p_m;
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u32 r_obss_level;
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u32 r_obss_level_m;
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u32 collision_r2t_th;
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u32 collision_r2t_th_m;
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u32 collision_t2r_th_mcs0;
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u32 collision_t2r_th_mcs0_m;
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u32 collision_t2r_th_mcs1;
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u32 collision_t2r_th_mcs1_m;
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u32 collision_t2r_th_mcs2;
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u32 collision_t2r_th_mcs2_m;
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u32 collision_t2r_th_mcs3;
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u32 collision_t2r_th_mcs3_m;
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u32 collision_t2r_th_mcs4;
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u32 collision_t2r_th_mcs4_m;
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u32 collision_t2r_th_mcs5;
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u32 collision_t2r_th_mcs5_m;
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u32 collision_t2r_th_mcs6;
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u32 collision_t2r_th_mcs6_m;
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u32 collision_t2r_th_mcs7;
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u32 collision_t2r_th_mcs7_m;
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u32 collision_t2r_th_mcs8;
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u32 collision_t2r_th_mcs8_m;
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u32 collision_t2r_th_mcs9;
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u32 collision_t2r_th_mcs9_m;
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u32 collision_t2r_th_mcs10;
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u32 collision_t2r_th_mcs10_m;
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u32 collision_t2r_th_mcs11;
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u32 collision_t2r_th_mcs11_m;
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u32 collision_t2r_th_mcs12;
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u32 collision_t2r_th_mcs12_m;
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u32 collision_t2r_th_mcs13;
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u32 collision_t2r_th_mcs13_m;
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u32 collision_t2r_th_cck;
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u32 collision_t2r_th_cck_m;
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u32 collision_t2r_th_cck_1M;
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u32 collision_t2r_th_cck_1M_m;
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u32 collision_t2r_th_cck_2M;
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u32 collision_t2r_th_cck_2M_m;
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u32 collision_t2r_th_cck_5p5M;
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u32 collision_t2r_th_cck_5p5M_m;
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u32 collision_t2r_th_cck_11M;
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u32 collision_t2r_th_cck_11M_m;
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u32 collision_map2dbm;
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u32 collision_map2dbm_m;
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u32 collision_t2r_th_he_dcm_mcs0;
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u32 collision_t2r_th_he_dcm_mcs0_m;
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u32 collision_t2r_th_he_dcm_mcs1;
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u32 collision_t2r_th_he_dcm_mcs1_m;
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u32 collision_t2r_th_he_dcm_mcs2;
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u32 collision_t2r_th_he_dcm_mcs2_m;
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u32 collision_t2r_th_he_dcm_mcs3;
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u32 collision_t2r_th_he_dcm_mcs3_m;
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u32 collision_t2r_th_he_dcm_mcs4;
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u32 collision_t2r_th_he_dcm_mcs4_m;
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u32 collision_t2r_th_eht_dcm_mcs14;
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u32 collision_t2r_th_eht_dcm_mcs14_m;
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u32 collision_t2r_th_eht_dcm_mcs15;
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u32 collision_t2r_th_eht_dcm_mcs15_m;
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u32 collision_t2r_th_legacy_6M;
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u32 collision_t2r_th_legacy_6M_m;
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u32 collision_t2r_th_legacy_9M;
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u32 collision_t2r_th_legacy_9M_m;
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u32 collision_t2r_th_legacy_12M;
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u32 collision_t2r_th_legacy_12M_m;
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u32 collision_t2r_th_legacy_18M;
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u32 collision_t2r_th_legacy_18M_m;
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u32 collision_t2r_th_legacy_24M;
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u32 collision_t2r_th_legacy_24M_m;
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u32 collision_t2r_th_legacy_36M;
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u32 collision_t2r_th_legacy_36M_m;
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u32 collision_t2r_th_legacy_48M;
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u32 collision_t2r_th_legacy_48M_m;
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u32 collision_t2r_th_legacy_54M;
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u32 collision_t2r_th_legacy_54M_m;
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u32 r_collision_t2r_state;
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u32 r_collision_t2r_state_m;
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u32 r_pwrofst;
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u32 r_pwrofst_m;
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u32 r_dc_remove;
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u32 r_dc_remove_m;
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};
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struct edcca_hw_rpt {
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s8 pwdb_fb; /*52A/52B is 0 when BW=40, 92XB would fix*/
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s8 pwdb_p20;
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s8 pwdb_s20;
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s8 pwdb_s40;
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s8 pwdb_s80;
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bool flag_fb;
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bool flag_p20;
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bool flag_s20;
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bool flag_s40;
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bool flag_s80;
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s8 pwdb_0;
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s8 pwdb_1;
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s8 pwdb_2;
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s8 pwdb_3;
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s8 pwdb_4;
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s8 pwdb_5;
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s8 pwdb_6;
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s8 pwdb_7;
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s8 pwdb_8;
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u8 path;
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s8 per20_bitmap_0;
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s8 per20_bitmap_1;
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s8 per20_bitmap_2;
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s8 per20_bitmap_3;
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s8 per20_bitmap_4;
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s8 per20_bitmap_5;
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s8 per20_bitmap_6;
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s8 per20_bitmap_7;
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};
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struct bb_edcca_info {
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struct bb_edcca_cr_info bb_edcca_cr_i;
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u8 th_l;
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u8 th_h;
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u8 th_hl_diff;
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u8 edcca_mode;
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u8 th_h_lb;
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u8 th_h_6g;
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u8 th_h_5g;
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u8 th_h_2p4g;
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u8 th_h_cs;
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u8 colli_th;
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u8 colli_ofst;
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struct edcca_hw_rpt edcca_rpt;
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u8 pwrofst; /*max(ext_loss, 2), 0~31=>[-16:1:15]*/
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u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
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};
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#ifdef HALBB_DYN_L2H_SUPPORT
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struct bb_dyn_l2h_info {
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bool en_dyn_l2h;
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u32 low_rate_rty_cnt;
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u32 drop_cnt;
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u8 l2h_th;
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};
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#endif
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struct bb_info;
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/*@--------------------------[Prptotype]-------------------------------------*/
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void halbb_edcca_get_result(struct bb_info *bb);
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void halbb_edcca(struct bb_info *bb);
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void halbb_edcca_thre_calc(struct bb_info * bb);
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void halbb_set_collision_th(struct bb_info *bb);
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void halbb_set_collision_thre(struct bb_info *bb);
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void halbb_set_edcca_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
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void halbb_edcca_event_nofity(struct bb_info * bb, u8 pause_type);
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void halbb_edcca_dev_hw_cap(struct bb_info * bb);
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void halbb_edcca_init(struct bb_info *bb);
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void halbb_cr_cfg_edcca_init(struct bb_info *bb);
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void halbb_edcca_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_edcca_cmn_log(struct bb_info *bb);
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#endif
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