/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_DIG_H__
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#define __HALBB_DIG_H__
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#define DIG_VERSION "5.0"
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//#define DIG_DBCC_DEV_TMP
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/*@--------------------------[Define] ---------------------------------------*/
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#define BB_LNA_SIZE 7
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#define BB_TIA_SIZE 2
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#define IGI_RSSI_TH_NUM 5
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#define FA_TH_NUM 4
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#define RSSI_MAX 110
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#define RSSI_MIN 0
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#ifdef DIG_DBCC_DEV_TMP
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#define IGI_NOLINK (38 + 20)
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#else
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#define IGI_NOLINK 38
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#endif
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#define LNA_IDX_MAX 6
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#define LNA_IDX_MIN 0
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#define TIA_IDX_MAX 1
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#define TIA_IDX_MIN 0
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#define RXB_IDX_MAX 31
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#define RXB_IDX_MIN 0
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#define LNA6_GAIN 24
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#define LNA5_GAIN 16
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#define LNA4_GAIN 8
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#define LNA3_GAIN 0
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#define LNA2_GAIN (-8)
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#define LNA1_GAIN (-16)
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#define LNA0_GAIN (-24)
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#define TIA1_GAIN_A 20
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#define TIA0_GAIN_A 12
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#define TIA1_GAIN_G 24
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#define TIA0_GAIN_G 16
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#define IGI_OFFSET_MAX 25 /* IGI window size */
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#define IGI_MAX_PERFORMANCE_MODE 0x5a
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#define IGI_MAX_BALANCE_MODE 0x3e
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#define PD_TH_MAX_RSSI 70 /* -40dBm */
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#define PD_TH_MIN_RSSI 8 /* -102dBm */
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#define PD_TH_BW80_CMP_VAL 6
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#define PD_TH_BW40_CMP_VAL 3
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#define PD_TH_BW20_CMP_VAL 0
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#define PD_TH_SB_FLTR_CMP_VAL 7
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#define DIG_CCX_WD_TRIGTIME 1900
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#define IGI_EDCCA_GAP_LIMIT 35
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#ifdef HALBB_DIG_TDMA_SUPPORT
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#define IGI_MAX_AT_STATE_L 0x26
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#define WACHDOG_PERIOD_IN_MS 2000
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#define H_STATE_NUM_MAX 20
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#define L_STATE_NUM_MAX 10
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#endif
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#define DIG_RECORD_NUM 6
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#define DIG_LIMIT_PERIOD 60 /*60 sec*/
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#ifdef HALBB_DBG_TRACE_SUPPORT
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#define BB_DIG_DBG(bb, lv, fmt, ...)\
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do {\
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if(bb->dbg_component & DBG_DIG && bb->bb_dig_i.dbg_lv >= lv) {\
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_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
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}\
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} while (0)
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#else
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#define BB_DIG_DBG(bb, lv, fmt, ...)
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#endif
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/*@--------------------------[Enum]------------------------------------------*/
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enum dig_noisy_level {
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DIG_NOISY_LV0 = 0, /*FA free*/
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DIG_NOISY_LV1 = 1,
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DIG_NOISY_LV2 = 2,
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DIG_NOISY_LV3 = 3,
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DIG_NOISY_LV_MAX = 4
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};
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#ifdef HALBB_DIG_TDMA_SUPPORT
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enum dig_tdma_state {
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DIG_TDMA_LOW = 0,
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DIG_TDMA_HIGH = 1
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};
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#endif
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enum dig_dbg_level {
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DIG_DBG_LV0 = 0,
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DIG_DBG_LV1 = 1,
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DIG_DBG_LV2 = 2
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct bb_dig_cr_info {
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u32 path0_ib_pbk;
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u32 path0_ib_pbk_m;
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u32 path0_ib_pkpwr;
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u32 path0_ib_pkpwr_m;
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u32 path1_ib_pbk;
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u32 path1_ib_pbk_m;
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u32 path1_ib_pkpwr;
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u32 path1_ib_pkpwr_m;
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u32 path0_lna_init_idx;
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u32 path0_lna_init_idx_m;
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u32 path1_lna_init_idx;
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u32 path1_lna_init_idx_m;
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u32 path0_tia_init_idx;
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u32 path0_tia_init_idx_m;
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u32 path1_tia_init_idx;
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u32 path1_tia_init_idx_m;
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u32 path0_rxb_init_idx;
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u32 path0_rxb_init_idx_m;
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u32 path1_rxb_init_idx;
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u32 path1_rxb_init_idx_m;
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u32 seg0r_pd_spatial_reuse_en_a;
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u32 seg0r_pd_spatial_reuse_en_a_m;
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u32 seg0r_pd_lower_bound_a;
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u32 seg0r_pd_lower_bound_a_m;
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u32 path0_p20_follow_by_pagcugc_en_a;
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u32 path0_s20_follow_by_pagcugc_en_a;
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u32 path1_p20_follow_by_pagcugc_en_a;
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u32 path1_s20_follow_by_pagcugc_en_a;
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u32 path0_p20_follow_by_pagcugc_en_a_m;
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u32 path0_s20_follow_by_pagcugc_en_a_m;
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u32 path1_p20_follow_by_pagcugc_en_a_m;
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u32 path1_s20_follow_by_pagcugc_en_a_m;
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u32 path0_lna_err_g0_a;
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u32 path0_lna_err_g0_a_m;
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u32 path0_lna_err_g0_g;
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u32 path0_lna_err_g0_g_m;
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u32 path0_lna_err_g1_a;
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u32 path0_lna_err_g1_a_m;
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u32 path0_lna_err_g1_g;
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u32 path0_lna_err_g1_g_m;
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u32 path0_lna_err_g2_a;
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u32 path0_lna_err_g2_a_m;
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u32 path0_lna_err_g2_g;
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u32 path0_lna_err_g2_g_m;
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u32 path0_lna_err_g3_a;
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u32 path0_lna_err_g3_a_m;
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u32 path0_lna_err_g3_g;
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u32 path0_lna_err_g3_g_m;
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u32 path0_lna_err_g4_a;
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u32 path0_lna_err_g4_a_m;
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u32 path0_lna_err_g4_g;
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u32 path0_lna_err_g4_g_m;
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u32 path0_lna_err_g5_a;
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u32 path0_lna_err_g5_a_m;
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u32 path0_lna_err_g5_g;
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u32 path0_lna_err_g5_g_m;
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u32 path0_lna_err_g6_a;
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u32 path0_lna_err_g6_a_m;
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u32 path0_lna_err_g6_g;
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u32 path0_lna_err_g6_g_m;
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u32 path0_tia_err_g0_a;
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u32 path0_tia_err_g0_a_m;
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u32 path0_tia_err_g0_g;
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u32 path0_tia_err_g0_g_m;
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u32 path0_tia_err_g1_a;
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u32 path0_tia_err_g1_a_m;
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u32 path0_tia_err_g1_g;
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u32 path0_tia_err_g1_g_m;
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u32 path1_lna_err_g0_a;
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u32 path1_lna_err_g0_a_m;
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u32 path1_lna_err_g0_g;
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u32 path1_lna_err_g0_g_m;
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u32 path1_lna_err_g1_a;
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u32 path1_lna_err_g1_a_m;
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u32 path1_lna_err_g1_g;
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u32 path1_lna_err_g1_g_m;
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u32 path1_lna_err_g2_a;
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u32 path1_lna_err_g2_a_m;
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u32 path1_lna_err_g2_g;
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u32 path1_lna_err_g2_g_m;
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u32 path1_lna_err_g3_a;
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u32 path1_lna_err_g3_a_m;
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u32 path1_lna_err_g3_g;
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u32 path1_lna_err_g3_g_m;
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u32 path1_lna_err_g4_a;
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u32 path1_lna_err_g4_a_m;
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u32 path1_lna_err_g4_g;
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u32 path1_lna_err_g4_g_m;
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u32 path1_lna_err_g5_a;
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u32 path1_lna_err_g5_a_m;
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u32 path1_lna_err_g5_g;
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u32 path1_lna_err_g5_g_m;
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u32 path1_lna_err_g6_a;
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u32 path1_lna_err_g6_a_m;
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u32 path1_lna_err_g6_g;
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u32 path1_lna_err_g6_g_m;
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u32 path1_tia_err_g0_a;
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u32 path1_tia_err_g0_a_m;
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u32 path1_tia_err_g0_g;
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u32 path1_tia_err_g0_g_m;
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u32 path1_tia_err_g1_a;
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u32 path1_tia_err_g1_a_m;
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u32 path1_tia_err_g1_g;
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u32 path1_tia_err_g1_g_m;
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u32 cca_rssi_lmt_en_a;
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u32 cca_rssi_lmt_en_a_m;
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u32 rssi_nocca_low_th_a;
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u32 rssi_nocca_low_th_a_m;
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u32 path0_dig_mode_en_a;
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u32 path0_dig_mode_en_a_m;
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u32 path0_igi_for_dig_a;
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u32 path0_igi_for_dig_a_m;
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u32 path0_backoff_wb_gain_a;
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u32 path0_backoff_wb_gain_a_m;
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u32 path1_dig_mode_en_a;
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u32 path1_dig_mode_en_a_m;
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u32 path1_igi_for_dig_a;
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u32 path1_igi_for_dig_a_m;
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u32 path1_backoff_wb_gain_a;
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u32 path1_backoff_wb_gain_a_m;
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};
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struct agc_gaincode_set {
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u8 lna_idx;
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u8 tia_idx;
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u8 rxb_idx;
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};
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struct bb_dig_fa_info {
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u16 fa_r_cck_onesec;
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u16 fa_r_ofdm_onesec;
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u16 fa_r_onesec; /* overall fa_ratio */
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};
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struct bb_dig_op_para_unit {
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bool dyn_pd_th_en;
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u8 igi_rssi_th[IGI_RSSI_TH_NUM];
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u16 fa_th[FA_TH_NUM]; /* permil */
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};
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#ifdef HALBB_DIG_DAMPING_CHK
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struct bb_dig_record_info {
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u8 igi_bitmap; /*@Don't add any new parameter before this*/
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u8 igi_history[DIG_RECORD_NUM];
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u32 fa_history[DIG_RECORD_NUM];
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bool damping_lock_en;
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u8 damping_limit_val; /*@Limit IGI_dyn_min*/
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u32 limit_time;
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u8 limit_rssi; /*s(8,1)*/
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};
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#endif
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/* struct for state unit, i.e., L/H */
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struct bb_dig_op_unit {
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#ifdef HALBB_DIG_TDMA_SUPPORT
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enum dig_tdma_state state_identifier; /* L/H */
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#endif
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struct agc_gaincode_set cur_gaincode;
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enum dig_noisy_level cur_noisy_lv;
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struct agc_gaincode_set force_gaincode;
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struct bb_dig_op_para_unit dig_op_para;
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u16 fa_r_acc; /* acced one shot fa_ratio */
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u16 fa_r_avg; /* acced one shot fa_ratio */
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u8 fa_valid_state_cnt;
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u8 state_num_lmt;
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u8 passed_state_cnt;
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u8 igi_fa_rssi; /*final IGI calaulated by FA & RSSI*/
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u8 fa_rssi_ofst;
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u8 abs_igi_max;
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u8 abs_igi_min;
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u8 dyn_igi_max;
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u8 dyn_igi_min;
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u8 pd_low_th_ofst; /* pd low safe cca region */
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bool sdagc_follow_pagc_en;
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};
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struct bb_dig_info {
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bool init_dig_cr_success;
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enum dig_op_mode dig_mode;
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enum dig_op_mode pre_dig_mode;
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struct bb_dig_cr_info bb_dig_cr_i;
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struct agc_gaincode_set max_gaincode;
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u8 igi_rssi; //rssi_min
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u8 ib_pbk;
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s8 ib_pkpwr;
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s8 lna_gain_a[BB_LNA_SIZE];
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s8 lna_gain_g[BB_LNA_SIZE];
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s8 *lna_gain;
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s8 tia_gain_a[BB_TIA_SIZE];
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s8 tia_gain_g[BB_TIA_SIZE];
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s8 *tia_gain;
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s8 le_igi_ofst; /* low end mode IGI offset */
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struct bb_dig_op_unit *p_cur_dig_unit;
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struct bb_dig_op_unit dig_state_h_i; /* high state */
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#ifdef HALBB_DIG_TDMA_SUPPORT
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struct bb_dig_op_unit dig_state_l_i; /* low state */
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bool gaincode_update_en;
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u16 tdma_passed_time_acc; /* check if 1sec reach */
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u8 tdma_timestamp_pre;
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u8 tdma_timestamp_cur;
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struct halbb_timer_info dig_timer_i;
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#endif
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#ifdef HALBB_ENV_MNTR_SUPPORT
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u8 fahm_timestamp;
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struct fahm_para_info fahm_para_i;
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bool fahm_is_triggered;
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#endif
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struct bb_dig_fa_info dig_fa_i;
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enum dig_dbg_level dbg_lv;
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u32 rvrt_val[DIG_PAUSE_INFO_SIZE]; /*[Pause fucntion] must set to u32*/
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u16 igi_pause_cnt; /*consective pause counter*/
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bool need_update;
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u16 dig_hold_cnt;
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#ifdef HALBB_DIG_DAMPING_CHK
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struct bb_dig_record_info bb_dig_record_i;
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u8 rls_rssi_diff_th; /*s(8,1)*/
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bool dig_dl_en; /*@damping limit function enable*/
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#endif
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};
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struct bb_info;
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/*@--------------------------[Prptotype]-------------------------------------*/
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#ifdef HALBB_DIG_TDMA_SUPPORT
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void halbb_dig_timercheck_watchdog(struct bb_info*);
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void halbb_tdmadig_io_en(struct bb_info *bb);
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void halbb_dig_timer_init(struct bb_info *bb);
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#endif
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void halbb_dig_lps(struct bb_info *bb);
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void halbb_dig_cfg_bbcr(struct bb_info *bb, u8 igi_new);
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u8 halbb_dig_igi_by_ofst(struct bb_info *bb, u8 igi_pre, s8 ofst);
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void halbb_dig(struct bb_info *bb);
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void halbb_dig_init(struct bb_info *bb);
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void halbb_dig_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_cr_cfg_dig_init(struct bb_info *bb);
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void* halbb_get_dig_fa_statistic(struct bb_info *bb);
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void halbb_set_dig_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
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#ifdef HALBB_DIG_MCC_SUPPORT
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void Halbb_init_mccdm(struct bb_info *bb);
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void halbb_mccdm_switch(struct bb_info *bb);
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u32 halbb_c2h_mccdm_check(struct bb_info *bb, u16 len, u8 *c2h);
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#endif
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u8 halbb_get_lna_idx(struct bb_info *bb, enum rf_path path);
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u8 halbb_get_tia_idx(struct bb_info *bb, enum rf_path path);
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u8 halbb_get_rxb_idx(struct bb_info *bb, enum rf_path path);
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#endif
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