/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_DBG_H__
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#define __HALBB_DBG_H__
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#include "../../hal_headers_le.h"
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/*@--------------------------[Define] ---------------------------------------*/
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#define HALBB_WATCHDOG_PERIOD 2 /*second*/
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#define PHY_HIST_SIZE 12
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#define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1)
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#define LA_CLK_EN 0x014 /*Just for dbg, will be removed*/
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#define LA_CLK_EN_M 0x1 /*Just for dbg, will be removed*/
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#define FRC_PRINT_LINE 0xffffffff
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#ifdef HALBB_DBG_TRACE_SUPPORT
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#ifdef HALBB_DBCC_SUPPORT
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#define BB_DBG(bb, comp, fmt, ...) \
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do {\
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if(bb->dbg_component & comp) {\
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_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
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} \
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} while (0)
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#define BB_TRACE1(bb, fmt, ...) \
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do {\
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_os_dbgdump("[BB][%d]" fmt, bb->bb_phy_idx, ##__VA_ARGS__);\
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} while (0)
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#else
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#define BB_DBG(bb, comp, fmt, ...) \
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do {\
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if(bb->dbg_component & comp) {\
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_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
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} \
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} while (0)
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#define BB_TRACE1(bb, fmt, ...) \
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do {\
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_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
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} while (0)
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#endif
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#define BB_TRACE(fmt, ...) \
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do {\
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_os_dbgdump("[BB]" fmt, ##__VA_ARGS__);\
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} while (0)
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#define BB_WARNING(fmt, ...) \
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do {\
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_os_dbgdump("[WARNING][BB]" fmt, ##__VA_ARGS__);\
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} while (0)
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#define BB_DBG_CNSL2(in_cnsl, max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
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do { \
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u32 *used_len_tmp = &(used_len); \
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u32 len_tmp = 0; \
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if (*used_len_tmp < max_buff_len) { \
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len_tmp = _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__); \
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if (in_cnsl) { \
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*used_len_tmp += len_tmp; \
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} else { \
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BB_TRACE("%s\n", buff_addr); \
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} \
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}\
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} while (0)
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#else
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#define BB_DBG
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#define BB_TRACE
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#define BB_TRACE1
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#define BB_WARNING
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#define BB_DBG_CNSL2(in_cnsl, max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
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do { \
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u32 *used_len_tmp = &(used_len); \
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if (*used_len_tmp < max_buff_len) \
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*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
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} while (0)
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#endif
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#define BB_DBG_VAST(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
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do {\
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_os_dbgdump("[CNSL]" fmt, ##__VA_ARGS__);\
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} while (0)
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#define BB_DBG_CNSL(max_buff_len, used_len, buff_addr, remain_len, fmt, ...)\
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do { \
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u32 *used_len_tmp = &(used_len); \
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if (*used_len_tmp < max_buff_len) \
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*used_len_tmp += _os_snprintf(buff_addr, remain_len, fmt, ##__VA_ARGS__);\
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} while (0)
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#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/
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#define DBGPORT_PRI_2 2 /*@Check hang function & Strong function*/
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#define DBGPORT_PRI_1 1 /*Watch dog function*/
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#define DBGPORT_RELEASE 0 /*@Init value (the lowest priority)*/
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/*@--------------------------[Enum]------------------------------------------*/
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enum bb_dbg_devider_len_t
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{
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BB_DEVIDER_LEN_32 = 0,
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BB_DEVIDER_LEN_16 = 1,
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};
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enum bb_dbg_port_ip_t
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{
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DBGPORT_IP_TD = 1,
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DBGPORT_IP_RX_INNER = 2,
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DBGPORT_IP_TX_INNER = 3,
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DBGPORT_IP_OUTER = 4,
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DBGPORT_IP_INTF = 5,
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DBGPORT_IP_CCK = 6,
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DBGPORT_IP_BF = 7,
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DBGPORT_IP_RX_OUTER = 8,
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DBGPORT_IP_RFC0 = 0X1B,
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DBGPORT_IP_RFC1 = 0X1C,
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DBGPORT_IP_RFC2 = 0X1D,
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DBGPORT_IP_RFC3 = 0X1E,
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DBGPORT_IP_TST = 0X1F,
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};
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enum bb_frc_phy_dump_reg
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{
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FRC_DUMP_PHY0 = 0,
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FRC_DUMP_PHY1 = 1,
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FRC_DUMP_ALL
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};
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enum bb_basic_dbg_info
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{
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BB_BASIC_DBG_01_SYSTEM = BIT1,
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BB_BASIC_DBG_02_ENVMNTR = BIT2,
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BB_BASIC_DBG_03_PMAC = BIT3,
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BB_BASIC_DBG_04_TX = BIT4,
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BB_BASIC_DBG_05_RX = BIT5,
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BB_BASIC_DBG_06_RSSI_RATE = BIT6,
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BB_BASIC_DBG_07_HIST = BIT7,
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BB_BASIC_DBG_08_RSSI_RATE_MU = BIT8,
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BB_BASIC_DBG_09_DM_SUMMARY = BIT9
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};
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enum FWBB_DBG_NUM {
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BBDBG_NUM_RA_WRITE_CMAC_0 = 0,
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BBDBG_NUM_RA_RATE_CHANGED_1 = 1,
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BBDBG_NUM_RA_CAL_PARA_2 = 2,
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BBDBG_NUM_RA_D_O_PARA_3 = 3,
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BBDBG_NUM_RA_UP_DOWN_TH_4 = 4,
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BBDBG_NUM_RA_TRY_RESULT_5 = 5,
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BBDBG_NUM_RA_RATE_DOWN_6 = 6,
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BBDBG_NUM_RA_RATE_FORCE_DOWN_7 = 7,
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BBDBG_NUM_RA_RATE_UP_8 = 8,
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BBDBG_NUM_RA_RATE_STAY_9 = 9
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct bb_dbg_cr_info {
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u32 dbgport_ip;
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u32 dbgport_ip_m;
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u32 dbgport_idx;
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u32 dbgport_idx_m;
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u32 dbgport_val;
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u32 dbgport_val_m;
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u32 clk_en;
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u32 clk_en_m;
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u32 dbgport_en;
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u32 dbgport_en_m;
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u32 bb_monitor_sel0;
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u32 bb_monitor_sel0_m;
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u32 bb_monitor0;
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u32 bb_monitor0_m;
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u32 bb_monitor_sel1;
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u32 bb_monitor_sel1_m;
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u32 bb_monitor1;
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u32 bb_monitor1_m;
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u32 mac_phy_intf_sel_phy1;
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u32 mac_phy_intf_sel_phy1_m;
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u32 mac_phy_txinfo[6];
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u32 mac_phy_txt2rct[2];
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u32 mac_phy_txcomct[2];
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u32 mac_phy_txusrct[4][2];
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u32 mac_phy_txtimct;
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u32 mac_phy_lsig;
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u32 mac_phy_siga_0;
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u32 mac_phy_siga_1;
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u32 mac_phy_vht_sigb_0;
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u32 mac_phy_usig_1;
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u32 mac_phy_usig_2;
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u32 path_0_txpw;
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u32 path_0_txpw_m;
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u32 path_1_txpw;
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u32 path_1_txpw_m;
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u32 bmode_tx;
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};
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struct bb_tx_info {
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/*From reg*/
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u8 type;
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u8 ppdu_var;
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u8 tx_path_en;
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u8 path_map;
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u8 txcmd_num;
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u8 txsc;
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u8 bw;
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u16 tx_pw; /*tmac*/
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u8 n_usr;
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u8 max_mcs;
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bool stbc;
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u8 gi;
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u8 ltf;
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u8 u_id[4];
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u8 n_sts[4];
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bool fec[4];
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u8 mcs[4];
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bool dcm[4];
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u8 precoding[4];
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u16 n_sym;
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u8 pkt_ext;
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u8 pre_fec;
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u32 l_sig;
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u32 sig_a1;
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u32 sig_a2;
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u32 sig_b;
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u32 usig_1;
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u32 usig_2;
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u32 txinfo[6];
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u32 txt2rct[2];
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u32 txcomct[2];
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u32 txusrct[4][2];
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u32 txtimct;
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u16 txpw_path0; /*bb_path0*/
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u16 txpw_path1; /*bb_path1*/
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u32 bmode;
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u8 bmode_rate;
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u16 bmode_length; /*1 = 1M, 2 = 2M, 4 = 5.5M, 8 = 11M*/
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u8 bmode_service;
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bool bmode_type; /*0 = TX long preamble, 1 = TX short preamble*/
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/*sw variable*/
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u16 t_data;
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u32 psdu_length;
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};
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struct bb_ra_dbgreg {
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u32 macid;
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u32 cmac_tbl_id0;
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u32 cmac_tbl_id1;
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u32 per;
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u32 rdr;
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u32 r4;
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u32 cls;
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u32 rate_up_lmt_cnt;
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u32 per_ma;
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u32 var;
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u32 d_o_n;
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u32 d_o_p;
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u32 rd_th;
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u32 ru_th;
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u32 try_per;
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u32 try_rdr;
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u32 try_r4;
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u32 txrpt_tot;
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u32 ra_timer;
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u32 tot_disra_trying_return;
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u32 r4_return;
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u32 ra_mask_h;
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u32 ra_mask_l;
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u32 highest_rate;
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u32 lowest_rate;
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u32 upd_all_h2c_0;
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u32 upd_all_h2c_1;
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u32 upd_all_h2c_2;
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u32 upd_all_h2c_3;
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u32 dyn_stbc;
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u32 mu_mcs;
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u32 mu_id_lowest_rate;
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u32 mu_rd_ru_th;
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u32 mu_per;
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};
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struct bb_dbg_info {
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bool cr_recorder_en;
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bool cr_mp_recorder_en;
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bool cr_init_hook_recorder_en;
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bool cr_fake_init_hook_en;
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u32 cr_fake_init_hook_val;
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bool cr_recorder_rf_en; /*HALRF write BB CR*/
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/*CR init debug control*/
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bool cr_dbg_mode_en;
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u32 cut_curr_dbg;
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u32 rfe_type_curr_dbg;
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#ifdef HALBB_TDMA_CR_SUPPORT
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struct halbb_timer_info tdma_cr_timer_i;
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bool tdma_cr_en;
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u8 tdma_cr_state;
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u32 tdma_cr_idx;
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u32 tdma_cr_mask;
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u32 tdma_cr_val_0;
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u32 tdma_cr_val_1;
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u32 tdma_cr_period_0;
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u32 tdma_cr_period_1;
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#endif
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struct bb_tx_info tx_info_i;
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struct bb_ra_dbgreg ra_dbgreg_i;
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struct bb_dbg_cr_info bb_dbg_cr_i;
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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struct bb_info;
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void halbb_print_devider(struct bb_info *bb, u8 len, bool with_space, u64 comp);
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#ifdef HALBB_TDMA_CR_SUPPORT
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void halbb_tdma_cr_sel_io_en(struct bb_info *bb);
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void halbb_tdma_cr_timer_init(struct bb_info *bb);
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void halbb_tdma_cr_sel_main(struct bb_info *bb);
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void halbb_tdma_cr_sel_init(struct bb_info *bb);
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#endif
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void halbb_dbg_comp_init(struct bb_info *bb);
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void halbb_bb_dbg_port_clock_en(struct bb_info *bb, u8 enable);
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u32 halbb_get_bb_dbg_port_idx(struct bb_info *bb);
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void halbb_set_bb_dbg_port(struct bb_info *bb, u32 dbg_port);
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void halbb_set_bb_dbg_port_ip(struct bb_info *bb, enum bb_dbg_port_ip_t ip);
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void halbb_release_bb_dbg_port(struct bb_info *bb);
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bool halbb_bb_dbg_port_racing(struct bb_info *bb, u8 curr_dbg_priority);
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u32 halbb_get_bb_dbg_port_val(struct bb_info *bb);
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u16 halbb_rx_utility(struct bb_info *bb, u16 avg_phy_rate, u8 rx_max_ss,
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enum channel_width bw);
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u16 halbb_rx_avg_phy_rate(struct bb_info *bb);
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void halbb_get_tx_dbg_reg(struct bb_info *bb);
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void halbb_basic_dbg_message(struct bb_info *bb);
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void halbb_basic_profile_dbg(struct bb_info *bb, u32 *_used, char *output, u32 *_out_len);
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void halbb_get_bb_para_pkg_ver(struct bb_info *bb, u32 *date, u32 *release_ver);
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void halbb_dump_reg_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
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void halbb_dd_dump_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
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void halbb_cr_table_dump(struct bb_info *bb, u32 *cr_table, u32 cr_len);
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void halbb_cr_hook_fake_init(struct bb_info *bb, u32 *str_table, u32 len);
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void halbb_cr_hook_init_dump(struct bb_info *bb, u32 *str_table, u32 len);
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void halbb_dump_bb_reg(struct bb_info *bb, u32 *_used, char *output,
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u32 *_out_len, bool dump_2_buff,
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enum bb_frc_phy_dump_reg frc_phy_dump);
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void halbb_tx_info_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_cmn_dbg(struct bb_info *bb, char input[][16], u32 *_used, char *output, u32 *_out_len);
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void halbb_dbg_setting_init(struct bb_info *bb);
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void halbb_cr_cfg_dbg_init(struct bb_info *bb);
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void halbb_mac_phy_intf_txcmd_txtp(struct bb_info *bb, u8 txcmd_num, char **txcmd);
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void halbb_mac_phy_intf_txcmd_txtp_7(struct bb_info *bb, u8 txcmd_num, char **txcmd);
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void halbb_mac_phy_intf_ppdu_type(struct bb_info *bb, u8 type, char **ppdu);
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void halbb_mac_phy_intf_ppdu_var_type_7(struct bb_info *bb, u8 ppdu_type, u8 ppdu_var, char **ppdu);
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u32 halbb_c2h_fw_dbg(struct bb_info *bb, u16 len, u8 *c2h);
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#endif
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