/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_CFO_TRK_H__
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#define __HALBB_CFO_TRK_H__
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/*@--------------------------[Define] ---------------------------------------*/
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#define CFO_TRK_TH_SIZE 4
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#define CFO_TRK_TH_4 30 /* @kHz disable CFO_Track threshold*/
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#define CFO_TRK_TH_3 20 /* @kHz disable CFO_Track threshold*/
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#define CFO_TRK_TH_2 10 /* @kHz disable CFO_Track threshold*/
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#define CFO_TRK_TH_1 3 /* @kHz disable CFO_Track threshold*/
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#define CFO_STEP_1 1 /* @kHz disable CFO_Track threshold*/
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#define CFO_STEP_2 1 /* @kHz disable CFO_Track threshold*/
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#define CFO_STEP_3 3 /* @kHz disable CFO_Track threshold*/
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#define CFO_STEP_4 3 /* @kHz disable CFO_Track threshold*/
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#define CFO_TRK_ENABLE_TH 3 /* @kHz enable CFO_Track threshold*/
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#define CFO_TRK_STOP_TH 3 /* @kHz disable CFO_Track threshold*/
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#define NO_PKT_RETURN_TH 10
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#define CFO_VALID_BOUNDARY 64
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#define CFO_SW_COMP_FINE_TUNE 5 /* @kHz expected CFO Comp. per Xcap ofst*/ /*0.8ppm~1ppm per Xcap ofst*/
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#define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
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#define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
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#define CFO_RECORD_NUM 6
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#define CFO_LIMIT_PERIOD 60 /*60 sec*/
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#define SC_XO 1 /* xcap setting output value */
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#define SC_XI 0 /* xcap setting input value */
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#define STA_CFO_TOLERANCE_2G 30 /* kHz */
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#define STA_CFO_TOLERANCE_5G 80 /* kHz */
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#define CFO_HW_RPT_2_KHZ(val) (((val) << 1) + ((val) >> 1))
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#define CFO_PERIOD_CNT 15
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#define CFO_TP_UPPER 100 /*MHz*/
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#define CFO_TP_LOWER 50 /*MHz*/
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#define CFO_COMP_PERIOD 250 /*ms*/
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#define CFO_TF_CNT_TH 300
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/*@--------------------------[Enum]------------------------------------------*/
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enum bb_cfo_trk_src_t {
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CFO_SRC_FD = 0,
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CFO_SRC_PREAMBLE = 1
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};
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enum bb_cfo_trk_st_t {
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CFO_STATE_0 = 0,
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CFO_STATE_1 = 1,
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CFO_STATE_2 =2
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};
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enum bb_cfo_trk_acc_mode_t {
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CFO_ACC_MODE_0 = 0, /*disable ul_ofdma cfo acc after 30s acc*/
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CFO_ACC_MODE_1 = 1, /*enable ul_ofdma cfo acc after 30s acc*/
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};
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enum multi_sta_cfo_mode_t {
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PKT_BASED_AVG_MODE = 0,
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ENTRY_BASED_AVG_MODE = 1,
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TP_BASED_AVG_MODE = 2,
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};
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#ifdef BB_DYN_CFO_TRK_LOP
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enum bb_dctl_state_t {
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DCTL_SNR = 0,
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DCTL_LINK = 1,
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DCTL_NUM
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};
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#endif
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/*@--------------------------[Structure]-------------------------------------*/
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#ifdef BB_DYN_CFO_TRK_LOP
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struct bb_cfo_trk_lop_cr_info {
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u8 dctl_data; /*data tracking loop filter bandwidth selection for 3rd step*/
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u8 dctl_pilot; /*pilot tracking loop filter bandwidth selection for 3rd step*/
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};
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struct bb_dyn_cfo_trk_lop_info {
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bool dyn_cfo_trk_loop_en;
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enum bb_dctl_state_t dyn_cfo_trk_loop_state;
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u16 dctl_snr_th_l;
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u16 dctl_snr_th_h;
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u8 dctl_hold_cnt;
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struct bb_cfo_trk_lop_cr_info bb_cfo_trk_lop_cr_i[DCTL_NUM];
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};
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#endif
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struct bb_cfo_trk_cr_info {
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u32 r_cfo_comp_seg0_312p5khz;
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u32 r_cfo_comp_seg0_312p5khz_m;
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u32 r_cfo_comp_seg0_312p5khz_1;
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u32 r_cfo_comp_seg0_312p5khz_1_m;
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u32 r_cfo_comp_seg0_312p5khz_2;
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u32 r_cfo_comp_seg0_312p5khz_2_m;
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u32 r_cfo_comp_seg0_312p5khz_3;
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u32 r_cfo_comp_seg0_312p5khz_3_m;
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u32 r_cfo_comp_seg0_vld;
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u32 r_cfo_comp_seg0_vld_m;
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u32 r_cfo_wgting;
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u32 r_cfo_wgting_m;
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};
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struct bb_cfo_rc_info {
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u8 step_history[CFO_RECORD_NUM];
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u8 step_bitmap;
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bool damping_lock_en;
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bool force_damping_step;
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u32 limit_time;
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};
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struct bb_cfo_diver_info {
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bool divergence_lock_en;
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u32 limit_time;
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};
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struct bb_cfo_trk_info {
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struct bb_cfo_trk_cr_info bb_cfo_trk_cr_i;
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#ifdef HALBB_CFO_DAMPING_CHK
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struct bb_cfo_rc_info bb_cfo_rc_i;
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#endif
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struct bb_cfo_diver_info bb_cfo_div_i;
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bool cfo_trig_by_timer_en;
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bool is_adjust; /*@already modify crystal cap*/
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u8 cfo_th[CFO_TRK_TH_SIZE]; /*u(8,2)*/
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u8 step[CFO_TRK_TH_SIZE];
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u8 cfo_th_en;
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u8 cfo_th_stop; /*u(8,2)*/
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s8 x_cap_ofst;
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u8 crystal_cap;
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u8 def_x_cap;
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u8 x_cap_ub;
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u8 x_cap_lb;
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s32 cfo_avg_pre; /*S(12,2), -512~+511.75 kHz*/
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u32 cfo_pkt_cnt;
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u8 no_pkt_cnt;
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u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
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u8 tb_tx_comp_cfo_th; /*u(8,2)*/
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u8 sw_comp_fine_tune; /*u(8,2)*/
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u8 bb_cfo_trk_cnt;
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u8 sta_cfo_tolerance;
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u8 shift4dcfo;
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s32 cfo_avg_4dcfo;
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s32 cfo_avg_4dcfo_pre;
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bool man_cfo_tol;
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bool cfo_dyn_acc_en;
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bool cfo_trk_by_data_en;
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u8 cfo_period_cnt;
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u32 cfo_tf_cnt_th;
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u32 cfo_tf_cnt_pre;
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s32 dcfo_comp_offset; /* For manually fine tune digital cfo*/
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enum bb_cfo_trk_src_t cfo_src;
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enum bb_cfo_trk_st_t bb_cfo_trk_state;
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enum bb_cfo_trk_acc_mode_t bb_cfo_trk_acc_mode;
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enum multi_sta_cfo_mode_t multi_sta_cfo_mode;
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#ifdef BB_DYN_CFO_TRK_LOP
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struct bb_dyn_cfo_trk_lop_info bb_dyn_cfo_trk_lop_i;
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#endif
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struct halbb_timer_info cfo_timer_i;
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};
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struct bb_info;
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/*@--------------------------[Prptotype]-------------------------------------*/
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#ifdef BB_DYN_CFO_TRK_LOP
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void halbb_dyn_cfo_trk_loop_en(struct bb_info *bb, bool en);
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void halbb_cfo_trk_loop_cr_cfg(struct bb_info *bb, enum bb_dctl_state_t state);
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void halbb_dyn_cfo_trk_loop(struct bb_info *bb);
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void halbb_dyn_cfo_trk_loop_init(struct bb_info *bb);
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#endif
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void halbb_cfo_trk_init(struct bb_info *bb);
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void halbb_set_crystal_cap(struct bb_info *bb, u8 crystal_cap);
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void halbb_set_cfo_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
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void halbb_cfo_acc_io_en(struct bb_info *bb);
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void halbb_cfo_acc_timer_init(struct bb_info *bb);
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void halbb_cfo_dm(struct bb_info *bb);
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void halbb_cfo_watchdog(struct bb_info *bb);
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void halbb_parsing_cfo(struct bb_info *bb, u32 physts_bitmap,
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struct physts_rxd *desc);
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void halbb_cfo_trk_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_cr_cfg_cfo_trk_init(struct bb_info *bb);
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void halbb_cfo_ul_ofdma_acc_enable(struct bb_info *bb);
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void halbb_cfo_ul_ofdma_acc_disable(struct bb_info *bb);
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void halbb_cfo_diver_init(struct bb_info *bb);
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#endif
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