/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALBB_ANT_DIV_H__
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#define __HALBB_ANT_DIV_H__
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/*@--------------------------[Define] ---------------------------------------*/
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#define EVM_BASED_ANTDIV 0
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#define CN_BASED_ANTDIV 1
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#define TP_MAX_DOMINATION 0
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#define TP_HIGHEST_DOMINATION 1
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#define TP_AVG_DOMINATION 2
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#define ANTDIV_INIT 0xff
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#define MAIN_ANT 1 /*@ant A or ant Main or S1*/
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#define AUX_ANT 2 /*@AntB or ant Aux or S0*/
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#define MAX_ANT 3 /* @3 for AP using*/
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#define ANT1_2G 0
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/* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
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#define ANT2_2G 1
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/* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
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#define ANTDIV_MAX_STA_NUM PHL_MAX_STA_NUM
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#define ANTDIV_RSSI_TH_HIGH 30
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#define ANTDIV_RSSI_TH_LOW 20
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#define ANTDIV_PERIOD 1
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#define ANTDIV_TRAINING_NUM 2
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#define ANTDIV_NOTRAINING_NUM 3
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#define FORCE_RSSI_DIFF 10
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#define ANTDIV_DELAY 110
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#define ANTDIV_INTVL 30
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#define ANTDIV_DEC_TP_HIGH 100
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#define ANTDIV_DEC_TP_LOW 5
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#define ANTDIV_DEC_EVM 8
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#define ANTDIV_DEC_EVM_1SS 8
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#define TP_LOWER_BOUND 1
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/*parameter for 1ss rssi-based antdiv*/
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#define ANTDIV_PERIOD_1SS 1
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#define ANTDIV_TRAINING_NUM_1SS 2
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#define ANTDIV_DELAY_1SS 1
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#define ANTDIV_INTVL_1SS 10
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#define ANTDIV_DEC_RSSI 3
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#define ANTDIV_FIXANT_RSSI 2
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/* @Antenna Diversty Control type */
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#define ODM_AUTO_ANT 0
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#define ODM_FIX_MAIN_ANT 1
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#define ODM_FIX_AUX_ANT 2
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#define ANTDIV_ON 1
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#define ANTDIV_OFF 0
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#define ANT_PATH_A 0
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#define ANT_PATH_B 1
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#define ANT_PATH_AB 2
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/*@--------------------------[Enum]------------------------------------------*/
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enum bb_antdiv_mode_t {
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AUTO_ANT = 0,
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FIX_MAIN_ANT = 1,
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FIX_AUX_ANT = 2,
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};
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enum bb_tp_method_t {
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TP_MAX = 0,
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TP_HIGHEST = 1,
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TP_AVG = 2,
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};
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enum bb_evm_method_t {
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EVM_LINEAR_AVG = 0,
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EVM_DB_AVG = 1,
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};
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enum bb_antdiv_method_t {
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EVM_BASED = 0,
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CN_BASED = 1,
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct bb_antdiv_rssi_info { /*all in U(8,1)*/
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/*acc value*/
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u32 rssi_cck_avg_acc;
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u32 rssi_ofdm_avg_acc;
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u32 rssi_t_avg_acc;
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u8 rssi_cck_avg;
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u8 rssi_ofdm_avg;
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u8 rssi_t_avg;
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u8 rssi_final;
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u16 pkt_cnt_t;
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u16 pkt_cnt_cck;
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u16 pkt_cnt_ofdm;
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u32 main_rssi_cck_avg_acc;
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u32 main_rssi_ofdm_avg_acc;
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u32 main_rssi_t_avg_acc;
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u8 main_rssi_cck_avg;
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u8 main_rssi_ofdm_avg;
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u8 main_rssi_t_avg;
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u8 main_rssi_final;
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u16 main_pkt_cnt_t;
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u16 main_pkt_cnt_cck;
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u16 main_pkt_cnt_ofdm;
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u32 aux_rssi_cck_avg_acc;
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u32 aux_rssi_ofdm_avg_acc;
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u32 aux_rssi_t_avg_acc;
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u8 aux_rssi_cck_avg;
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u8 aux_rssi_ofdm_avg;
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u8 aux_rssi_t_avg;
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u8 aux_rssi_final;
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u16 aux_pkt_cnt_t;
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u16 aux_pkt_cnt_cck;
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u16 aux_pkt_cnt_ofdm;
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u8 rssi_diff;
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bool no_change_flag;
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};
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struct bb_antdiv_cn_info {
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u32 main_cn_avg_acc; /*U(7,1)*/
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u32 aux_cn_avg_acc; /*U(7,1)*/
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};
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struct bb_antdiv_evm_info {
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u32 main_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/
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u32 main_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
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u32 main_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
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u32 aux_evm_1ss;/*U(8,2)*/ /*only for 1SS & L-OFDM*/
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u32 aux_evm_min_acc; /*U(8,2)*/ /*only for >= 2SS*/
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u32 aux_evm_max_acc; /*U(8,2)*/ /*only for >= 2SS*/
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u8 evm_diff;
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bool no_change_flag;
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};
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struct bb_antdiv_rate_info {
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/*====[Phy rate counter main ant]=============================================*/
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u16 main_pkt_cnt_cck;
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u16 main_pkt_cnt_ofdm; /*L-OFDM*/
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u16 main_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
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u16 main_pkt_cnt_1ss; /*HT, VHT, HE*/
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u16 main_pkt_cnt_2ss; /*HT, VHT, HE*/
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/*Legacy*/
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u16 main_pkt_cnt_legacy[LEGACY_RATE_NUM];
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/*HT*/
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u16 main_pkt_cnt_ht[HT_RATE_NUM];
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/*VHT*/
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u16 main_pkt_cnt_vht[VHT_RATE_NUM];
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/*HE*/
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u16 main_pkt_cnt_he[HE_RATE_NUM];
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u16 main_max_cnt;
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u16 main_max_idx;
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/*====[Phy rate counter] aux ant=============================================*/
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u16 aux_pkt_cnt_cck;
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u16 aux_pkt_cnt_ofdm; /*L-OFDM*/
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u16 aux_pkt_cnt_t; /*HT, VHT, HE = pkt_cnt_1ss + pkt_cnt_2ss*/
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u16 aux_pkt_cnt_1ss; /*HT, VHT, HE*/
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u16 aux_pkt_cnt_2ss; /*HT, VHT, HE*/
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/*Legacy*/
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u16 aux_pkt_cnt_legacy[LEGACY_RATE_NUM];
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/*HT*/
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u16 aux_pkt_cnt_ht[HT_RATE_NUM];
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/*VHT*/
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u16 aux_pkt_cnt_vht[VHT_RATE_NUM];
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/*HE*/
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u16 aux_pkt_cnt_he[HE_RATE_NUM];
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u16 aux_max_cnt;
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u16 aux_max_idx;
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u16 main_cnt_all;
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u16 aux_cnt_all;
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u64 main_tp;
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u64 aux_tp;
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u64 tp_diff;
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bool no_change_flag;
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bool main_ht_pkt_not_zero;
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bool main_vht_pkt_not_zero;
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bool main_he_pkt_not_zero;
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bool aux_ht_pkt_not_zero;
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bool aux_vht_pkt_not_zero;
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bool aux_he_pkt_not_zero;
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};
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struct bb_antdiv_cr_info {
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u32 path0_r_ant_train_en;
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u32 path0_r_ant_train_en_m;
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u32 path0_r_tx_ant_sel;
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u32 path0_r_tx_ant_sel_m;
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u32 path0_r_rfe_buf_en;
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u32 path0_r_rfe_buf_en_m;
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u32 path0_r_lnaon_agc;
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u32 path0_r_lnaon_agc_m;
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u32 path0_r_trsw_bit_bt;
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u32 path0_r_trsw_bit_bt_m;
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u32 path0_r_trsw_s;
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u32 path0_r_trsw_s_m;
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u32 path0_r_trsw_o;
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u32 path0_r_trsw_o_m;
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u32 path0_r_trswb_o;
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u32 path0_r_trswb_o_m;
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u32 path0_r_bt_force_antidx;
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u32 path0_r_bt_force_antidx_m;
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u32 path0_r_bt_force_antidx_en;
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u32 path0_r_bt_force_antidx_en_m;
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u32 path0_r_ant_module_rfe_opt;
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u32 path0_r_ant_module_rfe_opt_m;
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u32 path0_r_rfsw_tr;
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u32 path0_r_rfsw_tr_m;
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u32 path0_r_antsel;
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u32 path0_r_antsel_m;
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u32 path0_r_rfsw_ant_31_0;
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u32 path0_r_rfsw_ant_31_0_m;
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u32 path0_r_rfsw_ant_63_32;
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u32 path0_r_rfsw_ant_63_32_m;
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u32 path0_r_rfsw_ant_95_64;
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u32 path0_r_rfsw_ant_95_64_m;
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u32 path0_r_rfsw_ant_127_96;
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u32 path0_r_rfsw_ant_127_96_m;
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};
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struct bb_antdiv_info {
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struct bb_antdiv_cr_info bb_antdiv_cr_i;
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/* For CN cacluation */
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struct bb_antdiv_cn_info bb_cn_i;
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/* For EVM cacluation */
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struct bb_antdiv_evm_info bb_evm_i;
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/* For MCS cacluation */
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struct bb_antdiv_rate_info bb_rate_i;
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/* For RSSI */
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struct bb_antdiv_rssi_info bb_rssi_i;
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enum bb_antdiv_mode_t antdiv_mode;
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enum bb_antdiv_method_t antdiv_method;
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enum bb_antdiv_mode_t pre_antdiv_mode;
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enum bb_tp_method_t tp_decision_method;
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enum bb_evm_method_t evm_decision_method;
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bool tx_by_ext_pwr_lmt;
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/* Training state & period related*/
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u8 antdiv_wd_cnt;
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u8 antdiv_training_state_cnt;
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u32 antdiv_intvl;
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u32 antdiv_delay;
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u32 antdiv_train_num;
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u8 antdiv_period;
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u8 tp_lb;
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u8 rssi_pre;
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u8 antdiv_notrain_cnt;
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u8 antdiv_notrain_num;
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u8 fixant_rssi_diff;
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/* antenna setting */
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u8 pre_target_ant;
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u8 training_ant;
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u8 target_ant;
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u8 target_ant_cn;
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u8 target_ant_evm;
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u8 target_ant_tp;
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u8 target_ant_rssi;
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/* Decision*/
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u16 tp_diff_th_high;
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u16 tp_diff_th_low;
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u8 evm_diff_th;
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u8 rssi_diff_th;
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/*Phy-sts related */
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bool get_stats;
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bool antdiv_use_ctrl_frame;
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struct halbb_timer_info antdiv_timer_i;
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u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
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};
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struct bb_info;
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/*@--------------------------[Prptotype]-------------------------------------*/
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void halbb_antdiv_io_en(struct bb_info *bb);
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void halbb_antdiv_timer_init(struct bb_info *bb);
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void halbb_cr_cfg_antdiv_init(struct bb_info *bb);
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void halbb_antdiv_reg_init(struct bb_info *bb);
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void halbb_antdiv_init(struct bb_info *bb);
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void halbb_antdiv_reset(struct bb_info *bb);
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void halbb_antdiv_reset_training_stat(struct bb_info *bb);
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void halbb_antdiv_set_ant(struct bb_info *bb, u8 ant);
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void halbb_antdiv_get_highest_mcs(struct bb_info *bb);
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void halbb_antdiv_get_evm_target_ant(struct bb_info *bb);
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void halbb_antdiv_training_state(struct bb_info *bb);
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void halbb_antdiv_decision_state(struct bb_info *bb);
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void halbb_antdiv_1ss_decision_state(struct bb_info *bb);
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void halbb_evm_based_antdiv(struct bb_info *bb);
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void halbb_antenna_diversity(struct bb_info *bb);
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void halbb_antdiv_phy_sts(struct bb_info *bb, u32 physts_bitmap,
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struct physts_rxd *desc);
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void halbb_antdiv_dbg(struct bb_info *bb, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void halbb_set_antdiv_pause_val(struct bb_info *bb, u32 *val_buf, u8 val_len);
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#endif
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