/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef _HALBB_CR_INFO_8852B_H_
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#define _HALBB_CR_INFO_8852B_H_
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#define DIS_UPD_5MHZ_SYNC_EN_C 0x0000
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#define DIS_UPD_5MHZ_SYNC_EN_C_M 0x1
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#define UPD_5MHZ_CNT_EN_C 0x0000
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#define UPD_5MHZ_CNT_EN_C_M 0x2
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#define CLK_640M_EN_C 0x0000
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#define CLK_640M_EN_C_M 0x4
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#define RFC_CK_PHASE_SEL_C 0x0000
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#define RFC_CK_PHASE_SEL_C_M 0x8
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#define RFC_CKEN_C 0x0000
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#define RFC_CKEN_C_M 0x10
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#define DFS_PATH1_EN_C 0x0000
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#define DFS_PATH1_EN_C_M 0x80
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#define UPD_5MHZ_PHASE_SEL_P0_C 0x0000
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#define UPD_5MHZ_PHASE_SEL_P0_C_M 0x7F00
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#define UPD_5MHZ_PHASE_SEL_P0_EN_C 0x0000
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#define UPD_5MHZ_PHASE_SEL_P0_EN_C_M 0x8000
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#define UPD_5MHZ_PHASE_SEL_P1_C 0x0000
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#define UPD_5MHZ_PHASE_SEL_P1_C_M 0x7F0000
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#define UPD_5MHZ_PHASE_SEL_P1_EN_C 0x0000
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#define UPD_5MHZ_PHASE_SEL_P1_EN_C_M 0x800000
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#define CLK_640M_P0_EN_C 0x0000
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#define CLK_640M_P0_EN_C_M 0x1000000
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#define CLK_640M_P1_EN_C 0x0000
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#define CLK_640M_P1_EN_C_M 0x2000000
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#define UPD_TOP_CNT_P0_EN_C 0x0000
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#define UPD_TOP_CNT_P0_EN_C_M 0x4000000
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#define UPD_TOP_CNT_P1_EN_C 0x0000
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#define UPD_TOP_CNT_P1_EN_C_M 0x8000000
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#define P0_SMALL_BW_EN_C 0x0000
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#define P0_SMALL_BW_EN_C_M 0x10000000
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#define P1_SMALL_BW_EN_C 0x0000
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#define P1_SMALL_BW_EN_C_M 0x20000000
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#define EN_UPD_5MHZ_INV_C 0x0000
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#define EN_UPD_5MHZ_INV_C_M 0x40000000
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#define DFS_EN_C 0x0000
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#define DFS_EN_C_M 0x80000000
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#define UPD_TD_PHASE_SEL_P0_C 0x0004
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#define UPD_TD_PHASE_SEL_P0_C_M 0x1F
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#define UPD_TD_PHASE_SEL_P0_EN_C 0x0004
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#define UPD_TD_PHASE_SEL_P0_EN_C_M 0x80
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#define UPD_TD_PHASE_SEL_P1_C 0x0004
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#define UPD_TD_PHASE_SEL_P1_C_M 0x1F00
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#define UPD_TD_PHASE_SEL_P1_EN_C 0x0004
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#define UPD_TD_PHASE_SEL_P1_EN_C_M 0x8000
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#define UPD_IN_PHASE_SEL_P0_C 0x0004
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#define UPD_IN_PHASE_SEL_P0_C_M 0x1F0000
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#define UPD_IN_PHASE_SEL_P0_EN_C 0x0004
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#define UPD_IN_PHASE_SEL_P0_EN_C_M 0x800000
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#define UPD_IN_PHASE_SEL_P1_C 0x0004
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#define UPD_IN_PHASE_SEL_P1_C_M 0x1F000000
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#define UPD_IN_PHASE_SEL_P1_EN_C 0x0004
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#define UPD_IN_PHASE_SEL_P1_EN_C_M 0x80000000
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#define UPD_OUT_PHASE_SEL_P0_C 0x0008
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#define UPD_OUT_PHASE_SEL_P0_C_M 0x1F
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#define UPD_OUT_PHASE_SEL_P0_EN_C 0x0008
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#define UPD_OUT_PHASE_SEL_P0_EN_C_M 0x80
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#define UPD_OUT_PHASE_SEL_P1_C 0x0008
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#define UPD_OUT_PHASE_SEL_P1_C_M 0x1F00
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#define UPD_OUT_PHASE_SEL_P1_EN_C 0x0008
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#define UPD_OUT_PHASE_SEL_P1_EN_C_M 0x8000
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#define UPD_MCU_PHASE_SEL_P0_C 0x0008
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#define UPD_MCU_PHASE_SEL_P0_C_M 0x1F0000
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#define UPD_MCU_PHASE_SEL_P0_EN_C 0x0008
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#define UPD_MCU_PHASE_SEL_P0_EN_C_M 0x800000
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#define UPD_MCU_PHASE_SEL_P1_C 0x0008
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#define UPD_MCU_PHASE_SEL_P1_C_M 0x1F000000
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#define UPD_MCU_PHASE_SEL_P1_EN_C 0x0008
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#define UPD_MCU_PHASE_SEL_P1_EN_C_M 0x80000000
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#define RSTB_WATCH_DOG_P0_EN_C 0x000C
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#define RSTB_WATCH_DOG_P0_EN_C_M 0x1
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#define RSTB_WATCH_DOG_P1_EN_C 0x000C
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#define RSTB_WATCH_DOG_P1_EN_C_M 0x2
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#define MAC_RST_P0_EN_C 0x000C
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#define MAC_RST_P0_EN_C_M 0x4
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#define MAC_RST_P1_EN_C 0x000C
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#define MAC_RST_P1_EN_C_M 0x8
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#define WMAC_RST_P0_EN_C 0x000C
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#define WMAC_RST_P0_EN_C_M 0x10
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#define WMAC_RST_P1_EN_C 0x000C
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#define WMAC_RST_P1_EN_C_M 0x20
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#define P0_PATH_EN_C 0x0010
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#define P0_PATH_EN_C_M 0xF
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#define P1_PATH_EN_C 0x0010
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#define P1_PATH_EN_C_M 0xF0
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#define DBG_CKEN_C 0x0010
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#define DBG_CKEN_C_M 0x100
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#define RX_CKEN_CCK_P0_C 0x0010
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#define RX_CKEN_CCK_P0_C_M 0x200
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#define RX_CKEN_CCK_P1_C 0x0010
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#define RX_CKEN_CCK_P1_C_M 0x400
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#define TX_CKEN_CCK_P0_C 0x0010
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#define TX_CKEN_CCK_P0_C_M 0x800
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#define TX_CKEN_CCK_P1_C 0x0010
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#define TX_CKEN_CCK_P1_C_M 0x1000
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#define RX_TD_CKEN_OFDM_P0_C 0x0010
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#define RX_TD_CKEN_OFDM_P0_C_M 0x2000
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#define RX_TD_CKEN_OFDM_P1_C 0x0010
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#define RX_TD_CKEN_OFDM_P1_C_M 0x4000
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#define TX_TD_CKEN_OFDM_P0_C 0x0010
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#define TX_TD_CKEN_OFDM_P0_C_M 0x8000
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#define TX_TD_CKEN_OFDM_P1_C 0x0010
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#define TX_TD_CKEN_OFDM_P1_C_M 0x10000
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#define FORCE_GNT_WL_ON_C 0x0010
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#define FORCE_GNT_WL_ON_C_M 0x20000
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#define FORCE_GNT_WL_VAL_C 0x0010
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#define FORCE_GNT_WL_VAL_C_M 0x40000
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#define LA_CKEN_C 0x0014
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#define LA_CKEN_C_M 0x1
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#define PSD_CKEN_C 0x0014
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#define PSD_CKEN_C_M 0x2
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#define CCX_CKEN_C 0x0014
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#define CCX_CKEN_C_M 0x4
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#define IFS_CKEN_C 0x0014
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#define IFS_CKEN_C_M 0x8
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#define DFS_CKEN_C 0x0014
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#define DFS_CKEN_C_M 0x10
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#define FTM_CKEN_P0_C 0x0014
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#define FTM_CKEN_P0_C_M 0x20
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#define FTM_CKEN_P1_C 0x0014
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#define FTM_CKEN_P1_C_M 0x40
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#define TX_IN_CKEN_P0_C 0x0014
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#define TX_IN_CKEN_P0_C_M 0x80
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#define TX_IN_CKEN_P1_C 0x0014
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#define TX_IN_CKEN_P1_C_M 0x100
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#define BF_CKEN_P0_C 0x0014
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#define BF_CKEN_P0_C_M 0x200
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#define BF_CKEN_P1_C 0x0014
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#define BF_CKEN_P1_C_M 0x400
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#define SW_SI_CKEN_C 0x0014
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#define SW_SI_CKEN_C_M 0x800
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#define SW_SI_CK_PHASE_SEL_C 0x0014
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#define SW_SI_CK_PHASE_SEL_C_M 0x1000
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#define FTM_CKEN_C 0x0014
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#define FTM_CKEN_C_M 0x2000
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#define SNDCCA_S80_TIE1_C 0x0014
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#define SNDCCA_S80_TIE1_C_M 0x80000000
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#define PAGE00_1C_DUMMY_C 0x001C
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#define PAGE00_1C_DUMMY_C_M 0xFFFFFFFC
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#define RSTN_ADC_FIFO_PATH0_C 0x0020
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#define RSTN_ADC_FIFO_PATH0_C_M 0xFFFF
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#define PAGE00_20_RSV_C 0x0020
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#define PAGE00_20_RSV_C_M 0xFFFF0000
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#define RSTN_ADC_FIFO_PATH1_C 0x0024
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#define RSTN_ADC_FIFO_PATH1_C_M 0xFFFF
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#define PAGE00_24_RSV_C 0x0024
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#define PAGE00_24_RSV_C_M 0xFFFF0000
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#define RSTN_ADC_FIFO_PATH2_C 0x0028
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#define RSTN_ADC_FIFO_PATH2_C_M 0xFFFF
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#define PAGE00_28_RSV_C 0x0028
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#define PAGE00_28_RSV_C_M 0xFFFF0000
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#define RSTN_ADC_FIFO_PATH3_C 0x002C
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#define RSTN_ADC_FIFO_PATH3_C_M 0xFFFF
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#define PAGE00_2C_RSV_C 0x002C
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#define PAGE00_2C_RSV_C_M 0xFFFF0000
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#define VERSION0_C 0x00F0
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#define VERSION0_C_M 0xFFFFFFFF
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#define VERSION1_C 0x00F4
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#define VERSION1_C_M 0xFFFFFFFF
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#define VERSION2_C 0x00F8
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#define VERSION2_C_M 0xFFFFFFFF
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#define VERSION3_C 0x00FC
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#define VERSION3_C_M 0xFFFFFFFF
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#define TOP1_ALL_C 0x0100
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#define TOP1_ALL_C_M 0xFFFFFFFF
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#define BIST_MOD_2_31_0__C 0x0110
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#define BIST_MOD_2_31_0__C_M 0xFFFFFFFF
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#define BIST_MOD_2_63_32__C 0x0114
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#define BIST_MOD_2_63_32__C_M 0xFFFFFFFF
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#define BIST_MOD_2_95_64__C 0x0118
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#define BIST_MOD_2_95_64__C_M 0xFFFFFFFF
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#define BIST_MOD_2_127_96__C 0x011C
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#define BIST_MOD_2_127_96__C_M 0xFFFFFFFF
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#define DRF_BIST_MOD_2_31_0__C 0x0120
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#define DRF_BIST_MOD_2_31_0__C_M 0xFFFFFFFF
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#define DRF_BIST_MOD_2_63_32__C 0x0124
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#define DRF_BIST_MOD_2_63_32__C_M 0xFFFFFFFF
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#define DRF_BIST_MOD_2_95_64__C 0x0128
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#define DRF_BIST_MOD_2_95_64__C_M 0xFFFFFFFF
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#define DRF_BIST_MOD_2_127_96__C 0x012C
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#define DRF_BIST_MOD_2_127_96__C_M 0xFFFFFFFF
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#define BIST_DVSE_2_31_0__C 0x0130
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#define BIST_DVSE_2_31_0__C_M 0xFFFFFFFF
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#define BIST_DVSE_2_63_32__C 0x0134
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#define BIST_DVSE_2_63_32__C_M 0xFFFFFFFF
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#define BIST_DVSE_2_95_64__C 0x0138
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#define BIST_DVSE_2_95_64__C_M 0xFFFFFFFF
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#define BIST_DVSE_2_127_96__C 0x013C
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#define BIST_DVSE_2_127_96__C_M 0xFFFFFFFF
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#define P0_BAND_CR_LATCH_DIS_C 0x0140
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#define P0_BAND_CR_LATCH_DIS_C_M 0x1
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#define P1_BAND_CR_LATCH_DIS_C 0x0140
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#define P1_BAND_CR_LATCH_DIS_C_M 0x10
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#define TEST1_2_31_0__C 0x0150
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#define TEST1_2_31_0__C_M 0xFFFFFFFF
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#define TEST1_2_63_32__C 0x0154
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#define TEST1_2_63_32__C_M 0xFFFFFFFF
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#define TEST1_2_95_64__C 0x0158
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#define TEST1_2_95_64__C_M 0xFFFFFFFF
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#define TEST1_2_127_96__C 0x015C
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#define TEST1_2_127_96__C_M 0xFFFFFFFF
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#define INTF_R_MAC_SEL_DMA_C 0x0200
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#define INTF_R_MAC_SEL_DMA_C_M 0x3
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#define INTF_R_PMAC_CH_INFO_ON_C 0x0200
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#define INTF_R_PMAC_CH_INFO_ON_C_M 0x10
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#define INTF_R_PMAC_CH_INFO_C 0x0200
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#define INTF_R_PMAC_CH_INFO_C_M 0x100
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#define INTF_R_INTF_RPT_SEL_P1_C 0x0200
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#define INTF_R_INTF_RPT_SEL_P1_C_M 0x1000
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#define INTF_R_CH_INFO_EN_P0_C 0x025C
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#define INTF_R_CH_INFO_EN_P0_C_M 0x1
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#define INTF_R_CH_INFO_EN_P1_C 0x025C
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#define INTF_R_CH_INFO_EN_P1_C_M 0x2
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#define INTF_R_CH_INFO_DATA_SRC_C 0x025C
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#define INTF_R_CH_INFO_DATA_SRC_C_M 0x4
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#define INTF_R_COMPRESSION_C 0x025C
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#define INTF_R_COMPRESSION_C_M 0x8
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#define INTF_R_GRP_NUM_NON_HE_C 0x025C
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#define INTF_R_GRP_NUM_NON_HE_C_M 0x30
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#define INTF_R_GRP_NUM_HE_C 0x025C
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#define INTF_R_GRP_NUM_HE_C_M 0xC0
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#define INTF_R_BLOCK_START_IDX_C 0x025C
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#define INTF_R_BLOCK_START_IDX_C_M 0xF00
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#define INTF_R_BLOCK_END_IDX_C 0x025C
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#define INTF_R_BLOCK_END_IDX_C_M 0xF000
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#define INTF_R_TEST_CH_INFO_EN_C 0x025C
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#define INTF_R_TEST_CH_INFO_EN_C_M 0x10000
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#define INTF_R_TEST_SEG_LEN_C 0x025C
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#define INTF_R_TEST_SEG_LEN_C_M 0x60000
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#define INTF_R_TEST_SEG_NUM_C 0x025C
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#define INTF_R_TEST_SEG_NUM_C_M 0x3F80000
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#define INTF_R_TEST_VLD_BIT_C 0x025C
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#define INTF_R_TEST_VLD_BIT_C_M 0x4000000
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#define INTF_R_TEST_DFS_EN_C 0x025C
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#define INTF_R_TEST_DFS_EN_C_M 0x8000000
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#define INTF_R_TEST_DFS_PERIOD_C 0x025C
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#define INTF_R_TEST_DFS_PERIOD_C_M 0xF0000000
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#define INTF_R_ELE_BITMAP_C 0x0260
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#define INTF_R_ELE_BITMAP_C_M 0xFFFFFFFF
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#define INTF_R_TEST_DFS_START_DATA_31_0__C 0x0264
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#define INTF_R_TEST_DFS_START_DATA_31_0__C_M 0xFFFFFFFF
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#define INTF_R_TEST_DFS_START_DATA_63_32__C 0x0268
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#define INTF_R_TEST_DFS_START_DATA_63_32__C_M 0xFFFFFFFF
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#define INTF_R_TEST_CH_INFO_START_DATA_31_0__C 0x026C
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#define INTF_R_TEST_CH_INFO_START_DATA_31_0__C_M 0xFFFFFFFF
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#define INTF_R_TEST_CH_INFO_START_DATA_63_32__C 0x0270
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#define INTF_R_TEST_CH_INFO_START_DATA_63_32__C_M 0xFFFFFFFF
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#define INTF_R_CH20_WITH_DATA_BIT_FORCE_VAL_C 0x0274
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#define INTF_R_CH20_WITH_DATA_BIT_FORCE_VAL_C_M 0xFF
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#define INTF_R_CH20_WITH_DATA_BIT_FORCE_C 0x0274
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#define INTF_R_CH20_WITH_DATA_BIT_FORCE_C_M 0x100
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#define INTF_R_CH20_WITH_DATA_BIT_INV_C 0x0274
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#define INTF_R_CH20_WITH_DATA_BIT_INV_C_M 0x200
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#define INTF_R_CH20_WITH_DATA_BIT_REV_C 0x0274
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#define INTF_R_CH20_WITH_DATA_BIT_REV_C_M 0x400
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#define ANAPAR_PW_0_C 0x0300
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#define ANAPAR_PW_0_C_M 0xFF
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#define ANAPAR_PW_1_C 0x0300
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#define ANAPAR_PW_1_C_M 0xFF00
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#define ANAPAR_PW_2_C 0x0300
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#define ANAPAR_PW_2_C_M 0xFF0000
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#define ANAPAR_PW_3_C 0x0300
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#define ANAPAR_PW_3_C_M 0xFF000000
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#define ANAPAR_PW_4_C 0x0304
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#define ANAPAR_PW_4_C_M 0xFF
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#define ANAPAR_PW_5_C 0x0304
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#define ANAPAR_PW_5_C_M 0xFF00
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#define ANAPAR_PW_6_C 0x0304
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#define ANAPAR_PW_6_C_M 0xFF0000
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#define ANAPAR_PW_7_C 0x0304
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#define ANAPAR_PW_7_C_M 0xFF000000
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#define ANAPAR_PW_8_C 0x0308
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#define ANAPAR_PW_8_C_M 0xFF
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#define ANAPAR_PW_9_C 0x0308
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#define ANAPAR_PW_9_C_M 0xFF00
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#define ANAPAR_PW_10_C 0x0308
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#define ANAPAR_PW_10_C_M 0xFF0000
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#define ANAPAR_PW_11_C 0x0308
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#define ANAPAR_PW_11_C_M 0xFF000000
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#define ANAPAR_PW_12_C 0x030C
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#define ANAPAR_PW_12_C_M 0xFF
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#define ANAPAR_PW_13_C 0x030C
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#define ANAPAR_PW_13_C_M 0xFF00
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#define ANAPAR_PW_14_C 0x030C
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#define ANAPAR_PW_14_C_M 0xFF0000
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#define ANAPAR_PW_15_C 0x030C
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#define ANAPAR_PW_15_C_M 0xFF000000
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#define ANAPAR_0_C 0x0310
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#define ANAPAR_0_C_M 0xFFFF
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#define ANAPAR_1_C 0x0310
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#define ANAPAR_1_C_M 0xFFFF0000
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#define ANAPAR_2_C 0x0314
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#define ANAPAR_2_C_M 0xFFFF
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#define ANAPAR_3_C 0x0314
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#define ANAPAR_3_C_M 0xFFFF0000
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#define ANAPAR_4_C 0x0318
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#define ANAPAR_4_C_M 0xFFFF
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#define ANAPAR_5_C 0x0318
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#define ANAPAR_5_C_M 0xFFFF0000
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#define ANAPAR_6_C 0x031C
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#define ANAPAR_6_C_M 0xFFFF
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#define ANAPAR_7_C 0x031C
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#define ANAPAR_7_C_M 0xFFFF0000
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#define ANAPAR_8_C 0x0320
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#define ANAPAR_8_C_M 0xFFFF
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#define ANAPAR_9_C 0x0320
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#define ANAPAR_9_C_M 0xFFFF0000
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#define ANAPAR_10_C 0x0324
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#define ANAPAR_10_C_M 0xFFFF
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#define ANAPAR_11_C 0x0324
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#define ANAPAR_11_C_M 0xFFFF0000
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#define ANAPAR_12_C 0x0328
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#define ANAPAR_12_C_M 0xFFFF
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#define ANAPAR_13_C 0x0328
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#define ANAPAR_13_C_M 0xFFFF0000
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#define ANAPAR_14_C 0x032C
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#define ANAPAR_14_C_M 0xFFFF
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#define ANAPAR_15_C 0x032C
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#define ANAPAR_15_C_M 0xFFFF0000
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#define RFE_E_C 0x0334
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#define RFE_E_C_M 0xFFFFFFFF
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#define RFE_O_SEL_DBG_C 0x0338
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#define RFE_O_SEL_DBG_C_M 0xFFFFFFFF
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#define RFE_SEL_PATH_31_0__C 0x033C
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#define RFE_SEL_PATH_31_0__C_M 0xFFFFFFFF
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#define RFE_SEL_PATH_63_32__C 0x0340
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#define RFE_SEL_PATH_63_32__C_M 0xFFFFFFFF
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#define RFE_SEL_DBG_MAC1_C 0x0344
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#define RFE_SEL_DBG_MAC1_C_M 0xFFFFFFFF
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#define DLYSEL0_PINMUX_I_C 0x034C
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#define DLYSEL0_PINMUX_I_C_M 0xFFFF
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#define DLYSEL1_PINMUX_I_C 0x034C
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#define DLYSEL1_PINMUX_I_C_M 0xFFFF0000
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#define DLYSEL0_PINMUX_O_C 0x0350
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#define DLYSEL0_PINMUX_O_C_M 0xFFFF
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#define DLYSEL1_PINMUX_O_C 0x0350
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#define DLYSEL1_PINMUX_O_C_M 0xFFFF0000
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#define DBG_GPIO_SEL_P0_C 0x0354
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#define DBG_GPIO_SEL_P0_C_M 0xF
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#define DBG_GPIO_SEL_P1_C 0x0354
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#define DBG_GPIO_SEL_P1_C_M 0xF0
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#define DBG_GPIO_MAC_SEL_C 0x0354
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#define DBG_GPIO_MAC_SEL_C_M 0xFF00
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#define TEST_PIN_OE_C 0x0354
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#define TEST_PIN_OE_C_M 0xFFFF0000
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#define PINMUX_SEL_C 0x0358
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#define PINMUX_SEL_C_M 0x1F
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#define AFE_DEB_INFILTER_MSB_LSB_C 0x0358
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#define AFE_DEB_INFILTER_MSB_LSB_C_M 0x20
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#define AFE_DEB_PREFILTER_MSB_LSB_C 0x0358
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#define AFE_DEB_PREFILTER_MSB_LSB_C_M 0x40
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#define MBIST_PINMUX_SEL_C 0x0358
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#define MBIST_PINMUX_SEL_C_M 0x1F00
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#define AFE_UPD80_PHASE_C 0x0358
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#define AFE_UPD80_PHASE_C_M 0x2000
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#define AFE_DBG_SRAM_FREQ_C 0x0358
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#define AFE_DBG_SRAM_FREQ_C_M 0xC000
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#define LO_SEL_80P80_C 0x035C
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#define LO_SEL_80P80_C_M 0x3
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#define LO_SEL_2X2_C 0x035C
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#define LO_SEL_2X2_C_M 0xC
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#define LO_SEL_1X1_C 0x035C
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#define LO_SEL_1X1_C_M 0x30
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#define LO_SEL_DBCC_C 0x035C
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#define LO_SEL_DBCC_C_M 0xC0
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#define LO_SEL_HWEN_C 0x035C
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#define LO_SEL_HWEN_C_M 0x100
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#define LO_SEL_SW_C 0x035C
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#define LO_SEL_SW_C_M 0xC00
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#define LO_SEL_CH20_INV_C 0x035C
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#define LO_SEL_CH20_INV_C_M 0x1000
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#define DIS_CCK_CCA_TO_RFC_C 0x035C
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#define DIS_CCK_CCA_TO_RFC_C_M 0x10000
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#define DIS_OFDM_CCA_TO_RFC_C 0x035C
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#define DIS_OFDM_CCA_TO_RFC_C_M 0x20000
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#define RSTB_AFC_3WIRE_C 0x0360
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#define RSTB_AFC_3WIRE_C_M 0x1
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#define AFC_SI_WADDR_C 0x0360
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#define AFC_SI_WADDR_C_M 0x3FF0
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#define RST_AFC_SI_CONFLICT_CNT_C 0x0360
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#define RST_AFC_SI_CONFLICT_CNT_C_M 0x80000000
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#define AFC_SI_RADDR_C 0x0364
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#define AFC_SI_RADDR_C_M 0x3FF
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#define AFC_SI_WDATA_C 0x0368
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#define AFC_SI_WDATA_C_M 0xFFFFFFFF
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#define HW_SI_CLK_START_PHASE_C 0x036C
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#define HW_SI_CLK_START_PHASE_C_M 0x1
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#define RSTB_HW_SI_CLK_C 0x036C
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#define RSTB_HW_SI_CLK_C_M 0x2
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#define HW_SI_HALF_SPEED_EN_C 0x036C
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#define HW_SI_HALF_SPEED_EN_C_M 0x10
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#define SW_SI_HALF_SPEED_EN_C 0x036C
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#define SW_SI_HALF_SPEED_EN_C_M 0x20
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#define SW_SI_DATA_C 0x0370
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#define SW_SI_DATA_C_M 0xFFFFFFFF
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#define SW_SI_BIT_MASK_C 0x0374
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#define SW_SI_BIT_MASK_C_M 0xFFFFF
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#define RSTB_SW_SI_C 0x0374
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#define RSTB_SW_SI_C_M 0x100000
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#define SW_SI_CLK_START_PHASE_C 0x0374
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#define SW_SI_CLK_START_PHASE_C_M 0x200000
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#define SW_SI_DATA_E_INV_C 0x0374
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#define SW_SI_DATA_E_INV_C_M 0x400000
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#define SW_SI_ZERO_PADDING_EN_C 0x0374
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#define SW_SI_ZERO_PADDING_EN_C_M 0x800000
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#define SW_SI_ZERO_PADDING_NUM_C 0x0374
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#define SW_SI_ZERO_PADDING_NUM_C_M 0x3F000000
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#define RST_SW_SI_CONFLICT_CNT_C 0x0374
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#define RST_SW_SI_CONFLICT_CNT_C_M 0x80000000
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#define SW_SI_READ_ADDR_C 0x0378
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#define SW_SI_READ_ADDR_C_M 0x7FF
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#define SW_SI_WAIT_TIMING_C 0x037C
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#define SW_SI_WAIT_TIMING_C_M 0xF
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#define SW_SI_READ_EDGE_OPT_C 0x037C
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#define SW_SI_READ_EDGE_OPT_C_M 0x30
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#define SW_SI_DIS_W_TRIG_C 0x037C
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#define SW_SI_DIS_W_TRIG_C_M 0x1000
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#define SW_SI_DIS_R_TRIG_C 0x037C
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#define SW_SI_DIS_R_TRIG_C_M 0x2000
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#define HWSI_KEEPER_RSTB_C 0x0380
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#define HWSI_KEEPER_RSTB_C_M 0x1
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#define SWSI_KEEPER_RSTB_C 0x0380
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#define SWSI_KEEPER_RSTB_C_M 0x2
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#define HWSI_KEEPER_SEL_PATH_C 0x0380
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#define HWSI_KEEPER_SEL_PATH_C_M 0x30
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#define CCA_MASK_EN_C 0x0600
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#define CCA_MASK_EN_C_M 0xFFFFFFFF
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#define TIME_CCA_MASK_RX_I_C 0x0604
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#define TIME_CCA_MASK_RX_I_C_M 0x3F
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#define TIME_CCA_MASK_BRK_I_C 0x0604
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#define TIME_CCA_MASK_BRK_I_C_M 0x3F00
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#define TIME_CCA_MASK_BRK_CCK_I_C 0x0604
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#define TIME_CCA_MASK_BRK_CCK_I_C_M 0x3F0000
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#define TIME_CCA_MASK_RIFS_I_C 0x0604
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#define TIME_CCA_MASK_RIFS_I_C_M 0x3F000000
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#define TIME_CCA_MASK_HT_I_C 0x0608
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#define TIME_CCA_MASK_HT_I_C_M 0x3F
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#define TIME_CCA_MASK_T2R_I_C 0x0608
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#define TIME_CCA_MASK_T2R_I_C_M 0x3F00
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#define TIME_CCA_MASK_T2R_TB_I_C 0x0608
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#define TIME_CCA_MASK_T2R_TB_I_C_M 0x3F0000
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#define TIME_CCA_MASK_T2R_TXTP_I_C 0x0608
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#define TIME_CCA_MASK_T2R_TXTP_I_C_M 0x3F000000
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#define TIME_CCA_MASK_RX_NDP_I_C 0x060C
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#define TIME_CCA_MASK_RX_NDP_I_C_M 0x3F
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#define CCA_MASK_T2R_TXTP_I_C 0x060C
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#define CCA_MASK_T2R_TXTP_I_C_M 0x3F0000
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#define CCA_MASK_T2R_EN_I_C 0x060C
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#define CCA_MASK_T2R_EN_I_C_M 0x400000
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#define CCA_MASK_T2R_TB_EN_I_C 0x060C
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#define CCA_MASK_T2R_TB_EN_I_C_M 0x800000
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#define CCA_MASK_T2R_MURTS_EN_I_C 0x060C
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#define CCA_MASK_T2R_MURTS_EN_I_C_M 0x1000000
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#define CCA_MASK_T2R_TXTP_EN_I_C 0x060C
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#define CCA_MASK_T2R_TXTP_EN_I_C_M 0x2000000
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#define CCA_MASK_BRK_EN_I_C 0x060C
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#define CCA_MASK_BRK_EN_I_C_M 0x4000000
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#define CCA_MASK_BRK_CCK_EN_I_C 0x060C
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#define CCA_MASK_BRK_CCK_EN_I_C_M 0x8000000
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#define CCA_MASK_SEARCH_FAILED_EN_I_C 0x060C
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#define CCA_MASK_SEARCH_FAILED_EN_I_C_M 0x10000000
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#define CCA_MASK_RIFS_EN_I_C 0x060C
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#define CCA_MASK_RIFS_EN_I_C_M 0x20000000
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#define CCA_MASK_HT_EN_I_C 0x060C
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#define CCA_MASK_HT_EN_I_C_M 0x40000000
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#define R1B_CCA_MASK_EN_C 0x0610
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#define R1B_CCA_MASK_EN_C_M 0xFFFFFFFF
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#define TIME_B_CCA_MASK_RX_I_C 0x0614
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#define TIME_B_CCA_MASK_RX_I_C_M 0x3F
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#define TIME_B_CCA_MASK_BRK_I_C 0x0614
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#define TIME_B_CCA_MASK_BRK_I_C_M 0x3F00
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#define TIME_B_CCA_MASK_BRK_CCK_I_C 0x0614
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#define TIME_B_CCA_MASK_BRK_CCK_I_C_M 0x3F0000
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#define TIME_B_CCA_MASK_RIFS_I_C 0x0614
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#define TIME_B_CCA_MASK_RIFS_I_C_M 0x3F000000
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#define TIME_B_CCA_MASK_HT_I_C 0x0618
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#define TIME_B_CCA_MASK_HT_I_C_M 0x3F
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#define TIME_B_CCA_MASK_T2R_I_C 0x0618
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#define TIME_B_CCA_MASK_T2R_I_C_M 0x3F00
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#define TIME_B_CCA_MASK_T2R_TB_I_C 0x0618
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#define TIME_B_CCA_MASK_T2R_TB_I_C_M 0x3F0000
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#define TIME_B_CCA_MASK_T2R_TXTP_I_C 0x0618
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#define TIME_B_CCA_MASK_T2R_TXTP_I_C_M 0x3F000000
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#define TIME_B_CCA_MASK_RX_NDP_I_C 0x061C
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#define TIME_B_CCA_MASK_RX_NDP_I_C_M 0x3F
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#define R1B_CCA_MASK_T2R_TXTP_I_C 0x061C
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#define R1B_CCA_MASK_T2R_TXTP_I_C_M 0x3F0000
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#define R1B_CCA_MASK_T2R_EN_I_C 0x061C
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#define R1B_CCA_MASK_T2R_EN_I_C_M 0x400000
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#define R1B_CCA_MASK_T2R_TB_EN_I_C 0x061C
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#define R1B_CCA_MASK_T2R_TB_EN_I_C_M 0x800000
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#define R1B_CCA_MASK_T2R_MURTS_EN_I_C 0x061C
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#define R1B_CCA_MASK_T2R_MURTS_EN_I_C_M 0x1000000
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#define R1B_CCA_MASK_T2R_TXTP_EN_I_C 0x061C
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#define R1B_CCA_MASK_T2R_TXTP_EN_I_C_M 0x2000000
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#define R1B_CCA_MASK_BRK_EN_I_C 0x061C
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#define R1B_CCA_MASK_BRK_EN_I_C_M 0x4000000
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#define R1B_CCA_MASK_BRK_CCK_EN_I_C 0x061C
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#define R1B_CCA_MASK_BRK_CCK_EN_I_C_M 0x8000000
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#define R1B_CCA_MASK_SEARCH_FAILED_EN_I_C 0x061C
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#define R1B_CCA_MASK_SEARCH_FAILED_EN_I_C_M 0x10000000
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#define R1B_CCA_MASK_RIFS_EN_I_C 0x061C
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#define R1B_CCA_MASK_RIFS_EN_I_C_M 0x20000000
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#define R1B_CCA_MASK_HT_EN_I_C 0x061C
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#define R1B_CCA_MASK_HT_EN_I_C_M 0x40000000
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#define EN_RXHP_H2L_C 0x0620
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#define EN_RXHP_H2L_C_M 0x1
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#define EN_KEEP_AGC_FOR_RIFS_C 0x0620
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#define EN_KEEP_AGC_FOR_RIFS_C_M 0x2
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#define PWSAV_RIFS_C 0x0620
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#define PWSAV_RIFS_C_M 0x4
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#define EN_TB_FAIL_C 0x0620
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#define EN_TB_FAIL_C_M 0x8
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#define RFON_END_CCK_C 0x0620
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#define RFON_END_CCK_C_M 0xF0
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#define RFON_END_OFDM_C 0x0620
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#define RFON_END_OFDM_C_M 0x3F00
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#define RIFS_END_C 0x0620
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#define RIFS_END_C_M 0x3F0000
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#define TIME_TX_TO_RX_END_C 0x0624
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#define TIME_TX_TO_RX_END_C_M 0x3F
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#define TIME_RXHP_H2L_C 0x0624
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#define TIME_RXHP_H2L_C_M 0x3F00
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#define TIME_RX_NDP_END_C 0x0624
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#define TIME_RX_NDP_END_C_M 0x3F0000
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#define TIME_RX_CCK_END_C 0x0624
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#define TIME_RX_CCK_END_C_M 0x3F000000
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#define TIME_RX_OFDM_END_C 0x0628
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#define TIME_RX_OFDM_END_C_M 0x3F
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#define TIME_RX_BRK_END_C 0x0628
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#define TIME_RX_BRK_END_C_M 0x3F00
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#define TIME_RX2RX_HE_TB_END_C 0x0628
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#define TIME_RX2RX_HE_TB_END_C_M 0x3F0000
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#define TIME_HE_PE04U_I_C 0x062C
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#define TIME_HE_PE04U_I_C_M 0x7FF
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#define TIME_HE_PE08U_I_C 0x062C
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#define TIME_HE_PE08U_I_C_M 0x7FF0000
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#define TIME_HE_PE12U_I_C 0x0630
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#define TIME_HE_PE12U_I_C_M 0x7FF
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#define TIME_HE_PE16U_I_C 0x0630
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#define TIME_HE_PE16U_I_C_M 0x7FF0000
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#define RX_TD_CKEN_C 0x0634
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#define RX_TD_CKEN_C_M 0xFFFF
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#define RX_T2F_CKEN_C 0x0634
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#define RX_T2F_CKEN_C_M 0xFFFF0000
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#define RX_IN_CKEN_C 0x0638
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#define RX_IN_CKEN_C_M 0x1
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#define RX_OUT_CKEN_C 0x0638
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#define RX_OUT_CKEN_C_M 0x2
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#define TX_CKEN_CCK_C 0x0638
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#define TX_CKEN_CCK_C_M 0x4
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#define TX_CKEN_OFDM_C 0x0638
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#define TX_CKEN_OFDM_C_M 0x8
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#define TX_OFDM_DLY_C 0x063C
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#define TX_OFDM_DLY_C_M 0xF
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#define TX_CCK_DLY_C 0x063C
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#define TX_CCK_DLY_C_M 0xF0
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#define TX_OFDM_RF_DLY_160_C 0x0640
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#define TX_OFDM_RF_DLY_160_C_M 0x7F
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#define TX_OFDM_RF_DLY_80_C 0x0640
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#define TX_OFDM_RF_DLY_80_C_M 0x7F00
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#define TX_OFDM_RF_DLY_40_C 0x0640
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#define TX_OFDM_RF_DLY_40_C_M 0x7F0000
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#define TX_OFDM_RF_DLY_20_C 0x0640
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#define TX_OFDM_RF_DLY_20_C_M 0x7F000000
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#define TX_OFDM_PATH_DLY_160_C 0x0644
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#define TX_OFDM_PATH_DLY_160_C_M 0x7F
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#define TX_OFDM_PATH_DLY_80_C 0x0644
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#define TX_OFDM_PATH_DLY_80_C_M 0x7F00
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#define TX_OFDM_PATH_DLY_40_C 0x0644
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#define TX_OFDM_PATH_DLY_40_C_M 0x7F0000
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#define TX_OFDM_PATH_DLY_20_C 0x0644
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#define TX_OFDM_PATH_DLY_20_C_M 0x7F000000
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#define TX_CCK_RF_DLY_160_C 0x0648
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#define TX_CCK_RF_DLY_160_C_M 0x7F
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#define TX_CCK_RF_DLY_80_C 0x0648
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#define TX_CCK_RF_DLY_80_C_M 0x7F00
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#define TX_CCK_RF_DLY_40_C 0x0648
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#define TX_CCK_RF_DLY_40_C_M 0x7F0000
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#define TX_CCK_RF_DLY_20_C 0x0648
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#define TX_CCK_RF_DLY_20_C_M 0x7F000000
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#define TX_CCK_PATH_DLY_160_C 0x064C
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#define TX_CCK_PATH_DLY_160_C_M 0x7F
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#define TX_CCK_PATH_DLY_80_C 0x064C
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#define TX_CCK_PATH_DLY_80_C_M 0x7F00
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#define TX_CCK_PATH_DLY_40_C 0x064C
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#define TX_CCK_PATH_DLY_40_C_M 0x7F0000
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#define TX_CCK_PATH_DLY_20_C 0x064C
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#define TX_CCK_PATH_DLY_20_C_M 0x7F000000
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#define AFE_DATA_MASK_EN_C 0x0650
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#define AFE_DATA_MASK_EN_C_M 0xFFFFFFFF
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#define AFE_DATA_MASK_TH_SEL_C 0x0654
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#define AFE_DATA_MASK_TH_SEL_C_M 0xFFFFFFFF
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#define AFE_DATA_MASK_TH0_C 0x0658
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#define AFE_DATA_MASK_TH0_C_M 0xFF
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#define AFE_DATA_MASK_TH1_C 0x0658
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#define AFE_DATA_MASK_TH1_C_M 0xFF00
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#define AFE_DATA_MASK_TH2_C 0x0658
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#define AFE_DATA_MASK_TH2_C_M 0xFF0000
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#define AFE_DATA_MASK_TH3_C 0x0658
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#define AFE_DATA_MASK_TH3_C_M 0xFF000000
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#define MONITOR_SEL0_C 0x065C
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#define MONITOR_SEL0_C_M 0xF
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#define MONITOR_SEL1_C 0x065C
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#define MONITOR_SEL1_C_M 0xF0
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#define MONITOR_KEEP_C 0x065C
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#define MONITOR_KEEP_C_M 0x80000000
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#define REDUCE_PEAK_PW_EN_C 0x0660
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#define REDUCE_PEAK_PW_EN_C_M 0x1
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#define STOP_CLK_C 0x0700
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#define STOP_CLK_C_M 0x1
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#define SYNC_UPD_5MHZ_C 0x0700
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#define SYNC_UPD_5MHZ_C_M 0x2
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#define SMALL_BW_C 0x0700
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#define SMALL_BW_C_M 0xC
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#define ENABLE_OFDM_C 0x0700
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#define ENABLE_OFDM_C_M 0x10
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#define ENABLE_CCK_C 0x0700
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#define ENABLE_CCK_C_M 0x20
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#define ENABKE_LPS_CCK_C 0x0700
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#define ENABKE_LPS_CCK_C_M 0x40
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#define ENABLE_LPS_OFDM_C 0x0700
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#define ENABLE_LPS_OFDM_C_M 0x80
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#define R55MHZ_PHASE_C 0x0700
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#define R55MHZ_PHASE_C_M 0x7F00
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#define DIS_CLK_SOURCE_C 0x0700
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#define DIS_CLK_SOURCE_C_M 0xFF0000
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#define UPD_CLK_ADC_FORCE_ON_C 0x0700
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#define UPD_CLK_ADC_FORCE_ON_C_M 0x1000000
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#define UPD_CLK_ADC_FORCE_VAL_C 0x0700
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#define UPD_CLK_ADC_FORCE_VAL_C_M 0x6000000
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#define TD_UPD_GEN_FORCE_ON_C 0x0700
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#define TD_UPD_GEN_FORCE_ON_C_M 0x8000000
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#define RSTN_EARLY_RELEASE_C 0x0700
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#define RSTN_EARLY_RELEASE_C_M 0xF0000000
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#define RSTB_ASYNC_UPDGEN_C 0x0704
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#define RSTB_ASYNC_UPDGEN_C_M 0x1
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#define RSTB_ASYNC_ALL_C 0x0704
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#define RSTB_ASYNC_ALL_C_M 0x2
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#define RSTB_ASYNC_RXTD_C 0x0704
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#define RSTB_ASYNC_RXTD_C_M 0x4
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#define RSTB_ASYNC_TXTD_C 0x0704
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#define RSTB_ASYNC_TXTD_C_M 0x8
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#define RSTB_ASYNC_RXFD_C 0x0704
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#define RSTB_ASYNC_RXFD_C_M 0x10
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#define RSTB_ASYNC_TXFD_C 0x0704
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#define RSTB_ASYNC_TXFD_C_M 0x20
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#define RSTB_ASYNC_TX_OUT_C 0x0704
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#define RSTB_ASYNC_TX_OUT_C_M 0x40
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#define RSTB_ASYNC_RX_OUT_C 0x0704
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#define RSTB_ASYNC_RX_OUT_C_M 0x80
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#define UPD_CLK_ADC_TX_C 0x0704
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#define UPD_CLK_ADC_TX_C_M 0x300
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#define FTM_LBK_RFTXEN_CTL_EN_C 0x0704
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#define FTM_LBK_RFTXEN_CTL_EN_C_M 0x400
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#define RFTXEN_START_DLY_50NS_EN_C 0x0704
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#define RFTXEN_START_DLY_50NS_EN_C_M 0x800
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#define RST_HIT_ON_TX_EN_C 0x0704
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#define RST_HIT_ON_TX_EN_C_M 0x1000
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#define RSTN_DAC_FIFO_C 0x0704
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#define RSTN_DAC_FIFO_C_M 0xFFFF0000
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#define EN_POP_PRD_RST_ADC_FIFO_I_C 0x0708
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#define EN_POP_PRD_RST_ADC_FIFO_I_C_M 0x1
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#define RSTB_ASYNC_DAC_C 0x070C
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#define RSTB_ASYNC_DAC_C_M 0xFFFFFFFF
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#define PERIOD_CNT_EN_C 0x0710
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#define PERIOD_CNT_EN_C_M 0x1
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#define PERIOD_CNT_RST_C 0x0710
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#define PERIOD_CNT_RST_C_M 0x2
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#define PERIOD_UNIT_SEL_S1_C 0x0710
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#define PERIOD_UNIT_SEL_S1_C_M 0x30
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#define PERIOD_UNIT_SEL_S2_C 0x0710
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#define PERIOD_UNIT_SEL_S2_C_M 0xC0
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#define PERIOD_UNIT_SEL_S3_C 0x0710
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#define PERIOD_UNIT_SEL_S3_C_M 0x300
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#define PERIOD_UNIT_SEL_S4_C 0x0710
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#define PERIOD_UNIT_SEL_S4_C_M 0xC00
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#define PERIOD_KEEP_COND_S1_C 0x0710
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#define PERIOD_KEEP_COND_S1_C_M 0x1000
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#define PERIOD_KEEP_COND_S2_C 0x0710
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#define PERIOD_KEEP_COND_S2_C_M 0x2000
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#define PERIOD_KEEP_COND_S3_C 0x0710
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#define PERIOD_KEEP_COND_S3_C_M 0x4000
|
#define PERIOD_KEEP_COND_S4_C 0x0710
|
#define PERIOD_KEEP_COND_S4_C_M 0x8000
|
#define RSTN_ADC_FIFO_C 0x0710
|
#define RSTN_ADC_FIFO_C_M 0xFFFF0000
|
#define IDX_EN_BY_MUX_ST_C 0x0714
|
#define IDX_EN_BY_MUX_ST_C_M 0x3F
|
#define EN_BY_MUX_ST_C 0x0714
|
#define EN_BY_MUX_ST_C_M 0x40
|
#define FILL_EN_BY_MUX_ST_C 0x0714
|
#define FILL_EN_BY_MUX_ST_C_M 0x80
|
#define VAL_EN_BY_MUX_ST_C 0x0714
|
#define VAL_EN_BY_MUX_ST_C_M 0xFF00
|
#define APPLY_MUX_ST_C 0x0714
|
#define APPLY_MUX_ST_C_M 0x10000
|
#define LBK_C 0x0714
|
#define LBK_C_M 0x20000
|
#define LBK_MODE_C 0x0714
|
#define LBK_MODE_C_M 0x40000
|
#define ST_CCA_BYPASS_C 0x0714
|
#define ST_CCA_BYPASS_C_M 0x80000
|
#define PMAC_MOD_C 0x0714
|
#define PMAC_MOD_C_M 0x100000
|
#define PMAC_C 0x0714
|
#define PMAC_C_M 0x200000
|
#define PMAC_CORX_C 0x0714
|
#define PMAC_CORX_C_M 0x400000
|
#define PMAC_TX_C 0x0714
|
#define PMAC_TX_C_M 0x800000
|
#define PERIOD_R2R_C 0x0714
|
#define PERIOD_R2R_C_M 0xFF000000
|
#define DLY_EN_BY_MUX_ST_C 0x0718
|
#define DLY_EN_BY_MUX_ST_C_M 0xFFFFFFFF
|
#define SYMB_NUM_PKT_FMT_C 0x071C
|
#define SYMB_NUM_PKT_FMT_C_M 0xFF
|
#define SAMPLE_NUM_PKT_FMT_C 0x071C
|
#define SAMPLE_NUM_PKT_FMT_C_M 0xFF00
|
#define SYMB_NUM_CCA_C 0x071C
|
#define SYMB_NUM_CCA_C_M 0xFF0000
|
#define SAMPLE_NUM_CCA_C 0x071C
|
#define SAMPLE_NUM_CCA_C_M 0xFF000000
|
#define DBG_FPGA_C 0x0720
|
#define DBG_FPGA_C_M 0xFFF
|
#define RSTB_FPGA_C 0x0720
|
#define RSTB_FPGA_C_M 0x1000
|
#define CBW_FPGA_C 0x0720
|
#define CBW_FPGA_C_M 0xE000
|
#define PRICH_FPGA_C 0x0720
|
#define PRICH_FPGA_C_M 0xF0000
|
#define PATH_EN_FPGA_C 0x0720
|
#define PATH_EN_FPGA_C_M 0xF00000
|
#define PATH_EN_1RCCA_FPGA_C 0x0720
|
#define PATH_EN_1RCCA_FPGA_C_M 0xF000000
|
#define INVERSE_ADC_SIGN_BIT_C 0x0720
|
#define INVERSE_ADC_SIGN_BIT_C_M 0x10000000
|
#define INVERSE_WB_ADC_SIGN_BIT_C 0x0720
|
#define INVERSE_WB_ADC_SIGN_BIT_C_M 0x20000000
|
#define CHANGE_PHASE_FPGA_ADC_C 0x0720
|
#define CHANGE_PHASE_FPGA_ADC_C_M 0x40000000
|
#define CHANGE_PHASE_FPGA_WB_ADC_C 0x0720
|
#define CHANGE_PHASE_FPGA_WB_ADC_C_M 0x80000000
|
#define RFTXEN_START_C 0x0724
|
#define RFTXEN_START_C_M 0xF
|
#define RFTXEN_END_C 0x0724
|
#define RFTXEN_END_C_M 0xF0
|
#define PAPE_START_C 0x0724
|
#define PAPE_START_C_M 0xF00
|
#define PAPE_END_C 0x0724
|
#define PAPE_END_C_M 0xF000
|
#define TRSW_START_C 0x0724
|
#define TRSW_START_C_M 0xF0000
|
#define TRSW_END_C 0x0724
|
#define TRSW_END_C_M 0xF00000
|
#define LNAOFF_START_C 0x0724
|
#define LNAOFF_START_C_M 0xF000000
|
#define LNAOFF_END_C 0x0724
|
#define LNAOFF_END_C_M 0xF0000000
|
#define TRSW_TX_EXTEND_C 0x0728
|
#define TRSW_TX_EXTEND_C_M 0xF
|
#define PMAC_GNT_BT_C 0x0728
|
#define PMAC_GNT_BT_C_M 0x10
|
#define GNT_BT_C 0x0728
|
#define GNT_BT_C_M 0x20
|
#define GNT_BT_TX_C 0x0728
|
#define GNT_BT_TX_C_M 0x40
|
#define GNT_WL_C 0x0728
|
#define GNT_WL_C_M 0x80
|
#define RFAFE_PWSAV_EN_C 0x0728
|
#define RFAFE_PWSAV_EN_C_M 0x100
|
#define RFAFE_PWSAV_SEL_SLEEP_C 0x0728
|
#define RFAFE_PWSAV_SEL_SLEEP_C_M 0x200
|
#define RSTB_STANDBY_C 0x0728
|
#define RSTB_STANDBY_C_M 0x400
|
#define CCAMASK_TXDIS_C 0x0728
|
#define CCAMASK_TXDIS_C_M 0x800
|
#define HW_ANTSW_DIS_BY_GNT_BT_C 0x0728
|
#define HW_ANTSW_DIS_BY_GNT_BT_C_M 0x1000
|
#define NOTRSW_BT_C 0x0728
|
#define NOTRSW_BT_C_M 0x2000
|
#define IGNORE_MAC_ID_C 0x0728
|
#define IGNORE_MAC_ID_C_M 0x4000
|
#define ANTSEL_WATCHDOG_EN_C 0x0728
|
#define ANTSEL_WATCHDOG_EN_C_M 0x8000
|
#define ANTSEL_WATCHDOG_OPT_C 0x0728
|
#define ANTSEL_WATCHDOG_OPT_C_M 0x30000
|
#define ANTSEL_WATCHDOG_TH_EXT_C 0x0728
|
#define ANTSEL_WATCHDOG_TH_EXT_C_M 0xC0000
|
#define ANTSEL_WATCHDOG_TH_C 0x0728
|
#define ANTSEL_WATCHDOG_TH_C_M 0x300000
|
#define MAC_ID_MATCH_C 0x0728
|
#define MAC_ID_MATCH_C_M 0x400000
|
#define LTE_RX_C 0x0728
|
#define LTE_RX_C_M 0x800000
|
#define CCK_HIGHPW_C 0x0728
|
#define CCK_HIGHPW_C_M 0x1000000
|
#define AAGC_BY_TABLE_C 0x0728
|
#define AAGC_BY_TABLE_C_M 0x2000000
|
#define EN_LNA_TRSW_C 0x0728
|
#define EN_LNA_TRSW_C_M 0x4000000
|
#define EN_ANTSEL_CCK_C 0x0728
|
#define EN_ANTSEL_CCK_C_M 0x8000000
|
#define IBADC_SHIFT_FPGA_C 0x0728
|
#define IBADC_SHIFT_FPGA_C_M 0x30000000
|
#define WBADC_SHIFT_FPGA_C 0x0728
|
#define WBADC_SHIFT_FPGA_C_M 0xC0000000
|
#define BT_TRXMODE_C 0x072C
|
#define BT_TRXMODE_C_M 0xFFFF
|
#define BT_TXMODE_C 0x072C
|
#define BT_TXMODE_C_M 0xFFFF0000
|
#define RST_ALL_CNT_C 0x0730
|
#define RST_ALL_CNT_C_M 0x1
|
#define ENABLE_ALL_CNT_C 0x0730
|
#define ENABLE_ALL_CNT_C_M 0x2
|
#define PERIOD_KEEP_EN_S1_C 0x0730
|
#define PERIOD_KEEP_EN_S1_C_M 0x10
|
#define PERIOD_KEEP_EN_S2_C 0x0730
|
#define PERIOD_KEEP_EN_S2_C_M 0x20
|
#define PERIOD_KEEP_EN_S3_C 0x0730
|
#define PERIOD_KEEP_EN_S3_C_M 0x40
|
#define PERIOD_KEEP_EN_S4_C 0x0730
|
#define PERIOD_KEEP_EN_S4_C_M 0x80
|
#define CNT_PWDB_TH_C 0x0730
|
#define CNT_PWDB_TH_C_M 0xFFFF0000
|
#define MAC_PIN_SEL_C 0x0734
|
#define MAC_PIN_SEL_C_M 0xFFFF
|
#define CH_IDX_SEG0_C 0x0734
|
#define CH_IDX_SEG0_C_M 0xFF0000
|
#define CH_IDX_SEG1_C 0x0734
|
#define CH_IDX_SEG1_C_M 0xFF000000
|
#define PLCP_HISTOGRAM_EN_C 0x0738
|
#define PLCP_HISTOGRAM_EN_C_M 0x1
|
#define PLCP_HIST_TYPE_SEL_C 0x0738
|
#define PLCP_HIST_TYPE_SEL_C_M 0x2
|
#define STS_DIS_TRIG_BY_BRK_C 0x0738
|
#define STS_DIS_TRIG_BY_BRK_C_M 0x4
|
#define STS_DIS_TRIG_BY_FAIL_C 0x0738
|
#define STS_DIS_TRIG_BY_FAIL_C_M 0x8
|
#define STS_KEEPER_EN_C 0x0738
|
#define STS_KEEPER_EN_C_M 0x10
|
#define STS_KEEPER_READ_C 0x0738
|
#define STS_KEEPER_READ_C_M 0x20
|
#define STS_KEEPER_TRIG_COND_C 0x0738
|
#define STS_KEEPER_TRIG_COND_C_M 0xC0
|
#define STS_KEEPER_ADDR_C 0x0738
|
#define STS_KEEPER_ADDR_C_M 0xFF00
|
#define DATAON_TO_STS_FLAG_C 0x0738
|
#define DATAON_TO_STS_FLAG_C_M 0xF0000
|
#define STS_FLAG_GUARD_C 0x0738
|
#define STS_FLAG_GUARD_C_M 0xF00000
|
#define PHYSTS_INCR_DBG_EN_C 0x0738
|
#define PHYSTS_INCR_DBG_EN_C_M 0x1000000
|
#define STS_USER_SEL_C 0x0738
|
#define STS_USER_SEL_C_M 0x6000000
|
#define STS_SEG_SEL_C 0x0738
|
#define STS_SEG_SEL_C_M 0x8000000
|
#define STS_DBG_SEL_C 0x0738
|
#define STS_DBG_SEL_C_M 0x70000000
|
#define STS_TRIG_BY_FEQ_END_IN_NDP_C 0x0738
|
#define STS_TRIG_BY_FEQ_END_IN_NDP_C_M 0x80000000
|
#define PHY_STS_BITMAP_SEARCH_FAIL_C 0x073C
|
#define PHY_STS_BITMAP_SEARCH_FAIL_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_R2T_C 0x0740
|
#define PHY_STS_BITMAP_R2T_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_CCA_SPOOF_C 0x0744
|
#define PHY_STS_BITMAP_CCA_SPOOF_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_OFDM_BRK_C 0x0748
|
#define PHY_STS_BITMAP_OFDM_BRK_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_CCK_BRK_C 0x074C
|
#define PHY_STS_BITMAP_CCK_BRK_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_DL_MU_SPOOF_C 0x0750
|
#define PHY_STS_BITMAP_DL_MU_SPOOF_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_HE_MU_C 0x0754
|
#define PHY_STS_BITMAP_HE_MU_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_VHT_MU_C 0x0758
|
#define PHY_STS_BITMAP_VHT_MU_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_UL_TB_SPOOF_C 0x075C
|
#define PHY_STS_BITMAP_UL_TB_SPOOF_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_TRIGBASE_C 0x0760
|
#define PHY_STS_BITMAP_TRIGBASE_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_CCK_C 0x0764
|
#define PHY_STS_BITMAP_CCK_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_LEGACY_C 0x0768
|
#define PHY_STS_BITMAP_LEGACY_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_HT_C 0x076C
|
#define PHY_STS_BITMAP_HT_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_VHT_C 0x0770
|
#define PHY_STS_BITMAP_VHT_C_M 0xFFFFFFFF
|
#define PHY_STS_BITMAP_HE_C 0x0774
|
#define PHY_STS_BITMAP_HE_C_M 0xFFFFFFFF
|
#define PW_CUT_R2T_C 0x0778
|
#define PW_CUT_R2T_C_M 0xFF
|
#define PW_CUT_TXON_C 0x0778
|
#define PW_CUT_TXON_C_M 0xFF00
|
#define PW_CUT_WAIT_CCA_C 0x0778
|
#define PW_CUT_WAIT_CCA_C_M 0xFF0000
|
#define PW_CUT_RX_LEGACY_C 0x0778
|
#define PW_CUT_RX_LEGACY_C_M 0xFF000000
|
#define PW_CUT_RX_HTDATA_TIME_C 0x077C
|
#define PW_CUT_RX_HTDATA_TIME_C_M 0xFF
|
#define PW_CUT_RX_HTDATA_IORD_BCC_C 0x077C
|
#define PW_CUT_RX_HTDATA_IORD_BCC_C_M 0xFF00
|
#define PW_CUT_RX_HTDATA_IORD_LDPC_C 0x077C
|
#define PW_CUT_RX_HTDATA_IORD_LDPC_C_M 0xFF0000
|
#define PW_CUT_RX_HTDATA_CSI_RPT_C 0x077C
|
#define PW_CUT_RX_HTDATA_CSI_RPT_C_M 0xFF000000
|
#define SEL_V_COLUMN_VAL_EN_C 0x0800
|
#define SEL_V_COLUMN_VAL_EN_C_M 0x1
|
#define SEL_V_COLUMN_VAL_C 0x0800
|
#define SEL_V_COLUMN_VAL_C_M 0x3E
|
#define TXBF_SCAL_FCTR_C 0x0800
|
#define TXBF_SCAL_FCTR_C_M 0xFFC0
|
#define TXBF_SCAL_FCTR_EN_C 0x0800
|
#define TXBF_SCAL_FCTR_EN_C_M 0x10000
|
#define RST_BFER_EDGE_CNT_C 0x0800
|
#define RST_BFER_EDGE_CNT_C_M 0x20000
|
#define RST_BFEE_EDGE_CNT_C 0x0800
|
#define RST_BFEE_EDGE_CNT_C_M 0x40000
|
#define CSI_PARA_SEL_TO_RPT_C 0x0800
|
#define CSI_PARA_SEL_TO_RPT_C_M 0x7F80000
|
#define DIS_MU_GOUPING_TRIG_FB_CHK_C 0x0800
|
#define DIS_MU_GOUPING_TRIG_FB_CHK_C_M 0x8000000
|
#define GRPING_SEARCH_NUM_C 0x0804
|
#define GRPING_SEARCH_NUM_C_M 0xFF
|
#define GRP_USER_EN_C 0x0804
|
#define GRP_USER_EN_C_M 0x3FF00
|
#define DIS_MU_GRPING_C 0x0804
|
#define DIS_MU_GRPING_C_M 0x40000
|
#define DIS_BF_USER_CHK_C 0x0804
|
#define DIS_BF_USER_CHK_C_M 0x80000
|
#define SOUND_DONE_MUX_C 0x0804
|
#define SOUND_DONE_MUX_C_M 0x300000
|
#define ALWAYS_LAT_GRP_GMER_C 0x0804
|
#define ALWAYS_LAT_GRP_GMER_C_M 0x400000
|
#define BFEE_NR_NSTS_SEL_C 0x0808
|
#define BFEE_NR_NSTS_SEL_C_M 0x1
|
#define CAL_FEEDBACK_CSI_EN_C 0x0808
|
#define CAL_FEEDBACK_CSI_EN_C_M 0x2
|
#define RST_TXBF_COMPRESSOR_C 0x0808
|
#define RST_TXBF_COMPRESSOR_C_M 0x4
|
#define EN_SNR_RPT_COMP_C 0x0808
|
#define EN_SNR_RPT_COMP_C_M 0x8
|
#define TXBF_SNR_RPT_LIMT_EN_C 0x0808
|
#define TXBF_SNR_RPT_LIMT_EN_C_M 0x10
|
#define EN_DEF_SNR_C 0x0808
|
#define EN_DEF_SNR_C_M 0x20
|
#define DIS_BFEE_GCLK_C 0x0808
|
#define DIS_BFEE_GCLK_C_M 0x40
|
#define DIS_MAC_P_C 0x0808
|
#define DIS_MAC_P_C_M 0x80
|
#define DIS_CSI_CHKSUM_C 0x0808
|
#define DIS_CSI_CHKSUM_C_M 0x100
|
#define DIS_BFEE_CB_LMT_C 0x0808
|
#define DIS_BFEE_CB_LMT_C_M 0x200
|
#define BFMX_NDP_TRIG_SEL_C 0x0808
|
#define BFMX_NDP_TRIG_SEL_C_M 0x400
|
#define NDP_STANDBY_MUX_C 0x0808
|
#define NDP_STANDBY_MUX_C_M 0x1800
|
#define CSI_RPT_RATE_SEL_C 0x0808
|
#define CSI_RPT_RATE_SEL_C_M 0xE000
|
#define DIS_BFER_GCLK_C 0x0808
|
#define DIS_BFER_GCLK_C_M 0x10000
|
#define CSI_PARA_DBG_SEL_C 0x0808
|
#define CSI_PARA_DBG_SEL_C_M 0xFE0000
|
#define DIS_BF_CLK_C 0x0808
|
#define DIS_BF_CLK_C_M 0x1000000
|
#define DEF_DSNR_C 0x080C
|
#define DEF_DSNR_C_M 0xFFFF
|
#define BF_MIMO_BUS_DBG_EN_C 0x080C
|
#define BF_MIMO_BUS_DBG_EN_C_M 0x7F0000
|
#define BF_MIMO_BUS_DBG_SEL_C 0x080C
|
#define BF_MIMO_BUS_DBG_SEL_C_M 0x800000
|
#define DEF_SNR0_C 0x0810
|
#define DEF_SNR0_C_M 0xFF
|
#define DEF_SNR1_C 0x0810
|
#define DEF_SNR1_C_M 0xFF00
|
#define DEF_SNR2_C 0x0810
|
#define DEF_SNR2_C_M 0xFF0000
|
#define DEF_SNR3_C 0x0810
|
#define DEF_SNR3_C_M 0xFF000000
|
#define CSI_PARA_USER_EN_0_C 0x0814
|
#define CSI_PARA_USER_EN_0_C_M 0xFFFFFFFF
|
#define CSI_PARA_USER_EN_1_C 0x0818
|
#define CSI_PARA_USER_EN_1_C_M 0xFFFFFFFF
|
#define CSI_PARA_USER_EN_2_C 0x081C
|
#define CSI_PARA_USER_EN_2_C_M 0xFFFFFFFF
|
#define CSI_PARA_USER_EN_3_C 0x0820
|
#define CSI_PARA_USER_EN_3_C_M 0xFFFFFFFF
|
#define CSI_PARA_PARA_EN_C 0x0824
|
#define CSI_PARA_PARA_EN_C_M 0xFFFF
|
#define CSI_PARA_USE_EN_C 0x0824
|
#define CSI_PARA_USE_EN_C_M 0xF0000
|
#define CSI_PARA_READY_TIMEOUT_C 0x0824
|
#define CSI_PARA_READY_TIMEOUT_C_M 0x700000
|
#define CSI_PARA_END_SEL_C 0x0824
|
#define CSI_PARA_END_SEL_C_M 0x3800000
|
#define BFEE_CSI_DEF_MODE_C 0x0824
|
#define BFEE_CSI_DEF_MODE_C_M 0xC000000
|
#define CSI_PARA_IDX_0_C 0x0828
|
#define CSI_PARA_IDX_0_C_M 0xFFFFFFFF
|
#define CSI_PARA_IDX_1_C 0x082C
|
#define CSI_PARA_IDX_1_C_M 0xFFFF
|
#define CSI_PARA_C 0x082C
|
#define CSI_PARA_C_M 0xFFFF0000
|
#define BFEE_CSI_DEF_VAL_C 0x0830
|
#define BFEE_CSI_DEF_VAL_C_M 0xFFFFFFFF
|
#define DIS_BFEE_RST_CRTL_C 0x0834
|
#define DIS_BFEE_RST_CRTL_C_M 0xFF
|
#define CSI_RDRDY_TIME_OUT_SEL_C 0x0834
|
#define CSI_RDRDY_TIME_OUT_SEL_C_M 0xF00
|
#define INTF_R_CNT_RATE_C 0x0900
|
#define INTF_R_CNT_RATE_C_M 0xF
|
#define INTF_R_CNT_MCS_C 0x0900
|
#define INTF_R_CNT_MCS_C_M 0x7F0
|
#define INTF_R_CNT_VHT_MCS_C 0x0900
|
#define INTF_R_CNT_VHT_MCS_C_M 0x7800
|
#define INTF_R_CNT_HE_MCS_C 0x0900
|
#define INTF_R_CNT_HE_MCS_C_M 0x78000
|
#define INTF_R_CNT_VHT_NSS_C 0x0900
|
#define INTF_R_CNT_VHT_NSS_C_M 0x180000
|
#define INTF_R_CNT_HE_NSS_C 0x0900
|
#define INTF_R_CNT_HE_NSS_C_M 0x600000
|
#define INTF_R_MAC_HDR_TYPE_C 0x0900
|
#define INTF_R_MAC_HDR_TYPE_C_M 0x1F800000
|
#define INTF_R_PKT_TYPE_C 0x0904
|
#define INTF_R_PKT_TYPE_C_M 0xF
|
#define INTF_R_CRC32_TARGET_UID_C 0x0904
|
#define INTF_R_CRC32_TARGET_UID_C_M 0xFF0
|
#define INTF_R_CRC32_TARGET_UID_EN_C 0x0904
|
#define INTF_R_CRC32_TARGET_UID_EN_C_M 0x1000
|
#define INTF_R_RX_LBK_MODE_USER_EN_C 0x0904
|
#define INTF_R_RX_LBK_MODE_USER_EN_C_M 0x2000
|
#define INTF_R_RX_LBK_MODE_N_USER_C 0x0904
|
#define INTF_R_RX_LBK_MODE_N_USER_C_M 0x1C000
|
#define INTF_R_RX_LBK_MODE_AMPDU_EN_C 0x0904
|
#define INTF_R_RX_LBK_MODE_AMPDU_EN_C_M 0x20000
|
#define INTF_R_RX_LBK_MODE_N_USER_EXT_C 0x0904
|
#define INTF_R_RX_LBK_MODE_N_USER_EXT_C_M 0x3C0000
|
#define INTF_R_DIS_TB_BRK_PROTECT_C 0x0908
|
#define INTF_R_DIS_TB_BRK_PROTECT_C_M 0x1
|
#define INTF_R_DIS_TB_FIFO_CLR_C 0x0908
|
#define INTF_R_DIS_TB_FIFO_CLR_C_M 0x2
|
#define INTF_R_PMAC_TB_N_USER_CLR_TARGET_C 0x0908
|
#define INTF_R_PMAC_TB_N_USER_CLR_TARGET_C_M 0xF0
|
#define INTF_R_PMAC_TB_RSSI_C 0x0908
|
#define INTF_R_PMAC_TB_RSSI_C_M 0x7F00
|
#define INTF_R_MAC_TRX_SEL_C 0x090C
|
#define INTF_R_MAC_TRX_SEL_C_M 0xFFFF
|
#define INTF_R_MAC_INFO_RPT_USER_SEL_C 0x090C
|
#define INTF_R_MAC_INFO_RPT_USER_SEL_C_M 0x10000
|
#define INTF_R_TX_PMAC_EN_C 0x0980
|
#define INTF_R_TX_PMAC_EN_C_M 0x1
|
#define INTF_R_PMAC_TX_U_ID_PHASE_OPT_C 0x0980
|
#define INTF_R_PMAC_TX_U_ID_PHASE_OPT_C_M 0x30
|
#define INTF_R_PMAC_TXD_PHASE_OPT_C 0x0980
|
#define INTF_R_PMAC_TXD_PHASE_OPT_C_M 0xC0
|
#define INTF_R_PMAC_TX_INFO_DLY_CNT_C 0x0980
|
#define INTF_R_PMAC_TX_INFO_DLY_CNT_C_M 0x700
|
#define INTF_R_PMAC_TDRDY_EXT_CNT_C 0x0980
|
#define INTF_R_PMAC_TDRDY_EXT_CNT_C_M 0x7000
|
#define INTF_R_MAC_SEL_C 0x0980
|
#define INTF_R_MAC_SEL_C_M 0xFF0000
|
#define INTF_R_PMAC_TBTT_C 0x0980
|
#define INTF_R_PMAC_TBTT_C_M 0x1000000
|
#define INTF_R_PMAC_PMAC_MOD_C 0x0980
|
#define INTF_R_PMAC_PMAC_MOD_C_M 0x2000000
|
#define INTF_R_PMAC_GNT_BT_C 0x0980
|
#define INTF_R_PMAC_GNT_BT_C_M 0x4000000
|
#define INTF_R_PMAC_GNT_BT_TX_C 0x0980
|
#define INTF_R_PMAC_GNT_BT_TX_C_M 0x8000000
|
#define INTF_R_PMAC_GNT_WL_C 0x0980
|
#define INTF_R_PMAC_GNT_WL_C_M 0x10000000
|
#define INTF_R_PMAC_LTE_RX_C 0x0980
|
#define INTF_R_PMAC_LTE_RX_C_M 0x20000000
|
#define INTF_R_PMAC_RXPKT_OK_C 0x0980
|
#define INTF_R_PMAC_RXPKT_OK_C_M 0x40000000
|
#define INTF_R_PMAC_RXPKT_FAIL_C 0x0980
|
#define INTF_R_PMAC_RXPKT_FAIL_C_M 0x80000000
|
#define INTF_R_MAC_SEL_FTM_C 0x0984
|
#define INTF_R_MAC_SEL_FTM_C_M 0x3
|
#define INTF_R_PMAC_FTM_EN_C 0x0984
|
#define INTF_R_PMAC_FTM_EN_C_M 0x10
|
#define INTF_R_PMAC_FTM_RPT_TRIG_C 0x0984
|
#define INTF_R_PMAC_FTM_RPT_TRIG_C_M 0x100
|
#define INTF_R_MAC_SEL_RXD_C 0x0988
|
#define INTF_R_MAC_SEL_RXD_C_M 0x3F
|
#define INTF_R_RX_PMAC_EN_C 0x0988
|
#define INTF_R_RX_PMAC_EN_C_M 0x100
|
#define INTF_R_PMAC_RX_INVLD_PKT_C 0x0988
|
#define INTF_R_PMAC_RX_INVLD_PKT_C_M 0x200
|
#define INTF_R_PMAC_RX_ID_MATCH_C 0x0988
|
#define INTF_R_PMAC_RX_ID_MATCH_C_M 0x400
|
#define INTF_R_PMAC_DONT_RST_MAC_C 0x0988
|
#define INTF_R_PMAC_DONT_RST_MAC_C_M 0x800
|
#define INTF_R_PMAC_RX_TB_PPDU_STANDBY_C 0x0988
|
#define INTF_R_PMAC_RX_TB_PPDU_STANDBY_C_M 0x1000
|
#define INTF_R_PMAC_RX_TB_EN_C 0x0988
|
#define INTF_R_PMAC_RX_TB_EN_C_M 0x2000
|
#define INTF_R_MAC_RXD_PHASE_OPT_C 0x0988
|
#define INTF_R_MAC_RXD_PHASE_OPT_C_M 0xC000
|
#define INTF_R_TIME_RX_AIR_END_C 0x0988
|
#define INTF_R_TIME_RX_AIR_END_C_M 0x3F0000
|
#define INTF_R_TIME_RX_AIR_END_CCA_LAT_C 0x0988
|
#define INTF_R_TIME_RX_AIR_END_CCA_LAT_C_M 0x3F000000
|
#define INTF_R_PMAC_RX_TB_BUS_31_0_C 0x098C
|
#define INTF_R_PMAC_RX_TB_BUS_31_0_C_M 0xFFFFFFFF
|
#define INTF_R_PMAC_RX_TB_BUS_63_32_C 0x0990
|
#define INTF_R_PMAC_RX_TB_BUS_63_32_C_M 0xFFFFFFFF
|
#define INTF_R_MAC_SEL_BFMU_C 0x0994
|
#define INTF_R_MAC_SEL_BFMU_C_M 0xFF
|
#define INTF_R_PMAC_CSI_DATA_PAUSE_C 0x0994
|
#define INTF_R_PMAC_CSI_DATA_PAUSE_C_M 0x100
|
#define INTF_R_PMAC_NDP_STANDBY_C 0x0994
|
#define INTF_R_PMAC_NDP_STANDBY_C_M 0x200
|
#define INTF_R_PMAC_CSI_STANDBY_C 0x0994
|
#define INTF_R_PMAC_CSI_STANDBY_C_M 0x400
|
#define INTF_R_PMAC_SOUND_DONE_C 0x0994
|
#define INTF_R_PMAC_SOUND_DONE_C_M 0x800
|
#define INTF_R_PMAC_VHT_MU_USER_IDX_C 0x0994
|
#define INTF_R_PMAC_VHT_MU_USER_IDX_C_M 0x3000
|
#define INTF_R_PMAC_MIMO_PARA_EN_C 0x0994
|
#define INTF_R_PMAC_MIMO_PARA_EN_C_M 0x10000
|
#define INTF_R_PMAC_MIMO_FIELD_31_0_C 0x0998
|
#define INTF_R_PMAC_MIMO_FIELD_31_0_C_M 0xFFFFFFFF
|
#define INTF_R_PMAC_MIMO_FIELD_63_32_C 0x099C
|
#define INTF_R_PMAC_MIMO_FIELD_63_32_C_M 0xFFFFFFFF
|
#define INTF_R_PMAC_MIMO_FIELD_66_64_C 0x09A0
|
#define INTF_R_PMAC_MIMO_FIELD_66_64_C_M 0xFFFFFFFF
|
#define INTF_R_MAC_SEL_TXINFO_C 0x09A4
|
#define INTF_R_MAC_SEL_TXINFO_C_M 0xFFFFFFFF
|
#define INTF_R_TIME_RX_AIR_END_B_BW005_I_C 0x09A8
|
#define INTF_R_TIME_RX_AIR_END_B_BW005_I_C_M 0xFF
|
#define INTF_R_TIME_RX_AIR_END_B_BW010_I_C 0x09A8
|
#define INTF_R_TIME_RX_AIR_END_B_BW010_I_C_M 0xFF00
|
#define INTF_R_TIME_RX_AIR_END_B_BW020_I_C 0x09A8
|
#define INTF_R_TIME_RX_AIR_END_B_BW020_I_C_M 0xFF0000
|
#define INTF_R_TIME_RX_AIR_END_B_BW040_I_C 0x09A8
|
#define INTF_R_TIME_RX_AIR_END_B_BW040_I_C_M 0xFF000000
|
#define INTF_R_TIME_RX_AIR_END_B_BW080_I_C 0x09AC
|
#define INTF_R_TIME_RX_AIR_END_B_BW080_I_C_M 0xFF
|
#define INTF_R_TIME_RX_AIR_END_B_BW160_I_C 0x09AC
|
#define INTF_R_TIME_RX_AIR_END_B_BW160_I_C_M 0xFF00
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW005_I_C 0x09AC
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW005_I_C_M 0xFF0000
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW010_I_C 0x09AC
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW010_I_C_M 0xFF000000
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW020_I_C 0x09B0
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW020_I_C_M 0xFF
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW040_I_C 0x09B0
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW040_I_C_M 0xFF00
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW080_I_C 0x09B0
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW080_I_C_M 0xFF0000
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW160_I_C 0x09B0
|
#define INTF_R_TIME_RX_AIR_END_NHT6M_BW160_I_C_M 0xFF000000
|
#define INTF_R_TIME_RX_AIR_END_BW005_I_C 0x09B4
|
#define INTF_R_TIME_RX_AIR_END_BW005_I_C_M 0xFF
|
#define INTF_R_TIME_RX_AIR_END_BW010_I_C 0x09B4
|
#define INTF_R_TIME_RX_AIR_END_BW010_I_C_M 0xFF00
|
#define INTF_R_TIME_RX_AIR_END_BW020_I_C 0x09B4
|
#define INTF_R_TIME_RX_AIR_END_BW020_I_C_M 0xFF0000
|
#define INTF_R_TIME_RX_AIR_END_BW040_I_C 0x09B4
|
#define INTF_R_TIME_RX_AIR_END_BW040_I_C_M 0xFF000000
|
#define INTF_R_TIME_RX_AIR_END_BW080_I_C 0x09B8
|
#define INTF_R_TIME_RX_AIR_END_BW080_I_C_M 0xFF
|
#define INTF_R_TIME_RX_AIR_END_BW160_I_C 0x09B8
|
#define INTF_R_TIME_RX_AIR_END_BW160_I_C_M 0xFF00
|
#define INTF_R_EN_CLR_CCA_BKUP_BY_DROP_I_C 0x09B8
|
#define INTF_R_EN_CLR_CCA_BKUP_BY_DROP_I_C_M 0x10000
|
#define INTF_R_EN_CCA_OPT_I_C 0x09B8
|
#define INTF_R_EN_CCA_OPT_I_C_M 0x20000
|
#define INTF_R_EN_RECCA_I_C 0x09B8
|
#define INTF_R_EN_RECCA_I_C_M 0x40000
|
#define INTF_R_PMAC_TRIG_TB_C 0x09BC
|
#define INTF_R_PMAC_TRIG_TB_C_M 0x1
|
#define INTF_R_PMAC_TB_TRIG_MODE_C 0x09BC
|
#define INTF_R_PMAC_TB_TRIG_MODE_C_M 0x6
|
#define INTF_R_MAC_INFO_RPT_SEL_C 0x09BC
|
#define INTF_R_MAC_INFO_RPT_SEL_C_M 0x10
|
#define INTF_R_TX_EN_C 0x09C0
|
#define INTF_R_TX_EN_C_M 0x1
|
#define INTF_R_TX_CONTINUOUS_EN_C 0x09C4
|
#define INTF_R_TX_CONTINUOUS_EN_C_M 0x1
|
#define INTF_R_TX_ACK_EN_C 0x09C4
|
#define INTF_R_TX_ACK_EN_C_M 0x2
|
#define INTF_R_TX_N_PACKET_EN_C 0x09C4
|
#define INTF_R_TX_N_PACKET_EN_C_M 0x10
|
#define INTF_R_TX_N_PACKET_PERIOD_50NS_C 0x09C4
|
#define INTF_R_TX_N_PACKET_PERIOD_50NS_C_M 0xFFFFFF00
|
#define INTF_R_TX_N_PACKET_C 0x09C8
|
#define INTF_R_TX_N_PACKET_C_M 0xFFFFFFFF
|
#define INTF_R_TAR_TXINFO_TXTP_EN_C 0x09CC
|
#define INTF_R_TAR_TXINFO_TXTP_EN_C_M 0x1
|
#define INTF_R_TAR_TXINFO_TXTP_C 0x09CC
|
#define INTF_R_TAR_TXINFO_TXTP_C_M 0x3F0
|
#define INTF_R_TX_20M_MODE_EN_C 0x09D0
|
#define INTF_R_TX_20M_MODE_EN_C_M 0x1
|
#define INTF_R_TXBF_DIS_C 0x09D0
|
#define INTF_R_TXBF_DIS_C_M 0x10
|
#define INTF_R_TX_1SSCSD_ENABLE_C 0x09D0
|
#define INTF_R_TX_1SSCSD_ENABLE_C_M 0x100
|
#define INTF_R_TXBF_TRIG_DAGC_NEW_C 0x09D0
|
#define INTF_R_TXBF_TRIG_DAGC_NEW_C_M 0x1000
|
#define INTF_R_MAC_SEL1_TXINFO_C 0x09D4
|
#define INTF_R_MAC_SEL1_TXINFO_C_M 0xFFFFFFFF
|
#define INTF_R_TB_LSIG_MATCH_TARGET_C 0x09D8
|
#define INTF_R_TB_LSIG_MATCH_TARGET_C_M 0xFFFFFF
|
#define INTF_R_TB_LSIG_MATCH_SEL_C 0x09D8
|
#define INTF_R_TB_LSIG_MATCH_SEL_C_M 0x1000000
|
#define INTF_R_TB_FIFO_IN_SEL_C 0x09D8
|
#define INTF_R_TB_FIFO_IN_SEL_C_M 0x2000000
|
#define NOT_SUPPORT_STBC_NSS_LMT_C 0x0A00
|
#define NOT_SUPPORT_STBC_NSS_LMT_C_M 0xF
|
#define NOT_SUPPORT_DCM_NSS_LMT_C 0x0A00
|
#define NOT_SUPPORT_DCM_NSS_LMT_C_M 0xF0
|
#define NOT_SUPPORT_NSS_LMT_C 0x0A00
|
#define NOT_SUPPORT_NSS_LMT_C_M 0xF00
|
#define NOT_SUPPORT_MU_BCC_NSS_LMT_C 0x0A00
|
#define NOT_SUPPORT_MU_BCC_NSS_LMT_C_M 0xF000
|
#define EN_LDPC_RX_IN_C 0x0A00
|
#define EN_LDPC_RX_IN_C_M 0x10000
|
#define HEMUR_MUMIMO_EN_C 0x0A00
|
#define HEMUR_MUMIMO_EN_C_M 0x20000
|
#define BYPASS_HE_ERR_BCC_UP242_C 0x0A00
|
#define BYPASS_HE_ERR_BCC_UP242_C_M 0x40000
|
#define BYPASS_HE_ERR_BCC_MCS_C 0x0A00
|
#define BYPASS_HE_ERR_BCC_MCS_C_M 0x80000
|
#define BYPASS_HE_ERR_MCS_C 0x0A00
|
#define BYPASS_HE_ERR_MCS_C_M 0x100000
|
#define BYPASS_HE_ERR_NSTS_TOT_C 0x0A00
|
#define BYPASS_HE_ERR_NSTS_TOT_C_M 0x200000
|
#define BYPASS_HE_ERR_SPATIAL_CONFIG_C 0x0A00
|
#define BYPASS_HE_ERR_SPATIAL_CONFIG_C_M 0x400000
|
#define BYPASS_HE_ERR_STBC_MIMO_C 0x0A00
|
#define BYPASS_HE_ERR_STBC_MIMO_C_M 0x800000
|
#define BYPASS_HE_ERR_DCM_MIMO_C 0x0A00
|
#define BYPASS_HE_ERR_DCM_MIMO_C_M 0x1000000
|
#define BYPASS_HE_ERR_STBC_DCM_C 0x0A00
|
#define BYPASS_HE_ERR_STBC_DCM_C_M 0x2000000
|
#define BYPASS_HE_NOT_SUPPORT_STBC_NSS_C 0x0A00
|
#define BYPASS_HE_NOT_SUPPORT_STBC_NSS_C_M 0x4000000
|
#define BYPASS_HE_NOT_SUPPORT_DCM_NSS_C 0x0A00
|
#define BYPASS_HE_NOT_SUPPORT_DCM_NSS_C_M 0x8000000
|
#define BYPASS_HE_NOT_SUPPORT_NSS_C 0x0A00
|
#define BYPASS_HE_NOT_SUPPORT_NSS_C_M 0x10000000
|
#define BYPASS_HE_NOT_SUPPORT_MU_BCC_NSS_C 0x0A00
|
#define BYPASS_HE_NOT_SUPPORT_MU_BCC_NSS_C_M 0x20000000
|
#define BYPASS_HE_NOT_SUPPORT_MU_MIMO_C 0x0A00
|
#define BYPASS_HE_NOT_SUPPORT_MU_MIMO_C_M 0x40000000
|
#define QBPSK_FLAG_FIX_C 0x0A00
|
#define QBPSK_FLAG_FIX_C_M 0x80000000
|
#define BYPASS_SMO_NDP_SEL_C 0x0A04
|
#define BYPASS_SMO_NDP_SEL_C_M 0x1
|
#define FORCE_LS_NDP_C 0x0A04
|
#define FORCE_LS_NDP_C_M 0x2
|
#define CQI_DD_OPT_C 0x0A04
|
#define CQI_DD_OPT_C_M 0x3FC
|
#define CQI_TRIG_SEL_C 0x0A04
|
#define CQI_TRIG_SEL_C_M 0x400
|
#define EN_PILOT_TRACKING_ONLY_C 0x0A04
|
#define EN_PILOT_TRACKING_ONLY_C_M 0x800
|
#define HE_SIGB_STF_DELAY_SPACING_C 0x0A04
|
#define HE_SIGB_STF_DELAY_SPACING_C_M 0xFF000
|
#define TB_LTF_TRACK_CNT_START_VAL_C 0x0A04
|
#define TB_LTF_TRACK_CNT_START_VAL_C_M 0x700000
|
#define PILOT_DC_ALIGN_SEL_C 0x0A04
|
#define PILOT_DC_ALIGN_SEL_C_M 0x800000
|
#define CQI_EN_5SS_UP_C 0x0A04
|
#define CQI_EN_5SS_UP_C_M 0x1000000
|
#define RESERVED_C 0x0A04
|
#define RESERVED_C_M 0xFE000000
|
#define STS_NDP_KEEP_COND_IN_IN_C 0x0A08
|
#define STS_NDP_KEEP_COND_IN_IN_C_M 0x1
|
#define FTM_T_OFF_PKT_CNT_TO_BRK_C 0x0A08
|
#define FTM_T_OFF_PKT_CNT_TO_BRK_C_M 0x3800
|
#define BWD_VERYLOW_SNR_MODE_EN_C 0x0A08
|
#define BWD_VERYLOW_SNR_MODE_EN_C_M 0x4000
|
#define CCX_EN_C 0x0C00
|
#define CCX_EN_C_M 0x1
|
#define CCX_TRIG_OPT_C 0x0C00
|
#define CCX_TRIG_OPT_C_M 0x2
|
#define MEASUREMENT_TRIG_C 0x0C00
|
#define MEASUREMENT_TRIG_C_M 0x4
|
#define CCX_EDCCA_OPT_C 0x0C00
|
#define CCX_EDCCA_OPT_C_M 0x70
|
#define CCX_TXON_OPT_C 0x0C00
|
#define CCX_TXON_OPT_C_M 0x80
|
#define CLM_COUNTER_UNIT_C 0x0C00
|
#define CLM_COUNTER_UNIT_C_M 0xC00
|
#define CLM_EN_C 0x0C00
|
#define CLM_EN_C_M 0x1000
|
#define CLM_CCA_OPT_C 0x0C00
|
#define CLM_CCA_OPT_C_M 0xE000
|
#define CLM_PERIOD_C 0x0C00
|
#define CLM_PERIOD_C_M 0xFFFF0000
|
#define CLM_EDCCA_PERIOD_C 0x0C04
|
#define CLM_EDCCA_PERIOD_C_M 0xFFFF
|
#define CLM_EDCCA_COUNTER_UNIT_C 0x0C04
|
#define CLM_EDCCA_COUNTER_UNIT_C_M 0x30000
|
#define CLM_EDCCA_EN_C 0x0C04
|
#define CLM_EDCCA_EN_C_M 0x40000
|
#define CLM_FROM_DBG_SEL_C 0x0C04
|
#define CLM_FROM_DBG_SEL_C_M 0x3F00000
|
#define NHM_PERIOD_C 0x0C08
|
#define NHM_PERIOD_C_M 0xFFFF
|
#define NHM_COUNTER_UNIT_C 0x0C08
|
#define NHM_COUNTER_UNIT_C_M 0x30000
|
#define NHM_EN_C 0x0C08
|
#define NHM_EN_C_M 0x40000
|
#define NHM_IGNORE_CCA_C 0x0C08
|
#define NHM_IGNORE_CCA_C_M 0x80000
|
#define NHM_TH0_C 0x0C08
|
#define NHM_TH0_C_M 0xFF000000
|
#define NHM_TH1_C 0x0C0C
|
#define NHM_TH1_C_M 0xFF
|
#define NHM_TH2_C 0x0C0C
|
#define NHM_TH2_C_M 0xFF00
|
#define NHM_TH3_C 0x0C0C
|
#define NHM_TH3_C_M 0xFF0000
|
#define NHM_TH4_C 0x0C0C
|
#define NHM_TH4_C_M 0xFF000000
|
#define NHM_TH5_C 0x0C10
|
#define NHM_TH5_C_M 0xFF
|
#define NHM_TH6_C 0x0C10
|
#define NHM_TH6_C_M 0xFF00
|
#define NHM_TH7_C 0x0C10
|
#define NHM_TH7_C_M 0xFF0000
|
#define NHM_TH8_C 0x0C10
|
#define NHM_TH8_C_M 0xFF000000
|
#define NHM_TH9_C 0x0C14
|
#define NHM_TH9_C_M 0xFF
|
#define NHM_TH10_C 0x0C14
|
#define NHM_TH10_C_M 0xFF00
|
#define NHM_PWDB_METHOD_SEL_C 0x0C14
|
#define NHM_PWDB_METHOD_SEL_C_M 0x30000
|
#define NHM_PWDB_PATH_SEL_C 0x0C14
|
#define NHM_PWDB_PATH_SEL_C_M 0xF00000
|
#define AVG_IDLE_PW_IDX_C 0x0C14
|
#define AVG_IDLE_PW_IDX_C_M 0x7000000
|
#define T2F_BRK_CNT_END_C 0x0C14
|
#define T2F_BRK_CNT_END_C_M 0x38000000
|
#define T2F_IDLE_CNT_BRK_SWITCH_C 0x0C14
|
#define T2F_IDLE_CNT_BRK_SWITCH_C_M 0x40000000
|
#define T2F_HE_CDD_SKIP_EN_C 0x0C14
|
#define T2F_HE_CDD_SKIP_EN_C_M 0x80000000
|
#define FAHM_EN_C 0x0C18
|
#define FAHM_EN_C_M 0x1
|
#define FAHM_EN_OFDM_C 0x0C18
|
#define FAHM_EN_OFDM_C_M 0x2
|
#define FAHM_EN_CCK_C 0x0C18
|
#define FAHM_EN_CCK_C_M 0x4
|
#define FAHM_NUM_CANDIDATE_C 0x0C18
|
#define FAHM_NUM_CANDIDATE_C_M 0x38
|
#define FAHM_DEN_CANDIDATE_C 0x0C18
|
#define FAHM_DEN_CANDIDATE_C_M 0x1C0
|
#define FAHM_EN_TH_LMT_C 0x0C18
|
#define FAHM_EN_TH_LMT_C_M 0x200
|
#define FAHM_COUNTER_UNIT_C 0x0C18
|
#define FAHM_COUNTER_UNIT_C_M 0xC00
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#define FAHM_TH_UP_LMT_C 0x0C18
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#define FAHM_TH_UP_LMT_C_M 0xF000
|
#define FAHM_PERIOD_C 0x0C18
|
#define FAHM_PERIOD_C_M 0xFFFF0000
|
#define FAHM_CRC32_ERR_LEGACY_C 0x0C1C
|
#define FAHM_CRC32_ERR_LEGACY_C_M 0x1
|
#define FAHM_AMPDU_CRC32_OPT_C 0x0C1C
|
#define FAHM_AMPDU_CRC32_OPT_C_M 0x2
|
#define RX_TD_CKEN_OFDM_C 0x0C1C
|
#define RX_TD_CKEN_OFDM_C_M 0x4
|
#define R552B_ECOB_ST_STO_EN_C 0x0C1C
|
#define R552B_ECOB_ST_STO_EN_C_M 0x8
|
#define FAHM_PWDB_SEL_C 0x0C1C
|
#define FAHM_PWDB_SEL_C_M 0x70
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#define FAHM_TH0_C 0x0C1C
|
#define FAHM_TH0_C_M 0xFF0000
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#define FAHM_TH1_C 0x0C1C
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#define FAHM_TH1_C_M 0xFF000000
|
#define FAHM_TH2_C 0x0C20
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#define FAHM_TH2_C_M 0xFF
|
#define FAHM_TH3_C 0x0C20
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#define FAHM_TH3_C_M 0xFF00
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#define FAHM_TH4_C 0x0C20
|
#define FAHM_TH4_C_M 0xFF0000
|
#define FAHM_TH5_C 0x0C20
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#define FAHM_TH5_C_M 0xFF000000
|
#define FAHM_TH6_C 0x0C24
|
#define FAHM_TH6_C_M 0xFF
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#define FAHM_TH7_C 0x0C24
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#define FAHM_TH7_C_M 0xFF00
|
#define FAHM_TH8_C 0x0C24
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#define FAHM_TH8_C_M 0xFF0000
|
#define FAHM_TH9_C 0x0C24
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#define FAHM_TH9_C_M 0xFF000000
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#define FAHM_TH10_C 0x0C28
|
#define FAHM_TH10_C_M 0xFF
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#define FAHM_DIS_COUNT_EACH_MPDU_C 0x0C28
|
#define FAHM_DIS_COUNT_EACH_MPDU_C_M 0x100
|
#define IFS_COLLECT_EN_C 0x0C28
|
#define IFS_COLLECT_EN_C_M 0x1000
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#define IFS_COUNTER_CLR_C 0x0C28
|
#define IFS_COUNTER_CLR_C_M 0x2000
|
#define IFS_COUNTER_UNIT_C 0x0C28
|
#define IFS_COUNTER_UNIT_C_M 0xC000
|
#define IFS_COLLECT_TOTAL_TIME_C 0x0C28
|
#define IFS_COLLECT_TOTAL_TIME_C_M 0xFFFF0000
|
#define IFS_T1_TH_LOW_C 0x0C2C
|
#define IFS_T1_TH_LOW_C_M 0x7FFF
|
#define IFS_T1_EN_C 0x0C2C
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#define IFS_T1_EN_C_M 0x8000
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#define IFS_T1_TH_HIGH_C 0x0C2C
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#define IFS_T1_TH_HIGH_C_M 0xFFFF0000
|
#define IFS_T2_TH_LOW_C 0x0C30
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#define IFS_T2_TH_LOW_C_M 0x7FFF
|
#define IFS_T2_EN_C 0x0C30
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#define IFS_T2_EN_C_M 0x8000
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#define IFS_T2_TH_HIGH_C 0x0C30
|
#define IFS_T2_TH_HIGH_C_M 0xFFFF0000
|
#define IFS_T3_TH_LOW_C 0x0C34
|
#define IFS_T3_TH_LOW_C_M 0x7FFF
|
#define IFS_T3_EN_C 0x0C34
|
#define IFS_T3_EN_C_M 0x8000
|
#define IFS_T3_TH_HIGH_C 0x0C34
|
#define IFS_T3_TH_HIGH_C_M 0xFFFF0000
|
#define IFS_T4_TH_LOW_C 0x0C38
|
#define IFS_T4_TH_LOW_C_M 0x7FFF
|
#define IFS_T4_EN_C 0x0C38
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#define IFS_T4_EN_C_M 0x8000
|
#define IFS_T4_TH_HIGH_C 0x0C38
|
#define IFS_T4_TH_HIGH_C_M 0xFFFF0000
|
#define EN_AGC_C 0x0C3C
|
#define EN_AGC_C_M 0x1
|
#define EN_DFIR_TMP_C 0x0C3C
|
#define EN_DFIR_TMP_C_M 0x2
|
#define EN_ACI_DET_TMP_C 0x0C3C
|
#define EN_ACI_DET_TMP_C_M 0x4
|
#define EN_DCCL_TMP_C 0x0C3C
|
#define EN_DCCL_TMP_C_M 0x8
|
#define EN_NBIFLT_TMP_C 0x0C3C
|
#define EN_NBIFLT_TMP_C_M 0x10
|
#define EN_SUBFLT_TMP_C 0x0C3C
|
#define EN_SUBFLT_TMP_C_M 0x20
|
#define OPT_PW_C 0x0C3C
|
#define OPT_PW_C_M 0x40
|
#define DC_EN_C 0x0C3C
|
#define DC_EN_C_M 0x80
|
#define SMF_EN_C 0x0C3C
|
#define SMF_EN_C_M 0x100
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#define DIS_PD_FLAG_C 0x0C3C
|
#define DIS_PD_FLAG_C_M 0x200
|
#define DBG_OPT_SYNC_C 0x0C3C
|
#define DBG_OPT_SYNC_C_M 0x400
|
#define DIS_GATE_SYNC_PATH_BY_TXON_C 0x0C3C
|
#define DIS_GATE_SYNC_PATH_BY_TXON_C_M 0x800
|
#define DIS_RST_SYNC_PATH_BY_TXON_C 0x0C3C
|
#define DIS_RST_SYNC_PATH_BY_TXON_C_M 0x1000
|
#define EN_2ND20_C 0x0C3C
|
#define EN_2ND20_C_M 0x2000
|
#define SYNC_RST_OPT_C 0x0C3C
|
#define SYNC_RST_OPT_C_M 0xC000
|
#define BYPASS_BW20_INDICATE_C 0x0C3C
|
#define BYPASS_BW20_INDICATE_C_M 0x10000
|
#define FORCE_RXSC_EN_C 0x0C3C
|
#define FORCE_RXSC_EN_C_M 0x20000
|
#define FORCE_RXSC_C 0x0C3C
|
#define FORCE_RXSC_C_M 0x40000
|
#define FINE_TUNE_PROCESS_DELAY_EXT_C 0x0C3C
|
#define FINE_TUNE_PROCESS_DELAY_EXT_C_M 0x80000
|
#define FINE_TUNE_STOP_LMT_EXT_C 0x0C3C
|
#define FINE_TUNE_STOP_LMT_EXT_C_M 0x100000
|
#define DIS_RST_CR_OFST_BY_RFGC_C 0x0C3C
|
#define DIS_RST_CR_OFST_BY_RFGC_C_M 0x200000
|
#define LONG_CFO_EST_EN_C 0x0C3C
|
#define LONG_CFO_EST_EN_C_M 0x400000
|
#define LONG_CFO_EST_SEL_C 0x0C3C
|
#define LONG_CFO_EST_SEL_C_M 0x800000
|
#define RST_AGC_DCNF_BY_TRIG_C 0x0C3C
|
#define RST_AGC_DCNF_BY_TRIG_C_M 0x1000000
|
#define DIS_RST_CNT_BY_AGCSTS_CHANGE_C 0x0C3C
|
#define DIS_RST_CNT_BY_AGCSTS_CHANGE_C_M 0x2000000
|
#define SYNC_ALWAYS_ON_C 0x0C3C
|
#define SYNC_ALWAYS_ON_C_M 0x4000000
|
#define SBFLT5M_EN_TMP_C 0x0C3C
|
#define SBFLT5M_EN_TMP_C_M 0x8000000
|
#define SBDFT_FINE_CFO_EN_C 0x0C3C
|
#define SBDFT_FINE_CFO_EN_C_M 0x10000000
|
#define CFO_ANT_SUM_RTL_C 0x0C3C
|
#define CFO_ANT_SUM_RTL_C_M 0x20000000
|
#define MANUAL_COARSE_CFO_EN_C 0x0C3C
|
#define MANUAL_COARSE_CFO_EN_C_M 0x40000000
|
#define MANUAL_FINE_CFO_EN_C 0x0C3C
|
#define MANUAL_FINE_CFO_EN_C_M 0x80000000
|
#define CDD0_COUNT_LMT_RTL_C 0x0C40
|
#define CDD0_COUNT_LMT_RTL_C_M 0x1F
|
#define CDD0_JUMP_SUB_TUNE_RTL_C 0x0C40
|
#define CDD0_JUMP_SUB_TUNE_RTL_C_M 0x3E0
|
#define CDD0_DELAY_SPREAD_SIZE_RTL_C 0x0C40
|
#define CDD0_DELAY_SPREAD_SIZE_RTL_C_M 0x3C00
|
#define SYNC_DATA_DELAY_DIFF_C 0x0C40
|
#define SYNC_DATA_DELAY_DIFF_C_M 0x1FC000
|
#define MANUAL_COARSE_CFO_C 0x0C40
|
#define MANUAL_COARSE_CFO_C_M 0xFFE00000
|
#define L1_L2_PROCESS_DELAY_CFO_C 0x0C44
|
#define L1_L2_PROCESS_DELAY_CFO_C_M 0xF
|
#define SYNC_DATA_DELAY_DIFF_CFO_C 0x0C44
|
#define SYNC_DATA_DELAY_DIFF_CFO_C_M 0x7F0
|
#define FIX_SYNC_DGAIN_EN_C 0x0C44
|
#define FIX_SYNC_DGAIN_EN_C_M 0x800
|
#define OFST_SYNC_DAGC_C 0x0C44
|
#define OFST_SYNC_DAGC_C_M 0xF000
|
#define SYNC_DAGC_FREE_RUN_C 0x0C44
|
#define SYNC_DAGC_FREE_RUN_C_M 0x10000
|
#define FIX_SYNC_DGAIN_PWDB_C 0x0C44
|
#define FIX_SYNC_DGAIN_PWDB_C_M 0xFE0000
|
#define FIX_SYNC_DGAIN_C 0x0C44
|
#define FIX_SYNC_DGAIN_C_M 0xFF000000
|
#define MANUAL_FINE_CFO_C 0x0C48
|
#define MANUAL_FINE_CFO_C_M 0x3FFF
|
#define L1_CFO_CMP_EN_RTL_C 0x0C48
|
#define L1_CFO_CMP_EN_RTL_C_M 0x4000
|
#define DIS_CCA_MASK_C 0x0C48
|
#define DIS_CCA_MASK_C_M 0x8000
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#define FOLLOW_MAC_NDP_C 0x0C48
|
#define FOLLOW_MAC_NDP_C_M 0x10000
|
#define EN_LDPC_RX_C 0x0C48
|
#define EN_LDPC_RX_C_M 0x20000
|
#define VHTLEN_USE_LSIG_RX_BCC_C 0x0C48
|
#define VHTLEN_USE_LSIG_RX_BCC_C_M 0x40000
|
#define VHTLEN_USE_LSIG_RX_LDPC_C 0x0C48
|
#define VHTLEN_USE_LSIG_RX_LDPC_C_M 0x80000
|
#define RFC_TX_RATE_BIAS_AT_DL_OFDMA_C 0x0C48
|
#define RFC_TX_RATE_BIAS_AT_DL_OFDMA_C_M 0x300000
|
#define EN_SYNCDAGC_RFGCUP_C 0x0C48
|
#define EN_SYNCDAGC_RFGCUP_C_M 0x400000
|
#define RST_AGC_RPT_C 0x0C48
|
#define RST_AGC_RPT_C_M 0x800000
|
#define EN_AGC_RPT_C 0x0C48
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#define EN_AGC_RPT_C_M 0x1000000
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#define EN_FREERUN_C 0x0C48
|
#define EN_FREERUN_C_M 0x2000000
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#define OPT_FREERUN_C 0x0C48
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#define OPT_FREERUN_C_M 0x4000000
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#define SIZE_PWCAL_FREERUN_C 0x0C48
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#define SIZE_PWCAL_FREERUN_C_M 0x18000000
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#define HE_TB_RTL_C 0x0C48
|
#define HE_TB_RTL_C_M 0x20000000
|
#define SNDCCA_GNTBT_EN_C 0x0C48
|
#define SNDCCA_GNTBT_EN_C_M 0x40000000
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#define DIS_RST_BY_OFDM_ENABLE_C 0x0C48
|
#define DIS_RST_BY_OFDM_ENABLE_C_M 0x80000000
|
#define NCLKWAIT_LGY_C 0x0C4C
|
#define NCLKWAIT_LGY_C_M 0x3F
|
#define NCLKWAIT_HE_C 0x0C4C
|
#define NCLKWAIT_HE_C_M 0xFC0
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#define NCLKWAIT_ANTSW_C 0x0C4C
|
#define NCLKWAIT_ANTSW_C_M 0x3F000
|
#define NCLKWAIT_CCK_C 0x0C4C
|
#define NCLKWAIT_CCK_C_M 0xFC0000
|
#define NCLKWAIT_PRE_C 0x0C4C
|
#define NCLKWAIT_PRE_C_M 0x3F000000
|
#define NCLKWAIT_MANUAL_EN_C 0x0C4C
|
#define NCLKWAIT_MANUAL_EN_C_M 0x40000000
|
#define NCLKPW_MANUAL_EN_C 0x0C4C
|
#define NCLKPW_MANUAL_EN_C_M 0x80000000
|
#define NCLKWAIT_TIAEXTRA_C 0x0C50
|
#define NCLKWAIT_TIAEXTRA_C_M 0x3F
|
#define NCLKPW_MANUAL_PRE0_C 0x0C50
|
#define NCLKPW_MANUAL_PRE0_C_M 0xC0
|
#define NCLKPW_MANUAL_PRE1_C 0x0C50
|
#define NCLKPW_MANUAL_PRE1_C_M 0x300
|
#define MASK_POP_START_C 0x0C50
|
#define MASK_POP_START_C_M 0x1C00
|
#define MASK_POP_STOP_C 0x0C50
|
#define MASK_POP_STOP_C_M 0xFE000
|
#define DLY_FINETUNE_STF_C 0x0C50
|
#define DLY_FINETUNE_STF_C_M 0xFF00000
|
#define CG_RSSI_C 0x0C54
|
#define CG_RSSI_C_M 0x1
|
#define CG_SYNC_COMM_C 0x0C54
|
#define CG_SYNC_COMM_C_M 0x2
|
#define CG_BY_B_CCA_0_C 0x0C54
|
#define CG_BY_B_CCA_0_C_M 0x4
|
#define CG_BY_B_CCA_1_C 0x0C54
|
#define CG_BY_B_CCA_1_C_M 0x8
|
#define DIS_RST_SYNC_FSM_BY_B_PD_HIT_C 0x0C54
|
#define DIS_RST_SYNC_FSM_BY_B_PD_HIT_C_M 0x10
|
#define EN_PPDU_FIX_GAIN_C 0x0C54
|
#define EN_PPDU_FIX_GAIN_C_M 0x20
|
#define EN_CCA_PW_TH_C 0x0C54
|
#define EN_CCA_PW_TH_C_M 0x40
|
#define DIS_1RCCA_CCK_C 0x0C54
|
#define DIS_1RCCA_CCK_C_M 0x80
|
#define PATH_EN_NOT_FIND_80P80_C 0x0C54
|
#define PATH_EN_NOT_FIND_80P80_C_M 0xF00
|
#define DIS_CHANGE_PATH_80P80_C 0x0C54
|
#define DIS_CHANGE_PATH_80P80_C_M 0x1000
|
#define DIS_BRK_NOT_FIND_80P80_C 0x0C54
|
#define DIS_BRK_NOT_FIND_80P80_C_M 0x2000
|
#define BW80P80_C 0x0C54
|
#define BW80P80_C_M 0x1C000
|
#define HALT_WAIT_80P80_BY_RFGC_SEG0_C 0x0C54
|
#define HALT_WAIT_80P80_BY_RFGC_SEG0_C_M 0x20000
|
#define HALT_WAIT_80P80_BY_RFGC_SEG1_C 0x0C54
|
#define HALT_WAIT_80P80_BY_RFGC_SEG1_C_M 0x40000
|
#define DIS_1RCCA_OFDM_C 0x0C54
|
#define DIS_1RCCA_OFDM_C_M 0x80000
|
#define NSS_DEFINE_OPT_C 0x0C54
|
#define NSS_DEFINE_OPT_C_M 0x100000
|
#define BRK_RXTD_OPT_C 0x0C54
|
#define BRK_RXTD_OPT_C_M 0xFE00000
|
#define EN_SBDFT_C 0x0C54
|
#define EN_SBDFT_C_M 0x10000000
|
#define DIS_RST_BY_DIS_PD_FLAG_C 0x0C54
|
#define DIS_RST_BY_DIS_PD_FLAG_C_M 0x20000000
|
#define EN_RST_CHANGE_CORNER_C 0x0C54
|
#define EN_RST_CHANGE_CORNER_C_M 0x40000000
|
#define EN_POP_WHEN_TB_C 0x0C54
|
#define EN_POP_WHEN_TB_C_M 0x80000000
|
#define MASK_LSB_RXDFIR_C 0x0C58
|
#define MASK_LSB_RXDFIR_C_M 0xF
|
#define MASK_LSB_SYNC_PATH_C 0x0C58
|
#define MASK_LSB_SYNC_PATH_C_M 0xF0
|
#define TB_STS_ON_C 0x0C58
|
#define TB_STS_ON_C_M 0xFF00
|
#define SEL_RPTREG_C 0x0C58
|
#define SEL_RPTREG_C_M 0x30000
|
#define PW_HIT_OPT_C 0x0C58
|
#define PW_HIT_OPT_C_M 0x40000
|
#define PREAGC_RPT_OPT_C 0x0C58
|
#define PREAGC_RPT_OPT_C_M 0x80000
|
#define PATH_EN_FIX_C 0x0C58
|
#define PATH_EN_FIX_C_M 0x100000
|
#define TB_SYNC_PATH_END_OPT_C 0x0C58
|
#define TB_SYNC_PATH_END_OPT_C_M 0x200000
|
#define EN_SYNC_WHEN_TB_FIX_MODE_C 0x0C58
|
#define EN_SYNC_WHEN_TB_FIX_MODE_C_M 0x400000
|
#define TB_BW_COMB_OPT_C 0x0C58
|
#define TB_BW_COMB_OPT_C_M 0x800000
|
#define ELNA_INIT_IDX_C 0x0C58
|
#define ELNA_INIT_IDX_C_M 0x1000000
|
#define DIS_CCA_SPOOF_C 0x0C58
|
#define DIS_CCA_SPOOF_C_M 0x2000000
|
#define FORCE_CCA_SPOOF_C 0x0C58
|
#define FORCE_CCA_SPOOF_C_M 0x4000000
|
#define OPT_TB_KEEP_C 0x0C58
|
#define OPT_TB_KEEP_C_M 0x8000000
|
#define ON_SYNC_PATH_COMM_C 0x0C58
|
#define ON_SYNC_PATH_COMM_C_M 0x10000000
|
#define CONTI_CCA_PW_TH_C 0x0C58
|
#define CONTI_CCA_PW_TH_C_M 0x20000000
|
#define OPT_LMT_CCA_PW_TH_C 0x0C58
|
#define OPT_LMT_CCA_PW_TH_C_M 0xC0000000
|
#define LMT_PPDU_FIX_GAIN_C 0x0C5C
|
#define LMT_PPDU_FIX_GAIN_C_M 0xFF
|
#define LMT_CCA_PW_TH_C 0x0C5C
|
#define LMT_CCA_PW_TH_C_M 0xFF00
|
#define AGC_BT_SEL_PATH0_C 0x0C5C
|
#define AGC_BT_SEL_PATH0_C_M 0x30000
|
#define AGC_BT_SEL_PATH1_C 0x0C5C
|
#define AGC_BT_SEL_PATH1_C_M 0xC0000
|
#define AGC_BT_SEL_PATH2_C 0x0C5C
|
#define AGC_BT_SEL_PATH2_C_M 0x300000
|
#define AGC_BT_SEL_PATH3_C 0x0C5C
|
#define AGC_BT_SEL_PATH3_C_M 0xC00000
|
#define EN_TB_CCA_LMT_C 0x0C5C
|
#define EN_TB_CCA_LMT_C_M 0x1000000
|
#define TB_CCA_LMT_C 0x0C5C
|
#define TB_CCA_LMT_C_M 0xFE000000
|
#define IQK_DPK_CLK_ON_C 0x0C60
|
#define IQK_DPK_CLK_ON_C_M 0x1
|
#define EN_IOQ_IQK_DPK_C 0x0C60
|
#define EN_IOQ_IQK_DPK_C_M 0x2
|
#define IQK_OFDM_CCA_FORCE_ON_C 0x0C60
|
#define IQK_OFDM_CCA_FORCE_ON_C_M 0x4
|
#define IQK_CCK_CCA_FORCE_ON_C 0x0C60
|
#define IQK_CCK_CCA_FORCE_ON_C_M 0x8
|
#define RST_COMM_3_0__C 0x0C60
|
#define RST_COMM_3_0__C_M 0xF0
|
#define RST_COMM_SYNC_3_0__C 0x0C60
|
#define RST_COMM_SYNC_3_0__C_M 0xF00
|
#define RST_SYNC_3_0__C 0x0C60
|
#define RST_SYNC_3_0__C_M 0xF000
|
#define RST_COMM_5_4__C 0x0C60
|
#define RST_COMM_5_4__C_M 0x30000
|
#define RST_COMM_SYNC_5_4__C 0x0C60
|
#define RST_COMM_SYNC_5_4__C_M 0xC0000
|
#define RST_SYNC_5_4__C 0x0C60
|
#define RST_SYNC_5_4__C_M 0x300000
|
#define DLY_DET_OUT_C 0x0C60
|
#define DLY_DET_OUT_C_M 0xC00000
|
#define DLY_NORMAL_DET_OUT_C 0x0C60
|
#define DLY_NORMAL_DET_OUT_C_M 0x3000000
|
#define SNIFFER_MODE_C 0x0C60
|
#define SNIFFER_MODE_C_M 0x3C000000
|
#define OPT_LMT_PPDU_FIX_GAIN_C 0x0C60
|
#define OPT_LMT_PPDU_FIX_GAIN_C_M 0xC0000000
|
#define RFC_TX_CCK_IND_DIS_SEL_C 0x0C64
|
#define RFC_TX_CCK_IND_DIS_SEL_C_M 0xF
|
#define OPT_EN_CCA_PW_TH_C 0x0C64
|
#define OPT_EN_CCA_PW_TH_C_M 0x30
|
#define EN_2ND20_BW_C 0x0C64
|
#define EN_2ND20_BW_C_M 0x40
|
#define CG_BY_OFDM_ENABLE_0_C 0x0C64
|
#define CG_BY_OFDM_ENABLE_0_C_M 0x80
|
#define CG_BY_OFDM_ENABLE_1_C 0x0C64
|
#define CG_BY_OFDM_ENABLE_1_C_M 0x100
|
#define DIS_SBDFT_C 0x0C64
|
#define DIS_SBDFT_C_M 0x200
|
#define FPGA_OPT_PRD_C 0x0C64
|
#define FPGA_OPT_PRD_C_M 0xC00
|
#define MUX_ST_POP_C 0x0C64
|
#define MUX_ST_POP_C_M 0xF000
|
#define MUX_ST_VLD_POP_C 0x0C64
|
#define MUX_ST_VLD_POP_C_M 0xF0000
|
#define EN_CFIR_MODEL_C 0x0C64
|
#define EN_CFIR_MODEL_C_M 0x100000
|
#define LOCK_NBIFLT_C 0x0C64
|
#define LOCK_NBIFLT_C_M 0x200000
|
#define MANUAL_EN_CCA_PW_TH_C 0x0C64
|
#define MANUAL_EN_CCA_PW_TH_C_M 0x400000
|
#define CCA_PW_TH_C 0x0C64
|
#define CCA_PW_TH_C_M 0x7F800000
|
#define CCA_PW_TH_PRIORITY_C 0x0C64
|
#define CCA_PW_TH_PRIORITY_C_M 0x80000000
|
#define MAX_CNT_POP_C 0x0C68
|
#define MAX_CNT_POP_C_M 0xFF
|
#define CCA_MASK_CNT_POP_C 0x0C68
|
#define CCA_MASK_CNT_POP_C_M 0xFF00
|
#define OPT_ANT_EN_RSSI_C 0x0C68
|
#define OPT_ANT_EN_RSSI_C_M 0x10000
|
#define EN_NCLKWAIT_BY_IDX_C 0x0C68
|
#define EN_NCLKWAIT_BY_IDX_C_M 0x20000
|
#define OPT_MASK_POP_C 0x0C68
|
#define OPT_MASK_POP_C_M 0x40000
|
#define SYNCDLY_OFST_C 0x0C68
|
#define SYNCDLY_OFST_C_M 0xF80000
|
#define EN_SYNCDLY_OFST_PRIM_C 0x0C68
|
#define EN_SYNCDLY_OFST_PRIM_C_M 0x1000000
|
#define EN_SYNCDLY_OFST_DFE_C 0x0C68
|
#define EN_SYNCDLY_OFST_DFE_C_M 0x2000000
|
#define EN_SYNCDLY_OFST_DCCL_C 0x0C68
|
#define EN_SYNCDLY_OFST_DCCL_C_M 0x4000000
|
#define EN_SYNCDLY_OFST_SYNC_C 0x0C68
|
#define EN_SYNCDLY_OFST_SYNC_C_M 0x8000000
|
#define SBD_FAIL_OPT_C 0x0C68
|
#define SBD_FAIL_OPT_C_M 0x10000000
|
#define EN_POP_CFOE_LATE_C 0x0C68
|
#define EN_POP_CFOE_LATE_C_M 0x20000000
|
#define DIS_POP_CFOE_C 0x0C68
|
#define DIS_POP_CFOE_C_M 0x40000000
|
#define FORCE_SBD_BY_SYNC_DAGC_C 0x0C68
|
#define FORCE_SBD_BY_SYNC_DAGC_C_M 0x80000000
|
#define IQK_DPK_COM_RST_C 0x0C6C
|
#define IQK_DPK_COM_RST_C_M 0x1
|
#define FAGCRDY_DLY_C 0x0C6C
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#define FAGCRDY_DLY_C_M 0x1E
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#define INITRST_BY_BACKINIT_C 0x0C6C
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#define INITRST_BY_BACKINIT_C_M 0x20
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#define POP_MISS_BRK_EN_C 0x0C6C
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#define POP_MISS_BRK_EN_C_M 0x40
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#define RPT_CNT_OPT_C 0x0C6C
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#define RPT_CNT_OPT_C_M 0x380
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#define OPT_VLD_POP_C 0x0C6C
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#define OPT_VLD_POP_C_M 0x400
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#define CH_MUX_ST_MANUAL_C 0x0C6C
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#define CH_MUX_ST_MANUAL_C_M 0x800
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#define BT_GNT_SEG_OPT_C 0x0C6C
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#define BT_GNT_SEG_OPT_C_M 0x3000
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#define EN_PRERDY_BY_MAXITER_C 0x0C6C
|
#define EN_PRERDY_BY_MAXITER_C_M 0x4000
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#define RXTD_RESERVED_1_C 0x0C6C
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#define RXTD_RESERVED_1_C_M 0xFFFF8000
|
#define IQK_COM_TX_PATH_EN_FORCE_VAL_C 0x0C70
|
#define IQK_COM_TX_PATH_EN_FORCE_VAL_C_M 0xF
|
#define IQK_COM_TX_PATH_EN_FORCE_ON_C 0x0C70
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#define IQK_COM_TX_PATH_EN_FORCE_ON_C_M 0x10
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#define IQK_COM_RX_PATH_EN_FORCE_VAL_C 0x0C70
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#define IQK_COM_RX_PATH_EN_FORCE_VAL_C_M 0x1E0
|
#define IQK_COM_RX_PATH_EN_FORCE_ON_C 0x0C70
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#define IQK_COM_RX_PATH_EN_FORCE_ON_C_M 0x200
|
#define COLLISION_DET_EN_C 0x0C70
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#define COLLISION_DET_EN_C_M 0x400
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#define COLLISION_R2T_TH_C 0x0C70
|
#define COLLISION_R2T_TH_C_M 0xF800
|
#define COLLISION_R2T_PW_TIMING_C 0x0C70
|
#define COLLISION_R2T_PW_TIMING_C_M 0x30000
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#define COLLISION_T2R_PW_TIMING_C 0x0C70
|
#define COLLISION_T2R_PW_TIMING_C_M 0x40000
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#define COLLISION_PRIMARY_FLAG_C 0x0C70
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#define COLLISION_PRIMARY_FLAG_C_M 0x80000
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#define TX_COLLISION_T2R_ST_C 0x0C70
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#define TX_COLLISION_T2R_ST_C_M 0x3F00000
|
#define TX_COLLISION_R2T_ST_C 0x0C70
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#define TX_COLLISION_R2T_ST_C_M 0xFC000000
|
#define COLLISION_T2R_TH_MCS0_C 0x0C74
|
#define COLLISION_T2R_TH_MCS0_C_M 0x1F
|
#define COLLISION_T2R_TH_MCS1_C 0x0C74
|
#define COLLISION_T2R_TH_MCS1_C_M 0x3E0
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#define COLLISION_T2R_TH_MCS2_C 0x0C74
|
#define COLLISION_T2R_TH_MCS2_C_M 0x7C00
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#define COLLISION_T2R_TH_MCS3_C 0x0C74
|
#define COLLISION_T2R_TH_MCS3_C_M 0xF8000
|
#define COLLISION_T2R_TH_MCS4_C 0x0C74
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#define COLLISION_T2R_TH_MCS4_C_M 0x1F00000
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#define COLLISION_T2R_TH_MCS5_C 0x0C74
|
#define COLLISION_T2R_TH_MCS5_C_M 0x3E000000
|
#define TX_COLLISION_OR_CCA_MASK_C 0x0C74
|
#define TX_COLLISION_OR_CCA_MASK_C_M 0x80000000
|
#define COLLISION_T2R_TH_MCS6_C 0x0C78
|
#define COLLISION_T2R_TH_MCS6_C_M 0x1F
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#define COLLISION_T2R_TH_MCS7_C 0x0C78
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#define COLLISION_T2R_TH_MCS7_C_M 0x3E0
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#define COLLISION_T2R_TH_MCS8_C 0x0C78
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#define COLLISION_T2R_TH_MCS8_C_M 0x7C00
|
#define COLLISION_T2R_TH_MCS9_C 0x0C78
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#define COLLISION_T2R_TH_MCS9_C_M 0xF8000
|
#define COLLISION_T2R_TH_MCS10_C 0x0C78
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#define COLLISION_T2R_TH_MCS10_C_M 0x1F00000
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#define COLLISION_T2R_TH_MCS11_C 0x0C78
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#define COLLISION_T2R_TH_MCS11_C_M 0x3E000000
|
#define TXDAGC_DEF_N_RU0_3_C 0x0C78
|
#define TXDAGC_DEF_N_RU0_3_C_M 0x80000000
|
#define COLLISION_T2R_TH_CCK_C 0x0C7C
|
#define COLLISION_T2R_TH_CCK_C_M 0x1F
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#define TXDAGC_DBG_EN_C 0x0C7C
|
#define TXDAGC_DBG_EN_C_M 0x20
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#define DPD_OFF_BY_TXPW_TH_C 0x0C7C
|
#define DPD_OFF_BY_TXPW_TH_C_M 0x7FC0
|
#define DPD_OFF_BY_TXPW_OV_C 0x0C7C
|
#define DPD_OFF_BY_TXPW_OV_C_M 0x8000
|
#define DPD_OFF_BY_TXPW_BELOW_C 0x0C7C
|
#define DPD_OFF_BY_TXPW_BELOW_C_M 0x10000
|
#define T2F_ST_HANG_PROTECT_C 0x0C7C
|
#define T2F_ST_HANG_PROTECT_C_M 0x100000
|
#define TXRFC_RSTB_C 0x0C7C
|
#define TXRFC_RSTB_C_M 0x200000
|
#define DIS_TXRFC_IOWE_C 0x0C7C
|
#define DIS_TXRFC_IOWE_C_M 0x400000
|
#define DIS_TXRFC_IOQ_C 0x0C7C
|
#define DIS_TXRFC_IOQ_C_M 0x800000
|
#define T2F_BRK_PDHIT_AT_SAME_TIME_C 0x0C7C
|
#define T2F_BRK_PDHIT_AT_SAME_TIME_C_M 0x1000000
|
#define T2F_NEG_GI2OFST_CNT_TH_C 0x0C7C
|
#define T2F_NEG_GI2OFST_CNT_TH_C_M 0xFE000000
|
#define BRK_R_HT_BW020_1SS_BOUND_C 0x0D00
|
#define BRK_R_HT_BW020_1SS_BOUND_C_M 0xF
|
#define BRK_R_HT_BW020_2SS_BOUND_C 0x0D00
|
#define BRK_R_HT_BW020_2SS_BOUND_C_M 0xF0
|
#define BRK_R_HT_BW020_3SS_BOUND_C 0x0D00
|
#define BRK_R_HT_BW020_3SS_BOUND_C_M 0xF00
|
#define BRK_R_HT_BW020_4SS_BOUND_C 0x0D00
|
#define BRK_R_HT_BW020_4SS_BOUND_C_M 0xF000
|
#define BRK_R_HT_BW040_1SS_BOUND_C 0x0D00
|
#define BRK_R_HT_BW040_1SS_BOUND_C_M 0xF0000
|
#define BRK_R_HT_BW040_2SS_BOUND_C 0x0D00
|
#define BRK_R_HT_BW040_2SS_BOUND_C_M 0xF00000
|
#define BRK_R_HT_BW040_3SS_BOUND_C 0x0D00
|
#define BRK_R_HT_BW040_3SS_BOUND_C_M 0xF000000
|
#define BRK_R_HT_BW040_4SS_BOUND_C 0x0D00
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#define BRK_R_HT_BW040_4SS_BOUND_C_M 0xF0000000
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#define BRK_R_VHT_BW020_1SS_BOUND_C 0x0D04
|
#define BRK_R_VHT_BW020_1SS_BOUND_C_M 0xF
|
#define BRK_R_VHT_BW020_2SS_BOUND_C 0x0D04
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#define BRK_R_VHT_BW020_2SS_BOUND_C_M 0xF0
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#define BRK_R_VHT_BW020_3SS_BOUND_C 0x0D04
|
#define BRK_R_VHT_BW020_3SS_BOUND_C_M 0xF00
|
#define BRK_R_VHT_BW020_4SS_BOUND_C 0x0D04
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#define BRK_R_VHT_BW020_4SS_BOUND_C_M 0xF000
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#define BRK_R_VHT_BW040_1SS_BOUND_C 0x0D04
|
#define BRK_R_VHT_BW040_1SS_BOUND_C_M 0xF0000
|
#define BRK_R_VHT_BW040_2SS_BOUND_C 0x0D04
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#define BRK_R_VHT_BW040_2SS_BOUND_C_M 0xF00000
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#define BRK_R_VHT_BW040_3SS_BOUND_C 0x0D04
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#define BRK_R_VHT_BW040_3SS_BOUND_C_M 0xF000000
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#define BRK_R_VHT_BW040_4SS_BOUND_C 0x0D04
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#define BRK_R_VHT_BW040_4SS_BOUND_C_M 0xF0000000
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#define BRK_R_VHT_BW080_1SS_BOUND_C 0x0D08
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#define BRK_R_VHT_BW080_1SS_BOUND_C_M 0xF
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#define BRK_R_VHT_BW080_2SS_BOUND_C 0x0D08
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#define BRK_R_VHT_BW080_2SS_BOUND_C_M 0xF0
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#define BRK_R_VHT_BW080_3SS_BOUND_C 0x0D08
|
#define BRK_R_VHT_BW080_3SS_BOUND_C_M 0xF00
|
#define BRK_R_VHT_BW080_4SS_BOUND_C 0x0D08
|
#define BRK_R_VHT_BW080_4SS_BOUND_C_M 0xF000
|
#define BRK_R_VHT_BW160_1SS_BOUND_C 0x0D08
|
#define BRK_R_VHT_BW160_1SS_BOUND_C_M 0xF0000
|
#define BRK_R_VHT_BW160_2SS_BOUND_C 0x0D08
|
#define BRK_R_VHT_BW160_2SS_BOUND_C_M 0xF00000
|
#define BRK_R_VHT_BW160_3SS_BOUND_C 0x0D08
|
#define BRK_R_VHT_BW160_3SS_BOUND_C_M 0xF000000
|
#define BRK_R_VHT_BW160_4SS_BOUND_C 0x0D08
|
#define BRK_R_VHT_BW160_4SS_BOUND_C_M 0xF0000000
|
#define BRK_R_CHK_NDP_LSIG_VHT_C 0x0D0C
|
#define BRK_R_CHK_NDP_LSIG_VHT_C_M 0x1
|
#define BRK_R_CHK_NDP_LSIG_N_C 0x0D0C
|
#define BRK_R_CHK_NDP_LSIG_N_C_M 0x2
|
#define BRK_R_CHK_NDP_LSIG_VHT_34SS_C 0x0D0C
|
#define BRK_R_CHK_NDP_LSIG_VHT_34SS_C_M 0x4
|
#define BRK_R_CHK_NDP_LSIG_N_34SS_C 0x0D0C
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#define BRK_R_CHK_NDP_LSIG_N_34SS_C_M 0x8
|
#define BRK_R_VHT_MU_NSTS_LMT_C 0x0D0C
|
#define BRK_R_VHT_MU_NSTS_LMT_C_M 0x70
|
#define BRK_R_NSTS_SPEC_MU_SEL_C 0x0D0C
|
#define BRK_R_NSTS_SPEC_MU_SEL_C_M 0x780
|
#define BRK_R_L_LEN_OVER_TH_C 0x0D10
|
#define BRK_R_L_LEN_OVER_TH_C_M 0xFFF
|
#define BRK_R_L_LEN_UNDER_TH_C 0x0D10
|
#define BRK_R_L_LEN_UNDER_TH_C_M 0xF000
|
#define BRK_R_HT_LEN_UNDER_TH_C 0x0D10
|
#define BRK_R_HT_LEN_UNDER_TH_C_M 0xF0000
|
#define BRK_R_VHT_LEN_UNDER_TH_C 0x0D10
|
#define BRK_R_VHT_LEN_UNDER_TH_C_M 0xF00000
|
#define BRK_R_VHT_BW_SUPPORT_C 0x0D10
|
#define BRK_R_VHT_BW_SUPPORT_C_M 0x3000000
|
#define BRK_R_VHT_BW_SUPPORT_FORCE_C 0x0D10
|
#define BRK_R_VHT_BW_SUPPORT_FORCE_C_M 0x4000000
|
#define BRK_R_RX_SUPPORT_BW_C 0x0D10
|
#define BRK_R_RX_SUPPORT_BW_C_M 0x38000000
|
#define BRK_R_BRK_SEL_FOR_CNT_C 0x0D14
|
#define BRK_R_BRK_SEL_FOR_CNT_C_M 0xFF
|
#define BRK_R_HT_LEN_MAX_C 0x0D14
|
#define BRK_R_HT_LEN_MAX_C_M 0xFF00
|
#define BRK_R_VHT_LEN_MAX_C 0x0D14
|
#define BRK_R_VHT_LEN_MAX_C_M 0x3FFF0000
|
#define BRK_R_LRATE_DIS_C 0x0D18
|
#define BRK_R_LRATE_DIS_C_M 0xFF
|
#define BRK_R_HT_MCS_LMT_C 0x0D18
|
#define BRK_R_HT_MCS_LMT_C_M 0x300
|
#define BRK_R_EN_HT_MCS32_C 0x0D18
|
#define BRK_R_EN_HT_MCS32_C_M 0x400
|
#define BRK_R_EN_LDPC_RX_C 0x0D18
|
#define BRK_R_EN_LDPC_RX_C_M 0x800
|
#define BRK_R_EN_HT_SHORTGI_C 0x0D18
|
#define BRK_R_EN_HT_SHORTGI_C_M 0x1000
|
#define BRK_R_DIS_MASK_ILL_RATE_C 0x0D18
|
#define BRK_R_DIS_MASK_ILL_RATE_C_M 0x2000
|
#define BRK_R_EN_VHT_SHORTGI_C 0x0D18
|
#define BRK_R_EN_VHT_SHORTGI_C_M 0x8000
|
#define BRK_R_EN_VHT_LEN_LMT_C 0x0D18
|
#define BRK_R_EN_VHT_LEN_LMT_C_M 0x10000
|
#define BRK_R_HT_NOT_SUPPORT_C 0x0D18
|
#define BRK_R_HT_NOT_SUPPORT_C_M 0x20000
|
#define BRK_R_VHT_NOT_SUPPORT_C 0x0D18
|
#define BRK_R_VHT_NOT_SUPPORT_C_M 0x40000
|
#define BRK_R_OFDM_VBON_NEG_BRK_OPT_C 0x0D18
|
#define BRK_R_OFDM_VBON_NEG_BRK_OPT_C_M 0x180000
|
#define BRK_R_VHT_NSS_LMT_C 0x0D18
|
#define BRK_R_VHT_NSS_LMT_C_M 0x600000
|
#define BRK_R_BYPASS_VHT_NOT_SUPPORT_NSS_C 0x0D18
|
#define BRK_R_BYPASS_VHT_NOT_SUPPORT_NSS_C_M 0x1000000
|
#define BRK_R_EN_HT_STBC_1SS_C 0x0D18
|
#define BRK_R_EN_HT_STBC_1SS_C_M 0x10000000
|
#define BRK_R_EN_HT_STBC_2SS_C 0x0D18
|
#define BRK_R_EN_HT_STBC_2SS_C_M 0x20000000
|
#define BRK_R_EN_VHT_STBC_1SS_C 0x0D18
|
#define BRK_R_EN_VHT_STBC_1SS_C_M 0x40000000
|
#define BRK_R_EN_VHT_STBC_2SS_C 0x0D18
|
#define BRK_R_EN_VHT_STBC_2SS_C_M 0x80000000
|
#define BRK_R_ILL_ST0_C 0x0D20
|
#define BRK_R_ILL_ST0_C_M 0xFFFFFFFF
|
#define BRK_R_ILL_ST1_C 0x0D24
|
#define BRK_R_ILL_ST1_C_M 0xFFFFFFFF
|
#define BRK_R_ILL_ST2_C 0x0D28
|
#define BRK_R_ILL_ST2_C_M 0xFFFFFFFF
|
#define BRK_R_ILL_ST3_C 0x0D2C
|
#define BRK_R_ILL_ST3_C_M 0xFFFFFFFF
|
#define BRK_R_ILL_ST0_EN_C 0x0D30
|
#define BRK_R_ILL_ST0_EN_C_M 0xFFFFFFFF
|
#define BRK_R_ILL_ST1_EN_C 0x0D34
|
#define BRK_R_ILL_ST1_EN_C_M 0xFFFFFFFF
|
#define BRK_R_ILL_ST2_EN_C 0x0D38
|
#define BRK_R_ILL_ST2_EN_C_M 0xFFFFFFFF
|
#define BRK_R_ILL_ST3_EN_C 0x0D3C
|
#define BRK_R_ILL_ST3_EN_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_31_0__C 0x0D40
|
#define BRK_R_BRK_OPT_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_63_32__C 0x0D44
|
#define BRK_R_BRK_OPT_63_32__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_95_64__C 0x0D48
|
#define BRK_R_BRK_OPT_95_64__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_127_96__C 0x0D4C
|
#define BRK_R_BRK_OPT_127_96__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_NDP_31_0__C 0x0D50
|
#define BRK_R_BRK_OPT_NDP_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_NDP_63_32__C 0x0D54
|
#define BRK_R_BRK_OPT_NDP_63_32__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_NDP_95_64__C 0x0D58
|
#define BRK_R_BRK_OPT_NDP_95_64__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_NDP_127_96__C 0x0D5C
|
#define BRK_R_BRK_OPT_NDP_127_96__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT5_C 0x0D60
|
#define BRK_R_BRK_OPT5_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT5_NDP_C 0x0D64
|
#define BRK_R_BRK_OPT5_NDP_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT_MU_C 0x0D70
|
#define BRK_R_BRK_OPT_MU_C_M 0xFFFFFFFF
|
#define BRK_R_T2F_PDHIT_ST_LMT_IDX_C 0x0D78
|
#define BRK_R_T2F_PDHIT_ST_LMT_IDX_C_M 0x3
|
#define BRK_R_T2F_PFD3_ST_LMT_IDX_C 0x0D78
|
#define BRK_R_T2F_PFD3_ST_LMT_IDX_C_M 0x4
|
#define BRK_R_WATCH_DOG_ALWAYS_CHK_TXEN_C 0x0D78
|
#define BRK_R_WATCH_DOG_ALWAYS_CHK_TXEN_C_M 0x10
|
#define BRK_R_EN_HT_N_ESS_C 0x0D7C
|
#define BRK_R_EN_HT_N_ESS_C_M 0x1
|
#define BRK_R_EN_SOUND_WO_NDP_C 0x0D7C
|
#define BRK_R_EN_SOUND_WO_NDP_C_M 0x2
|
#define BRK_R_WATCH_DOG_TX_DUR_DATA_ON_C 0x0D7C
|
#define BRK_R_WATCH_DOG_TX_DUR_DATA_ON_C_M 0x4
|
#define BRK_R_WATCH_DOG_STBC_EXT_US_C 0x0D7C
|
#define BRK_R_WATCH_DOG_STBC_EXT_US_C_M 0x8
|
#define BRK_R_NORMAL_CCA_LMT_C 0x0D7C
|
#define BRK_R_NORMAL_CCA_LMT_C_M 0x7F0
|
#define BRK_R_EXTEND_CCA_LMT_C 0x0D7C
|
#define BRK_R_EXTEND_CCA_LMT_C_M 0x7F000
|
#define BRK_R_SPOOF_IVLD_PKT_EN_C 0x0D7C
|
#define BRK_R_SPOOF_IVLD_PKT_EN_C_M 0x80000
|
#define BRK_R_SPOOF_RXTD_EN_C 0x0D7C
|
#define BRK_R_SPOOF_RXTD_EN_C_M 0x100000
|
#define BRK_R_WATCH_DOG_NDP_EXT_US_C 0x0D7C
|
#define BRK_R_WATCH_DOG_NDP_EXT_US_C_M 0x800000
|
#define BRK_R_NDP_CCA_LMT_C 0x0D7C
|
#define BRK_R_NDP_CCA_LMT_C_M 0x7F000000
|
#define BRK_R_HE_SU_NOT_SUPPORT_C 0x0D80
|
#define BRK_R_HE_SU_NOT_SUPPORT_C_M 0x1
|
#define BRK_R_HE_MU_NOT_SUPPORT_C 0x0D80
|
#define BRK_R_HE_MU_NOT_SUPPORT_C_M 0x2
|
#define BRK_R_HE_ERSU_NOT_SUPPORT_C 0x0D80
|
#define BRK_R_HE_ERSU_NOT_SUPPORT_C_M 0x4
|
#define BRK_R_HE_TB_NOT_SUPPORT_C 0x0D80
|
#define BRK_R_HE_TB_NOT_SUPPORT_C_M 0x8
|
#define BRK_R_HE_STBC_NOT_SUPPORT_C 0x0D80
|
#define BRK_R_HE_STBC_NOT_SUPPORT_C_M 0x10
|
#define BRK_R_HE_DCM_NOT_SUPPORT_C 0x0D80
|
#define BRK_R_HE_DCM_NOT_SUPPORT_C_M 0x20
|
#define BRK_R_HE_N_USER_MAX_C 0x0D80
|
#define BRK_R_HE_N_USER_MAX_C_M 0x3FC0
|
#define BRK_R_HE_MAX_NSS_C 0x0D80
|
#define BRK_R_HE_MAX_NSS_C_M 0x1C000
|
#define BRK_R_HE_STBC_NSS_LMT_C 0x0D80
|
#define BRK_R_HE_STBC_NSS_LMT_C_M 0xE0000
|
#define BRK_R_HE_DCM_NSS_LMT_C 0x0D80
|
#define BRK_R_HE_DCM_NSS_LMT_C_M 0x700000
|
#define BRK_R_TB_MAX_NSS_C 0x0D80
|
#define BRK_R_TB_MAX_NSS_C_M 0x3800000
|
#define BRK_R_TB_STBC_NSS_LMT_C 0x0D80
|
#define BRK_R_TB_STBC_NSS_LMT_C_M 0x1C000000
|
#define BRK_R_TB_DCM_NSS_LMT_C 0x0D80
|
#define BRK_R_TB_DCM_NSS_LMT_C_M 0xE0000000
|
#define BRK_R_EN_HE_GI_0P8_C 0x0D84
|
#define BRK_R_EN_HE_GI_0P8_C_M 0x1
|
#define BRK_R_EN_HE_GI_1P6_C 0x0D84
|
#define BRK_R_EN_HE_GI_1P6_C_M 0x2
|
#define BRK_R_EN_HE_GI_3P2_C 0x0D84
|
#define BRK_R_EN_HE_GI_3P2_C_M 0x4
|
#define BRK_R_EN_HE_DOPPLER_C 0x0D84
|
#define BRK_R_EN_HE_DOPPLER_C_M 0x8
|
#define BRK_R_HE_MU_BCC_NSS_LMT_C 0x0D84
|
#define BRK_R_HE_MU_BCC_NSS_LMT_C_M 0x70
|
#define BRK_R_HEMU_MULTI_USER_MUMIMO_EN_C 0x0D84
|
#define BRK_R_HEMU_MULTI_USER_MUMIMO_EN_C_M 0x80
|
#define BRK_R_TB_MUMIMO_EN_C 0x0D84
|
#define BRK_R_TB_MUMIMO_EN_C_M 0x100
|
#define BRK_R_EN_HE_BEAM_CHANGE_C 0x0D84
|
#define BRK_R_EN_HE_BEAM_CHANGE_C_M 0x200
|
#define BRK_R_EN_HE_PREAMBLE_PUNC_C 0x0D84
|
#define BRK_R_EN_HE_PREAMBLE_PUNC_C_M 0x400
|
#define BRK_R_EN_HE_ZERO_USER_C 0x0D84
|
#define BRK_R_EN_HE_ZERO_USER_C_M 0x800
|
#define BRK_R_EN_HESU_TB_TYPE_C 0x0D84
|
#define BRK_R_EN_HESU_TB_TYPE_C_M 0x1000
|
#define BRK_R_CHK_20M_RU_ALLOC_EN_C 0x0D84
|
#define BRK_R_CHK_20M_RU_ALLOC_EN_C_M 0x2000
|
#define BRK_R_EN_NDP_NEG_CLR_COND_C 0x0D84
|
#define BRK_R_EN_NDP_NEG_CLR_COND_C_M 0x4000
|
#define BRK_R_SPOOF_FOR_ASYNC_RST_EN_C 0x0D84
|
#define BRK_R_SPOOF_FOR_ASYNC_RST_EN_C_M 0x8000
|
#define BRK_R_EN_HE_MSSBCC_MIX_LDPC_C 0x0D84
|
#define BRK_R_EN_HE_MSSBCC_MIX_LDPC_C_M 0x10000
|
#define BRK_R_RUALLOC_NOT_MAP_RU1992_C 0x0D84
|
#define BRK_R_RUALLOC_NOT_MAP_RU1992_C_M 0x20000
|
#define BRK_R_CHK_ST_IDX_T2F_C 0x0D88
|
#define BRK_R_CHK_ST_IDX_T2F_C_M 0x3F
|
#define BRK_R_ST_HANG_LMT_T2F_C 0x0D88
|
#define BRK_R_ST_HANG_LMT_T2F_C_M 0x7F00
|
#define BRK_R_CHK_ST_IDX_RX_FEQ_C 0x0D88
|
#define BRK_R_CHK_ST_IDX_RX_FEQ_C_M 0x1F0000
|
#define BRK_R_ST_HANG_LMT_RX_FEQ_C 0x0D88
|
#define BRK_R_ST_HANG_LMT_RX_FEQ_C_M 0x7F000000
|
#define BRK_R_BRK_OPT6_HE_USER_31_0__C 0x0D90
|
#define BRK_R_BRK_OPT6_HE_USER_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT7_SPOOF_HE_USER_31_0__C 0x0D94
|
#define BRK_R_BRK_OPT7_SPOOF_HE_USER_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT8_TB_USER_31_0__C 0x0D98
|
#define BRK_R_BRK_OPT8_TB_USER_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT9_SPOOF_TB_USER_31_0__C 0x0D9C
|
#define BRK_R_BRK_OPT9_SPOOF_TB_USER_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT6_HE_USER_NDP_31_0__C 0x0DA0
|
#define BRK_R_BRK_OPT6_HE_USER_NDP_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT7_SPOOF_HE_USER_NDP_31_0__C 0x0DA4
|
#define BRK_R_BRK_OPT7_SPOOF_HE_USER_NDP_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT8_TB_USER_NDP_31_0__C 0x0DA8
|
#define BRK_R_BRK_OPT8_TB_USER_NDP_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_OPT9_SPOOF_TB_USER_NDP_31_0__C 0x0DAC
|
#define BRK_R_BRK_OPT9_SPOOF_TB_USER_NDP_31_0__C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_1_C 0x0DC0
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_1_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_2_C 0x0DC4
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_2_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_3_C 0x0DC8
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_3_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_4_C 0x0DCC
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_4_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_5_C 0x0DD0
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_5_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_6_C 0x0DD4
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_6_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_7_C 0x0DD8
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_7_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_8_C 0x0DDC
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_8_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_9_C 0x0DE0
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_9_C_M 0xFFFFFFFF
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_MU_C 0x0DE4
|
#define BRK_R_BRK_FOR_ASYNC_RST_EN_MU_C_M 0xFFFFFFFF
|
#define PATH0_R_DAC_QINV_C 0x1000
|
#define PATH0_R_DAC_QINV_C_M 0x1
|
#define PATH0_R_FIFO_CLR_ENB_C 0x1000
|
#define PATH0_R_FIFO_CLR_ENB_C_M 0x10
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#define PATH0_R_T2F_FREERUN_BUF_EN_C 0x1004
|
#define PATH0_R_T2F_FREERUN_BUF_EN_C_M 0x1
|
#define PATH0_R_T2F_L1_LATE_EN_C 0x1004
|
#define PATH0_R_T2F_L1_LATE_EN_C_M 0x2
|
#define PATH0_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C 0x1004
|
#define PATH0_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C_M 0x10
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#define PATH0_R_T2F_DCCL_FILT_EN_C 0x1004
|
#define PATH0_R_T2F_DCCL_FILT_EN_C_M 0x100
|
#define PATH0_R_BT_GNT_RXTD_LATCH_EN_C 0x1004
|
#define PATH0_R_BT_GNT_RXTD_LATCH_EN_C_M 0x1000
|
#define PATH0_R_TD_CLK_GCK_EN_C 0x1008
|
#define PATH0_R_TD_CLK_GCK_EN_C_M 0x1
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#define PATH0_R_1RCCA_CLK_GCK_ON_C 0x1008
|
#define PATH0_R_1RCCA_CLK_GCK_ON_C_M 0x10
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#define PATH0_R_SYNC_RST_EN_TD_PATH_C 0x100C
|
#define PATH0_R_SYNC_RST_EN_TD_PATH_C_M 0x1
|
#define PATH0_R_SYNC_RST_EN_FFT_C 0x100C
|
#define PATH0_R_SYNC_RST_EN_FFT_C_M 0x10
|
#define PATH0_R_SYNC_RST_EN_TXBUF_C 0x100C
|
#define PATH0_R_SYNC_RST_EN_TXBUF_C_M 0x100
|
#define PATH0_R_SYNC_RST_EN_RXBUF_C 0x100C
|
#define PATH0_R_SYNC_RST_EN_RXBUF_C_M 0x1000
|
#define PATH0_R_SYNC_RST_EN_DCCL_C 0x100C
|
#define PATH0_R_SYNC_RST_EN_DCCL_C_M 0x10000
|
#define PATH0_R_SYNC_RST_EN_T2F_C 0x100C
|
#define PATH0_R_SYNC_RST_EN_T2F_C_M 0x100000
|
#define PATH0_R_SYNC_RST_EN_RXFIR_COMP_C 0x100C
|
#define PATH0_R_SYNC_RST_EN_RXFIR_COMP_C_M 0x1000000
|
#define PATH0_R_DCCL_CFO_TH_EN_C 0x1010
|
#define PATH0_R_DCCL_CFO_TH_EN_C_M 0x1
|
#define PATH0_R_DCCL_52B_SYMB_TH_EN_C 0x1010
|
#define PATH0_R_DCCL_52B_SYMB_TH_EN_C_M 0x10
|
#define PATH0_R_DCCL_52B_SYMB_TH_SEL_C 0x1010
|
#define PATH0_R_DCCL_52B_SYMB_TH_SEL_C_M 0x20
|
#define PATH0_R_TX_STO_TRIG_SELECT_C 0x1014
|
#define PATH0_R_TX_STO_TRIG_SELECT_C_M 0x1
|
#define PATH0_R_TX_STO_FIRST_PE_SELECT_C 0x1014
|
#define PATH0_R_TX_STO_FIRST_PE_SELECT_C_M 0x2
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_L_C 0x1018
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_L_C_M 0x7
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_L_C 0x1018
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_L_C_M 0x70
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_L_C 0x1018
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_L_C_M 0x700
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_L_C 0x1018
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_L_C_M 0x7000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_L_C 0x1018
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_L_C_M 0x70000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_L_C 0x1018
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_L_C_M 0x700000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_L_C 0x1018
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_L_C_M 0x7000000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_L_C 0x1018
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_L_C_M 0x70000000
|
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_L_C 0x101C
|
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_L_C_M 0x8
|
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C 0x101C
|
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C_M 0x10
|
#define PATH0_R_STO_INT_SEL_L_C 0x101C
|
#define PATH0_R_STO_INT_SEL_L_C_M 0x20
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C 0x101C
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C_M 0x380
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_L_C 0x101C
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_L_C_M 0x400
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_L_C 0x101C
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_L_C_M 0x800
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_L_C 0x101C
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_L_C_M 0x1000
|
#define PATH0_R_TXCFO_RX_OFST_C 0x101C
|
#define PATH0_R_TXCFO_RX_OFST_C_M 0xF0000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HT_C 0x1020
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HT_C_M 0x7
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HT_C 0x1020
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HT_C_M 0x70
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HT_C 0x1020
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HT_C_M 0x700
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HT_C 0x1020
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HT_C_M 0x7000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HT_C 0x1020
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HT_C_M 0x70000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HT_C 0x1020
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HT_C_M 0x700000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HT_C 0x1020
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HT_C_M 0x7000000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HT_C 0x1020
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HT_C_M 0x70000000
|
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HT_C 0x1024
|
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HT_C_M 0x8
|
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C 0x1024
|
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C_M 0x10
|
#define PATH0_R_STO_INT_SEL_HT_C 0x1024
|
#define PATH0_R_STO_INT_SEL_HT_C_M 0x20
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C 0x1024
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C_M 0x380
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HT_C 0x1024
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HT_C_M 0x400
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HT_C 0x1024
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HT_C_M 0x800
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HT_C 0x1024
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HT_C_M 0x1000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_VHT_C 0x1028
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_VHT_C_M 0x7
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_VHT_C 0x1028
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_VHT_C_M 0x70
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_VHT_C 0x1028
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_VHT_C_M 0x700
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_VHT_C 0x1028
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_VHT_C_M 0x7000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_VHT_C 0x1028
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_VHT_C_M 0x70000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_VHT_C 0x1028
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_VHT_C_M 0x700000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_VHT_C 0x1028
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_VHT_C_M 0x7000000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_VHT_C 0x1028
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_VHT_C_M 0x70000000
|
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_VHT_C 0x102C
|
#define PATH0_R_TX_STO_INT1_BYPASS_MODE_VHT_C_M 0x8
|
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C 0x102C
|
#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C_M 0x10
|
#define PATH0_R_STO_INT_SEL_VHT_C 0x102C
|
#define PATH0_R_STO_INT_SEL_VHT_C_M 0x20
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C 0x102C
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C_M 0x380
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C 0x102C
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C_M 0x400
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C 0x102C
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C_M 0x800
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C 0x102C
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C_M 0x1000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HE_C 0x1030
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET1_HE_C_M 0x7
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HE_C 0x1030
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET2_HE_C_M 0x70
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HE_C 0x1030
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET3_HE_C_M 0x700
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HE_C 0x1030
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET4_HE_C_M 0x7000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HE_C 0x1030
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET5_HE_C_M 0x70000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HE_C 0x1030
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET6_HE_C_M 0x700000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HE_C 0x1030
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET7_HE_C_M 0x7000000
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HE_C 0x1030
|
#define PATH0_R_TX_STO_INT_PART_BP_TARGET8_HE_C_M 0x70000000
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#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HE_C 0x1034
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#define PATH0_R_TX_STO_INT1_BYPASS_MODE_HE_C_M 0x8
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#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C 0x1034
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#define PATH0_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C_M 0x10
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#define PATH0_R_STO_INT_SEL_HE_C 0x1034
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#define PATH0_R_STO_INT_SEL_HE_C_M 0x20
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#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C 0x1034
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#define PATH0_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C_M 0x380
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#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HE_C 0x1034
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_20M_HE_C_M 0x400
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#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HE_C 0x1034
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_40M_HE_C_M 0x800
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#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HE_C 0x1034
|
#define PATH0_R_STO7_NXT_SYMBOL_SEL_80M_HE_C_M 0x1000
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#define PATH0_R_HW_SI_READ_ADDR_C 0x1200
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#define PATH0_R_HW_SI_READ_ADDR_C_M 0xFF
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#define PATH0_R_HW_SI_READ_EDGE_OPT_C 0x1200
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#define PATH0_R_HW_SI_READ_EDGE_OPT_C_M 0x300
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#define PATH0_R_HW_SI_ZERO_PADDING_EN_C 0x1200
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#define PATH0_R_HW_SI_ZERO_PADDING_EN_C_M 0x8000
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#define PATH0_R_HW_SI_BYPASS_ST_MASK_C 0x1200
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#define PATH0_R_HW_SI_BYPASS_ST_MASK_C_M 0x10000
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#define PATH0_R_HW_SI_DATA_E_INV_C 0x1200
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#define PATH0_R_HW_SI_DATA_E_INV_C_M 0x20000
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#define PATH0_R_HW_SI_SEL_DBG_C 0x1200
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#define PATH0_R_HW_SI_SEL_DBG_C_M 0xC0000
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#define PATH0_R_HW_SI_DBG_MODE_C 0x1200
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#define PATH0_R_HW_SI_DBG_MODE_C_M 0x100000
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#define PATH0_R_HW_SI_ZERO_PADDING_NUM_C 0x1200
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#define PATH0_R_HW_SI_ZERO_PADDING_NUM_C_M 0x3E00000
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#define PATH0_R_HW_SI_DBG_TX_TRIG_C 0x1200
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#define PATH0_R_HW_SI_DBG_TX_TRIG_C_M 0x4000000
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#define PATH0_R_HW_SI_DIS_W_RX_TRIG_C 0x1200
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#define PATH0_R_HW_SI_DIS_W_RX_TRIG_C_M 0x10000000
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#define PATH0_R_HW_SI_DIS_W_TX_TRIG_C 0x1200
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#define PATH0_R_HW_SI_DIS_W_TX_TRIG_C_M 0x20000000
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#define PATH0_R_HW_SI_DIS_R_TRIG_C 0x1200
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#define PATH0_R_HW_SI_DIS_R_TRIG_C_M 0x40000000
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#define PATH0_R_HW_SI_DBG_RX_CMD_0_C 0x1204
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#define PATH0_R_HW_SI_DBG_RX_CMD_0_C_M 0xFFFF
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#define PATH0_R_HW_SI_DBG_RX_CMD_1_C 0x1204
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#define PATH0_R_HW_SI_DBG_RX_CMD_1_C_M 0xFFFF0000
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#define PATH0_R_HW_SI_DBG_TX_CMD_0_C 0x1208
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#define PATH0_R_HW_SI_DBG_TX_CMD_0_C_M 0xFFFF
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#define PATH0_R_HW_SI_DBG_TX_CMD_1_C 0x1208
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#define PATH0_R_HW_SI_DBG_TX_CMD_1_C_M 0xFFFF0000
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#define PATH0_R_ANAPAR_ST1P5_SEL_C 0x120C
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#define PATH0_R_ANAPAR_ST1P5_SEL_C_M 0xF
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#define PATH0_R_ANAPAR_ST3P5_SEL_C 0x120C
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#define PATH0_R_ANAPAR_ST3P5_SEL_C_M 0xF0
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#define PATH0_R_ANAPAR_DIS_TSSI_DCK_ST_C 0x120C
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#define PATH0_R_ANAPAR_DIS_TSSI_DCK_ST_C_M 0x80000000
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#define PATH0_R_RFMODE_RSTB_EQ0_EN_C 0x1210
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#define PATH0_R_RFMODE_RSTB_EQ0_EN_C_M 0x1
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#define PATH0_R_PW_RSTB_EQ0_EN_C 0x1210
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#define PATH0_R_PW_RSTB_EQ0_EN_C_M 0x2
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#define PATH0_R_RSTB_EQ0_EN_C 0x1210
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#define PATH0_R_RSTB_EQ0_EN_C_M 0x4
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#define PATH0_R_RFMODE_RSTB_EQ0_C 0x1210
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#define PATH0_R_RFMODE_RSTB_EQ0_C_M 0xF0
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#define PATH0_R_PW_RSTB_EQ0_C 0x1210
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#define PATH0_R_PW_RSTB_EQ0_C_M 0xFF00
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#define PATH0_R_RSTB_EQ0_C 0x1210
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#define PATH0_R_RSTB_EQ0_C_M 0xFFFF0000
|
#define PATH0_R_RFC_SI_SEL_0_C 0x1214
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#define PATH0_R_RFC_SI_SEL_0_C_M 0x1
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#define PATH0_R_RFC_SI_SEL_1_C 0x1214
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#define PATH0_R_RFC_SI_SEL_1_C_M 0x10
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#define PATH0_R_HW_SI_W_RX_TRIG_DLY_EN_C 0x1218
|
#define PATH0_R_HW_SI_W_RX_TRIG_DLY_EN_C_M 0x1
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#define PATH0_R_HW_SI_W_TX_TRIG_DLY_EN_C 0x1218
|
#define PATH0_R_HW_SI_W_TX_TRIG_DLY_EN_C_M 0x2
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#define PATH0_R_HW_SI_R_TRIG_DLY_EN_C 0x1218
|
#define PATH0_R_HW_SI_R_TRIG_DLY_EN_C_M 0x4
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#define PATH0_R_HW_SI_W_RX_TRIG_DLY_C 0x1218
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#define PATH0_R_HW_SI_W_RX_TRIG_DLY_C_M 0xF0
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#define PATH0_R_HW_SI_W_TX_TRIG_DLY_C 0x1218
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#define PATH0_R_HW_SI_W_TX_TRIG_DLY_C_M 0xF00
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#define PATH0_R_HW_SI_R_TRIG_DLY_C 0x1218
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#define PATH0_R_HW_SI_R_TRIG_DLY_C_M 0xF000
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#define PATH0_R_ANAPAR_RST_SEL_C 0x12A0
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#define PATH0_R_ANAPAR_RST_SEL_C_M 0xF
|
#define PATH0_R_ANAPAR_RST_TX_SEL_C 0x12A0
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#define PATH0_R_ANAPAR_RST_TX_SEL_C_M 0xF0
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#define PATH0_R_ANAPAR_CTSDM_131_128__C 0x12A0
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#define PATH0_R_ANAPAR_CTSDM_131_128__C_M 0xF00
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#define PATH0_R_TXCK_FORCE_VAL_C 0x12A0
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#define PATH0_R_TXCK_FORCE_VAL_C_M 0x7000
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#define PATH0_R_TXCK_FORCE_ON_C 0x12A0
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#define PATH0_R_TXCK_FORCE_ON_C_M 0x8000
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#define PATH0_R_RXCK_FORCE_VAL_C 0x12A0
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#define PATH0_R_RXCK_FORCE_VAL_C_M 0x70000
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#define PATH0_R_RXCK_FORCE_ON_C 0x12A0
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#define PATH0_R_RXCK_FORCE_ON_C_M 0x80000
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#define PATH0_R_RXCK_RFBW0_C 0x12A0
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#define PATH0_R_RXCK_RFBW0_C_M 0x700000
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#define PATH0_R_RXCK_RFBW1_C 0x12A0
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#define PATH0_R_RXCK_RFBW1_C_M 0x3800000
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#define PATH0_R_RXCK_RFBW2_C 0x12A0
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#define PATH0_R_RXCK_RFBW2_C_M 0x1C000000
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#define PATH0_R_RXCK_RFBW3_C 0x12A0
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#define PATH0_R_RXCK_RFBW3_C_M 0xE0000000
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#define PATH0_R_RXCK_RFBW4_C 0x12A4
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#define PATH0_R_RXCK_RFBW4_C_M 0x7
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#define PATH0_R_RXCK_RFBW5_C 0x12A4
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#define PATH0_R_RXCK_RFBW5_C_M 0x38
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#define PATH0_R_RXCK_RFBW6_C 0x12A4
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#define PATH0_R_RXCK_RFBW6_C_M 0x1C0
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#define PATH0_R_TXCK_RFBW0_C 0x12A4
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#define PATH0_R_TXCK_RFBW0_C_M 0x3800
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#define PATH0_R_TXCK_RFBW1_C 0x12A4
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#define PATH0_R_TXCK_RFBW1_C_M 0x1C000
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#define PATH0_R_TXCK_RFBW2_C 0x12A4
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#define PATH0_R_TXCK_RFBW2_C_M 0xE0000
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#define PATH0_R_TXCK_RFBW3_C 0x12A4
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#define PATH0_R_TXCK_RFBW3_C_M 0x700000
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#define PATH0_R_TXCK_RFBW4_C 0x12A4
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#define PATH0_R_TXCK_RFBW4_C_M 0x3800000
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#define PATH0_R_TXCK_RFBW5_C 0x12A4
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#define PATH0_R_TXCK_RFBW5_C_M 0x1C000000
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#define PATH0_R_TXCK_RFBW6_C 0x12A4
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#define PATH0_R_TXCK_RFBW6_C_M 0xE0000000
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#define PATH0_R_EN_RXCK_TX_C 0x12A8
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#define PATH0_R_EN_RXCK_TX_C_M 0x1
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#define PATH0_R_RXCK_TX_C 0x12A8
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#define PATH0_R_RXCK_TX_C_M 0xE
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#define PATH0_R_RXCK_TX_FTM_C 0x12A8
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#define PATH0_R_RXCK_TX_FTM_C_M 0x70
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#define PATH0_R_CLK_RFC_GCK_EN_C 0x12A8
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#define PATH0_R_CLK_RFC_GCK_EN_C_M 0x80
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#define PATH0_R_RF0_GEN_DBG_SEL_C 0x12A8
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#define PATH0_R_RF0_GEN_DBG_SEL_C_M 0x300
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#define PATH0_R_RFMODE_GNT_WL_DIS_TX_OPT_C 0x12A8
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#define PATH0_R_RFMODE_GNT_WL_DIS_TX_OPT_C_M 0x800
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#define PATH0_R_RFAFE_PWSAV_EN_C 0x12A8
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#define PATH0_R_RFAFE_PWSAV_EN_C_M 0xF000
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#define PATH0_R_RFMODE_ORI_RXB_OFF_C 0x12A8
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#define PATH0_R_RFMODE_ORI_RXB_OFF_C_M 0xF0000
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#define PATH0_R_RFMODE_ORI_RXB_LOWPW_C 0x12A8
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#define PATH0_R_RFMODE_ORI_RXB_LOWPW_C_M 0xF00000
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#define PATH0_R_RFMODE_FTM_RXB_OFF_C 0x12A8
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#define PATH0_R_RFMODE_FTM_RXB_OFF_C_M 0xF000000
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#define PATH0_R_RFMODE_FTM_RXB_LOWPW_C 0x12A8
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#define PATH0_R_RFMODE_FTM_RXB_LOWPW_C_M 0xF0000000
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#define PATH0_R_RSTB_3WIRE_C 0x12AC
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#define PATH0_R_RSTB_3WIRE_C_M 0x1
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#define PATH0_R_EN_NRBW_AT_TX_C 0x12AC
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#define PATH0_R_EN_NRBW_AT_TX_C_M 0x4
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#define PATH0_R_RFMODE_ORI_TX_C 0x12AC
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#define PATH0_R_RFMODE_ORI_TX_C_M 0xF0
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#define PATH0_R_RFMODE_ORI_TX_TXOFF_C 0x12AC
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#define PATH0_R_RFMODE_ORI_TX_TXOFF_C_M 0xF00
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#define PATH0_R_RFMODE_ORI_RX_OFDM_CCA_C 0x12AC
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#define PATH0_R_RFMODE_ORI_RX_OFDM_CCA_C_M 0xF000
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#define PATH0_R_RFMODE_ORI_RX_CCK_CCA_C 0x12AC
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#define PATH0_R_RFMODE_ORI_RX_CCK_CCA_C_M 0xF0000
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#define PATH0_R_RFMODE_ORI_RX_IDLE_C 0x12AC
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#define PATH0_R_RFMODE_ORI_RX_IDLE_C_M 0xF00000
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#define PATH0_R_RFMODE_FTM_TX_C 0x12AC
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#define PATH0_R_RFMODE_FTM_TX_C_M 0xF000000
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#define PATH0_R_RFMODE_FTM_TX_TXOFF_C 0x12AC
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#define PATH0_R_RFMODE_FTM_TX_TXOFF_C_M 0xF0000000
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#define PATH0_R_RFMODE_FTM_RX_OFDM_CCA_C 0x12B0
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#define PATH0_R_RFMODE_FTM_RX_OFDM_CCA_C_M 0xF
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#define PATH0_R_RFMODE_FTM_RX_CCK_CCA_C 0x12B0
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#define PATH0_R_RFMODE_FTM_RX_CCK_CCA_C_M 0xF0
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#define PATH0_R_RFMODE_FTM_RX_IDLE_C 0x12B0
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#define PATH0_R_RFMODE_FTM_RX_IDLE_C_M 0xF00
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#define PATH0_R_RXB_IDX_AT_TX_C 0x12B0
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#define PATH0_R_RXB_IDX_AT_TX_C_M 0x1F000
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#define PATH0_R_TIA_IDX_AT_TX_C 0x12B0
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#define PATH0_R_TIA_IDX_AT_TX_C_M 0x20000
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#define PATH0_R_LNA_IDX_AT_TX_C 0x12B0
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#define PATH0_R_LNA_IDX_AT_TX_C_M 0x1C0000
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#define PATH0_R_TIA_EXT_BW_AT_TX_C 0x12B0
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#define PATH0_R_TIA_EXT_BW_AT_TX_C_M 0x200000
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#define PATH0_R_SI_RADDR_C 0x12B0
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#define PATH0_R_SI_RADDR_C_M 0x3FC00000
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#define PATH0_R_RST_3WIRE_CONFLICT_CNT_C 0x12B0
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#define PATH0_R_RST_3WIRE_CONFLICT_CNT_C_M 0x80000000
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#define PATH0_R_SOFT3WIRE_DATA_C 0x12B4
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#define PATH0_R_SOFT3WIRE_DATA_C_M 0xFFFFFFF
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#define PATH0_R_TXAGC_AT_SLEEP_C 0x12B8
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#define PATH0_R_TXAGC_AT_SLEEP_C_M 0x3F
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#define PATH0_R_RXB_IDX_AT_SLEEP_C 0x12B8
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#define PATH0_R_RXB_IDX_AT_SLEEP_C_M 0x7C0
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#define PATH0_R_TIA_IDX_AT_SLEEP_C 0x12B8
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#define PATH0_R_TIA_IDX_AT_SLEEP_C_M 0x800
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#define PATH0_R_LNA_IDX_AT_SLEEP_C 0x12B8
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#define PATH0_R_LNA_IDX_AT_SLEEP_C_M 0x7000
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#define PATH0_R_TIA_EXT_BW_AT_SLEEP_C 0x12B8
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#define PATH0_R_TIA_EXT_BW_AT_SLEEP_C_M 0x8000
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#define PATH0_R_EN_NRBW_AT_SLEEP_C 0x12B8
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#define PATH0_R_EN_NRBW_AT_SLEEP_C_M 0x10000
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#define PATH0_R_RFMODE_AT_SLEEP_C 0x12B8
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#define PATH0_R_RFMODE_AT_SLEEP_C_M 0x1E0000
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#define PATH0_R_TXAGC_BYPASS_C 0x12B8
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#define PATH0_R_TXAGC_BYPASS_C_M 0x200000
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#define PATH0_R_RXB_BYPASS_C 0x12B8
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#define PATH0_R_RXB_BYPASS_C_M 0x400000
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#define PATH0_R_TIA_BYPASS_C 0x12B8
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#define PATH0_R_TIA_BYPASS_C_M 0x800000
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#define PATH0_R_LNA_BYPASS_C 0x12B8
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#define PATH0_R_LNA_BYPASS_C_M 0x1000000
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#define PATH0_R_TIA_EXT_BYPASS_C 0x12B8
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#define PATH0_R_TIA_EXT_BYPASS_C_M 0x2000000
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#define PATH0_R_EN_NRBW_BYPASS_C 0x12B8
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#define PATH0_R_EN_NRBW_BYPASS_C_M 0x4000000
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#define PATH0_R_RFREG_DIS_GATING_C 0x12B8
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#define PATH0_R_RFREG_DIS_GATING_C_M 0x8000000
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#define PATH0_R_RSTB_ANAPAR_C 0x12B8
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#define PATH0_R_RSTB_ANAPAR_C_M 0x10000000
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#define PATH0_R_ANAPAR_SEL_OPT_C 0x12B8
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#define PATH0_R_ANAPAR_SEL_OPT_C_M 0x20000000
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#define PATH0_R_ANAPAR_DBG_MODE_C 0x12B8
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#define PATH0_R_ANAPAR_DBG_MODE_C_M 0x40000000
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#define PATH0_R_ANAPAR_DIS_GATING_C 0x12B8
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#define PATH0_R_ANAPAR_DIS_GATING_C_M 0x80000000
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#define PATH0_R_ANAPAR_ST0_SEL_C 0x12BC
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#define PATH0_R_ANAPAR_ST0_SEL_C_M 0xF
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#define PATH0_R_ANAPAR_ST1_SEL_C 0x12BC
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#define PATH0_R_ANAPAR_ST1_SEL_C_M 0xF0
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#define PATH0_R_ANAPAR_ST2_SEL_C 0x12BC
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#define PATH0_R_ANAPAR_ST2_SEL_C_M 0xF00
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#define PATH0_R_ANAPAR_ST3_SEL_C 0x12BC
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#define PATH0_R_ANAPAR_ST3_SEL_C_M 0xF000
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#define PATH0_R_ANAPAR_ST4_SEL_C 0x12BC
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#define PATH0_R_ANAPAR_ST4_SEL_C_M 0xF0000
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#define PATH0_R_ANAPAR_ST5_SEL_C 0x12BC
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#define PATH0_R_ANAPAR_ST5_SEL_C_M 0xF00000
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#define PATH0_R_ANAPAR_ST6_SEL_C 0x12BC
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#define PATH0_R_ANAPAR_ST6_SEL_C_M 0xF000000
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#define PATH0_R_ANAPAR_ST7_SEL_C 0x12BC
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#define PATH0_R_ANAPAR_ST7_SEL_C_M 0xF0000000
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#define PATH0_R_ANAPAR_ST8_SEL_C 0x12C0
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#define PATH0_R_ANAPAR_ST8_SEL_C_M 0xF
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#define PATH0_R_ANAPAR_ST9_SEL_C 0x12C0
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#define PATH0_R_ANAPAR_ST9_SEL_C_M 0xF0
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#define PATH0_R_ANAPAR_ST10_SEL_C 0x12C0
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#define PATH0_R_ANAPAR_ST10_SEL_C_M 0xF00
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#define PATH0_R_ANAPAR_ST11_SEL_C 0x12C0
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#define PATH0_R_ANAPAR_ST11_SEL_C_M 0xF000
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#define PATH0_R_ANAPAR_ST12_SEL_C 0x12C0
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#define PATH0_R_ANAPAR_ST12_SEL_C_M 0xF0000
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#define PATH0_R_ANAPAR_ST13_SEL_C 0x12C0
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#define PATH0_R_ANAPAR_ST13_SEL_C_M 0xF00000
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#define PATH0_R_ANAPAR_ST14_SEL_C 0x12C0
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#define PATH0_R_ANAPAR_ST14_SEL_C_M 0xF000000
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#define PATH0_R_ANAPAR_ST15_SEL_C 0x12C0
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#define PATH0_R_ANAPAR_ST15_SEL_C_M 0xF0000000
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#define PATH0_R_ANAPAR_ST16_SEL_C 0x12C4
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#define PATH0_R_ANAPAR_ST16_SEL_C_M 0xF
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#define PATH0_R_ANAPAR_ST17_SEL_C 0x12C4
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#define PATH0_R_ANAPAR_ST17_SEL_C_M 0xF0
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#define PATH0_R_ANAPAR_ST18_SEL_C 0x12C4
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#define PATH0_R_ANAPAR_ST18_SEL_C_M 0xF00
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#define PATH0_R_ANAPAR_ST19_SEL_C 0x12C4
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#define PATH0_R_ANAPAR_ST19_SEL_C_M 0xF000
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#define PATH0_R_ANAPAR_ST20_SEL_C 0x12C4
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#define PATH0_R_ANAPAR_ST20_SEL_C_M 0xF0000
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#define PATH0_R_ANAPAR_ST21_SEL_C 0x12C4
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#define PATH0_R_ANAPAR_ST21_SEL_C_M 0xF00000
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#define PATH0_R_ANAPAR_ST22_SEL_C 0x12C4
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#define PATH0_R_ANAPAR_ST22_SEL_C_M 0xF000000
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#define PATH0_R_ANAPAR_ST23_SEL_C 0x12C4
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#define PATH0_R_ANAPAR_ST23_SEL_C_M 0xF0000000
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#define PATH0_R_ANAPAR_ST24_SEL_C 0x12C8
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#define PATH0_R_ANAPAR_ST24_SEL_C_M 0xF
|
#define PATH0_R_ANAPAR_ST25_SEL_C 0x12C8
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#define PATH0_R_ANAPAR_ST25_SEL_C_M 0xF0
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#define PATH0_R_ANAPAR_ST26_SEL_C 0x12C8
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#define PATH0_R_ANAPAR_ST26_SEL_C_M 0xF00
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#define PATH0_R_ANAPAR_ST27_SEL_C 0x12C8
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#define PATH0_R_ANAPAR_ST27_SEL_C_M 0xF000
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#define PATH0_R_ANAPAR_ST28_SEL_C 0x12C8
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#define PATH0_R_ANAPAR_ST28_SEL_C_M 0xF0000
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#define PATH0_R_ANAPAR_ST29_SEL_C 0x12C8
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#define PATH0_R_ANAPAR_ST29_SEL_C_M 0xF00000
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#define PATH0_R_ANAPAR_ST30_SEL_C 0x12C8
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#define PATH0_R_ANAPAR_ST30_SEL_C_M 0xF000000
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#define PATH0_R_ANAPAR_ST31_SEL_C 0x12C8
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#define PATH0_R_ANAPAR_ST31_SEL_C_M 0xF0000000
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#define PATH0_R_ANAPAR_CTSDM_31_0__C 0x12CC
|
#define PATH0_R_ANAPAR_CTSDM_31_0__C_M 0xFFFFFFFF
|
#define PATH0_R_ANAPAR_CTSDM_63_32__C 0x12D0
|
#define PATH0_R_ANAPAR_CTSDM_63_32__C_M 0xFFFFFFFF
|
#define PATH0_R_ANAPAR_CTSDM_95_64__C 0x12D4
|
#define PATH0_R_ANAPAR_CTSDM_95_64__C_M 0xFFFFFFFF
|
#define PATH0_R_ANAPAR_CTSDM_127_96__C 0x12D8
|
#define PATH0_R_ANAPAR_CTSDM_127_96__C_M 0xFFFFFFFF
|
#define PATH0_R_ANAPAR_31_0__C 0x12DC
|
#define PATH0_R_ANAPAR_31_0__C_M 0xFFFFFFFF
|
#define PATH0_R_ANAPAR_63_32__C 0x12E0
|
#define PATH0_R_ANAPAR_63_32__C_M 0xFFFFFFFF
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#define PATH0_R_ANAPAR_95_64__C 0x12E4
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#define PATH0_R_ANAPAR_95_64__C_M 0xFFFFFFFF
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#define PATH0_R_ANAPAR_127_96__C 0x12E8
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#define PATH0_R_ANAPAR_127_96__C_M 0xFFFFFFFF
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#define PATH0_R_ANAPAR_143_128__C 0x12EC
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#define PATH0_R_ANAPAR_143_128__C_M 0xFFFF
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#define PATH0_R_ANAPAR_LBK_15_0__C 0x12EC
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#define PATH0_R_ANAPAR_LBK_15_0__C_M 0xFFFF0000
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#define PATH0_R_ANAPAR_LBK_47_16__C 0x12F0
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#define PATH0_R_ANAPAR_LBK_47_16__C_M 0xFFFFFFFF
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#define PATH0_R_ANAPAR_LBK_79_48__C 0x12F4
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#define PATH0_R_ANAPAR_LBK_79_48__C_M 0xFFFFFFFF
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#define PATH0_R_ANAPAR_LBK_111_80__C 0x12F8
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#define PATH0_R_ANAPAR_LBK_111_80__C_M 0xFFFFFFFF
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#define PATH0_R_ANAPAR_LBK_143_112__C 0x12FC
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#define PATH0_R_ANAPAR_LBK_143_112__C_M 0xFFFFFFFF
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#define CNT_LA_TRIG_C 0x1700
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#define CNT_LA_TRIG_C_M 0xFFFF
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#define CNT_CCKTXEN_C 0x1700
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#define CNT_CCKTXEN_C_M 0xFFFF0000
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#define CNT_CCKTXON_C 0x1704
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#define CNT_CCKTXON_C_M 0xFFFF
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#define CNT_DBG_BIT_C 0x1704
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#define CNT_DBG_BIT_C_M 0xFFFF0000
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#define CNT_CCK_CCA_P0_C 0x1710
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#define CNT_CCK_CCA_P0_C_M 0xFFFF
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#define CNT_CCK_CRC16FAIL_P0_C 0x1710
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#define CNT_CCK_CRC16FAIL_P0_C_M 0xFFFF0000
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#define CNT_CCK_CRC32OK_P0_C 0x1714
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#define CNT_CCK_CRC32OK_P0_C_M 0xFFFF
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#define CNT_CCK_CRC32FAIL_P0_C 0x1714
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#define CNT_CCK_CRC32FAIL_P0_C_M 0xFFFF0000
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#define CNT_CCK_CCA_P1_C 0x1718
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#define CNT_CCK_CCA_P1_C_M 0xFFFF
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#define CNT_CCK_CRC16FAIL_P1_C 0x1718
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#define CNT_CCK_CRC16FAIL_P1_C_M 0xFFFF0000
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#define CNT_CCK_CRC32OK_P1_C 0x171C
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#define CNT_CCK_CRC32OK_P1_C_M 0xFFFF
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#define CNT_CCK_CRC32FAIL_P1_C 0x171C
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#define CNT_CCK_CRC32FAIL_P1_C_M 0xFFFF0000
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#define AXTOP_BIST_C 0x1720
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#define AXTOP_BIST_C_M 0xFFFFFFFF
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#define AXRX_IN_BIST_C 0x1724
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#define AXRX_IN_BIST_C_M 0xFFFFFFFF
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#define AXTD_BIST_C 0x1728
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#define AXTD_BIST_C_M 0xFFFFFFFF
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#define AXOUT_BIST_C 0x172C
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#define AXOUT_BIST_C_M 0xFFFFFFFF
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#define DBG32_D_C 0x1730
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#define DBG32_D_C_M 0xFFFFFFFF
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#define PSD_PW_C 0x1734
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#define PSD_PW_C_M 0x1FFFFFF
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#define PSD_OK_FLAG_C 0x1734
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#define PSD_OK_FLAG_C_M 0x2000000
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#define EDCCA_IOQ_P0_A_C 0x1738
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#define EDCCA_IOQ_P0_A_C_M 0xFFFFFFFF
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#define EDCCA_IOQ_P0_B_C 0x173C
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#define EDCCA_IOQ_P0_B_C_M 0xFFFFFFFF
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#define EDCCA_IOQ_P1_A_C 0x1740
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#define EDCCA_IOQ_P1_A_C_M 0xFFFFFFFF
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#define EDCCA_IOQ_P1_B_C 0x1744
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#define EDCCA_IOQ_P1_B_C_M 0xFFFFFFFF
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#define RO_SI_R_DATA_AFC_C 0x1748
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#define RO_SI_R_DATA_AFC_C_M 0xFFFFFFFF
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#define SW_SI_READ_DATA_C 0x174C
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#define SW_SI_READ_DATA_C_M 0xFFFFF
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#define SW_SI_CNT_CONFLICT_C 0x174C
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#define SW_SI_CNT_CONFLICT_C_M 0xF00000
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#define SW_SI_W_BUSY_C 0x174C
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#define SW_SI_W_BUSY_C_M 0x1000000
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#define SW_SI_R_BUSY_C 0x174C
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#define SW_SI_R_BUSY_C_M 0x2000000
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#define SW_SI_READ_DATA_DONE_C 0x174C
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#define SW_SI_READ_DATA_DONE_C_M 0x4000000
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#define CNT_SW_SI_R_C 0x1750
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#define CNT_SW_SI_R_C_M 0xFFFF
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#define CNT_SW_SI_W_C 0x1750
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#define CNT_SW_SI_W_C_M 0xFFFF0000
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#define SWSI_RECORD_1ST_C 0x1758
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#define SWSI_RECORD_1ST_C_M 0x3FFFFF
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#define SWSI_RECORD_2ND_C 0x1760
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#define SWSI_RECORD_2ND_C_M 0x3FFFFF
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#define SWSI_CMD_CNT_C 0x1764
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#define SWSI_CMD_CNT_C_M 0x3F
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#define SWSI_NOW_IS_1ST_C 0x1764
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#define SWSI_NOW_IS_1ST_C_M 0x40000000
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#define SWSI_NOW_IS_2ND_C 0x1764
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#define SWSI_NOW_IS_2ND_C_M 0x80000000
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#define HWSI_RECORD_1ST_0_C 0x1768
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#define HWSI_RECORD_1ST_0_C_M 0x1FFF
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#define HWSI_RECORD_1ST_1_C 0x1768
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#define HWSI_RECORD_1ST_1_C_M 0x1FFF0000
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#define HWSI_RECORD_2ND_0_C 0x176C
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#define HWSI_RECORD_2ND_0_C_M 0x1FFF
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#define HWSI_RECORD_2ND_1_C 0x176C
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#define HWSI_RECORD_2ND_1_C_M 0x1FFF0000
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#define HWSI_RECORD_3RD_0_C 0x1770
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#define HWSI_RECORD_3RD_0_C_M 0x1FFF
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#define HWSI_RECORD_3RD_1_C 0x1770
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#define HWSI_RECORD_3RD_1_C_M 0x1FFF0000
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#define HWSI_RECORD_4TH_0_C 0x1774
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#define HWSI_RECORD_4TH_0_C_M 0x1FFF
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#define HWSI_RECORD_4TH_1_C 0x1774
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#define HWSI_RECORD_4TH_1_C_M 0x1FFF0000
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#define HWSI_CMD_CNT_C 0x1778
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#define HWSI_CMD_CNT_C_M 0x3F
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#define HWSI_NOW_IS_1ST_C 0x1778
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#define HWSI_NOW_IS_1ST_C_M 0x10000000
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#define HWSI_NOW_IS_2ND_C 0x1778
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#define HWSI_NOW_IS_2ND_C_M 0x20000000
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#define HWSI_NOW_IS_3RD_C 0x1778
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#define HWSI_NOW_IS_3RD_C_M 0x40000000
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#define HWSI_NOW_IS_4TH_C 0x1778
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#define HWSI_NOW_IS_4TH_C_M 0x80000000
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#define WLS0_RFMODE_C 0x177C
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#define WLS0_RFMODE_C_M 0xF
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#define WLS0_TSSI_OFST_C 0x177C
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#define WLS0_TSSI_OFST_C_M 0x1F0
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#define WLS0_TX_CCK_IND_C 0x177C
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#define WLS0_TX_CCK_IND_C_M 0x200
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#define WLS0_TX_GAIN_C 0x177C
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#define WLS0_TX_GAIN_C_M 0xFC00
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#define WLS0_EN_PAD_GAPK_C 0x177C
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#define WLS0_EN_PAD_GAPK_C_M 0x10000
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#define WLS0_EN_PA_GAPK_C 0x177C
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#define WLS0_EN_PA_GAPK_C_M 0x20000
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#define WLS0_PAD_GAPK_IDX_C 0x177C
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#define WLS0_PAD_GAPK_IDX_C_M 0x1FC0000
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#define WLS0_PA_GAPK_IDX_C 0x177C
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#define WLS0_PA_GAPK_IDX_C_M 0x7E000000
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#define WLS1_RFMODE_C 0x1780
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#define WLS1_RFMODE_C_M 0xF
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#define WLS1_TSSI_OFST_C 0x1780
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#define WLS1_TSSI_OFST_C_M 0x1F0
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#define WLS1_TX_CCK_IND_C 0x1780
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#define WLS1_TX_CCK_IND_C_M 0x200
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#define WLS1_TX_GAIN_C 0x1780
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#define WLS1_TX_GAIN_C_M 0xFC00
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#define WLS1_EN_PAD_GAPK_C 0x1780
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#define WLS1_EN_PAD_GAPK_C_M 0x10000
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#define WLS1_EN_PA_GAPK_C 0x1780
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#define WLS1_EN_PA_GAPK_C_M 0x20000
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#define WLS1_PAD_GAPK_IDX_C 0x1780
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#define WLS1_PAD_GAPK_IDX_C_M 0x1FC0000
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#define WLS1_PA_GAPK_IDX_C 0x1780
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#define WLS1_PA_GAPK_IDX_C_M 0x7E000000
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#define BW_TXS0_C 0x1784
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#define BW_TXS0_C_M 0x7
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#define DAC_0P5DB_S0_C 0x1784
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#define DAC_0P5DB_S0_C_M 0x8
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#define GAIN_TX_S0_C 0x1784
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#define GAIN_TX_S0_C_M 0x1F0
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#define GAIN_TX_GAPK_S0_C 0x1784
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#define GAIN_TX_GAPK_S0_C_M 0x1E00
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#define BW_TXS1_C 0x1784
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#define BW_TXS1_C_M 0x70000
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#define DAC_0P5DB_S1_C 0x1784
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#define DAC_0P5DB_S1_C_M 0x80000
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#define GAIN_TX_S1_C 0x1784
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#define GAIN_TX_S1_C_M 0x1F00000
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#define GAIN_TX_GAPK_S1_C 0x1784
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#define GAIN_TX_GAPK_S1_C_M 0x1E000000
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#define LO_SEL_C 0x1784
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#define LO_SEL_C_M 0xC0000000
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#define INTF_TXINFO_PPDU_TYPE_3_0__C 0x1800
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#define INTF_TXINFO_PPDU_TYPE_3_0__C_M 0xF
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#define INTF_TXINFO_CH20_WITH_DATA_7_0__C 0x1800
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#define INTF_TXINFO_CH20_WITH_DATA_7_0__C_M 0xFF0
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#define INTF_TXINFO_PATH_EN_3_0__C 0x1800
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#define INTF_TXINFO_PATH_EN_3_0__C_M 0xF000
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#define INTF_TXINFO_PATH_MAP_A_1_0__C 0x1800
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#define INTF_TXINFO_PATH_MAP_A_1_0__C_M 0x30000
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#define INTF_TXINFO_PATH_MAP_B_1_0__C 0x1800
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#define INTF_TXINFO_PATH_MAP_B_1_0__C_M 0xC0000
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#define INTF_TXINFO_PATH_MAP_C_1_0__C 0x1800
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#define INTF_TXINFO_PATH_MAP_C_1_0__C_M 0x300000
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#define INTF_TXINFO_PATH_MAP_D_1_0__C 0x1800
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#define INTF_TXINFO_PATH_MAP_D_1_0__C_M 0xC00000
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#define INTF_TXINFO_TXCMD_TXTP_5_0__C 0x1800
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#define INTF_TXINFO_TXCMD_TXTP_5_0__C_M 0x3F000000
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#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_1_0__C 0x1800
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#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_1_0__C_M 0xC0000000
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#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_3_2__C 0x1804
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#define INTF_TXINFO_OBW_CTS2SELF_DUP_TYPE_3_2__C_M 0x3
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#define INTF_TXINFO_CFIR_BY_RATE_OFF_0__C 0x1804
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#define INTF_TXINFO_CFIR_BY_RATE_OFF_0__C_M 0x4
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#define INTF_TXINFO_DPD_BY_RATE_OFF_0__C 0x1804
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#define INTF_TXINFO_DPD_BY_RATE_OFF_0__C_M 0x8
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#define INTF_TXINFO_TXSC_3_0__C 0x1804
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#define INTF_TXINFO_TXSC_3_0__C_M 0xF0
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#define INTF_TXINFO_TX_SWING_3_0__C 0x1804
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#define INTF_TXINFO_TX_SWING_3_0__C_M 0xF00
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#define INTF_TXINFO_RATE_BIAS_1_0__C 0x1804
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#define INTF_TXINFO_RATE_BIAS_1_0__C_M 0x3000
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#define INTF_TXINFO_DBW_IDX_1_0__C 0x1804
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#define INTF_TXINFO_DBW_IDX_1_0__C_M 0x30000
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#define INTF_TXINFO_TX_PW_DBM_8_0__C 0x1804
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#define INTF_TXINFO_TX_PW_DBM_8_0__C_M 0x7FC0000
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#define INTF_TXINFO_CFO_COMP_2_0__C 0x1804
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#define INTF_TXINFO_CFO_COMP_2_0__C_M 0x38000000
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#define INTF_TXINFO_ANTIDX_ANT_SEL_A_0__C 0x1808
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#define INTF_TXINFO_ANTIDX_ANT_SEL_A_0__C_M 0x1
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#define INTF_TXINFO_ANTIDX_ANT_SEL_B_0__C 0x1808
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#define INTF_TXINFO_ANTIDX_ANT_SEL_B_0__C_M 0x2
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#define INTF_TXINFO_ANTIDX_ANT_SEL_C_0__C 0x1808
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#define INTF_TXINFO_ANTIDX_ANT_SEL_C_0__C_M 0x4
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#define INTF_TXINFO_ANTIDX_ANT_SEL_D_0__C 0x1808
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#define INTF_TXINFO_ANTIDX_ANT_SEL_D_0__C_M 0x8
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#define INTF_TXINFO_N_USR_7_0__C 0x1808
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#define INTF_TXINFO_N_USR_7_0__C_M 0xFF0
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#define INTF_TXINFO_CCA_PW_TH_7_0__C 0x1808
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#define INTF_TXINFO_CCA_PW_TH_7_0__C_M 0xFF000
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#define INTF_TXINFO_CCA_PW_TH_EN_0__C 0x1808
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#define INTF_TXINFO_CCA_PW_TH_EN_0__C_M 0x100000
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#define INTF_TXINFO_RF_GAIN_IDX_9_0__C 0x1808
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#define INTF_TXINFO_RF_GAIN_IDX_9_0__C_M 0x7FE00000
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#define INTF_TXINFO_RF_FIXED_GAIN_EN_0__C 0x1808
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#define INTF_TXINFO_RF_FIXED_GAIN_EN_0__C_M 0x80000000
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#define INTF_TXINFO_UL_CQI_RPT_TRI_0__C 0x180C
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#define INTF_TXINFO_UL_CQI_RPT_TRI_0__C_M 0x1
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#define INTF_TXCOMCT_STBC_EN_0__C 0x1810
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#define INTF_TXCOMCT_STBC_EN_0__C_M 0x1
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#define INTF_TXCOMCT_DOPPLER_EN_0__C 0x1810
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#define INTF_TXCOMCT_DOPPLER_EN_0__C_M 0x4
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#define INTF_TXCOMCT_MIDAMBLE_MODE_0__C 0x1810
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#define INTF_TXCOMCT_MIDAMBLE_MODE_0__C_M 0x8
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#define INTF_TXCOMCT_GI_TYPE_1_0__C 0x1810
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#define INTF_TXCOMCT_GI_TYPE_1_0__C_M 0x30
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#define INTF_TXCOMCT_LTF_TYPE_1_0__C 0x1810
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#define INTF_TXCOMCT_LTF_TYPE_1_0__C_M 0xC0
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#define INTF_TXCOMCT_N_LTF_2_0__C 0x1810
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#define INTF_TXCOMCT_N_LTF_2_0__C_M 0x700
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#define INTF_TXCOMCT_FB_MUMIMO_EN_0__C 0x1810
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#define INTF_TXCOMCT_FB_MUMIMO_EN_0__C_M 0x800
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#define INTF_TXCOMCT_MUMIMO_LTF_MODE_EN_0__C 0x1814
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#define INTF_TXCOMCT_MUMIMO_LTF_MODE_EN_0__C_M 0x8
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#define INTF_TXCOMCT_NDP_0__C 0x1814
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#define INTF_TXCOMCT_NDP_0__C_M 0x10
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#define INTF_TXCOMCT_FEEDBACK_STATUS_0__C 0x1814
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#define INTF_TXCOMCT_FEEDBACK_STATUS_0__C_M 0x20
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#define INTF_TXCOMCT_BEAM_CHANGE_EN_0__C 0x1814
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#define INTF_TXCOMCT_BEAM_CHANGE_EN_0__C_M 0x40
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#define INTF_TXCOMCT_HE_SIGB_MCS_2_0__C 0x1814
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#define INTF_TXCOMCT_HE_SIGB_MCS_2_0__C_M 0x380
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#define INTF_TXCOMCT_HE_SIGB_DCM_EN_0__C 0x1814
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#define INTF_TXCOMCT_HE_SIGB_DCM_EN_0__C_M 0x400
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#define INTF_TXUSRCT0_U_ID_7_0__C 0x1818
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#define INTF_TXUSRCT0_U_ID_7_0__C_M 0xFF
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#define INTF_TXUSRCT0_RU_ALLOC_7_0__C 0x1818
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#define INTF_TXUSRCT0_RU_ALLOC_7_0__C_M 0xFF00
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#define INTF_TXUSRCT0_N_STS_RU_TOT_2_0__C 0x1818
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#define INTF_TXUSRCT0_N_STS_RU_TOT_2_0__C_M 0x70000
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#define INTF_TXUSRCT0_STRT_STS_2_0__C 0x1818
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#define INTF_TXUSRCT0_STRT_STS_2_0__C_M 0xE00000
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#define INTF_TXUSRCT0_N_STS_2_0__C 0x1818
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#define INTF_TXUSRCT0_N_STS_2_0__C_M 0x7000000
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#define INTF_TXUSRCT0_FEC_TYPE_0__C 0x1818
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#define INTF_TXUSRCT0_FEC_TYPE_0__C_M 0x8000000
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#define INTF_TXUSRCT0_MCS_3_0__C 0x1818
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#define INTF_TXUSRCT0_MCS_3_0__C_M 0xF0000000
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#define INTF_TXUSRCT0_MCS_5_4__C 0x181C
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#define INTF_TXUSRCT0_MCS_5_4__C_M 0x3
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#define INTF_TXUSRCT0_DCM_EN_0__C 0x181C
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#define INTF_TXUSRCT0_DCM_EN_0__C_M 0x4
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#define INTF_TXUSRCT0_CSI_BUF_ID_10_0__C 0x181C
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#define INTF_TXUSRCT0_CSI_BUF_ID_10_0__C_M 0x3FF8
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#define INTF_TXUSRCT0_TXBF_EN_0__C 0x181C
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#define INTF_TXUSRCT0_TXBF_EN_0__C_M 0x4000
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#define INTF_TXUSRCT0_PW_BOOST_FCTR_DB_4_0__C 0x181C
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#define INTF_TXUSRCT0_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000
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#define INTF_TXUSRCT1_U_ID_7_0__C 0x1820
|
#define INTF_TXUSRCT1_U_ID_7_0__C_M 0xFF
|
#define INTF_TXUSRCT1_RU_ALLOC_7_0__C 0x1820
|
#define INTF_TXUSRCT1_RU_ALLOC_7_0__C_M 0xFF00
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#define INTF_TXUSRCT1_N_STS_RU_TOT_2_0__C 0x1820
|
#define INTF_TXUSRCT1_N_STS_RU_TOT_2_0__C_M 0x70000
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#define INTF_TXUSRCT1_STRT_STS_2_0__C 0x1820
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#define INTF_TXUSRCT1_STRT_STS_2_0__C_M 0xE00000
|
#define INTF_TXUSRCT1_N_STS_2_0__C 0x1820
|
#define INTF_TXUSRCT1_N_STS_2_0__C_M 0x7000000
|
#define INTF_TXUSRCT1_FEC_TYPE_0__C 0x1820
|
#define INTF_TXUSRCT1_FEC_TYPE_0__C_M 0x8000000
|
#define INTF_TXUSRCT1_MCS_3_0__C 0x1820
|
#define INTF_TXUSRCT1_MCS_3_0__C_M 0xF0000000
|
#define INTF_TXUSRCT1_MCS_5_4__C 0x1824
|
#define INTF_TXUSRCT1_MCS_5_4__C_M 0x3
|
#define INTF_TXUSRCT1_DCM_EN_0__C 0x1824
|
#define INTF_TXUSRCT1_DCM_EN_0__C_M 0x4
|
#define INTF_TXUSRCT1_CSI_BUF_ID_10_0__C 0x1824
|
#define INTF_TXUSRCT1_CSI_BUF_ID_10_0__C_M 0x3FF8
|
#define INTF_TXUSRCT1_TXBF_EN_0__C 0x1824
|
#define INTF_TXUSRCT1_TXBF_EN_0__C_M 0x4000
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#define INTF_TXUSRCT1_PW_BOOST_FCTR_DB_4_0__C 0x1824
|
#define INTF_TXUSRCT1_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000
|
#define INTF_TXUSRCT2_U_ID_7_0__C 0x1828
|
#define INTF_TXUSRCT2_U_ID_7_0__C_M 0xFF
|
#define INTF_TXUSRCT2_RU_ALLOC_7_0__C 0x1828
|
#define INTF_TXUSRCT2_RU_ALLOC_7_0__C_M 0xFF00
|
#define INTF_TXUSRCT2_N_STS_RU_TOT_2_0__C 0x1828
|
#define INTF_TXUSRCT2_N_STS_RU_TOT_2_0__C_M 0x70000
|
#define INTF_TXUSRCT2_STRT_STS_2_0__C 0x1828
|
#define INTF_TXUSRCT2_STRT_STS_2_0__C_M 0xE00000
|
#define INTF_TXUSRCT2_N_STS_2_0__C 0x1828
|
#define INTF_TXUSRCT2_N_STS_2_0__C_M 0x7000000
|
#define INTF_TXUSRCT2_FEC_TYPE_0__C 0x1828
|
#define INTF_TXUSRCT2_FEC_TYPE_0__C_M 0x8000000
|
#define INTF_TXUSRCT2_MCS_3_0__C 0x1828
|
#define INTF_TXUSRCT2_MCS_3_0__C_M 0xF0000000
|
#define INTF_TXUSRCT2_MCS_5_4__C 0x182C
|
#define INTF_TXUSRCT2_MCS_5_4__C_M 0x3
|
#define INTF_TXUSRCT2_DCM_EN_0__C 0x182C
|
#define INTF_TXUSRCT2_DCM_EN_0__C_M 0x4
|
#define INTF_TXUSRCT2_CSI_BUF_ID_10_0__C 0x182C
|
#define INTF_TXUSRCT2_CSI_BUF_ID_10_0__C_M 0x3FF8
|
#define INTF_TXUSRCT2_TXBF_EN_0__C 0x182C
|
#define INTF_TXUSRCT2_TXBF_EN_0__C_M 0x4000
|
#define INTF_TXUSRCT2_PW_BOOST_FCTR_DB_4_0__C 0x182C
|
#define INTF_TXUSRCT2_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000
|
#define INTF_TXUSRCT3_U_ID_7_0__C 0x1830
|
#define INTF_TXUSRCT3_U_ID_7_0__C_M 0xFF
|
#define INTF_TXUSRCT3_RU_ALLOC_7_0__C 0x1830
|
#define INTF_TXUSRCT3_RU_ALLOC_7_0__C_M 0xFF00
|
#define INTF_TXUSRCT3_N_STS_RU_TOT_2_0__C 0x1830
|
#define INTF_TXUSRCT3_N_STS_RU_TOT_2_0__C_M 0x70000
|
#define INTF_TXUSRCT3_STRT_STS_2_0__C 0x1830
|
#define INTF_TXUSRCT3_STRT_STS_2_0__C_M 0xE00000
|
#define INTF_TXUSRCT3_N_STS_2_0__C 0x1830
|
#define INTF_TXUSRCT3_N_STS_2_0__C_M 0x7000000
|
#define INTF_TXUSRCT3_FEC_TYPE_0__C 0x1830
|
#define INTF_TXUSRCT3_FEC_TYPE_0__C_M 0x8000000
|
#define INTF_TXUSRCT3_MCS_3_0__C 0x1830
|
#define INTF_TXUSRCT3_MCS_3_0__C_M 0xF0000000
|
#define INTF_TXUSRCT3_MCS_5_4__C 0x1834
|
#define INTF_TXUSRCT3_MCS_5_4__C_M 0x3
|
#define INTF_TXUSRCT3_DCM_EN_0__C 0x1834
|
#define INTF_TXUSRCT3_DCM_EN_0__C_M 0x4
|
#define INTF_TXUSRCT3_CSI_BUF_ID_10_0__C 0x1834
|
#define INTF_TXUSRCT3_CSI_BUF_ID_10_0__C_M 0x3FF8
|
#define INTF_TXUSRCT3_TXBF_EN_0__C 0x1834
|
#define INTF_TXUSRCT3_TXBF_EN_0__C_M 0x4000
|
#define INTF_TXUSRCT3_PW_BOOST_FCTR_DB_4_0__C 0x1834
|
#define INTF_TXUSRCT3_PW_BOOST_FCTR_DB_4_0__C_M 0xF8000
|
#define INTF_TXTIMCT_N_SYM_10_0__C 0x1838
|
#define INTF_TXTIMCT_N_SYM_10_0__C_M 0x7FF
|
#define INTF_TXTIMCT_N_SYM_HESIGB_5_0__C 0x1838
|
#define INTF_TXTIMCT_N_SYM_HESIGB_5_0__C_M 0x3F0000
|
#define INTF_TXTIMCT_LDPC_EXTR_0__C 0x1838
|
#define INTF_TXTIMCT_LDPC_EXTR_0__C_M 0x1000000
|
#define INTF_TXTIMCT_PKT_EXT_IDX_2_0__C 0x1838
|
#define INTF_TXTIMCT_PKT_EXT_IDX_2_0__C_M 0xE000000
|
#define INTF_TXTIMCT_PRE_FEC_FCTR_1_0__C 0x1838
|
#define INTF_TXTIMCT_PRE_FEC_FCTR_1_0__C_M 0x30000000
|
#define INTF_TX_LSIG_LATCH_31_0__C 0x1840
|
#define INTF_TX_LSIG_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_LSIG_LATCH_63_32__C 0x1844
|
#define INTF_TX_LSIG_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_SIGA_LATCH_31_0__C 0x1848
|
#define INTF_TX_SIGA_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_SIGA_LATCH_63_32__C 0x184C
|
#define INTF_TX_SIGA_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_VHT_SIGB0_LATCH_31_0__C 0x1850
|
#define INTF_TX_VHT_SIGB0_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_VHT_SIGB0_LATCH_63_32__C 0x1854
|
#define INTF_TX_VHT_SIGB0_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_VHT_SIGB1_LATCH_31_0__C 0x1858
|
#define INTF_TX_VHT_SIGB1_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_VHT_SIGB1_LATCH_63_32__C 0x185C
|
#define INTF_TX_VHT_SIGB1_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_0_LATCH_31_0__C 0x1860
|
#define INTF_TX_HE_SIGB_CH0_0_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_0_LATCH_63_32__C 0x1864
|
#define INTF_TX_HE_SIGB_CH0_0_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_1_LATCH_31_0__C 0x1868
|
#define INTF_TX_HE_SIGB_CH0_1_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_1_LATCH_63_32__C 0x186C
|
#define INTF_TX_HE_SIGB_CH0_1_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_2_LATCH_31_0__C 0x1870
|
#define INTF_TX_HE_SIGB_CH0_2_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_2_LATCH_63_32__C 0x1874
|
#define INTF_TX_HE_SIGB_CH0_2_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_3_LATCH_31_0__C 0x1878
|
#define INTF_TX_HE_SIGB_CH0_3_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_3_LATCH_63_32__C 0x187C
|
#define INTF_TX_HE_SIGB_CH0_3_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_4_LATCH_31_0__C 0x1880
|
#define INTF_TX_HE_SIGB_CH0_4_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_4_LATCH_63_32__C 0x1884
|
#define INTF_TX_HE_SIGB_CH0_4_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_5_LATCH_31_0__C 0x1888
|
#define INTF_TX_HE_SIGB_CH0_5_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_5_LATCH_63_32__C 0x188C
|
#define INTF_TX_HE_SIGB_CH0_5_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_6_LATCH_31_0__C 0x1890
|
#define INTF_TX_HE_SIGB_CH0_6_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_6_LATCH_63_32__C 0x1894
|
#define INTF_TX_HE_SIGB_CH0_6_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_7_LATCH_31_0__C 0x1898
|
#define INTF_TX_HE_SIGB_CH0_7_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH0_7_LATCH_63_32__C 0x189C
|
#define INTF_TX_HE_SIGB_CH0_7_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_0_LATCH_31_0__C 0x18A0
|
#define INTF_TX_HE_SIGB_CH1_0_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_0_LATCH_63_32__C 0x18A4
|
#define INTF_TX_HE_SIGB_CH1_0_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_1_LATCH_31_0__C 0x18A8
|
#define INTF_TX_HE_SIGB_CH1_1_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_1_LATCH_63_32__C 0x18AC
|
#define INTF_TX_HE_SIGB_CH1_1_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_2_LATCH_31_0__C 0x18B0
|
#define INTF_TX_HE_SIGB_CH1_2_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_2_LATCH_63_32__C 0x18B4
|
#define INTF_TX_HE_SIGB_CH1_2_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_3_LATCH_31_0__C 0x18B8
|
#define INTF_TX_HE_SIGB_CH1_3_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_3_LATCH_63_32__C 0x18BC
|
#define INTF_TX_HE_SIGB_CH1_3_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_4_LATCH_31_0__C 0x18C0
|
#define INTF_TX_HE_SIGB_CH1_4_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_4_LATCH_63_32__C 0x18C4
|
#define INTF_TX_HE_SIGB_CH1_4_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_5_LATCH_31_0__C 0x18C8
|
#define INTF_TX_HE_SIGB_CH1_5_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_5_LATCH_63_32__C 0x18CC
|
#define INTF_TX_HE_SIGB_CH1_5_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_6_LATCH_31_0__C 0x18D0
|
#define INTF_TX_HE_SIGB_CH1_6_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_6_LATCH_63_32__C 0x18D4
|
#define INTF_TX_HE_SIGB_CH1_6_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_7_LATCH_31_0__C 0x18D8
|
#define INTF_TX_HE_SIGB_CH1_7_LATCH_31_0__C_M 0xFFFFFFFF
|
#define INTF_TX_HE_SIGB_CH1_7_LATCH_63_32__C 0x18DC
|
#define INTF_TX_HE_SIGB_CH1_7_LATCH_63_32__C_M 0xFFFFFFFF
|
#define INTF_MAC_PHY_TXEN_C 0x18E0
|
#define INTF_MAC_PHY_TXEN_C_M 0x1
|
#define INTF_MAC_PHY_TXON_C 0x18E0
|
#define INTF_MAC_PHY_TXON_C_M 0x10
|
#define CNT_CCA_SPOOFING_C 0x1A00
|
#define CNT_CCA_SPOOFING_C_M 0xFFFF
|
#define CNT_LSIG_BRK_S_TH_C 0x1A00
|
#define CNT_LSIG_BRK_S_TH_C_M 0xFFFF0000
|
#define CNT_LSIG_BRK_L_TH_C 0x1A04
|
#define CNT_LSIG_BRK_L_TH_C_M 0xFFFF
|
#define CNT_HTSIG_CRC8_ERR_S_TH_C 0x1A04
|
#define CNT_HTSIG_CRC8_ERR_S_TH_C_M 0xFFFF0000
|
#define CNT_HTSIG_CRC8_ERR_L_TH_C 0x1A08
|
#define CNT_HTSIG_CRC8_ERR_L_TH_C_M 0xFFFF
|
#define CNT_BRK_C 0x1A08
|
#define CNT_BRK_C_M 0xFFFF0000
|
#define CNT_BRK_SEL_C 0x1A0C
|
#define CNT_BRK_SEL_C_M 0xFFFF
|
#define CNT_RXL_ERR_PARITY_C 0x1A0C
|
#define CNT_RXL_ERR_PARITY_C_M 0xFFFF0000
|
#define CNT_RXL_ERR_RATE_C 0x1A10
|
#define CNT_RXL_ERR_RATE_C_M 0xFFFF
|
#define CNT_HT_ERR_CRC8_C 0x1A10
|
#define CNT_HT_ERR_CRC8_C_M 0xFFFF0000
|
#define CNT_VHT_ERR_SIGA_CRC8_C 0x1A14
|
#define CNT_VHT_ERR_SIGA_CRC8_C_M 0xFFFF
|
#define CNT_HT_NOT_SUPPORT_MCS_C 0x1A18
|
#define CNT_HT_NOT_SUPPORT_MCS_C_M 0xFFFF
|
#define CNT_VHT_NOT_SUPPORT_MCS_C 0x1A18
|
#define CNT_VHT_NOT_SUPPORT_MCS_C_M 0xFFFF0000
|
#define CNT_ERR_DURING_BT_TX_C 0x1A1C
|
#define CNT_ERR_DURING_BT_TX_C_M 0xFFFF
|
#define CNT_ERR_DURING_BT_RX_C 0x1A1C
|
#define CNT_ERR_DURING_BT_RX_C_M 0xFFFF0000
|
#define CNT_EDGE_MURX_NSTS0_C 0x1A20
|
#define CNT_EDGE_MURX_NSTS0_C_M 0xFFFF
|
#define CNT_SEARCH_FAIL_C 0x1A20
|
#define CNT_SEARCH_FAIL_C_M 0xFFFF0000
|
#define CNT_OFDM_CCA_C 0x1A24
|
#define CNT_OFDM_CCA_C_M 0xFFFF
|
#define CNT_OFDM_CCA_S20_C 0x1A24
|
#define CNT_OFDM_CCA_S20_C_M 0xFFFF0000
|
#define CNT_OFDM_CCA_S40_C 0x1A28
|
#define CNT_OFDM_CCA_S40_C_M 0xFFFF
|
#define CNT_OFDM_CCA_S80_C 0x1A28
|
#define CNT_OFDM_CCA_S80_C_M 0xFFFF0000
|
#define CNT_INVLD_CCA1_CCK_PKT_C 0x1A2C
|
#define CNT_INVLD_CCA1_CCK_PKT_C_M 0xFFFF
|
#define CNT_INVLD_CCA1_OFDM_PKT_C 0x1A2C
|
#define CNT_INVLD_CCA1_OFDM_PKT_C_M 0xFFFF0000
|
#define CNT_INVLD_PKT_C 0x1A30
|
#define CNT_INVLD_PKT_C_M 0xFFFF
|
#define CNT_INVLD_CCA0_PKT_C 0x1A30
|
#define CNT_INVLD_CCA0_PKT_C_M 0xFFFF0000
|
#define CNT_OFDM_CCA_MAC_C 0x1A34
|
#define CNT_OFDM_CCA_MAC_C_M 0xFFFF
|
#define CNT_CCK_CCA_MAC_C 0x1A34
|
#define CNT_CCK_CCA_MAC_C_M 0xFFFF0000
|
#define CNT_MAC_PIN_C 0x1A38
|
#define CNT_MAC_PIN_C_M 0xFFFF
|
#define CNT_GNT_CONFLICT_TX_C 0x1A38
|
#define CNT_GNT_CONFLICT_TX_C_M 0xFFFF0000
|
#define CNT_GNT_CONFLICT_RX_C 0x1A3C
|
#define CNT_GNT_CONFLICT_RX_C_M 0xFFFF
|
#define CNT_FTM_LBK_C 0x1A3C
|
#define CNT_FTM_LBK_C_M 0xFFFF0000
|
#define CNT_OFDMTXON_C 0x1A40
|
#define CNT_OFDMTXON_C_M 0xFFFF
|
#define CNT_OFDMTXEN_C 0x1A40
|
#define CNT_OFDMTXEN_C_M 0xFFFF0000
|
#define CNT_DROP_TRIG_C 0x1A44
|
#define CNT_DROP_TRIG_C_M 0xFFFF
|
#define CNT_POP_TRIG_C 0x1A44
|
#define CNT_POP_TRIG_C_M 0xFFFF0000
|
#define CNT_TX_CONFLICT_C 0x1A48
|
#define CNT_TX_CONFLICT_C_M 0xFFFF
|
#define CNT_WMAC_RSTB_C 0x1A48
|
#define CNT_WMAC_RSTB_C_M 0xFFFF0000
|
#define CNT_EN_TB_PPDU_FIX_GAIN_C 0x1A4C
|
#define CNT_EN_TB_PPDU_FIX_GAIN_C_M 0xFFFF
|
#define CNT_EN_TB_CCA_PW_TH_C 0x1A4C
|
#define CNT_EN_TB_CCA_PW_TH_C_M 0xFFFF0000
|
#define CNT_TB_FAIL_FREERUN_C 0x1A50
|
#define CNT_TB_FAIL_FREERUN_C_M 0xFFFF
|
#define CNT_TB_PD_HIT_SEG0_C 0x1A50
|
#define CNT_TB_PD_HIT_SEG0_C_M 0xFFFF0000
|
#define CNT_TB_SBDRDY_SEG0_C 0x1A54
|
#define CNT_TB_SBDRDY_SEG0_C_M 0xFFFF
|
#define CNT_FAIL_FORCE_CCA_PW_TB_C 0x1A54
|
#define CNT_FAIL_FORCE_CCA_PW_TB_C_M 0xFF0000
|
#define CNT_FAIL_FORCE_GAIN_TB_C 0x1A54
|
#define CNT_FAIL_FORCE_GAIN_TB_C_M 0xFF000000
|
#define CNT_HE_CRC_OK_C 0x1A58
|
#define CNT_HE_CRC_OK_C_M 0xFFFF
|
#define CNT_HE_CRC_ERR_C 0x1A58
|
#define CNT_HE_CRC_ERR_C_M 0xFFFF0000
|
#define CNT_VHT_CRC_OK_C 0x1A5C
|
#define CNT_VHT_CRC_OK_C_M 0xFFFF
|
#define CNT_VHT_CRC_ERR_C 0x1A5C
|
#define CNT_VHT_CRC_ERR_C_M 0xFFFF0000
|
#define CNT_HT_CRC_OK_C 0x1A60
|
#define CNT_HT_CRC_OK_C_M 0xFFFF
|
#define CNT_HT_CRC_ERR_C 0x1A60
|
#define CNT_HT_CRC_ERR_C_M 0xFFFF0000
|
#define CNT_L_CRC_OK_C 0x1A64
|
#define CNT_L_CRC_OK_C_M 0xFFFF
|
#define CNT_L_CRC_ERR_C 0x1A64
|
#define CNT_L_CRC_ERR_C_M 0xFFFF0000
|
#define CNT_HE_CRC_OK2_C 0x1A68
|
#define CNT_HE_CRC_OK2_C_M 0xFFFF
|
#define CNT_HE_CRC_ERR2_C 0x1A68
|
#define CNT_HE_CRC_ERR2_C_M 0xFFFF0000
|
#define CNT_VHT_CRC_OK2_C 0x1A6C
|
#define CNT_VHT_CRC_OK2_C_M 0xFFFF
|
#define CNT_VHT_CRC_ERR2_C 0x1A6C
|
#define CNT_VHT_CRC_ERR2_C_M 0xFFFF0000
|
#define CNT_HT_CRC_OK2_C 0x1A70
|
#define CNT_HT_CRC_OK2_C_M 0xFFFF
|
#define CNT_HT_CRC_ERR2_C 0x1A70
|
#define CNT_HT_CRC_ERR2_C_M 0xFFFF0000
|
#define CNT_L_CRC_OK2_C 0x1A74
|
#define CNT_L_CRC_OK2_C_M 0xFFFF
|
#define CNT_L_CRC_ERR2_C 0x1A74
|
#define CNT_L_CRC_ERR2_C_M 0xFFFF0000
|
#define CNT_L_CRC_OK3_C 0x1A78
|
#define CNT_L_CRC_OK3_C_M 0xFFFF
|
#define CNT_L_CRC_ERR3_C 0x1A78
|
#define CNT_L_CRC_ERR3_C_M 0xFFFF0000
|
#define CNT_AMPDU_RXON_C 0x1A7C
|
#define CNT_AMPDU_RXON_C_M 0xFFFF
|
#define CNT_AMPDU_MISS_C 0x1A7C
|
#define CNT_AMPDU_MISS_C_M 0xFFFF0000
|
#define CNT_AMPDU_RX_CRC32_OK_C 0x1A80
|
#define CNT_AMPDU_RX_CRC32_OK_C_M 0xFFFF
|
#define CNT_AMPDU_RX_CRC32_ERR_C 0x1A80
|
#define CNT_AMPDU_RX_CRC32_ERR_C_M 0xFFFF0000
|
#define CNT_PKT_FMT_MATCH_C 0x1A84
|
#define CNT_PKT_FMT_MATCH_C_M 0xFFFF
|
#define CNT_LA_FRAME_CTRL_MATCH_C 0x1A84
|
#define CNT_LA_FRAME_CTRL_MATCH_C_M 0xFFFF0000
|
#define NHM_CNT0_C 0x1A88
|
#define NHM_CNT0_C_M 0xFFFF
|
#define NHM_CNT1_C 0x1A88
|
#define NHM_CNT1_C_M 0xFFFF0000
|
#define NHM_CNT2_C 0x1A8C
|
#define NHM_CNT2_C_M 0xFFFF
|
#define NHM_CNT3_C 0x1A8C
|
#define NHM_CNT3_C_M 0xFFFF0000
|
#define NHM_CNT4_C 0x1A90
|
#define NHM_CNT4_C_M 0xFFFF
|
#define NHM_CNT5_C 0x1A90
|
#define NHM_CNT5_C_M 0xFFFF0000
|
#define NHM_CNT6_C 0x1A94
|
#define NHM_CNT6_C_M 0xFFFF
|
#define NHM_CNT7_C 0x1A94
|
#define NHM_CNT7_C_M 0xFFFF0000
|
#define NHM_CNT8_C 0x1A98
|
#define NHM_CNT8_C_M 0xFFFF
|
#define NHM_CNT9_C 0x1A98
|
#define NHM_CNT9_C_M 0xFFFF0000
|
#define NHM_CNT10_C 0x1A9C
|
#define NHM_CNT10_C_M 0xFFFF
|
#define NHM_CNT11_C 0x1A9C
|
#define NHM_CNT11_C_M 0xFFFF0000
|
#define NHM_CCA_CNT_C 0x1AA0
|
#define NHM_CCA_CNT_C_M 0xFFFF
|
#define NHM_TXON_CNT_C 0x1AA0
|
#define NHM_TXON_CNT_C_M 0xFFFF0000
|
#define NHM_IDLE_CNT_C 0x1AA4
|
#define NHM_IDLE_CNT_C_M 0xFFFF
|
#define NHM_RDY_C 0x1AA4
|
#define NHM_RDY_C_M 0x10000
|
#define RO_FAHM_NUM0_C 0x1AA8
|
#define RO_FAHM_NUM0_C_M 0xFFFF
|
#define RO_FAHM_NUM1_C 0x1AA8
|
#define RO_FAHM_NUM1_C_M 0xFFFF0000
|
#define RO_FAHM_NUM2_C 0x1AAC
|
#define RO_FAHM_NUM2_C_M 0xFFFF
|
#define RO_FAHM_NUM3_C 0x1AAC
|
#define RO_FAHM_NUM3_C_M 0xFFFF0000
|
#define RO_FAHM_NUM4_C 0x1AB0
|
#define RO_FAHM_NUM4_C_M 0xFFFF
|
#define RO_FAHM_NUM5_C 0x1AB0
|
#define RO_FAHM_NUM5_C_M 0xFFFF0000
|
#define RO_FAHM_NUM6_C 0x1AB4
|
#define RO_FAHM_NUM6_C_M 0xFFFF
|
#define RO_FAHM_NUM7_C 0x1AB4
|
#define RO_FAHM_NUM7_C_M 0xFFFF0000
|
#define RO_FAHM_NUM8_C 0x1AB8
|
#define RO_FAHM_NUM8_C_M 0xFFFF
|
#define RO_FAHM_NUM9_C 0x1AB8
|
#define RO_FAHM_NUM9_C_M 0xFFFF0000
|
#define RO_FAHM_NUM10_C 0x1ABC
|
#define RO_FAHM_NUM10_C_M 0xFFFF
|
#define RO_FAHM_NUM11_C 0x1ABC
|
#define RO_FAHM_NUM11_C_M 0xFFFF0000
|
#define RO_FAHM_DEN_C 0x1AC0
|
#define RO_FAHM_DEN_C_M 0xFFFF
|
#define RO_FAHM_RDY_C 0x1AC0
|
#define RO_FAHM_RDY_C_M 0x10000
|
#define RO_CLM_RESULT_C 0x1AC4
|
#define RO_CLM_RESULT_C_M 0xFFFF
|
#define RO_CLM_RDY_C 0x1AC4
|
#define RO_CLM_RDY_C_M 0x10000
|
#define RO_CLM_EDCCA_RESULT_C 0x1AC8
|
#define RO_CLM_EDCCA_RESULT_C_M 0xFFFF
|
#define RO_CLM_EDCCA_RDY_C 0x1AC8
|
#define RO_CLM_EDCCA_RDY_C_M 0x10000
|
#define IFSCNT_CNT_TX_C 0x1ACC
|
#define IFSCNT_CNT_TX_C_M 0xFFFF
|
#define IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C 0x1ACC
|
#define IFSCNT_CNT_EDCCA_EXCLUDE_CCA_FA_C_M 0xFFFF0000
|
#define IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C 0x1AD0
|
#define IFSCNT_CNT_CCKCCA_EXCLUDE_FA_C_M 0xFFFF
|
#define IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C 0x1AD0
|
#define IFSCNT_CNT_OFDMCCA_EXCLUDE_FA_C_M 0xFFFF0000
|
#define IFSCNT_CNT_CCKFA_C 0x1AD4
|
#define IFSCNT_CNT_CCKFA_C_M 0xFFFF
|
#define IFSCNT_CNT_OFDMFA_C 0x1AD4
|
#define IFSCNT_CNT_OFDMFA_C_M 0xFFFF0000
|
#define IFS_T1_AVG_C 0x1ADC
|
#define IFS_T1_AVG_C_M 0xFFFF
|
#define IFS_T2_AVG_C 0x1ADC
|
#define IFS_T2_AVG_C_M 0xFFFF0000
|
#define IFS_T3_AVG_C 0x1AE0
|
#define IFS_T3_AVG_C_M 0xFFFF
|
#define IFS_T4_AVG_C 0x1AE0
|
#define IFS_T4_AVG_C_M 0xFFFF0000
|
#define IFS_T1_CLM_C 0x1AE4
|
#define IFS_T1_CLM_C_M 0xFFFF
|
#define IFS_T2_CLM_C 0x1AE4
|
#define IFS_T2_CLM_C_M 0xFFFF0000
|
#define IFS_T3_CLM_C 0x1AE8
|
#define IFS_T3_CLM_C_M 0xFFFF
|
#define IFS_T4_CLM_C 0x1AE8
|
#define IFS_T4_CLM_C_M 0xFFFF0000
|
#define IFS_TOTAL_C 0x1AEC
|
#define IFS_TOTAL_C_M 0xFFFF
|
#define IFSCNT_DONE_C 0x1AEC
|
#define IFSCNT_DONE_C_M 0x10000
|
#define IFS_COUNTING_C 0x1AEC
|
#define IFS_COUNTING_C_M 0x20000
|
#define STS_KEEPER_DATA_C 0x1AF0
|
#define STS_KEEPER_DATA_C_M 0xFFFFFFFF
|
#define PERIOD_S1_C 0x1AF4
|
#define PERIOD_S1_C_M 0xFFFF
|
#define PERIOD_S2_C 0x1AF4
|
#define PERIOD_S2_C_M 0xFFFF0000
|
#define PERIOD_S3_C 0x1AF8
|
#define PERIOD_S3_C_M 0xFFFF
|
#define PERIOD_S4_C 0x1AF8
|
#define PERIOD_S4_C_M 0xFFFF0000
|
#define OFDM_CRC32_OK_OR_C 0x1AFC
|
#define OFDM_CRC32_OK_OR_C_M 0xFFFF
|
#define CNT_NO_DATA_RECEIVED_C 0x1AFC
|
#define CNT_NO_DATA_RECEIVED_C_M 0xFFFF0000
|
#define CNT_HESU_ERR_SIG_A_CRC4_C 0x1B00
|
#define CNT_HESU_ERR_SIG_A_CRC4_C_M 0xFFFF
|
#define CNT_HEERSU_ERR_SIG_A_CRC4_C 0x1B00
|
#define CNT_HEERSU_ERR_SIG_A_CRC4_C_M 0xFFFF0000
|
#define CNT_HEMU_ERR_SIG_A_CRC4_C 0x1B04
|
#define CNT_HEMU_ERR_SIG_A_CRC4_C_M 0xFFFF
|
#define CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C 0x1B04
|
#define CNT_HEMU_ERR_SIGB_CH1_COMM_CRC4_C_M 0xFFFF0000
|
#define CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C 0x1B08
|
#define CNT_HEMU_ERR_SIGB_CH2_COMM_CRC4_C_M 0xFFFF
|
#define CNT_HE_U0_ERR_BCC_MCS_C 0x1B08
|
#define CNT_HE_U0_ERR_BCC_MCS_C_M 0xFFFF0000
|
#define CNT_HE_U0_ERR_MCS_C 0x1B0C
|
#define CNT_HE_U0_ERR_MCS_C_M 0xFFFF
|
#define CNT_HE_U0_ERR_DCM_MCS_C 0x1B0C
|
#define CNT_HE_U0_ERR_DCM_MCS_C_M 0xFFFF0000
|
#define MONITOR0_C 0x1B10
|
#define MONITOR0_C_M 0xFFFFFFFF
|
#define MONITOR1_C 0x1B14
|
#define MONITOR1_C_M 0xFFFFFFFF
|
#define CNT_TXINFO_TXTP_MATCH_C 0x1B18
|
#define CNT_TXINFO_TXTP_MATCH_C_M 0xFFFF
|
#define CNT_RX_PMAC_CRC32_OK_USER0_C 0x1B1C
|
#define CNT_RX_PMAC_CRC32_OK_USER0_C_M 0xFFFF
|
#define CNT_RX_PMAC_CRC32_OK_USER1_C 0x1B1C
|
#define CNT_RX_PMAC_CRC32_OK_USER1_C_M 0xFFFF0000
|
#define CNT_RX_PMAC_CRC32_OK_USER2_C 0x1B20
|
#define CNT_RX_PMAC_CRC32_OK_USER2_C_M 0xFFFF
|
#define CNT_RX_PMAC_CRC32_OK_USER3_C 0x1B20
|
#define CNT_RX_PMAC_CRC32_OK_USER3_C_M 0xFFFF0000
|
#define CNT_PFD_STAGE2B_MISS_C 0x1B24
|
#define CNT_PFD_STAGE2B_MISS_C_M 0xFF
|
#define CNT_PFD_STAGE2A_MISS_C 0x1B24
|
#define CNT_PFD_STAGE2A_MISS_C_M 0xFF00
|
#define CNT_PFD_STAGE0_MISS_C 0x1B24
|
#define CNT_PFD_STAGE0_MISS_C_M 0xFF0000
|
#define CNT_RX_IN_HT_DET_C 0x1B28
|
#define CNT_RX_IN_HT_DET_C_M 0xFFFF
|
#define CNT_RX_IN_NHT_DET_C 0x1B28
|
#define CNT_RX_IN_NHT_DET_C_M 0xFFFF0000
|
#define CNT_RX_IN_HE_DET_C 0x1B2C
|
#define CNT_RX_IN_HE_DET_C_M 0xFFFF
|
#define CNT_RX_IN_VHT_DET_C 0x1B2C
|
#define CNT_RX_IN_VHT_DET_C_M 0xFFFF0000
|
#define CNT_BRK_IN_HE_TB_C 0x1B30
|
#define CNT_BRK_IN_HE_TB_C_M 0xFFFF
|
#define CNT_NEG_GI2_OFST_OCCUR_C 0x1B34
|
#define CNT_NEG_GI2_OFST_OCCUR_C_M 0xFFFF
|
#define P0_L_TOT_PW_DBFS_RX0_C 0x1B38
|
#define P0_L_TOT_PW_DBFS_RX0_C_M 0xFFF
|
#define P0_L_TOT_PW_DBFS_RX1_C 0x1B38
|
#define P0_L_TOT_PW_DBFS_RX1_C_M 0xFFF000
|
#define P0_ANT_GAIN_DBM_RX_0_C 0x1B3C
|
#define P0_ANT_GAIN_DBM_RX_0_C_M 0x3FF
|
#define P0_ANT_GAIN_DBM_RX_1_C 0x1B3C
|
#define P0_ANT_GAIN_DBM_RX_1_C_M 0xFFC00
|
#define P0_PWINFO_RPL_DBM_TO_RPT_C 0x1B3C
|
#define P0_PWINFO_RPL_DBM_TO_RPT_C_M 0x1FF00000
|
#define P0_TOT_PW_DBFS_RX0_C 0x1B40
|
#define P0_TOT_PW_DBFS_RX0_C_M 0xFFF
|
#define P0_TOT_PW_DBFS_RX1_C 0x1B40
|
#define P0_TOT_PW_DBFS_RX1_C_M 0xFFF000
|
#define P0_RPL_COM_TERM_C 0x1B44
|
#define P0_RPL_COM_TERM_C_M 0x3FFF
|
#define P0_TB_RSSI_COM_TERM_C 0x1B44
|
#define P0_TB_RSSI_COM_TERM_C_M 0xFFFC000
|
#define P0_L_TOT_PW_DBM_RX0_C 0x1B48
|
#define P0_L_TOT_PW_DBM_RX0_C_M 0x1FFF
|
#define P0_L_TOT_PW_DBM_RX1_C 0x1B48
|
#define P0_L_TOT_PW_DBM_RX1_C_M 0x3FFE000
|
#define P0_TX_TD_CFO_C 0x1B4C
|
#define P0_TX_TD_CFO_C_M 0xFFF
|
#define IFS_T1_HIS_C 0x1B50
|
#define IFS_T1_HIS_C_M 0xFFFF
|
#define IFS_T2_HIS_C 0x1B50
|
#define IFS_T2_HIS_C_M 0xFFFF0000
|
#define IFS_T3_HIS_C 0x1B54
|
#define IFS_T3_HIS_C_M 0xFFFF
|
#define IFS_T4_HIS_C 0x1B54
|
#define IFS_T4_HIS_C_M 0xFFFF0000
|
#define PATH0_TSSI_DBG_PORT_C 0x1C00
|
#define PATH0_TSSI_DBG_PORT_C_M 0xFFFFFFFF
|
#define PATH0_DCK_AUTO_AVG_DC_C 0x1C04
|
#define PATH0_DCK_AUTO_AVG_DC_C_M 0xFFF000
|
#define PATH0_HE_LSTF_PW_OFST_C 0x1C04
|
#define PATH0_HE_LSTF_PW_OFST_C_M 0xFF000000
|
#define PATH0_DCK_AUTO_MAX_DC_C 0x1C08
|
#define PATH0_DCK_AUTO_MAX_DC_C_M 0xFFF
|
#define PATH0_DCK_AUTO_MIN_DC_C 0x1C08
|
#define PATH0_DCK_AUTO_MIN_DC_C_M 0xFFF000
|
#define PATH0_TMETER_F_C 0x1C08
|
#define PATH0_TMETER_F_C_M 0xFF000000
|
#define PATH0_TSSI_AVG_R_C 0x1C10
|
#define PATH0_TSSI_AVG_R_C_M 0xFFF
|
#define PATH0_TSSI_MAX_R_C 0x1C10
|
#define PATH0_TSSI_MAX_R_C_M 0xFFF000
|
#define PATH0_TSSI_F_NOW_C 0x1C10
|
#define PATH0_TSSI_F_NOW_C_M 0xFF000000
|
#define PATH0_TSSI_MID_R_C 0x1C14
|
#define PATH0_TSSI_MID_R_C_M 0xFFF
|
#define PATH0_TSSI_LAST_R_C 0x1C14
|
#define PATH0_TSSI_LAST_R_C_M 0xFFF000
|
#define PATH0_GAIN_TX_IPA_MX_C 0x1C14
|
#define PATH0_GAIN_TX_IPA_MX_C_M 0x7000000
|
#define PATH0_TSSI_VAL_AVG_C 0x1C18
|
#define PATH0_TSSI_VAL_AVG_C_M 0x3FF
|
#define PATH0_TSSI_VAL_AVG_OUT_VLD_C 0x1C18
|
#define PATH0_TSSI_VAL_AVG_OUT_VLD_C_M 0x10000
|
#define PATH0_ADC_RE_C 0x1C18
|
#define PATH0_ADC_RE_C_M 0xFFF00000
|
#define PATH0_TSSI_VAL_D00_C 0x1C1C
|
#define PATH0_TSSI_VAL_D00_C_M 0x3FF
|
#define PATH0_TSSI_VAL_VLD_IDX_0_C 0x1C1C
|
#define PATH0_TSSI_VAL_VLD_IDX_0_C_M 0x8000
|
#define PATH0_TSSI_VAL_D01_C 0x1C1C
|
#define PATH0_TSSI_VAL_D01_C_M 0x3FF0000
|
#define PATH0_TSSI_VAL_VLD_IDX_1_C 0x1C1C
|
#define PATH0_TSSI_VAL_VLD_IDX_1_C_M 0x80000000
|
#define PATH0_TSSI_VAL_D02_C 0x1C20
|
#define PATH0_TSSI_VAL_D02_C_M 0x3FF
|
#define PATH0_TSSI_VAL_VLD_IDX_2_C 0x1C20
|
#define PATH0_TSSI_VAL_VLD_IDX_2_C_M 0x8000
|
#define PATH0_TSSI_VAL_D03_C 0x1C20
|
#define PATH0_TSSI_VAL_D03_C_M 0x3FF0000
|
#define PATH0_TSSI_VAL_VLD_IDX_3_C 0x1C20
|
#define PATH0_TSSI_VAL_VLD_IDX_3_C_M 0x80000000
|
#define PATH0_TSSI_VAL_D04_C 0x1C24
|
#define PATH0_TSSI_VAL_D04_C_M 0x3FF
|
#define PATH0_TSSI_VAL_VLD_IDX_4_C 0x1C24
|
#define PATH0_TSSI_VAL_VLD_IDX_4_C_M 0x8000
|
#define PATH0_TSSI_VAL_D05_C 0x1C24
|
#define PATH0_TSSI_VAL_D05_C_M 0x3FF0000
|
#define PATH0_TSSI_VAL_VLD_IDX_5_C 0x1C24
|
#define PATH0_TSSI_VAL_VLD_IDX_5_C_M 0x80000000
|
#define PATH0_TSSI_VAL_D06_C 0x1C28
|
#define PATH0_TSSI_VAL_D06_C_M 0x3FF
|
#define PATH0_TSSI_VAL_VLD_IDX_6_C 0x1C28
|
#define PATH0_TSSI_VAL_VLD_IDX_6_C_M 0x8000
|
#define PATH0_TSSI_VAL_D07_C 0x1C28
|
#define PATH0_TSSI_VAL_D07_C_M 0x3FF0000
|
#define PATH0_TSSI_VAL_VLD_IDX_7_C 0x1C28
|
#define PATH0_TSSI_VAL_VLD_IDX_7_C_M 0x80000000
|
#define PATH0_TSSI_VAL_D08_C 0x1C2C
|
#define PATH0_TSSI_VAL_D08_C_M 0x3FF
|
#define PATH0_TSSI_VAL_VLD_IDX_8_C 0x1C2C
|
#define PATH0_TSSI_VAL_VLD_IDX_8_C_M 0x8000
|
#define PATH0_TSSI_VAL_D09_C 0x1C2C
|
#define PATH0_TSSI_VAL_D09_C_M 0x3FF0000
|
#define PATH0_TSSI_VAL_VLD_IDX_9_C 0x1C2C
|
#define PATH0_TSSI_VAL_VLD_IDX_9_C_M 0x80000000
|
#define PATH0_TSSI_VAL_D10_C 0x1C30
|
#define PATH0_TSSI_VAL_D10_C_M 0x3FF
|
#define PATH0_TSSI_VAL_VLD_IDX_10_C 0x1C30
|
#define PATH0_TSSI_VAL_VLD_IDX_10_C_M 0x8000
|
#define PATH0_TSSI_VAL_D11_C 0x1C30
|
#define PATH0_TSSI_VAL_D11_C_M 0x3FF0000
|
#define PATH0_TSSI_VAL_VLD_IDX_11_C 0x1C30
|
#define PATH0_TSSI_VAL_VLD_IDX_11_C_M 0x80000000
|
#define PATH0_TSSI_VAL_D12_C 0x1C34
|
#define PATH0_TSSI_VAL_D12_C_M 0x3FF
|
#define PATH0_TSSI_VAL_VLD_IDX_12_C 0x1C34
|
#define PATH0_TSSI_VAL_VLD_IDX_12_C_M 0x8000
|
#define PATH0_TSSI_VAL_D13_C 0x1C34
|
#define PATH0_TSSI_VAL_D13_C_M 0x3FF0000
|
#define PATH0_TSSI_VAL_VLD_IDX_13_C 0x1C34
|
#define PATH0_TSSI_VAL_VLD_IDX_13_C_M 0x80000000
|
#define PATH0_TSSI_VAL_D14_C 0x1C38
|
#define PATH0_TSSI_VAL_D14_C_M 0x3FF
|
#define PATH0_TSSI_VAL_VLD_IDX_14_C 0x1C38
|
#define PATH0_TSSI_VAL_VLD_IDX_14_C_M 0x8000
|
#define PATH0_TSSI_VAL_D15_C 0x1C38
|
#define PATH0_TSSI_VAL_D15_C_M 0x3FF0000
|
#define PATH0_TSSI_VAL_VLD_IDX_15_C 0x1C38
|
#define PATH0_TSSI_VAL_VLD_IDX_15_C_M 0x80000000
|
#define PATH0_TSSI_OSCILLATION_CNT_C 0x1C3C
|
#define PATH0_TSSI_OSCILLATION_CNT_C_M 0xFFFF
|
#define PATH0_TSSI_VAL_VLD_IDX_C 0x1C3C
|
#define PATH0_TSSI_VAL_VLD_IDX_C_M 0xFFFF0000
|
#define PATH0_PRE_TXAGC_OFST_C 0x1C40
|
#define PATH0_PRE_TXAGC_OFST_C_M 0xFF00
|
#define PATH0_DELTA_TSSI_PW_C 0x1C40
|
#define PATH0_DELTA_TSSI_PW_C_M 0xFF0000
|
#define PATH0SWING_MIN_C 0x1C40
|
#define PATH0SWING_MIN_C_M 0xF000000
|
#define PATH0SWING_MAX_C 0x1C40
|
#define PATH0SWING_MAX_C_M 0xF0000000
|
#define PATH0_TSSI_C_RAW0_C 0x1C44
|
#define PATH0_TSSI_C_RAW0_C_M 0x1FF000
|
#define PATH0_TSSI_F_C 0x1C48
|
#define PATH0_TSSI_F_C_M 0xFF
|
#define PATH0_TSSI_G_C 0x1C48
|
#define PATH0_TSSI_G_C_M 0x3FF00
|
#define PATH0_TSSI_S_C 0x1C48
|
#define PATH0_TSSI_S_C_M 0x1FF00000
|
#define PATH0_AVG_R_SQUARE_C 0x1C4C
|
#define PATH0_AVG_R_SQUARE_C_M 0xFFFFFF
|
#define PATH0_TSSI_F_RDY_C 0x1C4C
|
#define PATH0_TSSI_F_RDY_C_M 0x20000000
|
#define PATH0_TSSI_G_RDY_C 0x1C4C
|
#define PATH0_TSSI_G_RDY_C_M 0x40000000
|
#define PATH0_TSSI_C_RDY_C 0x1C4C
|
#define PATH0_TSSI_C_RDY_C_M 0x80000000
|
#define PATH0_IN_R_SQUARE_MAX_C 0x1C50
|
#define PATH0_IN_R_SQUARE_MAX_C_M 0xFFFFFF
|
#define PATH0_SPEC_IDX_C 0x1C50
|
#define PATH0_SPEC_IDX_C_M 0x7000000
|
#define PATH0_IN_R_SQUARE_MIN_C 0x1C54
|
#define PATH0_IN_R_SQUARE_MIN_C_M 0xFFFFFF
|
#define PATH0_AVG_R_RMS_C 0x1C58
|
#define PATH0_AVG_R_RMS_C_M 0xFFF
|
#define PATH0_AVG_R_RMS_RDY_C 0x1C58
|
#define PATH0_AVG_R_RMS_RDY_C_M 0x80000000
|
#define PATH0_DAC_GAIN_COMP_TBL_IDX_C 0x1C5C
|
#define PATH0_DAC_GAIN_COMP_TBL_IDX_C_M 0xFF
|
#define PATH0_DAC_GAIN_COMP_DBG_C 0x1C5C
|
#define PATH0_DAC_GAIN_COMP_DBG_C_M 0xFFFFF00
|
#define PATH0_TXAGC_RF_C 0x1C60
|
#define PATH0_TXAGC_RF_C_M 0x3F
|
#define PATH0_TSSI_OFST_C 0x1C60
|
#define PATH0_TSSI_OFST_C_M 0x1F00
|
#define PATH0_TXAGC_C 0x1C60
|
#define PATH0_TXAGC_C_M 0xFF0000
|
#define PATH0_TXAGC_ORIG_C 0x1C64
|
#define PATH0_TXAGC_ORIG_C_M 0x1FF
|
#define PATH0_TXAGC_ORIG_RAW_C 0x1C64
|
#define PATH0_TXAGC_ORIG_RAW_C_M 0x1FF000
|
#define PATH0_TXAGC_OFST_SEL_NONRFC_RPT_C 0x1C64
|
#define PATH0_TXAGC_OFST_SEL_NONRFC_RPT_C_M 0xFF000000
|
#define PATH0_TXAGC_TO_TSSI_CW_RPT_C 0x1C68
|
#define PATH0_TXAGC_TO_TSSI_CW_RPT_C_M 0xFFFFFFFF
|
#define PATH0_TSSI_C_RAW1_C 0x1C6C
|
#define PATH0_TSSI_C_RAW1_C_M 0x1FF
|
#define PATH0_DAC_GAIN_COMP_MX_C 0x1C70
|
#define PATH0_DAC_GAIN_COMP_MX_C_M 0xFF0000
|
#define PATH0_TSSI_CW_COMP_MX_C 0x1C70
|
#define PATH0_TSSI_CW_COMP_MX_C_M 0xFF000000
|
#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_C 0x1C74
|
#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_C_M 0x1FF
|
#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_C 0x1C74
|
#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_C_M 0x1FF000
|
#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x1C74
|
#define PATH0_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x1000000
|
#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x1C74
|
#define PATH0_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x2000000
|
#define PATH0_RFC_PREAMLE_PW_TYPE_C 0x1C74
|
#define PATH0_RFC_PREAMLE_PW_TYPE_C_M 0x70000000
|
#define PATH0_TXPW_C 0x1C78
|
#define PATH0_TXPW_C_M 0x1FF
|
#define PATH0_TXAGCSWING_C 0x1C78
|
#define PATH0_TXAGCSWING_C_M 0x1E00
|
#define PATH0_HE_ER_SU_EN_C 0x1C78
|
#define PATH0_HE_ER_SU_EN_C_M 0x2000
|
#define PATH0_HE_TB_EN_C 0x1C78
|
#define PATH0_HE_TB_EN_C_M 0x4000
|
#define PATH0_CCK_PPDU_C 0x1C78
|
#define PATH0_CCK_PPDU_C_M 0x8000
|
#define PATH0_TXINFO_CH_WITH_DATA_C 0x1C78
|
#define PATH0_TXINFO_CH_WITH_DATA_C_M 0xFF0000
|
#define PATH0_TXSC_C 0x1C78
|
#define PATH0_TXSC_C_M 0xF000000
|
#define PATH0_RF_BW_IDX_C 0x1C78
|
#define PATH0_RF_BW_IDX_C_M 0x30000000
|
#define PATH0_ISOFDM_PREAMBLE_C 0x1C78
|
#define PATH0_ISOFDM_PREAMBLE_C_M 0x40000000
|
#define PATH0_ISCCK_PREAMBLE_C 0x1C78
|
#define PATH0_ISCCK_PREAMBLE_C_M 0x80000000
|
#define PATH0_TXAGC_OFST_MX_C 0x1C7C
|
#define PATH0_TXAGC_OFST_MX_C_M 0xFF
|
#define PATH0_TXAGC_OFST_C 0x1C7C
|
#define PATH0_TXAGC_OFST_C_M 0xFF00
|
#define PATH0_TXAGC_OFST_VARIATION_POS_FLAG_C 0x1C7C
|
#define PATH0_TXAGC_OFST_VARIATION_POS_FLAG_C_M 0x10000
|
#define PATH0_TXAGC_OFST_VARIATION_NEG_FLAG_C 0x1C7C
|
#define PATH0_TXAGC_OFST_VARIATION_NEG_FLAG_C_M 0x20000
|
#define PATH0_BYPASS_TSSI_BY_C_C 0x1C7C
|
#define PATH0_BYPASS_TSSI_BY_C_C_M 0x40000
|
#define PATH0_ADC_VARIATION_C 0x1C7C
|
#define PATH0_ADC_VARIATION_C_M 0xFFF00000
|
#define PATH0_DBG_IQK_PATH_C 0x1C80
|
#define PATH0_DBG_IQK_PATH_C_M 0xFFFFFFFF
|
#define PATH0_FTM_RFLBK_BYPASS_C 0x1C84
|
#define PATH0_FTM_RFLBK_BYPASS_C_M 0x1
|
#define PATH0_FTM_LBK_BYPASS_C 0x1C84
|
#define PATH0_FTM_LBK_BYPASS_C_M 0x2
|
#define PATH0_FTM_A2A_AFELBK_BYPASS_C 0x1C84
|
#define PATH0_FTM_A2A_AFELBK_BYPASS_C_M 0x4
|
#define PATH0_GNT_BT_TX_BYPASS_C 0x1C84
|
#define PATH0_GNT_BT_TX_BYPASS_C_M 0x8
|
#define PATH0_GNT_BT_BYPASS_C 0x1C84
|
#define PATH0_GNT_BT_BYPASS_C_M 0x10
|
#define PATH0_GNT_WL_BYPASS_C 0x1C84
|
#define PATH0_GNT_WL_BYPASS_C_M 0x20
|
#define PATH0_LTE_RX_BYPASS_C 0x1C84
|
#define PATH0_LTE_RX_BYPASS_C_M 0x40
|
#define PATH0_TSSI_BYPASS_TXPW_MIN_C 0x1C84
|
#define PATH0_TSSI_BYPASS_TXPW_MIN_C_M 0x80
|
#define PATH0_TSSI_BYPASS_TXPW_MAX_C 0x1C84
|
#define PATH0_TSSI_BYPASS_TXPW_MAX_C_M 0x100
|
#define PATH0_BYPASS_TSSI_BY_RATE_CCK_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_CCK_C_M 0x200
|
#define PATH0_BYPASS_TSSI_BY_RATE_LEGACY_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_LEGACY_C_M 0x400
|
#define PATH0_BYPASS_TSSI_BY_RATE_HT_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_HT_C_M 0x800
|
#define PATH0_BYPASS_TSSI_BY_RATE_VHT_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_VHT_C_M 0x1000
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_SU_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_SU_C_M 0x2000
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_ER_SU_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_ER_SU_C_M 0x4000
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_TB_EN_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_TB_EN_C_M 0x8000
|
#define PATH0_BYPASS_TSSI_BY_RATE_VHT_MU_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_VHT_MU_C_M 0x10000
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_MU_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_MU_C_M 0x20000
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_RU_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RATE_HE_RU_C_M 0x40000
|
#define PATH0_BYPASS_TSSI_BY_TXBF_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_TXBF_C_M 0x80000
|
#define PATH0_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x1C84
|
#define PATH0_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x100000
|
#define PATH0_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x1C84
|
#define PATH0_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x200000
|
#define PATH0_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C 0x1C84
|
#define PATH0_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x400000
|
#define PATH0_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C 0x1C84
|
#define PATH0_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x800000
|
#define PATH0_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C 0x1C84
|
#define PATH0_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C_M 0x40000000
|
#define PATH0_BYPASS_TSSI_C 0x1C84
|
#define PATH0_BYPASS_TSSI_C_M 0x80000000
|
#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_C 0x1C88
|
#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_C_M 0xF
|
#define PATH0_DIGI_AGC_C 0x1C88
|
#define PATH0_DIGI_AGC_C_M 0x3FF0
|
#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_MX_C 0x1C88
|
#define PATH0_WLS_WL_GAIN_TX_GAPK_BUF_MX_C_M 0xF0000
|
#define PATH0_WLS_WL_GAIN_TX_PAD_BUF_MX_C 0x1C88
|
#define PATH0_WLS_WL_GAIN_TX_PAD_BUF_MX_C_M 0x1F00000
|
#define PATH0_WLS_WL_GAIN_TX_BUF_MX_C 0x1C88
|
#define PATH0_WLS_WL_GAIN_TX_BUF_MX_C_M 0x3E000000
|
#define PATH0_RX_CFIR_TAP_DEC_C 0x1C88
|
#define PATH0_RX_CFIR_TAP_DEC_C_M 0x40000000
|
#define PATH0_CLK_HIGH_RATE_MX_C 0x1C88
|
#define PATH0_CLK_HIGH_RATE_MX_C_M 0x80000000
|
#define PATH0_CFIR_OUT_IM_DBG_C 0x1C8C
|
#define PATH0_CFIR_OUT_IM_DBG_C_M 0xFFF
|
#define PATH0_CFIR_OUT_RE_DBG_C 0x1C8C
|
#define PATH0_CFIR_OUT_RE_DBG_C_M 0xFFF000
|
#define PATH0_EN_RX_CFIR_C 0x1C8C
|
#define PATH0_EN_RX_CFIR_C_M 0x1000000
|
#define PATH0_CLK_HIGH_RATE_C 0x1C8C
|
#define PATH0_CLK_HIGH_RATE_C_M 0x2000000
|
#define PATH0_EN_TX_CFIR_C 0x1C8C
|
#define PATH0_EN_TX_CFIR_C_M 0x4000000
|
#define PATH0_TX_CCK_IND_C 0x1C8C
|
#define PATH0_TX_CCK_IND_C_M 0x8000000
|
#define PATH0_CFIR_IN_IM_DBG_C 0x1C90
|
#define PATH0_CFIR_IN_IM_DBG_C_M 0xFFF
|
#define PATH0_CFIR_IN_RE_DBG_C 0x1C90
|
#define PATH0_CFIR_IN_RE_DBG_C_M 0xFFF000
|
#define PATH0_CCK_CCA_C 0x1C90
|
#define PATH0_CCK_CCA_C_M 0x80000000
|
#define PATH0_RX_C 0x1C94
|
#define PATH0_RX_C_M 0x1F
|
#define PATH0_LNA_SETTING_C 0x1C94
|
#define PATH0_LNA_SETTING_C_M 0x700
|
#define PATH0_TIA_C 0x1C94
|
#define PATH0_TIA_C_M 0x1000
|
#define PATH0_DB2FLT_O_C 0x1C94
|
#define PATH0_DB2FLT_O_C_M 0x7FF8000
|
#define PATH0_LSTF_SUM_LINEAR_PW_C 0x1C98
|
#define PATH0_LSTF_SUM_LINEAR_PW_C_M 0xFFFFFFFF
|
#define PATH0_LSTF_MAX_LINEAR_PW_C 0x1C9C
|
#define PATH0_LSTF_MAX_LINEAR_PW_C_M 0x7FFFFF
|
#define PATH0_TSSI_C_C 0x1CA0
|
#define PATH0_TSSI_C_C_M 0x1FF
|
#define PATH0_TSSI_C_SRC_C 0x1CA0
|
#define PATH0_TSSI_C_SRC_C_M 0x3FF000
|
#define PATH0_TXAGC_TP_C 0x1CA0
|
#define PATH0_TXAGC_TP_C_M 0xFF000000
|
#define PATH0_LOG_VAL_O_C 0x1CA4
|
#define PATH0_LOG_VAL_O_C_M 0xFFFFF
|
#define PATH0_TXAGC_OFST_ADJ_C 0x1CA4
|
#define PATH0_TXAGC_OFST_ADJ_C_M 0xFF000000
|
#define PATH0_TX_GAIN_FOR_DPD_DB2FLOAT_C 0x1CA8
|
#define PATH0_TX_GAIN_FOR_DPD_DB2FLOAT_C_M 0xFF
|
#define PATH0_TX_GAIN_FOR_DPD_DBAGC_COMB_C 0x1CA8
|
#define PATH0_TX_GAIN_FOR_DPD_DBAGC_COMB_C_M 0xFF00
|
#define PATH0_TMETER_TX_C 0x1CAC
|
#define PATH0_TMETER_TX_C_M 0x3F
|
#define PATH0_TMETER_CCA_POS_C 0x1CAC
|
#define PATH0_TMETER_CCA_POS_C_M 0x3F00
|
#define PATH0_TMETER_CCA_NEG_C 0x1CAC
|
#define PATH0_TMETER_CCA_NEG_C_M 0x3F0000
|
#define PATH0_AFE_ANAPAR_PW_O_C 0x1CB0
|
#define PATH0_AFE_ANAPAR_PW_O_C_M 0xFF
|
#define PATH0_AFE_ANAPAR_CTRL_O_C 0x1CB0
|
#define PATH0_AFE_ANAPAR_CTRL_O_C_M 0xFFFF00
|
#define PATH0_MUX_ST_PATH_C 0x1CB0
|
#define PATH0_MUX_ST_PATH_C_M 0xF000000
|
#define PATH0_TSSI_J_CCK_C 0x1CB4
|
#define PATH0_TSSI_J_CCK_C_M 0x3FF
|
#define PATH0_TSSI_J_OFDM_C 0x1CB4
|
#define PATH0_TSSI_J_OFDM_C_M 0xFFC00
|
#define PATH0_TSSI_CURVE_C 0x1CB4
|
#define PATH0_TSSI_CURVE_C_M 0x70000000
|
#define PATH0_R_TXAGC_OFDM_REF_CW_CMB_C 0x1CB8
|
#define PATH0_R_TXAGC_OFDM_REF_CW_CMB_C_M 0x1FF
|
#define PATH0_R_TXAGC_CCK_REF_CW_CMB_C 0x1CB8
|
#define PATH0_R_TXAGC_CCK_REF_CW_CMB_C_M 0x1FF000
|
#define PATH0_AFE_ANAPAR_CTSDM_OUT_I_C 0x1E00
|
#define PATH0_AFE_ANAPAR_CTSDM_OUT_I_C_M 0xFFFFF
|
#define PATH0_RO_SI_R_DATA_P_C 0x1E04
|
#define PATH0_RO_SI_R_DATA_P_C_M 0xFFFFF
|
#define PATH0_NLGC_STEP_CNT_AT_AGC_RDY_C 0x1E08
|
#define PATH0_NLGC_STEP_CNT_AT_AGC_RDY_C_M 0x7
|
#define PATH0_POST_PD_STEP_CNT_AT_AGC_RDY_C 0x1E08
|
#define PATH0_POST_PD_STEP_CNT_AT_AGC_RDY_C_M 0x38
|
#define PATH0_LINEAR_STEP_CNT_AT_AGC_RDY_C 0x1E08
|
#define PATH0_LINEAR_STEP_CNT_AT_AGC_RDY_C_M 0x1C0
|
#define PATH0_PRE_PD_STEP_CNT_AT_AGC_RDY_C 0x1E08
|
#define PATH0_PRE_PD_STEP_CNT_AT_AGC_RDY_C_M 0xE00
|
#define PATH0_TIA_SAT_DET_AT_AGC_RDY_C 0x1E08
|
#define PATH0_TIA_SAT_DET_AT_AGC_RDY_C_M 0x1000
|
#define PATH0_LNA_SAT_DET_AT_AGC_RDY_C 0x1E08
|
#define PATH0_LNA_SAT_DET_AT_AGC_RDY_C_M 0x2000
|
#define PATH0_NRBW_AT_AGC_RDY_C 0x1E08
|
#define PATH0_NRBW_AT_AGC_RDY_C_M 0x4000
|
#define PATH0_TIA_SHRINK_AT_AGC_RDY_C 0x1E08
|
#define PATH0_TIA_SHRINK_AT_AGC_RDY_C_M 0x8000
|
#define PATH0_P_DIFF_AT_AGC_RDY_C 0x1E08
|
#define PATH0_P_DIFF_AT_AGC_RDY_C_M 0xFF0000
|
#define PATH0_ELNA_IDX_AT_AGC_RDY_C 0x1E0C
|
#define PATH0_ELNA_IDX_AT_AGC_RDY_C_M 0x1
|
#define PATH0_ELNA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_ELNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x2
|
#define PATH0_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x4
|
#define PATH0_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x8
|
#define PATH0_NRBW_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_NRBW_AT_PRE_PD_AGC_RDY_C_M 0x10
|
#define PATH0_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C_M 0x20
|
#define PATH0_P_DIFF_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_P_DIFF_AT_PRE_PD_AGC_RDY_C_M 0x7FC0
|
#define PATH0_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C_M 0x7F8000
|
#define PATH0_RXIDX_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_RXIDX_AT_PRE_PD_AGC_RDY_C_M 0xF800000
|
#define PATH0_TIA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_TIA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x10000000
|
#define PATH0_LNA_IDX_AT_PRE_PD_AGC_RDY_C 0x1E0C
|
#define PATH0_LNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0xE0000000
|
#define PATH0_ELNA_IDX_AT_PD_HIT_C 0x1E10
|
#define PATH0_ELNA_IDX_AT_PD_HIT_C_M 0x2
|
#define PATH0_TIA_SAT_DET_AT_PD_HIT_C 0x1E10
|
#define PATH0_TIA_SAT_DET_AT_PD_HIT_C_M 0x4
|
#define PATH0_LNA_SAT_DET_AT_PD_HIT_C 0x1E10
|
#define PATH0_LNA_SAT_DET_AT_PD_HIT_C_M 0x8
|
#define PATH0_NRBW_AT_PD_HIT_C 0x1E10
|
#define PATH0_NRBW_AT_PD_HIT_C_M 0x10
|
#define PATH0_TIA_SHRINK_AT_PD_HIT_C 0x1E10
|
#define PATH0_TIA_SHRINK_AT_PD_HIT_C_M 0x20
|
#define PATH0_P_DIFF_AT_PD_HIT_C 0x1E10
|
#define PATH0_P_DIFF_AT_PD_HIT_C_M 0x7FC0
|
#define PATH0_G_NLGC_DAGC_AT_PD_HIT_C 0x1E10
|
#define PATH0_G_NLGC_DAGC_AT_PD_HIT_C_M 0x7F8000
|
#define PATH0_RXIDX_AT_PD_HIT_C 0x1E10
|
#define PATH0_RXIDX_AT_PD_HIT_C_M 0xF800000
|
#define PATH0_TIA_IDX_AT_PD_HIT_C 0x1E10
|
#define PATH0_TIA_IDX_AT_PD_HIT_C_M 0x10000000
|
#define PATH0_LNA_IDX_AT_PD_HIT_C 0x1E10
|
#define PATH0_LNA_IDX_AT_PD_HIT_C_M 0xE0000000
|
#define PATH0_ELNA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_ELNA_IDX_AT_POST_PD_AGC_RDY_C_M 0x2
|
#define PATH0_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x4
|
#define PATH0_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x8
|
#define PATH0_NRBW_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_NRBW_AT_POST_PD_AGC_RDY_C_M 0x10
|
#define PATH0_TIA_SHRINK_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_TIA_SHRINK_AT_POST_PD_AGC_RDY_C_M 0x20
|
#define PATH0_P_DIFF_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_P_DIFF_AT_POST_PD_AGC_RDY_C_M 0x7FC0
|
#define PATH0_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C_M 0x7F8000
|
#define PATH0_RXIDX_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_RXIDX_AT_POST_PD_AGC_RDY_C_M 0xF800000
|
#define PATH0_TIA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_TIA_IDX_AT_POST_PD_AGC_RDY_C_M 0x10000000
|
#define PATH0_LNA_IDX_AT_POST_PD_AGC_RDY_C 0x1E14
|
#define PATH0_LNA_IDX_AT_POST_PD_AGC_RDY_C_M 0xE0000000
|
#define PATH0_ELNA_IDX_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_ELNA_IDX_AT_NLGC_AGC_RDY_C_M 0x2
|
#define PATH0_TIA_SAT_DET_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_TIA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x4
|
#define PATH0_LNA_SAT_DET_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_LNA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x8
|
#define PATH0_NRBW_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_NRBW_AT_NLGC_AGC_RDY_C_M 0x10
|
#define PATH0_TIA_SHRINK_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_TIA_SHRINK_AT_NLGC_AGC_RDY_C_M 0x20
|
#define PATH0_P_DIFF_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_P_DIFF_AT_NLGC_AGC_RDY_C_M 0x7FC0
|
#define PATH0_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C_M 0x7F8000
|
#define PATH0_RXIDX_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_RXIDX_AT_NLGC_AGC_RDY_C_M 0xF800000
|
#define PATH0_TIA_IDX_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_TIA_IDX_AT_NLGC_AGC_RDY_C_M 0x10000000
|
#define PATH0_LNA_IDX_AT_NLGC_AGC_RDY_C 0x1E18
|
#define PATH0_LNA_IDX_AT_NLGC_AGC_RDY_C_M 0xE0000000
|
#define PATH0_RSSI_AT_AGC_RDY_C 0x1E1C
|
#define PATH0_RSSI_AT_AGC_RDY_C_M 0x3FF
|
#define PATH0_G_TOTAL_AT_AGC_RDY_C 0x1E1C
|
#define PATH0_G_TOTAL_AT_AGC_RDY_C_M 0x7FC00
|
#define PATH0_P_DFIR_DBM_AT_AGC_RDY_C 0x1E1C
|
#define PATH0_P_DFIR_DBM_AT_AGC_RDY_C_M 0xFF80000
|
#define PATH0_TIA_IDX_AT_AGC_RDY_C 0x1E1C
|
#define PATH0_TIA_IDX_AT_AGC_RDY_C_M 0x10000000
|
#define PATH0_LNA_IDX_AT_AGC_RDY_C 0x1E1C
|
#define PATH0_LNA_IDX_AT_AGC_RDY_C_M 0xE0000000
|
#define PATH0_RSSI_ALWAYS_RUN_C 0x1E20
|
#define PATH0_RSSI_ALWAYS_RUN_C_M 0x3FF
|
#define PATH0_TIA_SAT_DET_C 0x1E20
|
#define PATH0_TIA_SAT_DET_C_M 0x400
|
#define PATH0_LNA_SAT_DET_C 0x1E20
|
#define PATH0_LNA_SAT_DET_C_M 0x800
|
#define PATH0_NRBW_C 0x1E20
|
#define PATH0_NRBW_C_M 0x1000
|
#define PATH0_TIA_SHRINK_C 0x1E20
|
#define PATH0_TIA_SHRINK_C_M 0x2000
|
#define PATH0_G_LGC_DAGC_C 0x1E20
|
#define PATH0_G_LGC_DAGC_C_M 0x3FC000
|
#define PATH0_G_TOTAL_C 0x1E20
|
#define PATH0_G_TOTAL_C_M 0xFFC00000
|
#define PATH0_HW_SI_READ_DATA_C 0x1E24
|
#define PATH0_HW_SI_READ_DATA_C_M 0xFFFFF
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C_M 0x1
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C_M 0x2
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C_M 0x4
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C_M 0x8
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C_M 0x10
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C_M 0x20
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C_M 0x40
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C_M 0x80
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C_M 0x100
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C_M 0x200
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C_M 0x400
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C 0x1E28
|
#define PATH0_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C_M 0x800
|
#define PATH0_CNT_HW_SI_W_TX_CMD_START_PATH_C 0x1E2C
|
#define PATH0_CNT_HW_SI_W_TX_CMD_START_PATH_C_M 0xFFFF
|
#define PATH0_CNT_HW_SI_W_RX_CMD_START_PATH_C 0x1E2C
|
#define PATH0_CNT_HW_SI_W_RX_CMD_START_PATH_C_M 0xFFFF0000
|
#define PATH0_CNT_HW_SI_R_CMD_START_PATH_C 0x1E30
|
#define PATH0_CNT_HW_SI_R_CMD_START_PATH_C_M 0xFFFF
|
#define RFMOD_C 0x2000
|
#define RFMOD_C_M 0x3
|
#define DFS_MASK_RX_OPT_C 0x2000
|
#define DFS_MASK_RX_OPT_C_M 0xC
|
#define DFS_MASK_TRANSIENT_OPT_C 0x2000
|
#define DFS_MASK_TRANSIENT_OPT_C_M 0xF0
|
#define PXP_SEL_SNR_C 0x2000
|
#define PXP_SEL_SNR_C_M 0x3F00
|
#define CH_INFO_TYPE_C 0x2000
|
#define CH_INFO_TYPE_C_M 0x4000
|
#define DFS_MASK_TRANSIENT_EN_C 0x2000
|
#define DFS_MASK_TRANSIENT_EN_C_M 0x8000
|
#define DFS_MASK_TRANSIENT_TH_C 0x2000
|
#define DFS_MASK_TRANSIENT_TH_C_M 0xFF0000
|
#define DFS_CHIRP_FLAG_ACC_TH_C 0x2000
|
#define DFS_CHIRP_FLAG_ACC_TH_C_M 0xFF000000
|
#define BIST_SEL_C 0x2004
|
#define BIST_SEL_C_M 0x1F
|
#define TX_CKEN_BOTH_PATH_FORCE_VAL_C 0x2008
|
#define TX_CKEN_BOTH_PATH_FORCE_VAL_C_M 0xF
|
#define TD_CLK_GEN_RX_PATH_EN_FORCE_VAL_C 0x2008
|
#define TD_CLK_GEN_RX_PATH_EN_FORCE_VAL_C_M 0xF0
|
#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_VAL_C 0x2008
|
#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_VAL_C_M 0xF00
|
#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_VAL_C 0x2008
|
#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_VAL_C_M 0xF000
|
#define TD_CLK_GEN_TX_PATH_EN_FORCE_VAL_C 0x2008
|
#define TD_CLK_GEN_TX_PATH_EN_FORCE_VAL_C_M 0xF0000
|
#define TX_CKEN_BOTH_PATH_FORCE_ON_C 0x2008
|
#define TX_CKEN_BOTH_PATH_FORCE_ON_C_M 0x100000
|
#define TD_CLK_GEN_RX_PATH_EN_FORCE_ON_C 0x2008
|
#define TD_CLK_GEN_RX_PATH_EN_FORCE_ON_C_M 0x200000
|
#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_ON_C 0x2008
|
#define CLK_RST_GEN_TOP_TX_PATH_EN_FORCE_ON_C_M 0x400000
|
#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_ON_C 0x2008
|
#define CLK_RST_GEN_TOP_RX_PATH_EN_FORCE_ON_C_M 0x800000
|
#define TD_CLK_GEN_TX_PATH_EN_FORCE_ON_C 0x2008
|
#define TD_CLK_GEN_TX_PATH_EN_FORCE_ON_C_M 0x1000000
|
#define CH_INFO_SEG_LEN_C 0x2008
|
#define CH_INFO_SEG_LEN_C_M 0x6000000
|
#define CH_INFO_MASK_OPT_C 0x2008
|
#define CH_INFO_MASK_OPT_C_M 0x8000000
|
#define BIST_RSTB_C 0x200C
|
#define BIST_RSTB_C_M 0x2
|
#define TEST_RESUME_C 0x200C
|
#define TEST_RESUME_C_M 0x10
|
#define BIST_VDDR_TEST_C 0x200C
|
#define BIST_VDDR_TEST_C_M 0x100
|
#define BIST_EN_7_0__C 0x200C
|
#define BIST_EN_7_0__C_M 0xFF000000
|
#define BIST_MOD_31_0__C 0x2010
|
#define BIST_MOD_31_0__C_M 0xFFFFFFFF
|
#define BIST_MOD_63_32__C 0x2014
|
#define BIST_MOD_63_32__C_M 0xFFFFFFFF
|
#define BIST_MOD_95_64__C 0x2018
|
#define BIST_MOD_95_64__C_M 0xFFFFFFFF
|
#define BIST_MOD_127_96__C 0x201C
|
#define BIST_MOD_127_96__C_M 0xFFFFFFFF
|
#define BIST_MOD_159_128__C 0x2020
|
#define BIST_MOD_159_128__C_M 0xFFFFFFFF
|
#define BIST_MOD_191_160__C 0x2024
|
#define BIST_MOD_191_160__C_M 0xFFFFFFFF
|
#define DRF_BIST_MOD_31_0__C 0x2028
|
#define DRF_BIST_MOD_31_0__C_M 0xFFFFFFFF
|
#define DRF_BIST_MOD_63_32__C 0x202C
|
#define DRF_BIST_MOD_63_32__C_M 0xFFFFFFFF
|
#define DRF_BIST_MOD_95_64__C 0x2030
|
#define DRF_BIST_MOD_95_64__C_M 0xFFFFFFFF
|
#define DRF_BIST_MOD_127_96__C 0x2034
|
#define DRF_BIST_MOD_127_96__C_M 0xFFFFFFFF
|
#define DRF_BIST_MOD_159_128__C 0x2038
|
#define DRF_BIST_MOD_159_128__C_M 0xFFFFFFFF
|
#define DRF_BIST_MOD_191_160__C 0x203C
|
#define DRF_BIST_MOD_191_160__C_M 0xFFFFFFFF
|
#define BIST_DVSE_31_0__C 0x2040
|
#define BIST_DVSE_31_0__C_M 0xFFFFFFFF
|
#define BIST_DVSE_63_32__C 0x2044
|
#define BIST_DVSE_63_32__C_M 0xFFFFFFFF
|
#define BIST_DVSE_95_64__C 0x2048
|
#define BIST_DVSE_95_64__C_M 0xFFFFFFFF
|
#define BIST_DVSE_127_96__C 0x204C
|
#define BIST_DVSE_127_96__C_M 0xFFFFFFFF
|
#define BIST_DVSE_159_128__C 0x2050
|
#define BIST_DVSE_159_128__C_M 0xFFFFFFFF
|
#define BIST_DVSE_191_160__C 0x2054
|
#define BIST_DVSE_191_160__C_M 0xFFFFFFFF
|
#define BIST_DVS_31_0__C 0x2058
|
#define BIST_DVS_31_0__C_M 0xFFFFFFFF
|
#define BIST_DVS_63_32__C 0x205C
|
#define BIST_DVS_63_32__C_M 0xFFFFFFFF
|
#define BIST_DVS_95_64__C 0x2060
|
#define BIST_DVS_95_64__C_M 0xFFFFFFFF
|
#define BIST_DVS_127_96__C 0x2064
|
#define BIST_DVS_127_96__C_M 0xFFFFFFFF
|
#define BIST_DVS_159_128__C 0x2068
|
#define BIST_DVS_159_128__C_M 0xFFFFFFFF
|
#define BIST_DVS_191_160__C 0x206C
|
#define BIST_DVS_191_160__C_M 0xFFFFFFFF
|
#define BIST_TEST1_31_0__C 0x2070
|
#define BIST_TEST1_31_0__C_M 0xFFFFFFFF
|
#define BIST_TEST1_63_32__C 0x2074
|
#define BIST_TEST1_63_32__C_M 0xFFFFFFFF
|
#define BIST_TEST1_95_64__C 0x2078
|
#define BIST_TEST1_95_64__C_M 0xFFFFFFFF
|
#define BIST_TEST1_127_96__C 0x207C
|
#define BIST_TEST1_127_96__C_M 0xFFFFFFFF
|
#define BIST_TEST1_159_128__C 0x2080
|
#define BIST_TEST1_159_128__C_M 0xFFFFFFFF
|
#define BIST_TEST1_191_160__C 0x2084
|
#define BIST_TEST1_191_160__C_M 0xFFFFFFFF
|
#define BIST_GRP_EN_31_0__C 0x2088
|
#define BIST_GRP_EN_31_0__C_M 0xFFFFFFFF
|
#define BIST_GRP_EN_63_32__C 0x208C
|
#define BIST_GRP_EN_63_32__C_M 0xFFFFFFFF
|
#define LA_EN_C 0x2090
|
#define LA_EN_C_M 0x1
|
#define LA_DBGPORT_BASE_N_C 0x2090
|
#define LA_DBGPORT_BASE_N_C_M 0x3E
|
#define LA_TYPEA_PATH_SEL_C 0x2090
|
#define LA_TYPEA_PATH_SEL_C_M 0xC0
|
#define LA_TYPEB_PATH_SEL_C 0x2090
|
#define LA_TYPEB_PATH_SEL_C_M 0x300
|
#define LA_TYPEC_PATH_SEL_C 0x2090
|
#define LA_TYPEC_PATH_SEL_C_M 0xC00
|
#define LA_TYPED_PATH_SEL_C 0x2090
|
#define LA_TYPED_PATH_SEL_C_M 0x3000
|
#define LA_TYPEA_SRC_SEL_C 0x2090
|
#define LA_TYPEA_SRC_SEL_C_M 0x1C000
|
#define LA_TYPEB_SRC_SEL_C 0x2090
|
#define LA_TYPEB_SRC_SEL_C_M 0xE0000
|
#define LA_TYPEC_SRC_SEL_C 0x2090
|
#define LA_TYPEC_SRC_SEL_C_M 0x700000
|
#define LA_TYPED_SRC_SEL_C 0x2090
|
#define LA_TYPED_SRC_SEL_C_M 0x3800000
|
#define LA_SMP_RT_SEL_C 0x2090
|
#define LA_SMP_RT_SEL_C_M 0x1C000000
|
#define LA_RDRDY_3PHASE_EN_C 0x2090
|
#define LA_RDRDY_3PHASE_EN_C_M 0x20000000
|
#define LA_EDGE_SEL_C 0x2090
|
#define LA_EDGE_SEL_C_M 0x40000000
|
#define LA_HDR_SEL_63_C 0x2094
|
#define LA_HDR_SEL_63_C_M 0xF
|
#define LA_HDR_SEL_62_C 0x2094
|
#define LA_HDR_SEL_62_C_M 0xF0
|
#define LA_HDR_SEL_61_C 0x2094
|
#define LA_HDR_SEL_61_C_M 0xF00
|
#define LA_HDR_SEL_60_C 0x2094
|
#define LA_HDR_SEL_60_C_M 0xF000
|
#define LA_TYPEA_CK160_DLY_EN_C 0x2094
|
#define LA_TYPEA_CK160_DLY_EN_C_M 0x10000
|
#define LA_TYPEB_CK160_DLY_EN_C 0x2094
|
#define LA_TYPEB_CK160_DLY_EN_C_M 0x20000
|
#define LA_DBGPORT_SRC_SEL_C 0x2094
|
#define LA_DBGPORT_SRC_SEL_C_M 0x40000
|
#define LA_DATA_C 0x2094
|
#define LA_DATA_C_M 0x1F80000
|
#define LA_RDRDY_C 0x2094
|
#define LA_RDRDY_C_M 0x6000000
|
#define LA_IQSHFT_C 0x2094
|
#define LA_IQSHFT_C_M 0x18000000
|
#define LA_MONITOR_SEL_C 0x2094
|
#define LA_MONITOR_SEL_C_M 0x60000000
|
#define LA_SEL_P1_C 0x2094
|
#define LA_SEL_P1_C_M 0x80000000
|
#define LA_TRIG_C 0x2098
|
#define LA_TRIG_C_M 0x1F
|
#define LA_TRIG_CNT_C 0x2098
|
#define LA_TRIG_CNT_C_M 0x1FE0
|
#define LA_TRIG_NEW_ONLY_C 0x2098
|
#define LA_TRIG_NEW_ONLY_C_M 0x2000
|
#define LA_TRIG_AND1_INV_C 0x2098
|
#define LA_TRIG_AND1_INV_C_M 0x4000
|
#define LA_TRIG_AND2_EN_C 0x2098
|
#define LA_TRIG_AND2_EN_C_M 0x8000
|
#define LA_TRIG_AND2_INV_C 0x2098
|
#define LA_TRIG_AND2_INV_C_M 0x10000
|
#define LA_TRIG_AND3_EN_C 0x2098
|
#define LA_TRIG_AND3_EN_C_M 0x20000
|
#define LA_TRIG_AND3_INV_C 0x2098
|
#define LA_TRIG_AND3_INV_C_M 0x40000
|
#define LA_TRIG_AND4_EN_C 0x2098
|
#define LA_TRIG_AND4_EN_C_M 0x80000
|
#define LA_TRIG_AND4_VAL_C 0x2098
|
#define LA_TRIG_AND4_VAL_C_M 0x1FF00000
|
#define LA_TRIG_AND4_INV_C 0x2098
|
#define LA_TRIG_AND4_INV_C_M 0x20000000
|
#define LA_TRIG_AND1_BIT_EN_C 0x209C
|
#define LA_TRIG_AND1_BIT_EN_C_M 0xFFFFFFFF
|
#define LA_TRIG_AND1_VAL_C 0x20A0
|
#define LA_TRIG_AND1_VAL_C_M 0xFFFFFFFF
|
#define LA_TRIG_AND2_MASK_C 0x20A4
|
#define LA_TRIG_AND2_MASK_C_M 0xFFFFFFFF
|
#define LA_TRIG_AND2_VAL_C 0x20A8
|
#define LA_TRIG_AND2_VAL_C_M 0xFFFFFFFF
|
#define LA_TRIG_AND3_MASK_C 0x20AC
|
#define LA_TRIG_AND3_MASK_C_M 0xFFFFFFFF
|
#define LA_TRIG_AND3_VAL_C 0x20B0
|
#define LA_TRIG_AND3_VAL_C_M 0xFFFFFFFF
|
#define LA_TRIG_AND5_C 0x20B4
|
#define LA_TRIG_AND5_C_M 0xF
|
#define LA_TRIG_AND5_VAL_C 0x20B4
|
#define LA_TRIG_AND5_VAL_C_M 0x1F0
|
#define LA_TRIG_AND5_INV_C 0x20B4
|
#define LA_TRIG_AND5_INV_C_M 0x200
|
#define LA_TRIG_AND6_C 0x20B4
|
#define LA_TRIG_AND6_C_M 0x3C00
|
#define LA_TRIG_AND6_VAL_C 0x20B4
|
#define LA_TRIG_AND6_VAL_C_M 0x7C000
|
#define LA_TRIG_AND6_INV_C 0x20B4
|
#define LA_TRIG_AND6_INV_C_M 0x80000
|
#define LA_TRIG_AND7_C 0x20B4
|
#define LA_TRIG_AND7_C_M 0xF00000
|
#define LA_TRIG_AND7_VAL_C 0x20B4
|
#define LA_TRIG_AND7_VAL_C_M 0x1F000000
|
#define LA_TRIG_AND7_INV_C 0x20B4
|
#define LA_TRIG_AND7_INV_C_M 0x20000000
|
#define LA_M_AND1_EN_C 0x20B4
|
#define LA_M_AND1_EN_C_M 0x40000000
|
#define LA_M_AND2_EN_C 0x20B4
|
#define LA_M_AND2_EN_C_M 0x80000000
|
#define LA_DBG_EN_C 0x20B8
|
#define LA_DBG_EN_C_M 0x1
|
#define LA_DBG_POLARITY_C 0x20B8
|
#define LA_DBG_POLARITY_C_M 0x2
|
#define LA_DBG_TRIG_SEL_C 0x20B8
|
#define LA_DBG_TRIG_SEL_C_M 0xFC
|
#define LA_DBG_INTERVAL_C 0x20B8
|
#define LA_DBG_INTERVAL_C_M 0x700
|
#define LA_DBG_SEL_0_C 0x20B8
|
#define LA_DBG_SEL_0_C_M 0x7FF800
|
#define LA_M_AND0_SEL_C 0x20B8
|
#define LA_M_AND0_SEL_C_M 0x3800000
|
#define LA_M_AND0_EN_C 0x20B8
|
#define LA_M_AND0_EN_C_M 0x4000000
|
#define LA_SIGN2_C 0x20B8
|
#define LA_SIGN2_C_M 0x18000000
|
#define LA_SIGN3_C 0x20B8
|
#define LA_SIGN3_C_M 0x60000000
|
#define LA_DBG_SEL_1_C 0x20BC
|
#define LA_DBG_SEL_1_C_M 0xFFF
|
#define LA_DBG_SEL_2_C 0x20BC
|
#define LA_DBG_SEL_2_C_M 0xFFF000
|
#define LA_DBG_SEL_3_C 0x20C0
|
#define LA_DBG_SEL_3_C_M 0xFFF
|
#define LA_DBG_SEL_4_C 0x20C0
|
#define LA_DBG_SEL_4_C_M 0xFFF000
|
#define WIFI_LOC_P1_C 0x20C0
|
#define WIFI_LOC_P1_C_M 0xFF000000
|
#define LA_DBG_SEL_5_C 0x20C4
|
#define LA_DBG_SEL_5_C_M 0xFFF
|
#define LA_DBG_SEL_6_C 0x20C4
|
#define LA_DBG_SEL_6_C_M 0xFFF000
|
#define WIFI_LOC_C 0x20C4
|
#define WIFI_LOC_C_M 0xFF000000
|
#define LA_DBG_SEL_7_C 0x20C8
|
#define LA_DBG_SEL_7_C_M 0xFFF
|
#define LA_RE_INIT_POLARITY_C 0x20C8
|
#define LA_RE_INIT_POLARITY_C_M 0x1000
|
#define LA_RE_INIT_AND1_C 0x20C8
|
#define LA_RE_INIT_AND1_C_M 0x1E000
|
#define LA_RE_INIT_AND1_VAL_C 0x20C8
|
#define LA_RE_INIT_AND1_VAL_C_M 0x3E0000
|
#define LA_RE_INIT_AND1_INV_C 0x20C8
|
#define LA_RE_INIT_AND1_INV_C_M 0x400000
|
#define PSD_DD_OPT_C 0x20C8
|
#define PSD_DD_OPT_C_M 0xFF800000
|
#define EDCCA_RPTREG_SEL_P0_C 0x20CC
|
#define EDCCA_RPTREG_SEL_P0_C_M 0x7
|
#define EDCCA_RPTREG_SEL_P1_C 0x20CC
|
#define EDCCA_RPTREG_SEL_P1_C_M 0x38
|
#define FTM_C 0x20CC
|
#define FTM_C_M 0xFF0000
|
#define DIS_IOQ_RFC_C 0x20D0
|
#define DIS_IOQ_RFC_C_M 0x1
|
#define DIS_IOQ_AFE_C 0x20D0
|
#define DIS_IOQ_AFE_C_M 0x2
|
#define BT_WL_RF_MODEAGH_C 0x20D0
|
#define BT_WL_RF_MODEAGH_C_M 0xC
|
#define FTM_T_LBK_FORCE_EN_C 0x20D0
|
#define FTM_T_LBK_FORCE_EN_C_M 0x2000
|
#define FTM_T_LBK_FORCE_VAL_C 0x20D0
|
#define FTM_T_LBK_FORCE_VAL_C_M 0xFFFFC000
|
#define MAC0_PIN_SEL_C 0x20D4
|
#define MAC0_PIN_SEL_C_M 0xFFFF
|
#define MAC1_PIN_SEL_C 0x20D4
|
#define MAC1_PIN_SEL_C_M 0xFFFF0000
|
#define PWDB_CNT_TH_P0_C 0x20D8
|
#define PWDB_CNT_TH_P0_C_M 0xFF
|
#define PWDB_CNT_TH_P1_C 0x20D8
|
#define PWDB_CNT_TH_P1_C_M 0xFF00
|
#define LBK_SEL_C 0x20EC
|
#define LBK_SEL_C_M 0x7
|
#define MUX_ST_BYPASS_TXEN_C 0x20EC
|
#define MUX_ST_BYPASS_TXEN_C_M 0x10
|
#define DUMMY_P09_EC_C 0x20EC
|
#define DUMMY_P09_EC_C_M 0xFFFFFFE0
|
#define DBG_PORT_SEL_C 0x20F0
|
#define DBG_PORT_SEL_C_M 0xFFFF
|
#define DBG_PORT_IP_SEL_C 0x20F0
|
#define DBG_PORT_IP_SEL_C_M 0xFF0000
|
#define DUMMY_P09_F0_C 0x20F0
|
#define DUMMY_P09_F0_C_M 0xFF000000
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#define DBG_CNT_SEL_C 0x20F4
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#define DBG_CNT_SEL_C_M 0x1F
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#define DUMMY_P09_F4_0_C 0x20F4
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#define DUMMY_P09_F4_0_C_M 0xE0
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#define DBG_PORT_REF_CLK_SEL_C 0x20F4
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#define DBG_PORT_REF_CLK_SEL_C_M 0xFF00
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#define DBG_PORT_REF_CLK_RATE_C 0x20F4
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#define DBG_PORT_REF_CLK_RATE_C_M 0xFF0000
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#define DBG_PORT_REF_CLK_EN_C 0x20F4
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#define DBG_PORT_REF_CLK_EN_C_M 0x1000000
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#define DBG32_UPD_SEL_C 0x20F4
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#define DBG32_UPD_SEL_C_M 0x6000000
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#define DBG_PORT_REF_CLK_SYNC_EN_C 0x20F4
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#define DBG_PORT_REF_CLK_SYNC_EN_C_M 0x8000000
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#define DUMMY_P09_F4_1_C 0x20F4
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#define DUMMY_P09_F4_1_C_M 0xF0000000
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#define DUMMY_P09_F8_C 0x20F8
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#define DUMMY_P09_F8_C_M 0x7FFFFFFF
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#define DBG_PORT_EN_C 0x20F8
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#define DBG_PORT_EN_C_M 0x80000000
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#define DBG_PORT_CKEN_TOP_C 0x20FC
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#define DBG_PORT_CKEN_TOP_C_M 0x1
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#define DBG_PORT_CKEN_TD_C 0x20FC
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#define DBG_PORT_CKEN_TD_C_M 0x10
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#define DBG_PORT_CKEN_IN_C 0x20FC
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#define DBG_PORT_CKEN_IN_C_M 0x100
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#define DBG_PORT_CKEN_OUT_C 0x20FC
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#define DBG_PORT_CKEN_OUT_C_M 0x1000
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#define DA2AD_SEL_C 0x20FC
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#define DA2AD_SEL_C_M 0x2000
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#define FORCE_DAC_FIFO_PATH_RST_ON_C 0x20FC
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#define FORCE_DAC_FIFO_PATH_RST_ON_C_M 0xF0000
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#define FORCE_DAC_FIFO_PATH_RST_C 0x20FC
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#define FORCE_DAC_FIFO_PATH_RST_C_M 0xF00000
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#define FORCE_ADC_FIFO_PATH_RST_ON_C 0x20FC
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#define FORCE_ADC_FIFO_PATH_RST_ON_C_M 0xF000000
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#define FORCE_ADC_FIFO_PATH_RST_C 0x20FC
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#define FORCE_ADC_FIFO_PATH_RST_C_M 0xF0000000
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#define TXBF_MEM_C 0x2214
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#define TXBF_MEM_C_M 0xFFFFFFFF
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#define TXBF_MEM_DIN_C 0x2218
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#define TXBF_MEM_DIN_C_M 0xFFFFFFFF
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#define TXBF_MEM_ADDR_C 0x221C
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#define TXBF_MEM_ADDR_C_M 0xFFFFFFFF
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#define TXBF_MEM_EN_C 0x2220
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#define TXBF_MEM_EN_C_M 0xFFFFFFFF
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#define R1B_TX_FIR_COEF0_C 0x2300
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#define R1B_TX_FIR_COEF0_C_M 0xFFF
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#define R1B_TX_FIR_COEF1_C 0x2300
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#define R1B_TX_FIR_COEF1_C_M 0xFFF000
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#define R1B_TX_FIR_SCALE_OPT_C 0x2300
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#define R1B_TX_FIR_SCALE_OPT_C_M 0x3000000
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#define R1B_TX_STOP_TX_C 0x2300
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#define R1B_TX_STOP_TX_C_M 0x4000000
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#define R1B_TX_BLOCK_TX_C 0x2300
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#define R1B_TX_BLOCK_TX_C_M 0x8000000
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#define R1B_TX_CONTINUOUS_TX_C 0x2300
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#define R1B_TX_CONTINUOUS_TX_C_M 0x10000000
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#define R1B_TX_TERMINATE_OPT_C 0x2300
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#define R1B_TX_TERMINATE_OPT_C_M 0xE0000000
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#define R1B_TX_FIR_COEF2_C 0x2304
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#define R1B_TX_FIR_COEF2_C_M 0xFFF
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#define R1B_TX_FIR_COEF3_C 0x2304
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#define R1B_TX_FIR_COEF3_C_M 0xFFF000
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#define R1B_TX_DUMMY_TDRDY64_OPT_C 0x2304
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#define R1B_TX_DUMMY_TDRDY64_OPT_C_M 0x3000000
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#define R1B_TX_DIS_SCRAMBLER_C 0x2304
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#define R1B_TX_DIS_SCRAMBLER_C_M 0x4000000
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#define R1B_TX_IFMOD_5M_OPT_C 0x2304
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#define R1B_TX_IFMOD_5M_OPT_C_M 0x18000000
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#define R1B_TX_FIR_COEF4_C 0x2308
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#define R1B_TX_FIR_COEF4_C_M 0xFFF
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#define R1B_TX_FIR_COEF5_C 0x2308
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#define R1B_TX_FIR_COEF5_C_M 0xFFF000
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#define R1B_TX_SCRAMBLER_OPT_C 0x2308
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#define R1B_TX_SCRAMBLER_OPT_C_M 0xFF000000
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#define R1B_TX_FIR_COEF6_C 0x230C
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#define R1B_TX_FIR_COEF6_C_M 0xFFF
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#define R1B_TX_FIR_COEF7_C 0x230C
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#define R1B_TX_FIR_COEF7_C_M 0xFFF000
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#define R1B_TX_FORCE_PATH_EN_ON_C 0x230C
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#define R1B_TX_FORCE_PATH_EN_ON_C_M 0x1000000
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#define R1B_TX_FORCE_PATH_EN_PATH0_C 0x230C
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#define R1B_TX_FORCE_PATH_EN_PATH0_C_M 0x2000000
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#define R1B_TX_FORCE_PATH_EN_PATH1_C 0x230C
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#define R1B_TX_FORCE_PATH_EN_PATH1_C_M 0x4000000
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#define R1B_TX_FORCE_PATH_EN_PATH2_C 0x230C
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#define R1B_TX_FORCE_PATH_EN_PATH2_C_M 0x8000000
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#define R1B_TX_FORCE_PATH_EN_PATH3_C 0x230C
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#define R1B_TX_FORCE_PATH_EN_PATH3_C_M 0x10000000
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#define R1B_TX_FIR_COEF8_C 0x2310
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#define R1B_TX_FIR_COEF8_C_M 0xFFF
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#define R1B_TX_FIR_COEF9_C 0x2310
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#define R1B_TX_FIR_COEF9_C_M 0xFFF000
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#define R1B_TX_DELAY_DIVERSITY_OPT_PATH0_C 0x2310
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#define R1B_TX_DELAY_DIVERSITY_OPT_PATH0_C_M 0x3000000
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#define R1B_TX_DELAY_DIVERSITY_OPT_PATH1_C 0x2310
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#define R1B_TX_DELAY_DIVERSITY_OPT_PATH1_C_M 0xC000000
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#define R1B_TX_DELAY_DIVERSITY_OPT_PATH2_C 0x2310
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#define R1B_TX_DELAY_DIVERSITY_OPT_PATH2_C_M 0x30000000
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#define R1B_TX_DELAY_DIVERSITY_OPT_PATH3_C 0x2310
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#define R1B_TX_DELAY_DIVERSITY_OPT_PATH3_C_M 0xC0000000
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#define R1B_TX_FIR_COEFA_C 0x2314
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#define R1B_TX_FIR_COEFA_C_M 0xFFF
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#define R1B_TX_FIR_COEFB_C 0x2314
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#define R1B_TX_FIR_COEFB_C_M 0xFFF000
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#define R1B_TX_NORM_FCTR_C 0x2314
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#define R1B_TX_NORM_FCTR_C_M 0x3F000000
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#define R1B_TX_FIR_COEFC_C 0x2318
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#define R1B_TX_FIR_COEFC_C_M 0xFFF
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#define R1B_TX_FIR_COEFD_C 0x2318
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#define R1B_TX_FIR_COEFD_C_M 0xFFF000
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#define R1B_TX_FIR_COEFE_C 0x231C
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#define R1B_TX_FIR_COEFE_C_M 0xFFF
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#define R1B_TX_FIR_COEFF_C 0x231C
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#define R1B_TX_FIR_COEFF_C_M 0xFFF000
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#define R1B_TX_PMAC_HEADER_0_C 0x2320
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#define R1B_TX_PMAC_HEADER_0_C_M 0xFFFFFFFF
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#define R1B_TX_PMAC_HEADER_1_C 0x2324
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#define R1B_TX_PMAC_HEADER_1_C_M 0xFFFFFFFF
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#define R1B_TX_PMAC_HEADER_2_C 0x2328
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#define R1B_TX_PMAC_HEADER_2_C_M 0xFFFFFFFF
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#define R1B_TX_PMAC_HEADER_3_C 0x232C
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#define R1B_TX_PMAC_HEADER_3_C_M 0xFFFFFFFF
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#define R1B_TX_PMAC_HEADER_4_C 0x2330
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#define R1B_TX_PMAC_HEADER_4_C_M 0xFFFFFFFF
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#define R1B_TX_PMAC_HEADER_5_C 0x2334
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#define R1B_TX_PMAC_HEADER_5_C_M 0xFFFFFFFF
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#define R1B_TX_PMAC_PSDU_BYTE_C 0x2338
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#define R1B_TX_PMAC_PSDU_BYTE_C_M 0x1FFFF
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#define R1B_TX_PMAC_CONTINUOUS_TX_C 0x2338
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#define R1B_TX_PMAC_CONTINUOUS_TX_C_M 0x20000
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#define R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C 0x2338
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#define R1B_TX_PMAC_CARRIER_SUPPRESS_TX_C_M 0x40000
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#define R1B_TX_PMAC_PPDU_TYPE_C 0x2338
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#define R1B_TX_PMAC_PPDU_TYPE_C_M 0x80000
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#define R1B_TX_PMAC_PSDU_RATE_C 0x2338
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#define R1B_TX_PMAC_PSDU_RATE_C_M 0x300000
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#define R1B_TX_PMAC_SERVICE_BIT2_C 0x2338
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#define R1B_TX_PMAC_SERVICE_BIT2_C_M 0x400000
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#define R1B_TX_PMAC_PAYLOAD_INITIAL_VAL_C 0x2338
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#define R1B_TX_PMAC_PAYLOAD_INITIAL_VAL_C_M 0x7F800000
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#define R1B_FPGA_LBK_EN_C 0x2338
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#define R1B_FPGA_LBK_EN_C_M 0x80000000
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#define R1B_RX_CS_RATIO_BW20_1R_C 0x233C
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#define R1B_RX_CS_RATIO_BW20_1R_C_M 0x1F
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#define R1B_RX_CS_RATIO_BW20_2R_C 0x233C
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#define R1B_RX_CS_RATIO_BW20_2R_C_M 0x3E0
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#define R1B_RX_CS_RATIO_BW20_3R_C 0x233C
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#define R1B_RX_CS_RATIO_BW20_3R_C_M 0x7C00
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#define R1B_RX_CS_RATIO_BW20_4R_C 0x233C
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#define R1B_RX_CS_RATIO_BW20_4R_C_M 0xF8000
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#define R1B_RX_CCA_IN_SHIFT_C 0x233C
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#define R1B_RX_CCA_IN_SHIFT_C_M 0x1E00000
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#define R1B_RX_PRECCA_WGT_EN_C 0x233C
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#define R1B_RX_PRECCA_WGT_EN_C_M 0x2000000
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#define R1B_RX_FORCE_PRECCA_WGT_EN_C 0x233C
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#define R1B_RX_FORCE_PRECCA_WGT_EN_C_M 0x4000000
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#define R1B_RX_CCA_SMEN_C 0x233C
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#define R1B_RX_CCA_SMEN_C_M 0x8000000
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#define R1B_RX_MBC_RATIO_C 0x233C
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#define R1B_RX_MBC_RATIO_C_M 0x30000000
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#define R1B_RX_MDC_RATIO_C 0x233C
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#define R1B_RX_MDC_RATIO_C_M 0xC0000000
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#define R1B_RX_CS_RATIO_BW40_1R_C 0x2340
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#define R1B_RX_CS_RATIO_BW40_1R_C_M 0x1F
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#define R1B_RX_CS_RATIO_BW40_2R_C 0x2340
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#define R1B_RX_CS_RATIO_BW40_2R_C_M 0x3E0
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#define R1B_RX_CS_RATIO_BW40_3R_C 0x2340
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#define R1B_RX_CS_RATIO_BW40_3R_C_M 0x7C00
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#define R1B_RX_CS_RATIO_BW40_4R_C 0x2340
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#define R1B_RX_CS_RATIO_BW40_4R_C_M 0xF8000
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#define R1B_RX_FORCE_PRECCA_WGT_PATH0_C 0x2340
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#define R1B_RX_FORCE_PRECCA_WGT_PATH0_C_M 0x700000
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#define R1B_RX_FORCE_PRECCA_WGT_PATH1_C 0x2340
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#define R1B_RX_FORCE_PRECCA_WGT_PATH1_C_M 0x3800000
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#define R1B_RX_FORCE_PRECCA_WGT_PATH2_C 0x2340
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#define R1B_RX_FORCE_PRECCA_WGT_PATH2_C_M 0x1C000000
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#define R1B_RX_FORCE_PRECCA_WGT_PATH3_C 0x2340
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#define R1B_RX_FORCE_PRECCA_WGT_PATH3_C_M 0xE0000000
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#define R1B_RX_DC_RATIO_BW20_1R_C 0x2344
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#define R1B_RX_DC_RATIO_BW20_1R_C_M 0x1F
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#define R1B_RX_DC_RATIO_BW20_2R_C 0x2344
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#define R1B_RX_DC_RATIO_BW20_2R_C_M 0x3E0
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#define R1B_RX_DC_RATIO_BW20_3R_C 0x2344
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#define R1B_RX_DC_RATIO_BW20_3R_C_M 0x7C00
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#define R1B_RX_DC_RATIO_BW20_4R_C 0x2344
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#define R1B_RX_DC_RATIO_BW20_4R_C_M 0xF8000
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#define R1B_RX_FORCE_DC_CMP_EN_C 0x2344
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#define R1B_RX_FORCE_DC_CMP_EN_C_M 0x100000
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#define R1B_RX_FORCE_DC_CMP_C 0x2344
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#define R1B_RX_FORCE_DC_CMP_C_M 0x1FE00000
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#define R1B_RX_MBC_WIN_C 0x2344
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#define R1B_RX_MBC_WIN_C_M 0x60000000
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#define R1B_RX_DIS_CCA_C 0x2344
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#define R1B_RX_DIS_CCA_C_M 0x80000000
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#define R1B_RX_DC_RATIO_BW40_1R_C 0x2348
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#define R1B_RX_DC_RATIO_BW40_1R_C_M 0x1F
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#define R1B_RX_DC_RATIO_BW40_2R_C 0x2348
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#define R1B_RX_DC_RATIO_BW40_2R_C_M 0x3E0
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#define R1B_RX_DC_RATIO_BW40_3R_C 0x2348
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#define R1B_RX_DC_RATIO_BW40_3R_C_M 0x7C00
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#define R1B_RX_DC_RATIO_BW40_4R_C 0x2348
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#define R1B_RX_DC_RATIO_BW40_4R_C_M 0xF8000
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#define R1B_RX_CCA_PIN_DET_OPT_C 0x2348
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#define R1B_RX_CCA_PIN_DET_OPT_C_M 0x100000
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#define R1B_RX_CCA_PIN_DET_TH_C 0x2348
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#define R1B_RX_CCA_PIN_DET_TH_C_M 0x1FE00000
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#define R1B_RX_CCS_MODE_C 0x2348
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#define R1B_RX_CCS_MODE_C_M 0xE0000000
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#define R1B_RX_PD_TH_BW20_1R_C 0x234C
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#define R1B_RX_PD_TH_BW20_1R_C_M 0x1F
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#define R1B_RX_PD_TH_BW20_2R_C 0x234C
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#define R1B_RX_PD_TH_BW20_2R_C_M 0x3E0
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#define R1B_RX_PD_TH_BW20_3R_C 0x234C
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#define R1B_RX_PD_TH_BW20_3R_C_M 0x7C00
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#define R1B_RX_PD_TH_BW20_4R_C 0x234C
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#define R1B_RX_PD_TH_BW20_4R_C_M 0xF8000
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#define R1B_RX_FORCE_PD_CMP_EN_C 0x234C
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#define R1B_RX_FORCE_PD_CMP_EN_C_M 0x100000
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#define R1B_RX_FORCE_PD_CMP_C 0x234C
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#define R1B_RX_FORCE_PD_CMP_C_M 0x1FE00000
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#define R1B_RX_MF_OPT_C 0x234C
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#define R1B_RX_MF_OPT_C_M 0xE0000000
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#define R1B_RX_PD_TH_BW40_1R_C 0x2350
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#define R1B_RX_PD_TH_BW40_1R_C_M 0x1F
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#define R1B_RX_PD_TH_BW40_2R_C 0x2350
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#define R1B_RX_PD_TH_BW40_2R_C_M 0x3E0
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#define R1B_RX_PD_TH_BW40_3R_C 0x2350
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#define R1B_RX_PD_TH_BW40_3R_C_M 0x7C00
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#define R1B_RX_PD_TH_BW40_4R_C 0x2350
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#define R1B_RX_PD_TH_BW40_4R_C_M 0xF8000
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#define R1B_RX_FORCE_ANT_CCA_EN_C 0x2350
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#define R1B_RX_FORCE_ANT_CCA_EN_C_M 0x100000
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#define R1B_RX_FORCE_ANT_CCA_PATH0_C 0x2350
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#define R1B_RX_FORCE_ANT_CCA_PATH0_C_M 0x200000
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#define R1B_RX_FORCE_ANT_CCA_PATH1_C 0x2350
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#define R1B_RX_FORCE_ANT_CCA_PATH1_C_M 0x400000
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#define R1B_RX_FORCE_ANT_CCA_PATH2_C 0x2350
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#define R1B_RX_FORCE_ANT_CCA_PATH2_C_M 0x800000
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#define R1B_RX_FORCE_ANT_CCA_PATH3_C 0x2350
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#define R1B_RX_FORCE_ANT_CCA_PATH3_C_M 0x1000000
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#define R1B_RX_CCA_TRIG_DLY_C 0x2350
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#define R1B_RX_CCA_TRIG_DLY_C_M 0x1E000000
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#define R1B_RX_NULL_POINT_IDX_OFST_C 0x2350
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#define R1B_RX_NULL_POINT_IDX_OFST_C_M 0xE0000000
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#define R1B_RX_BTTX_CS_RATIO_BW20_1R_C 0x2354
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#define R1B_RX_BTTX_CS_RATIO_BW20_1R_C_M 0x1F
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#define R1B_RX_BTTX_CS_RATIO_BW20_2R_C 0x2354
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#define R1B_RX_BTTX_CS_RATIO_BW20_2R_C_M 0x3E0
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#define R1B_RX_BTTX_CS_RATIO_BW20_3R_C 0x2354
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#define R1B_RX_BTTX_CS_RATIO_BW20_3R_C_M 0x7C00
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#define R1B_RX_BTTX_CS_RATIO_BW20_4R_C 0x2354
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#define R1B_RX_BTTX_CS_RATIO_BW20_4R_C_M 0xF8000
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#define R1B_RX_BTTX_CCA_TH_EN_C 0x2354
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#define R1B_RX_BTTX_CCA_TH_EN_C_M 0x80000000
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#define R1B_RX_BTTX_CS_RATIO_BW40_1R_C 0x2358
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#define R1B_RX_BTTX_CS_RATIO_BW40_1R_C_M 0x1F
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#define R1B_RX_BTTX_CS_RATIO_BW40_2R_C 0x2358
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#define R1B_RX_BTTX_CS_RATIO_BW40_2R_C_M 0x3E0
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#define R1B_RX_BTTX_CS_RATIO_BW40_3R_C 0x2358
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#define R1B_RX_BTTX_CS_RATIO_BW40_3R_C_M 0x7C00
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#define R1B_RX_BTTX_CS_RATIO_BW40_4R_C 0x2358
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#define R1B_RX_BTTX_CS_RATIO_BW40_4R_C_M 0xF8000
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#define R1B_RX_CCA_DIS_5M_EN_C 0x2358
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#define R1B_RX_CCA_DIS_5M_EN_C_M 0x100000
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#define R1B_RX_CCA_DIS_TB_OFF_C 0x2358
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#define R1B_RX_CCA_DIS_TB_OFF_C_M 0x200000
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#define R1B_RX_CCA_DIS_NDP_OFF_C 0x2358
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#define R1B_RX_CCA_DIS_NDP_OFF_C_M 0x400000
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#define R1B_RX_DAGC_TARGET_LVL_C 0x235C
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#define R1B_RX_DAGC_TARGET_LVL_C_M 0x1F
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#define R1B_RX_DAGC_MIN_VAL_C 0x235C
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#define R1B_RX_DAGC_MIN_VAL_C_M 0x3E0
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#define R1B_RX_DAGC_MAX_VAL_C 0x235C
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#define R1B_RX_DAGC_MAX_VAL_C_M 0x7C00
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#define R1B_RX_DAGC_STANDBY_OPT_C 0x235C
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#define R1B_RX_DAGC_STANDBY_OPT_C_M 0xF8000
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#define R1B_RX_DAGC_FORCE_VAL_C 0x235C
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#define R1B_RX_DAGC_FORCE_VAL_C_M 0x1F00000
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#define R1B_RX_DAGC_FORCE_EN_C 0x235C
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#define R1B_RX_DAGC_FORCE_EN_C_M 0x2000000
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#define R1B_RX_DAGC_EN_C 0x235C
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#define R1B_RX_DAGC_EN_C_M 0x4000000
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#define R1B_RX_DAGC_OPT_C 0x235C
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#define R1B_RX_DAGC_OPT_C_M 0x8000000
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#define R1B_RX_DAGC_TWO_STAGE_EN_C 0x235C
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#define R1B_RX_DAGC_TWO_STAGE_EN_C_M 0x10000000
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#define R1B_RX_SBD_SYMBOL_OPT_C 0x2360
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#define R1B_RX_SBD_SYMBOL_OPT_C_M 0x3
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#define R1B_RX_SBD_SMOOTH_EN_C 0x2360
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#define R1B_RX_SBD_SMOOTH_EN_C_M 0x4
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#define R1B_RX_SBD_SQUARE_EN_C 0x2360
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#define R1B_RX_SBD_SQUARE_EN_C_M 0x8
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#define R1B_RX_SBD_FINE_TUNE_OPT_C 0x2360
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#define R1B_RX_SBD_FINE_TUNE_OPT_C_M 0x30
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#define R1B_RX_SBD_FINE_TUNE_MODE_C 0x2360
|
#define R1B_RX_SBD_FINE_TUNE_MODE_C_M 0xC0
|
#define R1B_RX_SBD_RSSI_HIGH_PIN_TH_C 0x2360
|
#define R1B_RX_SBD_RSSI_HIGH_PIN_TH_C_M 0xFF00
|
#define R1B_RX_DAGC_TO_SBD_C 0x2360
|
#define R1B_RX_DAGC_TO_SBD_C_M 0x3F0000
|
#define R1B_RX_SBD_MODE_C 0x2360
|
#define R1B_RX_SBD_MODE_C_M 0x400000
|
#define R1B_RX_SBD_ANALYZER_EN_C 0x2360
|
#define R1B_RX_SBD_ANALYZER_EN_C_M 0x800000
|
#define R1B_RX_SBD_SMOOTH_FCTR_C 0x2360
|
#define R1B_RX_SBD_SMOOTH_FCTR_C_M 0x3000000
|
#define R1B_RX_SBD_ANALYZER_OPT_C 0x2360
|
#define R1B_RX_SBD_ANALYZER_OPT_C_M 0x4000000
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH0_C 0x2364
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH0_C_M 0x1F
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH1_C 0x2364
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH1_C_M 0x3E0
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH2_C 0x2364
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH2_C_M 0x7C00
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH3_C 0x2364
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH3_C_M 0xF8000
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH4_C 0x2364
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH4_C_M 0x1F00000
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH5_C 0x2364
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH5_C_M 0x3E000000
|
#define R1B_RX_ANT_WGT_EN_C 0x2364
|
#define R1B_RX_ANT_WGT_EN_C_M 0x40000000
|
#define R1B_RX_ANT_WGT_MODE_C 0x2364
|
#define R1B_RX_ANT_WGT_MODE_C_M 0x80000000
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH6_C 0x2368
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH6_C_M 0x1F
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH7_C 0x2368
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH7_C_M 0x3E0
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH8_C 0x2368
|
#define R1B_RX_ANT_WGT_GAIN_DIFF_TH8_C_M 0x7C00
|
#define R1B_RX_RSSI_HIGH_PIN_TH_C 0x2368
|
#define R1B_RX_RSSI_HIGH_PIN_TH_C_M 0x7F8000
|
#define R1B_RX_ANT_WGT_NULL_CONNECT_RSSI_TH_C 0x2368
|
#define R1B_RX_ANT_WGT_NULL_CONNECT_RSSI_TH_C_M 0x7F800000
|
#define R1B_RX_ANT_WGT_EQUAL_EN_C 0x2368
|
#define R1B_RX_ANT_WGT_EQUAL_EN_C_M 0x80000000
|
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH0_C 0x236C
|
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH0_C_M 0x1FF
|
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH1_C 0x236C
|
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH1_C_M 0x3FE00
|
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH2_C 0x236C
|
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH2_C_M 0x7FC0000
|
#define R1B_RX_ANT_WGT_NULL_CONNECT_CHK_EN_C 0x236C
|
#define R1B_RX_ANT_WGT_NULL_CONNECT_CHK_EN_C_M 0x8000000
|
#define R1B_RX_ANT_WGT_FORCE_EN_C 0x236C
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#define R1B_RX_ANT_WGT_FORCE_EN_C_M 0x10000000
|
#define R1B_RX_ANT_PW_SAVE_EN_C 0x236C
|
#define R1B_RX_ANT_PW_SAVE_EN_C_M 0x20000000
|
#define R1B_RX_MRC_OPT_C 0x236C
|
#define R1B_RX_MRC_OPT_C_M 0xC0000000
|
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH3_C 0x2370
|
#define R1B_RX_ANT_WGT_FORCE_VAL_PATH3_C_M 0x1FF
|
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH0_C 0x2370
|
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH0_C_M 0x3FE00
|
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH1_C 0x2370
|
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH1_C_M 0x7FC0000
|
#define R1B_RX_ANT_WGT_BCC_CHK_RATIO_C 0x2370
|
#define R1B_RX_ANT_WGT_BCC_CHK_RATIO_C_M 0x78000000
|
#define R1B_RX_I_ONLY_EN_C 0x2370
|
#define R1B_RX_I_ONLY_EN_C_M 0x80000000
|
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH2_C 0x2374
|
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH2_C_M 0x1FF
|
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH3_C 0x2374
|
#define R1B_RX_ANT_WGT_SQRT_FORCE_VAL_PATH3_C_M 0x3FE00
|
#define R1B_RX_RSSI_OFST_C 0x2374
|
#define R1B_RX_RSSI_OFST_C_M 0x3FC0000
|
#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_OPT_C 0x2374
|
#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_OPT_C_M 0xC000000
|
#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_DIS_C 0x2374
|
#define R1B_RX_ANTWGT_MAX_TOTAL_THRESH_DIS_C_M 0x10000000
|
#define R1B_RX_ANT_PW_SAVE_RSSI_TH_C 0x2378
|
#define R1B_RX_ANT_PW_SAVE_RSSI_TH_C_M 0xFF
|
#define R1B_RX_LPF1_EN_C 0x2378
|
#define R1B_RX_LPF1_EN_C_M 0x100
|
#define R1B_RX_LPF1_MODE_BEFORE_CCA_C 0x2378
|
#define R1B_RX_LPF1_MODE_BEFORE_CCA_C_M 0x600
|
#define R1B_RX_LPF1_MODE_AFTER_CCA_C 0x2378
|
#define R1B_RX_LPF1_MODE_AFTER_CCA_C_M 0x1800
|
#define R1B_RX_GAIN_IS_READY_TO_EN_INTP_C 0x2378
|
#define R1B_RX_GAIN_IS_READY_TO_EN_INTP_C_M 0xFF0000
|
#define R1B_RX_INTP_UPD044_OPT_C 0x2378
|
#define R1B_RX_INTP_UPD044_OPT_C_M 0x1F000000
|
#define R1B_RX_INTP_SCO_DELAY_EN_C 0x2378
|
#define R1B_RX_INTP_SCO_DELAY_EN_C_M 0x20000000
|
#define R1B_RX_INTP_DOWNSAMPLE_PHASE_OPT_C 0x2378
|
#define R1B_RX_INTP_DOWNSAMPLE_PHASE_OPT_C_M 0x40000000
|
#define R1B_RX_RXSC_C 0x237C
|
#define R1B_RX_RXSC_C_M 0x1
|
#define R1B_RX_DCEST_EN_C 0x237C
|
#define R1B_RX_DCEST_EN_C_M 0x2
|
#define R1B_RX_DCCOMP_EN_C 0x237C
|
#define R1B_RX_DCCOMP_EN_C_M 0x4
|
#define R1B_RX_AAGC_DONE_TO_DCEST_C 0x237C
|
#define R1B_RX_AAGC_DONE_TO_DCEST_C_M 0x18
|
#define R1B_RX_DCNF_EN_C 0x237C
|
#define R1B_RX_DCNF_EN_C_M 0x10000
|
#define R1B_RX_DCNF_MODE_1_C 0x237C
|
#define R1B_RX_DCNF_MODE_1_C_M 0xE0000
|
#define R1B_RX_DCNF_MODE_2_C 0x237C
|
#define R1B_RX_DCNF_MODE_2_C_M 0x700000
|
#define R1B_RX_DCNF_MODE_3_C 0x237C
|
#define R1B_RX_DCNF_MODE_3_C_M 0x3800000
|
#define R1B_RX_LF_K1_HD_C 0x2380
|
#define R1B_RX_LF_K1_HD_C_M 0xFF
|
#define R1B_RX_LF_K1_PD_C 0x2380
|
#define R1B_RX_LF_K1_PD_C_M 0xFF00
|
#define R1B_RX_LF_K0_HD_C 0x2380
|
#define R1B_RX_LF_K0_HD_C_M 0xFF0000
|
#define R1B_RX_LF_K0_PD_C 0x2380
|
#define R1B_RX_LF_K0_PD_C_M 0xFF000000
|
#define R1B_RX_FREQ_EST_NUM_C 0x2384
|
#define R1B_RX_FREQ_EST_NUM_C_M 0x3
|
#define R1B_RX_DC_WIN_EN_C 0x2384
|
#define R1B_RX_DC_WIN_EN_C_M 0x4
|
#define R1B_RX_PHASE_COMP_EN_C 0x2384
|
#define R1B_RX_PHASE_COMP_EN_C_M 0x8
|
#define R1B_RX_PHROT_IDX_BKC_C 0x2384
|
#define R1B_RX_PHROT_IDX_BKC_C_M 0xF0
|
#define R1B_RX_PHROT_IDX_CCK_C 0x2384
|
#define R1B_RX_PHROT_IDX_CCK_C_M 0xF00
|
#define R1B_RX_SCO_QWQ_C 0x2384
|
#define R1B_RX_SCO_QWQ_C_M 0x8000
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#define R1B_RX_SCO_EN_C 0x2384
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#define R1B_RX_SCO_EN_C_M 0x10000
|
#define R1B_RX_SBD_TO_SCO_C 0x2384
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#define R1B_RX_SBD_TO_SCO_C_M 0x60000
|
#define R1B_RX_SCO_PLCP_MODE_C 0x2384
|
#define R1B_RX_SCO_PLCP_MODE_C_M 0x80000
|
#define R1B_RX_SCO_PSDU_MODE_C 0x2384
|
#define R1B_RX_SCO_PSDU_MODE_C_M 0x300000
|
#define R1B_RX_SCO_BC_NON_SYNC_MODE_TH_C 0x2384
|
#define R1B_RX_SCO_BC_NON_SYNC_MODE_TH_C_M 0x7C00000
|
#define R1B_RX_SCO_CCK_NON_SYNC_MODE_TH_C 0x2384
|
#define R1B_RX_SCO_CCK_NON_SYNC_MODE_TH_C_M 0xF8000000
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#define R1B_RX_CHEST_TARGET_TH_C 0x2388
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#define R1B_RX_CHEST_TARGET_TH_C_M 0xFF
|
#define R1B_RX_CHEST_ANT_GAIN_DIFF_TH_C 0x2388
|
#define R1B_RX_CHEST_ANT_GAIN_DIFF_TH_C_M 0x1F00
|
#define R1B_RX_RAKE_EN_C 0x2388
|
#define R1B_RX_RAKE_EN_C_M 0x2000
|
#define R1B_RX_EQISI_EN_C 0x2388
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#define R1B_RX_EQISI_EN_C_M 0x4000
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#define R1B_RX_RPT_RST_C 0x2388
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#define R1B_RX_RPT_RST_C_M 0x8000
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#define R1B_TRX_DBG_SEL_C 0x2388
|
#define R1B_TRX_DBG_SEL_C_M 0x3F0000
|
#define R1B_DBG_PORT_SWITCH_C 0x2388
|
#define R1B_DBG_PORT_SWITCH_C_M 0x400000
|
#define R1B_RR_SEL_C 0x2388
|
#define R1B_RR_SEL_C_M 0x1800000
|
#define R1B_RXIN_MUL_OPT_C 0x2388
|
#define R1B_RXIN_MUL_OPT_C_M 0x6000000
|
#define R1B_RX_CHEST_MULTIPLY_OPT_C 0x2388
|
#define R1B_RX_CHEST_MULTIPLY_OPT_C_M 0x18000000
|
#define R1B_RX_CHEST_INVLD_SYMBOL_DOUBLE_CHK_DIS_C 0x2388
|
#define R1B_RX_CHEST_INVLD_SYMBOL_DOUBLE_CHK_DIS_C_M 0x20000000
|
#define R1B_RX_EDCCA_EN_C 0x238C
|
#define R1B_RX_EDCCA_EN_C_M 0x1
|
#define R1B_RX_FORCE_EDCCA_PATH_EN_C 0x238C
|
#define R1B_RX_FORCE_EDCCA_PATH_EN_C_M 0x2
|
#define R1B_RX_FORCE_EDCCA_PATH_C 0x238C
|
#define R1B_RX_FORCE_EDCCA_PATH_C_M 0xC
|
#define R1B_RX_EDCCA_PERIOD_C 0x238C
|
#define R1B_RX_EDCCA_PERIOD_C_M 0x30
|
#define R1B_RX_EDCCA_VLD_TH_C 0x238C
|
#define R1B_RX_EDCCA_VLD_TH_C_M 0xC0
|
#define R1B_RX_EDCCA_ENERGY_TH_C 0x238C
|
#define R1B_RX_EDCCA_ENERGY_TH_C_M 0xFF00
|
#define R1B_RX_EDCCA_OFST_C 0x238C
|
#define R1B_RX_EDCCA_OFST_C_M 0x1F0000
|
#define R1B_RX_EDCCA_WGTSEL_EN_C 0x238C
|
#define R1B_RX_EDCCA_WGTSEL_EN_C_M 0x200000
|
#define R1B_RX_EDCCA_BTTX_OFF_C 0x238C
|
#define R1B_RX_EDCCA_BTTX_OFF_C_M 0x400000
|
#define R1B_RX_EVM_TH_5M_1R_C 0x2390
|
#define R1B_RX_EVM_TH_5M_1R_C_M 0x1F
|
#define R1B_RX_EVM_TH_5M_2R_C 0x2390
|
#define R1B_RX_EVM_TH_5M_2R_C_M 0x3E0
|
#define R1B_RX_EVM_TH_5M_3R_C 0x2390
|
#define R1B_RX_EVM_TH_5M_3R_C_M 0x7C00
|
#define R1B_RX_EVM_TH_5M_4R_C 0x2390
|
#define R1B_RX_EVM_TH_5M_4R_C_M 0xF8000
|
#define R1B_RX_EVM_SIG_OPT_C 0x2390
|
#define R1B_RX_EVM_SIG_OPT_C_M 0x300000
|
#define R1B_RX_EVM_DATA_OPT_C 0x2390
|
#define R1B_RX_EVM_DATA_OPT_C_M 0xC00000
|
#define R1B_RX_EVM_SYM_C 0x2390
|
#define R1B_RX_EVM_SYM_C_M 0x7000000
|
#define R1B_RX_EVM_SCALE_C 0x2390
|
#define R1B_RX_EVM_SCALE_C_M 0x38000000
|
#define R1B_RX_EVM_ABANDON_EN_C 0x2390
|
#define R1B_RX_EVM_ABANDON_EN_C_M 0x40000000
|
#define R1B_RX_EVM_TH_11M_1R_C 0x2394
|
#define R1B_RX_EVM_TH_11M_1R_C_M 0x1F
|
#define R1B_RX_EVM_TH_11M_2R_C 0x2394
|
#define R1B_RX_EVM_TH_11M_2R_C_M 0x3E0
|
#define R1B_RX_EVM_TH_11M_3R_C 0x2394
|
#define R1B_RX_EVM_TH_11M_3R_C_M 0x7C00
|
#define R1B_RX_EVM_TH_11M_4R_C 0x2394
|
#define R1B_RX_EVM_TH_11M_4R_C_M 0xF8000
|
#define R1B_RX_EVM_BCC_OFST_C 0x2394
|
#define R1B_RX_EVM_BCC_OFST_C_M 0x1F00000
|
#define R1B_RX_EVM_CCK_OFST_C 0x2394
|
#define R1B_RX_EVM_CCK_OFST_C_M 0x3E000000
|
#define R1B_RX_DUMMY_RDRDY_OPT_C 0x2398
|
#define R1B_RX_DUMMY_RDRDY_OPT_C_M 0x3
|
#define R1B_RX_SFD_SEARCH_OPT_C 0x2398
|
#define R1B_RX_SFD_SEARCH_OPT_C_M 0xC
|
#define R1B_RX_SUPPORT_RATE_C 0x2398
|
#define R1B_RX_SUPPORT_RATE_C_M 0xF0
|
#define R1B_RX_SPOOF_LEN_C 0x2398
|
#define R1B_RX_SPOOF_LEN_C_M 0xFFFFF00
|
#define R1B_RX_SUPPORT_MAX_LEN_C 0x239C
|
#define R1B_RX_SUPPORT_MAX_LEN_C_M 0xFFFF
|
#define R1B_RX_SUPPORT_MIN_LEN_C 0x239C
|
#define R1B_RX_SUPPORT_MIN_LEN_C_M 0xFFFF0000
|
#define R1B_RX_SCOREBOARD_LEN_0_C 0x23A0
|
#define R1B_RX_SCOREBOARD_LEN_0_C_M 0xFFFF
|
#define R1B_RX_SCOREBOARD_LEN_1_C 0x23A0
|
#define R1B_RX_SCOREBOARD_LEN_1_C_M 0xFFFF0000
|
#define R1B_RX_SCOREBOARD_LEN_2_C 0x23A4
|
#define R1B_RX_SCOREBOARD_LEN_2_C_M 0xFFFF
|
#define R1B_RX_SCOREBOARD_LEN_3_C 0x23A4
|
#define R1B_RX_SCOREBOARD_LEN_3_C_M 0xFFFF0000
|
#define R1B_RX_SUICIDE_OPT_C 0x23A8
|
#define R1B_RX_SUICIDE_OPT_C_M 0xFF
|
#define R1B_RX_AIR_DELAY_BCC_C 0x23A8
|
#define R1B_RX_AIR_DELAY_BCC_C_M 0x7F00
|
#define R1B_RX_IDLE_HANG_LEN_C 0x23A8
|
#define R1B_RX_IDLE_HANG_LEN_C_M 0x3F8000
|
#define R1B_RX_SYNC_RST_LEN_C 0x23A8
|
#define R1B_RX_SYNC_RST_LEN_C_M 0x3C00000
|
#define R1B_RX_CCA_RST_LEN_C 0x23A8
|
#define R1B_RX_CCA_RST_LEN_C_M 0x3C000000
|
#define R1B_RX_RPL_OFST_C 0x23AC
|
#define R1B_RX_RPL_OFST_C_M 0x7F
|
#define R1B_RX_RPL_BW_OFST_C 0x23AC
|
#define R1B_RX_RPL_BW_OFST_C_M 0x180
|
#define R1B_RX_AGC_CCA_ILLEGAL_EN_C 0x23AC
|
#define R1B_RX_AGC_CCA_ILLEGAL_EN_C_M 0x200
|
#define R1B_RX_AGC_CCA_ILLEGAL_ST_1_C 0x23AC
|
#define R1B_RX_AGC_CCA_ILLEGAL_ST_1_C_M 0x3C00
|
#define R1B_RX_AGC_CCA_ILLEGAL_ST_2_C 0x23AC
|
#define R1B_RX_AGC_CCA_ILLEGAL_ST_2_C_M 0x3C000
|
#define R1B_RX_AGC_CCA_ILLEGAL_ST_3_C 0x23AC
|
#define R1B_RX_AGC_CCA_ILLEGAL_ST_3_C_M 0x3C0000
|
#define R1B_RX_AGC_CCA_ILLEGAL_ST_4_C 0x23AC
|
#define R1B_RX_AGC_CCA_ILLEGAL_ST_4_C_M 0x3C00000
|
#define R1B_RX_POP_MASK_SRC_OPT_C 0x23AC
|
#define R1B_RX_POP_MASK_SRC_OPT_C_M 0x4000000
|
#define R1B_RX_FAGCRDY_FIX_OFF_C 0x23AC
|
#define R1B_RX_FAGCRDY_FIX_OFF_C_M 0x8000000
|
#define R1B_RX_OFF_CLK_EN_C 0x23AC
|
#define R1B_RX_OFF_CLK_EN_C_M 0x10000000
|
#define R1B_RX_SCO_BC_SYNC_MODE_TH_C 0x23B0
|
#define R1B_RX_SCO_BC_SYNC_MODE_TH_C_M 0x7FFFF
|
#define R1B_RX_SCO_FPGA_DOWNRATE4_C 0x23B0
|
#define R1B_RX_SCO_FPGA_DOWNRATE4_C_M 0x80000
|
#define R1B_RX_CCA_RSSI_LMT_EN_C 0x23B0
|
#define R1B_RX_CCA_RSSI_LMT_EN_C_M 0x800000
|
#define R1B_RX_RSSI_NOCCA_LOW_TH_C 0x23B0
|
#define R1B_RX_RSSI_NOCCA_LOW_TH_C_M 0xFF000000
|
#define R1B_RX_SCO_CCK_SYNC_MODE_TH_C 0x23B4
|
#define R1B_RX_SCO_CCK_SYNC_MODE_TH_C_M 0x7FFFF
|
#define R1B_RX_RSSI_NOCCA_HIGH_TH_C 0x23B4
|
#define R1B_RX_RSSI_NOCCA_HIGH_TH_C_M 0xFF000000
|
#define HOLD_LDPC_MIN_TIME_C 0x2400
|
#define HOLD_LDPC_MIN_TIME_C_M 0x3FF
|
#define HOLD_LDPC_MIN_TIME_EN_C 0x2400
|
#define HOLD_LDPC_MIN_TIME_EN_C_M 0x10000
|
#define RXVB_OFF_PKT_END_C 0x2404
|
#define RXVB_OFF_PKT_END_C_M 0x1
|
#define LDPC_LBK_MODE_C 0x2404
|
#define LDPC_LBK_MODE_C_M 0x2
|
#define TX_OUT_BUFFER_FSM_RD_COND_C 0x2404
|
#define TX_OUT_BUFFER_FSM_RD_COND_C_M 0x4
|
#define RX_PHY_ST_DELAY_C 0x2408
|
#define RX_PHY_ST_DELAY_C_M 0xFF
|
#define HE_TB_PLCP_BYPASS_I_C 0x2408
|
#define HE_TB_PLCP_BYPASS_I_C_M 0x100
|
#define LDPC_0_CLOCK_EN_C 0x240C
|
#define LDPC_0_CLOCK_EN_C_M 0x1
|
#define LDPC_1_CLOCK_EN_C 0x240C
|
#define LDPC_1_CLOCK_EN_C_M 0x2
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#define DIS_NEW_REPT_ERROR_FIX_C 0x2410
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#define DIS_NEW_REPT_ERROR_FIX_C_M 0x1
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#define USER_TXBF_TYPE_C 0x2410
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#define USER_TXBF_TYPE_C_M 0x10
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#define DIS_TX_HE_RU26_FLAG_C 0x2410
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#define DIS_TX_HE_RU26_FLAG_C_M 0x100
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#define TX_HE_RU26_ACTIVE_FLAG_C 0x2410
|
#define TX_HE_RU26_ACTIVE_FLAG_C_M 0x1000
|
#define P0_TXEN_ADVANCE_C 0x241C
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#define P0_TXEN_ADVANCE_C_M 0x1
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#define P1_TXEN_ADVANCE_C 0x241C
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#define P1_TXEN_ADVANCE_C_M 0x10
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#define MAC_TRX_SEL_I_C 0x2420
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#define MAC_TRX_SEL_I_C_M 0xFFFFFFFF
|
#define TX_OUT_BUFFER_FSM_SEL_C 0x2424
|
#define TX_OUT_BUFFER_FSM_SEL_C_M 0x2
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#define RXPHY_BRK_WO_DATA_SEL_C 0x2424
|
#define RXPHY_BRK_WO_DATA_SEL_C_M 0x4
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#define TB_AIR_FIX_EN_C 0x2424
|
#define TB_AIR_FIX_EN_C_M 0x8
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#define RXINFO_RXSC_DELAY_SEL_C 0x2424
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#define RXINFO_RXSC_DELAY_SEL_C_M 0x10
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#define PATH1_R_DAC_QINV_C 0x3000
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#define PATH1_R_DAC_QINV_C_M 0x1
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#define PATH1_R_FIFO_CLR_ENB_C 0x3000
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#define PATH1_R_FIFO_CLR_ENB_C_M 0x10
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#define PATH1_R_T2F_FREERUN_BUF_EN_C 0x3004
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#define PATH1_R_T2F_FREERUN_BUF_EN_C_M 0x1
|
#define PATH1_R_T2F_L1_LATE_EN_C 0x3004
|
#define PATH1_R_T2F_L1_LATE_EN_C_M 0x2
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#define PATH1_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C 0x3004
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#define PATH1_R_T2F_DCCL_BT_GNT_BEFORE_CCA_MODE_C_M 0x10
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#define PATH1_R_T2F_DCCL_FILT_EN_C 0x3004
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#define PATH1_R_T2F_DCCL_FILT_EN_C_M 0x100
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#define PATH1_R_BT_GNT_RXTD_LATCH_EN_C 0x3004
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#define PATH1_R_BT_GNT_RXTD_LATCH_EN_C_M 0x1000
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#define PATH1_R_TD_CLK_GCK_EN_C 0x3008
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#define PATH1_R_TD_CLK_GCK_EN_C_M 0x1
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#define PATH1_R_1RCCA_CLK_GCK_ON_C 0x3008
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#define PATH1_R_1RCCA_CLK_GCK_ON_C_M 0x10
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#define PATH1_R_SYNC_RST_EN_TD_PATH_C 0x300C
|
#define PATH1_R_SYNC_RST_EN_TD_PATH_C_M 0x1
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#define PATH1_R_SYNC_RST_EN_FFT_C 0x300C
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#define PATH1_R_SYNC_RST_EN_FFT_C_M 0x10
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#define PATH1_R_SYNC_RST_EN_TXBUF_C 0x300C
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#define PATH1_R_SYNC_RST_EN_TXBUF_C_M 0x100
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#define PATH1_R_SYNC_RST_EN_RXBUF_C 0x300C
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#define PATH1_R_SYNC_RST_EN_RXBUF_C_M 0x1000
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#define PATH1_R_SYNC_RST_EN_DCCL_C 0x300C
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#define PATH1_R_SYNC_RST_EN_DCCL_C_M 0x10000
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#define PATH1_R_SYNC_RST_EN_T2F_C 0x300C
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#define PATH1_R_SYNC_RST_EN_T2F_C_M 0x100000
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#define PATH1_R_SYNC_RST_EN_RXFIR_COMP_C 0x300C
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#define PATH1_R_SYNC_RST_EN_RXFIR_COMP_C_M 0x1000000
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#define PATH1_R_DCCL_CFO_TH_EN_C 0x3010
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#define PATH1_R_DCCL_CFO_TH_EN_C_M 0x1
|
#define PATH1_R_DCCL_52B_SYMB_TH_EN_C 0x3010
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#define PATH1_R_DCCL_52B_SYMB_TH_EN_C_M 0x10
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#define PATH1_R_DCCL_52B_SYMB_TH_SEL_C 0x3010
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#define PATH1_R_DCCL_52B_SYMB_TH_SEL_C_M 0x20
|
#define PATH1_R_TX_STO_TRIG_SELECT_C 0x3014
|
#define PATH1_R_TX_STO_TRIG_SELECT_C_M 0x1
|
#define PATH1_R_TX_STO_FIRST_PE_SELECT_C 0x3014
|
#define PATH1_R_TX_STO_FIRST_PE_SELECT_C_M 0x2
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_L_C 0x3018
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_L_C_M 0x7
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_L_C 0x3018
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_L_C_M 0x70
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_L_C 0x3018
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_L_C_M 0x700
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_L_C 0x3018
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_L_C_M 0x7000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_L_C 0x3018
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_L_C_M 0x70000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_L_C 0x3018
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_L_C_M 0x700000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_L_C 0x3018
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_L_C_M 0x7000000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_L_C 0x3018
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_L_C_M 0x70000000
|
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_L_C 0x301C
|
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_L_C_M 0x8
|
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C 0x301C
|
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_L_C_M 0x10
|
#define PATH1_R_STO_INT_SEL_L_C 0x301C
|
#define PATH1_R_STO_INT_SEL_L_C_M 0x20
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C 0x301C
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_L_C_M 0x380
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_L_C 0x301C
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_L_C_M 0x400
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_L_C 0x301C
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_L_C_M 0x800
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_L_C 0x301C
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_L_C_M 0x1000
|
#define PATH1_R_TXCFO_RX_OFST_C 0x301C
|
#define PATH1_R_TXCFO_RX_OFST_C_M 0xF0000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HT_C 0x3020
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HT_C_M 0x7
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HT_C 0x3020
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HT_C_M 0x70
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HT_C 0x3020
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HT_C_M 0x700
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HT_C 0x3020
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HT_C_M 0x7000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HT_C 0x3020
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HT_C_M 0x70000
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HT_C 0x3020
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HT_C_M 0x700000
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HT_C 0x3020
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HT_C_M 0x7000000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HT_C 0x3020
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HT_C_M 0x70000000
|
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HT_C 0x3024
|
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HT_C_M 0x8
|
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C 0x3024
|
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HT_C_M 0x10
|
#define PATH1_R_STO_INT_SEL_HT_C 0x3024
|
#define PATH1_R_STO_INT_SEL_HT_C_M 0x20
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C 0x3024
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HT_C_M 0x380
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#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HT_C 0x3024
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HT_C_M 0x400
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HT_C 0x3024
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#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HT_C_M 0x800
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#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HT_C 0x3024
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#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HT_C_M 0x1000
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_VHT_C 0x3028
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_VHT_C_M 0x7
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_VHT_C 0x3028
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_VHT_C_M 0x70
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_VHT_C 0x3028
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_VHT_C_M 0x700
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_VHT_C 0x3028
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_VHT_C_M 0x7000
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_VHT_C 0x3028
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_VHT_C_M 0x70000
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_VHT_C 0x3028
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_VHT_C_M 0x700000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_VHT_C 0x3028
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_VHT_C_M 0x7000000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_VHT_C 0x3028
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_VHT_C_M 0x70000000
|
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_VHT_C 0x302C
|
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_VHT_C_M 0x8
|
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C 0x302C
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#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_VHT_C_M 0x10
|
#define PATH1_R_STO_INT_SEL_VHT_C 0x302C
|
#define PATH1_R_STO_INT_SEL_VHT_C_M 0x20
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C 0x302C
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#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_VHT_C_M 0x380
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C 0x302C
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_VHT_C_M 0x400
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C 0x302C
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_VHT_C_M 0x800
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C 0x302C
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_VHT_C_M 0x1000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HE_C 0x3030
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET1_HE_C_M 0x7
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HE_C 0x3030
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET2_HE_C_M 0x70
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HE_C 0x3030
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET3_HE_C_M 0x700
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HE_C 0x3030
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET4_HE_C_M 0x7000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HE_C 0x3030
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET5_HE_C_M 0x70000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HE_C 0x3030
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET6_HE_C_M 0x700000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HE_C 0x3030
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET7_HE_C_M 0x7000000
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HE_C 0x3030
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET8_HE_C_M 0x70000000
|
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HE_C 0x3034
|
#define PATH1_R_TX_STO_INT1_BYPASS_MODE_HE_C_M 0x8
|
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C 0x3034
|
#define PATH1_R_TX_STO_INT1_BYPASS_ALWAYS_HIGH_HE_C_M 0x10
|
#define PATH1_R_STO_INT_SEL_HE_C 0x3034
|
#define PATH1_R_STO_INT_SEL_HE_C_M 0x20
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C 0x3034
|
#define PATH1_R_TX_STO_INT_PART_BP_TARGET_STOP_HE_C_M 0x380
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HE_C 0x3034
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_20M_HE_C_M 0x400
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HE_C 0x3034
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_40M_HE_C_M 0x800
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HE_C 0x3034
|
#define PATH1_R_STO7_NXT_SYMBOL_SEL_80M_HE_C_M 0x1000
|
#define PATH1_R_HW_SI_READ_ADDR_C 0x3200
|
#define PATH1_R_HW_SI_READ_ADDR_C_M 0xFF
|
#define PATH1_R_HW_SI_READ_EDGE_OPT_C 0x3200
|
#define PATH1_R_HW_SI_READ_EDGE_OPT_C_M 0x300
|
#define PATH1_R_HW_SI_ZERO_PADDING_EN_C 0x3200
|
#define PATH1_R_HW_SI_ZERO_PADDING_EN_C_M 0x8000
|
#define PATH1_R_HW_SI_BYPASS_ST_MASK_C 0x3200
|
#define PATH1_R_HW_SI_BYPASS_ST_MASK_C_M 0x10000
|
#define PATH1_R_HW_SI_DATA_E_INV_C 0x3200
|
#define PATH1_R_HW_SI_DATA_E_INV_C_M 0x20000
|
#define PATH1_R_HW_SI_SEL_DBG_C 0x3200
|
#define PATH1_R_HW_SI_SEL_DBG_C_M 0xC0000
|
#define PATH1_R_HW_SI_DBG_MODE_C 0x3200
|
#define PATH1_R_HW_SI_DBG_MODE_C_M 0x100000
|
#define PATH1_R_HW_SI_ZERO_PADDING_NUM_C 0x3200
|
#define PATH1_R_HW_SI_ZERO_PADDING_NUM_C_M 0x3E00000
|
#define PATH1_R_HW_SI_DBG_TX_TRIG_C 0x3200
|
#define PATH1_R_HW_SI_DBG_TX_TRIG_C_M 0x4000000
|
#define PATH1_R_HW_SI_DIS_W_RX_TRIG_C 0x3200
|
#define PATH1_R_HW_SI_DIS_W_RX_TRIG_C_M 0x10000000
|
#define PATH1_R_HW_SI_DIS_W_TX_TRIG_C 0x3200
|
#define PATH1_R_HW_SI_DIS_W_TX_TRIG_C_M 0x20000000
|
#define PATH1_R_HW_SI_DIS_R_TRIG_C 0x3200
|
#define PATH1_R_HW_SI_DIS_R_TRIG_C_M 0x40000000
|
#define PATH1_R_HW_SI_DBG_RX_CMD_0_C 0x3204
|
#define PATH1_R_HW_SI_DBG_RX_CMD_0_C_M 0xFFFF
|
#define PATH1_R_HW_SI_DBG_RX_CMD_1_C 0x3204
|
#define PATH1_R_HW_SI_DBG_RX_CMD_1_C_M 0xFFFF0000
|
#define PATH1_R_HW_SI_DBG_TX_CMD_0_C 0x3208
|
#define PATH1_R_HW_SI_DBG_TX_CMD_0_C_M 0xFFFF
|
#define PATH1_R_HW_SI_DBG_TX_CMD_1_C 0x3208
|
#define PATH1_R_HW_SI_DBG_TX_CMD_1_C_M 0xFFFF0000
|
#define PATH1_R_ANAPAR_ST1P5_SEL_C 0x320C
|
#define PATH1_R_ANAPAR_ST1P5_SEL_C_M 0xF
|
#define PATH1_R_ANAPAR_ST3P5_SEL_C 0x320C
|
#define PATH1_R_ANAPAR_ST3P5_SEL_C_M 0xF0
|
#define PATH1_R_ANAPAR_DIS_TSSI_DCK_ST_C 0x320C
|
#define PATH1_R_ANAPAR_DIS_TSSI_DCK_ST_C_M 0x80000000
|
#define PATH1_R_RFMODE_RSTB_EQ0_EN_C 0x3210
|
#define PATH1_R_RFMODE_RSTB_EQ0_EN_C_M 0x1
|
#define PATH1_R_PW_RSTB_EQ0_EN_C 0x3210
|
#define PATH1_R_PW_RSTB_EQ0_EN_C_M 0x2
|
#define PATH1_R_RSTB_EQ0_EN_C 0x3210
|
#define PATH1_R_RSTB_EQ0_EN_C_M 0x4
|
#define PATH1_R_RFMODE_RSTB_EQ0_C 0x3210
|
#define PATH1_R_RFMODE_RSTB_EQ0_C_M 0xF0
|
#define PATH1_R_PW_RSTB_EQ0_C 0x3210
|
#define PATH1_R_PW_RSTB_EQ0_C_M 0xFF00
|
#define PATH1_R_RSTB_EQ0_C 0x3210
|
#define PATH1_R_RSTB_EQ0_C_M 0xFFFF0000
|
#define PATH1_R_RFC_SI_SEL_0_C 0x3214
|
#define PATH1_R_RFC_SI_SEL_0_C_M 0x1
|
#define PATH1_R_RFC_SI_SEL_1_C 0x3214
|
#define PATH1_R_RFC_SI_SEL_1_C_M 0x10
|
#define PATH1_R_HW_SI_W_RX_TRIG_DLY_EN_C 0x3218
|
#define PATH1_R_HW_SI_W_RX_TRIG_DLY_EN_C_M 0x1
|
#define PATH1_R_HW_SI_W_TX_TRIG_DLY_EN_C 0x3218
|
#define PATH1_R_HW_SI_W_TX_TRIG_DLY_EN_C_M 0x2
|
#define PATH1_R_HW_SI_R_TRIG_DLY_EN_C 0x3218
|
#define PATH1_R_HW_SI_R_TRIG_DLY_EN_C_M 0x4
|
#define PATH1_R_HW_SI_W_RX_TRIG_DLY_C 0x3218
|
#define PATH1_R_HW_SI_W_RX_TRIG_DLY_C_M 0xF0
|
#define PATH1_R_HW_SI_W_TX_TRIG_DLY_C 0x3218
|
#define PATH1_R_HW_SI_W_TX_TRIG_DLY_C_M 0xF00
|
#define PATH1_R_HW_SI_R_TRIG_DLY_C 0x3218
|
#define PATH1_R_HW_SI_R_TRIG_DLY_C_M 0xF000
|
#define PATH1_R_ANAPAR_RST_SEL_C 0x32A0
|
#define PATH1_R_ANAPAR_RST_SEL_C_M 0xF
|
#define PATH1_R_ANAPAR_RST_TX_SEL_C 0x32A0
|
#define PATH1_R_ANAPAR_RST_TX_SEL_C_M 0xF0
|
#define PATH1_R_ANAPAR_CTSDM_131_128__C 0x32A0
|
#define PATH1_R_ANAPAR_CTSDM_131_128__C_M 0xF00
|
#define PATH1_R_TXCK_FORCE_VAL_C 0x32A0
|
#define PATH1_R_TXCK_FORCE_VAL_C_M 0x7000
|
#define PATH1_R_TXCK_FORCE_ON_C 0x32A0
|
#define PATH1_R_TXCK_FORCE_ON_C_M 0x8000
|
#define PATH1_R_RXCK_FORCE_VAL_C 0x32A0
|
#define PATH1_R_RXCK_FORCE_VAL_C_M 0x70000
|
#define PATH1_R_RXCK_FORCE_ON_C 0x32A0
|
#define PATH1_R_RXCK_FORCE_ON_C_M 0x80000
|
#define PATH1_R_RXCK_RFBW0_C 0x32A0
|
#define PATH1_R_RXCK_RFBW0_C_M 0x700000
|
#define PATH1_R_RXCK_RFBW1_C 0x32A0
|
#define PATH1_R_RXCK_RFBW1_C_M 0x3800000
|
#define PATH1_R_RXCK_RFBW2_C 0x32A0
|
#define PATH1_R_RXCK_RFBW2_C_M 0x1C000000
|
#define PATH1_R_RXCK_RFBW3_C 0x32A0
|
#define PATH1_R_RXCK_RFBW3_C_M 0xE0000000
|
#define PATH1_R_RXCK_RFBW4_C 0x32A4
|
#define PATH1_R_RXCK_RFBW4_C_M 0x7
|
#define PATH1_R_RXCK_RFBW5_C 0x32A4
|
#define PATH1_R_RXCK_RFBW5_C_M 0x38
|
#define PATH1_R_RXCK_RFBW6_C 0x32A4
|
#define PATH1_R_RXCK_RFBW6_C_M 0x1C0
|
#define PATH1_R_TXCK_RFBW0_C 0x32A4
|
#define PATH1_R_TXCK_RFBW0_C_M 0x3800
|
#define PATH1_R_TXCK_RFBW1_C 0x32A4
|
#define PATH1_R_TXCK_RFBW1_C_M 0x1C000
|
#define PATH1_R_TXCK_RFBW2_C 0x32A4
|
#define PATH1_R_TXCK_RFBW2_C_M 0xE0000
|
#define PATH1_R_TXCK_RFBW3_C 0x32A4
|
#define PATH1_R_TXCK_RFBW3_C_M 0x700000
|
#define PATH1_R_TXCK_RFBW4_C 0x32A4
|
#define PATH1_R_TXCK_RFBW4_C_M 0x3800000
|
#define PATH1_R_TXCK_RFBW5_C 0x32A4
|
#define PATH1_R_TXCK_RFBW5_C_M 0x1C000000
|
#define PATH1_R_TXCK_RFBW6_C 0x32A4
|
#define PATH1_R_TXCK_RFBW6_C_M 0xE0000000
|
#define PATH1_R_EN_RXCK_TX_C 0x32A8
|
#define PATH1_R_EN_RXCK_TX_C_M 0x1
|
#define PATH1_R_RXCK_TX_C 0x32A8
|
#define PATH1_R_RXCK_TX_C_M 0xE
|
#define PATH1_R_RXCK_TX_FTM_C 0x32A8
|
#define PATH1_R_RXCK_TX_FTM_C_M 0x70
|
#define PATH1_R_CLK_RFC_GCK_EN_C 0x32A8
|
#define PATH1_R_CLK_RFC_GCK_EN_C_M 0x80
|
#define PATH1_R_RF0_GEN_DBG_SEL_C 0x32A8
|
#define PATH1_R_RF0_GEN_DBG_SEL_C_M 0x300
|
#define PATH1_R_RFMODE_GNT_WL_DIS_TX_OPT_C 0x32A8
|
#define PATH1_R_RFMODE_GNT_WL_DIS_TX_OPT_C_M 0x800
|
#define PATH1_R_RFAFE_PWSAV_EN_C 0x32A8
|
#define PATH1_R_RFAFE_PWSAV_EN_C_M 0xF000
|
#define PATH1_R_RFMODE_ORI_RXB_OFF_C 0x32A8
|
#define PATH1_R_RFMODE_ORI_RXB_OFF_C_M 0xF0000
|
#define PATH1_R_RFMODE_ORI_RXB_LOWPW_C 0x32A8
|
#define PATH1_R_RFMODE_ORI_RXB_LOWPW_C_M 0xF00000
|
#define PATH1_R_RFMODE_FTM_RXB_OFF_C 0x32A8
|
#define PATH1_R_RFMODE_FTM_RXB_OFF_C_M 0xF000000
|
#define PATH1_R_RFMODE_FTM_RXB_LOWPW_C 0x32A8
|
#define PATH1_R_RFMODE_FTM_RXB_LOWPW_C_M 0xF0000000
|
#define PATH1_R_RSTB_3WIRE_C 0x32AC
|
#define PATH1_R_RSTB_3WIRE_C_M 0x1
|
#define PATH1_R_EN_NRBW_AT_TX_C 0x32AC
|
#define PATH1_R_EN_NRBW_AT_TX_C_M 0x4
|
#define PATH1_R_RFMODE_ORI_TX_C 0x32AC
|
#define PATH1_R_RFMODE_ORI_TX_C_M 0xF0
|
#define PATH1_R_RFMODE_ORI_TX_TXOFF_C 0x32AC
|
#define PATH1_R_RFMODE_ORI_TX_TXOFF_C_M 0xF00
|
#define PATH1_R_RFMODE_ORI_RX_OFDM_CCA_C 0x32AC
|
#define PATH1_R_RFMODE_ORI_RX_OFDM_CCA_C_M 0xF000
|
#define PATH1_R_RFMODE_ORI_RX_CCK_CCA_C 0x32AC
|
#define PATH1_R_RFMODE_ORI_RX_CCK_CCA_C_M 0xF0000
|
#define PATH1_R_RFMODE_ORI_RX_IDLE_C 0x32AC
|
#define PATH1_R_RFMODE_ORI_RX_IDLE_C_M 0xF00000
|
#define PATH1_R_RFMODE_FTM_TX_C 0x32AC
|
#define PATH1_R_RFMODE_FTM_TX_C_M 0xF000000
|
#define PATH1_R_RFMODE_FTM_TX_TXOFF_C 0x32AC
|
#define PATH1_R_RFMODE_FTM_TX_TXOFF_C_M 0xF0000000
|
#define PATH1_R_RFMODE_FTM_RX_OFDM_CCA_C 0x32B0
|
#define PATH1_R_RFMODE_FTM_RX_OFDM_CCA_C_M 0xF
|
#define PATH1_R_RFMODE_FTM_RX_CCK_CCA_C 0x32B0
|
#define PATH1_R_RFMODE_FTM_RX_CCK_CCA_C_M 0xF0
|
#define PATH1_R_RFMODE_FTM_RX_IDLE_C 0x32B0
|
#define PATH1_R_RFMODE_FTM_RX_IDLE_C_M 0xF00
|
#define PATH1_R_RXB_IDX_AT_TX_C 0x32B0
|
#define PATH1_R_RXB_IDX_AT_TX_C_M 0x1F000
|
#define PATH1_R_TIA_IDX_AT_TX_C 0x32B0
|
#define PATH1_R_TIA_IDX_AT_TX_C_M 0x20000
|
#define PATH1_R_LNA_IDX_AT_TX_C 0x32B0
|
#define PATH1_R_LNA_IDX_AT_TX_C_M 0x1C0000
|
#define PATH1_R_TIA_EXT_BW_AT_TX_C 0x32B0
|
#define PATH1_R_TIA_EXT_BW_AT_TX_C_M 0x200000
|
#define PATH1_R_SI_RADDR_C 0x32B0
|
#define PATH1_R_SI_RADDR_C_M 0x3FC00000
|
#define PATH1_R_RST_3WIRE_CONFLICT_CNT_C 0x32B0
|
#define PATH1_R_RST_3WIRE_CONFLICT_CNT_C_M 0x80000000
|
#define PATH1_R_SOFT3WIRE_DATA_C 0x32B4
|
#define PATH1_R_SOFT3WIRE_DATA_C_M 0xFFFFFFF
|
#define PATH1_R_TXAGC_AT_SLEEP_C 0x32B8
|
#define PATH1_R_TXAGC_AT_SLEEP_C_M 0x3F
|
#define PATH1_R_RXB_IDX_AT_SLEEP_C 0x32B8
|
#define PATH1_R_RXB_IDX_AT_SLEEP_C_M 0x7C0
|
#define PATH1_R_TIA_IDX_AT_SLEEP_C 0x32B8
|
#define PATH1_R_TIA_IDX_AT_SLEEP_C_M 0x800
|
#define PATH1_R_LNA_IDX_AT_SLEEP_C 0x32B8
|
#define PATH1_R_LNA_IDX_AT_SLEEP_C_M 0x7000
|
#define PATH1_R_TIA_EXT_BW_AT_SLEEP_C 0x32B8
|
#define PATH1_R_TIA_EXT_BW_AT_SLEEP_C_M 0x8000
|
#define PATH1_R_EN_NRBW_AT_SLEEP_C 0x32B8
|
#define PATH1_R_EN_NRBW_AT_SLEEP_C_M 0x10000
|
#define PATH1_R_RFMODE_AT_SLEEP_C 0x32B8
|
#define PATH1_R_RFMODE_AT_SLEEP_C_M 0x1E0000
|
#define PATH1_R_TXAGC_BYPASS_C 0x32B8
|
#define PATH1_R_TXAGC_BYPASS_C_M 0x200000
|
#define PATH1_R_RXB_BYPASS_C 0x32B8
|
#define PATH1_R_RXB_BYPASS_C_M 0x400000
|
#define PATH1_R_TIA_BYPASS_C 0x32B8
|
#define PATH1_R_TIA_BYPASS_C_M 0x800000
|
#define PATH1_R_LNA_BYPASS_C 0x32B8
|
#define PATH1_R_LNA_BYPASS_C_M 0x1000000
|
#define PATH1_R_TIA_EXT_BYPASS_C 0x32B8
|
#define PATH1_R_TIA_EXT_BYPASS_C_M 0x2000000
|
#define PATH1_R_EN_NRBW_BYPASS_C 0x32B8
|
#define PATH1_R_EN_NRBW_BYPASS_C_M 0x4000000
|
#define PATH1_R_RFREG_DIS_GATING_C 0x32B8
|
#define PATH1_R_RFREG_DIS_GATING_C_M 0x8000000
|
#define PATH1_R_RSTB_ANAPAR_C 0x32B8
|
#define PATH1_R_RSTB_ANAPAR_C_M 0x10000000
|
#define PATH1_R_ANAPAR_SEL_OPT_C 0x32B8
|
#define PATH1_R_ANAPAR_SEL_OPT_C_M 0x20000000
|
#define PATH1_R_ANAPAR_DBG_MODE_C 0x32B8
|
#define PATH1_R_ANAPAR_DBG_MODE_C_M 0x40000000
|
#define PATH1_R_ANAPAR_DIS_GATING_C 0x32B8
|
#define PATH1_R_ANAPAR_DIS_GATING_C_M 0x80000000
|
#define PATH1_R_ANAPAR_ST0_SEL_C 0x32BC
|
#define PATH1_R_ANAPAR_ST0_SEL_C_M 0xF
|
#define PATH1_R_ANAPAR_ST1_SEL_C 0x32BC
|
#define PATH1_R_ANAPAR_ST1_SEL_C_M 0xF0
|
#define PATH1_R_ANAPAR_ST2_SEL_C 0x32BC
|
#define PATH1_R_ANAPAR_ST2_SEL_C_M 0xF00
|
#define PATH1_R_ANAPAR_ST3_SEL_C 0x32BC
|
#define PATH1_R_ANAPAR_ST3_SEL_C_M 0xF000
|
#define PATH1_R_ANAPAR_ST4_SEL_C 0x32BC
|
#define PATH1_R_ANAPAR_ST4_SEL_C_M 0xF0000
|
#define PATH1_R_ANAPAR_ST5_SEL_C 0x32BC
|
#define PATH1_R_ANAPAR_ST5_SEL_C_M 0xF00000
|
#define PATH1_R_ANAPAR_ST6_SEL_C 0x32BC
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#define PATH1_R_ANAPAR_ST6_SEL_C_M 0xF000000
|
#define PATH1_R_ANAPAR_ST7_SEL_C 0x32BC
|
#define PATH1_R_ANAPAR_ST7_SEL_C_M 0xF0000000
|
#define PATH1_R_ANAPAR_ST8_SEL_C 0x32C0
|
#define PATH1_R_ANAPAR_ST8_SEL_C_M 0xF
|
#define PATH1_R_ANAPAR_ST9_SEL_C 0x32C0
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#define PATH1_R_ANAPAR_ST9_SEL_C_M 0xF0
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#define PATH1_R_ANAPAR_ST10_SEL_C 0x32C0
|
#define PATH1_R_ANAPAR_ST10_SEL_C_M 0xF00
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#define PATH1_R_ANAPAR_ST11_SEL_C 0x32C0
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#define PATH1_R_ANAPAR_ST11_SEL_C_M 0xF000
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#define PATH1_R_ANAPAR_ST12_SEL_C 0x32C0
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#define PATH1_R_ANAPAR_ST12_SEL_C_M 0xF0000
|
#define PATH1_R_ANAPAR_ST13_SEL_C 0x32C0
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#define PATH1_R_ANAPAR_ST13_SEL_C_M 0xF00000
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#define PATH1_R_ANAPAR_ST14_SEL_C 0x32C0
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#define PATH1_R_ANAPAR_ST14_SEL_C_M 0xF000000
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#define PATH1_R_ANAPAR_ST15_SEL_C 0x32C0
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#define PATH1_R_ANAPAR_ST15_SEL_C_M 0xF0000000
|
#define PATH1_R_ANAPAR_ST16_SEL_C 0x32C4
|
#define PATH1_R_ANAPAR_ST16_SEL_C_M 0xF
|
#define PATH1_R_ANAPAR_ST17_SEL_C 0x32C4
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#define PATH1_R_ANAPAR_ST17_SEL_C_M 0xF0
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#define PATH1_R_ANAPAR_ST18_SEL_C 0x32C4
|
#define PATH1_R_ANAPAR_ST18_SEL_C_M 0xF00
|
#define PATH1_R_ANAPAR_ST19_SEL_C 0x32C4
|
#define PATH1_R_ANAPAR_ST19_SEL_C_M 0xF000
|
#define PATH1_R_ANAPAR_ST20_SEL_C 0x32C4
|
#define PATH1_R_ANAPAR_ST20_SEL_C_M 0xF0000
|
#define PATH1_R_ANAPAR_ST21_SEL_C 0x32C4
|
#define PATH1_R_ANAPAR_ST21_SEL_C_M 0xF00000
|
#define PATH1_R_ANAPAR_ST22_SEL_C 0x32C4
|
#define PATH1_R_ANAPAR_ST22_SEL_C_M 0xF000000
|
#define PATH1_R_ANAPAR_ST23_SEL_C 0x32C4
|
#define PATH1_R_ANAPAR_ST23_SEL_C_M 0xF0000000
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#define PATH1_R_ANAPAR_ST24_SEL_C 0x32C8
|
#define PATH1_R_ANAPAR_ST24_SEL_C_M 0xF
|
#define PATH1_R_ANAPAR_ST25_SEL_C 0x32C8
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#define PATH1_R_ANAPAR_ST25_SEL_C_M 0xF0
|
#define PATH1_R_ANAPAR_ST26_SEL_C 0x32C8
|
#define PATH1_R_ANAPAR_ST26_SEL_C_M 0xF00
|
#define PATH1_R_ANAPAR_ST27_SEL_C 0x32C8
|
#define PATH1_R_ANAPAR_ST27_SEL_C_M 0xF000
|
#define PATH1_R_ANAPAR_ST28_SEL_C 0x32C8
|
#define PATH1_R_ANAPAR_ST28_SEL_C_M 0xF0000
|
#define PATH1_R_ANAPAR_ST29_SEL_C 0x32C8
|
#define PATH1_R_ANAPAR_ST29_SEL_C_M 0xF00000
|
#define PATH1_R_ANAPAR_ST30_SEL_C 0x32C8
|
#define PATH1_R_ANAPAR_ST30_SEL_C_M 0xF000000
|
#define PATH1_R_ANAPAR_ST31_SEL_C 0x32C8
|
#define PATH1_R_ANAPAR_ST31_SEL_C_M 0xF0000000
|
#define PATH1_R_ANAPAR_CTSDM_31_0__C 0x32CC
|
#define PATH1_R_ANAPAR_CTSDM_31_0__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_CTSDM_63_32__C 0x32D0
|
#define PATH1_R_ANAPAR_CTSDM_63_32__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_CTSDM_95_64__C 0x32D4
|
#define PATH1_R_ANAPAR_CTSDM_95_64__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_CTSDM_127_96__C 0x32D8
|
#define PATH1_R_ANAPAR_CTSDM_127_96__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_31_0__C 0x32DC
|
#define PATH1_R_ANAPAR_31_0__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_63_32__C 0x32E0
|
#define PATH1_R_ANAPAR_63_32__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_95_64__C 0x32E4
|
#define PATH1_R_ANAPAR_95_64__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_127_96__C 0x32E8
|
#define PATH1_R_ANAPAR_127_96__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_143_128__C 0x32EC
|
#define PATH1_R_ANAPAR_143_128__C_M 0xFFFF
|
#define PATH1_R_ANAPAR_LBK_15_0__C 0x32EC
|
#define PATH1_R_ANAPAR_LBK_15_0__C_M 0xFFFF0000
|
#define PATH1_R_ANAPAR_LBK_47_16__C 0x32F0
|
#define PATH1_R_ANAPAR_LBK_47_16__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_LBK_79_48__C 0x32F4
|
#define PATH1_R_ANAPAR_LBK_79_48__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_LBK_111_80__C 0x32F8
|
#define PATH1_R_ANAPAR_LBK_111_80__C_M 0xFFFFFFFF
|
#define PATH1_R_ANAPAR_LBK_143_112__C 0x32FC
|
#define PATH1_R_ANAPAR_LBK_143_112__C_M 0xFFFFFFFF
|
#define PATH1_TSSI_DBG_PORT_C 0x3C00
|
#define PATH1_TSSI_DBG_PORT_C_M 0xFFFFFFFF
|
#define PATH1_DCK_AUTO_AVG_DC_C 0x3C04
|
#define PATH1_DCK_AUTO_AVG_DC_C_M 0xFFF000
|
#define PATH1_HE_LSTF_PW_OFST_C 0x3C04
|
#define PATH1_HE_LSTF_PW_OFST_C_M 0xFF000000
|
#define PATH1_DCK_AUTO_MAX_DC_C 0x3C08
|
#define PATH1_DCK_AUTO_MAX_DC_C_M 0xFFF
|
#define PATH1_DCK_AUTO_MIN_DC_C 0x3C08
|
#define PATH1_DCK_AUTO_MIN_DC_C_M 0xFFF000
|
#define PATH1_TMETER_F_C 0x3C08
|
#define PATH1_TMETER_F_C_M 0xFF000000
|
#define PATH1_TSSI_AVG_R_C 0x3C10
|
#define PATH1_TSSI_AVG_R_C_M 0xFFF
|
#define PATH1_TSSI_MAX_R_C 0x3C10
|
#define PATH1_TSSI_MAX_R_C_M 0xFFF000
|
#define PATH1_TSSI_F_NOW_C 0x3C10
|
#define PATH1_TSSI_F_NOW_C_M 0xFF000000
|
#define PATH1_TSSI_MID_R_C 0x3C14
|
#define PATH1_TSSI_MID_R_C_M 0xFFF
|
#define PATH1_TSSI_LAST_R_C 0x3C14
|
#define PATH1_TSSI_LAST_R_C_M 0xFFF000
|
#define PATH1_GAIN_TX_IPA_MX_C 0x3C14
|
#define PATH1_GAIN_TX_IPA_MX_C_M 0x7000000
|
#define PATH1_TSSI_VAL_AVG_C 0x3C18
|
#define PATH1_TSSI_VAL_AVG_C_M 0x3FF
|
#define PATH1_TSSI_VAL_AVG_OUT_VLD_C 0x3C18
|
#define PATH1_TSSI_VAL_AVG_OUT_VLD_C_M 0x10000
|
#define PATH1_ADC_RE_C 0x3C18
|
#define PATH1_ADC_RE_C_M 0xFFF00000
|
#define PATH1_TSSI_VAL_D00_C 0x3C1C
|
#define PATH1_TSSI_VAL_D00_C_M 0x3FF
|
#define PATH1_TSSI_VAL_VLD_IDX_0_C 0x3C1C
|
#define PATH1_TSSI_VAL_VLD_IDX_0_C_M 0x8000
|
#define PATH1_TSSI_VAL_D01_C 0x3C1C
|
#define PATH1_TSSI_VAL_D01_C_M 0x3FF0000
|
#define PATH1_TSSI_VAL_VLD_IDX_1_C 0x3C1C
|
#define PATH1_TSSI_VAL_VLD_IDX_1_C_M 0x80000000
|
#define PATH1_TSSI_VAL_D02_C 0x3C20
|
#define PATH1_TSSI_VAL_D02_C_M 0x3FF
|
#define PATH1_TSSI_VAL_VLD_IDX_2_C 0x3C20
|
#define PATH1_TSSI_VAL_VLD_IDX_2_C_M 0x8000
|
#define PATH1_TSSI_VAL_D03_C 0x3C20
|
#define PATH1_TSSI_VAL_D03_C_M 0x3FF0000
|
#define PATH1_TSSI_VAL_VLD_IDX_3_C 0x3C20
|
#define PATH1_TSSI_VAL_VLD_IDX_3_C_M 0x80000000
|
#define PATH1_TSSI_VAL_D04_C 0x3C24
|
#define PATH1_TSSI_VAL_D04_C_M 0x3FF
|
#define PATH1_TSSI_VAL_VLD_IDX_4_C 0x3C24
|
#define PATH1_TSSI_VAL_VLD_IDX_4_C_M 0x8000
|
#define PATH1_TSSI_VAL_D05_C 0x3C24
|
#define PATH1_TSSI_VAL_D05_C_M 0x3FF0000
|
#define PATH1_TSSI_VAL_VLD_IDX_5_C 0x3C24
|
#define PATH1_TSSI_VAL_VLD_IDX_5_C_M 0x80000000
|
#define PATH1_TSSI_VAL_D06_C 0x3C28
|
#define PATH1_TSSI_VAL_D06_C_M 0x3FF
|
#define PATH1_TSSI_VAL_VLD_IDX_6_C 0x3C28
|
#define PATH1_TSSI_VAL_VLD_IDX_6_C_M 0x8000
|
#define PATH1_TSSI_VAL_D07_C 0x3C28
|
#define PATH1_TSSI_VAL_D07_C_M 0x3FF0000
|
#define PATH1_TSSI_VAL_VLD_IDX_7_C 0x3C28
|
#define PATH1_TSSI_VAL_VLD_IDX_7_C_M 0x80000000
|
#define PATH1_TSSI_VAL_D08_C 0x3C2C
|
#define PATH1_TSSI_VAL_D08_C_M 0x3FF
|
#define PATH1_TSSI_VAL_VLD_IDX_8_C 0x3C2C
|
#define PATH1_TSSI_VAL_VLD_IDX_8_C_M 0x8000
|
#define PATH1_TSSI_VAL_D09_C 0x3C2C
|
#define PATH1_TSSI_VAL_D09_C_M 0x3FF0000
|
#define PATH1_TSSI_VAL_VLD_IDX_9_C 0x3C2C
|
#define PATH1_TSSI_VAL_VLD_IDX_9_C_M 0x80000000
|
#define PATH1_TSSI_VAL_D10_C 0x3C30
|
#define PATH1_TSSI_VAL_D10_C_M 0x3FF
|
#define PATH1_TSSI_VAL_VLD_IDX_10_C 0x3C30
|
#define PATH1_TSSI_VAL_VLD_IDX_10_C_M 0x8000
|
#define PATH1_TSSI_VAL_D11_C 0x3C30
|
#define PATH1_TSSI_VAL_D11_C_M 0x3FF0000
|
#define PATH1_TSSI_VAL_VLD_IDX_11_C 0x3C30
|
#define PATH1_TSSI_VAL_VLD_IDX_11_C_M 0x80000000
|
#define PATH1_TSSI_VAL_D12_C 0x3C34
|
#define PATH1_TSSI_VAL_D12_C_M 0x3FF
|
#define PATH1_TSSI_VAL_VLD_IDX_12_C 0x3C34
|
#define PATH1_TSSI_VAL_VLD_IDX_12_C_M 0x8000
|
#define PATH1_TSSI_VAL_D13_C 0x3C34
|
#define PATH1_TSSI_VAL_D13_C_M 0x3FF0000
|
#define PATH1_TSSI_VAL_VLD_IDX_13_C 0x3C34
|
#define PATH1_TSSI_VAL_VLD_IDX_13_C_M 0x80000000
|
#define PATH1_TSSI_VAL_D14_C 0x3C38
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#define PATH1_TSSI_VAL_D14_C_M 0x3FF
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#define PATH1_TSSI_VAL_VLD_IDX_14_C 0x3C38
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#define PATH1_TSSI_VAL_VLD_IDX_14_C_M 0x8000
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#define PATH1_TSSI_VAL_D15_C 0x3C38
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#define PATH1_TSSI_VAL_D15_C_M 0x3FF0000
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#define PATH1_TSSI_VAL_VLD_IDX_15_C 0x3C38
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#define PATH1_TSSI_VAL_VLD_IDX_15_C_M 0x80000000
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#define PATH1_TSSI_OSCILLATION_CNT_C 0x3C3C
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#define PATH1_TSSI_OSCILLATION_CNT_C_M 0xFFFF
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#define PATH1_TSSI_VAL_VLD_IDX_C 0x3C3C
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#define PATH1_TSSI_VAL_VLD_IDX_C_M 0xFFFF0000
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#define PATH1_PRE_TXAGC_OFST_C 0x3C40
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#define PATH1_PRE_TXAGC_OFST_C_M 0xFF00
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#define PATH1_DELTA_TSSI_PW_C 0x3C40
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#define PATH1_DELTA_TSSI_PW_C_M 0xFF0000
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#define PATH1SWING_MIN_C 0x3C40
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#define PATH1SWING_MIN_C_M 0xF000000
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#define PATH1SWING_MAX_C 0x3C40
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#define PATH1SWING_MAX_C_M 0xF0000000
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#define PATH1_TSSI_C_RAW0_C 0x3C44
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#define PATH1_TSSI_C_RAW0_C_M 0x1FF000
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#define PATH1_TSSI_F_C 0x3C48
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#define PATH1_TSSI_F_C_M 0xFF
|
#define PATH1_TSSI_G_C 0x3C48
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#define PATH1_TSSI_G_C_M 0x3FF00
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#define PATH1_TSSI_S_C 0x3C48
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#define PATH1_TSSI_S_C_M 0x1FF00000
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#define PATH1_AVG_R_SQUARE_C 0x3C4C
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#define PATH1_AVG_R_SQUARE_C_M 0xFFFFFF
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#define PATH1_TSSI_F_RDY_C 0x3C4C
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#define PATH1_TSSI_F_RDY_C_M 0x20000000
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#define PATH1_TSSI_G_RDY_C 0x3C4C
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#define PATH1_TSSI_G_RDY_C_M 0x40000000
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#define PATH1_TSSI_C_RDY_C 0x3C4C
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#define PATH1_TSSI_C_RDY_C_M 0x80000000
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#define PATH1_IN_R_SQUARE_MAX_C 0x3C50
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#define PATH1_IN_R_SQUARE_MAX_C_M 0xFFFFFF
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#define PATH1_SPEC_IDX_C 0x3C50
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#define PATH1_SPEC_IDX_C_M 0x7000000
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#define PATH1_IN_R_SQUARE_MIN_C 0x3C54
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#define PATH1_IN_R_SQUARE_MIN_C_M 0xFFFFFF
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#define PATH1_AVG_R_RMS_C 0x3C58
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#define PATH1_AVG_R_RMS_C_M 0xFFF
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#define PATH1_AVG_R_RMS_RDY_C 0x3C58
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#define PATH1_AVG_R_RMS_RDY_C_M 0x80000000
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#define PATH1_DAC_GAIN_COMP_TBL_IDX_C 0x3C5C
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#define PATH1_DAC_GAIN_COMP_TBL_IDX_C_M 0xFF
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#define PATH1_DAC_GAIN_COMP_DBG_C 0x3C5C
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#define PATH1_DAC_GAIN_COMP_DBG_C_M 0xFFFFF00
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#define PATH1_TXAGC_RF_C 0x3C60
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#define PATH1_TXAGC_RF_C_M 0x3F
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#define PATH1_TSSI_OFST_C 0x3C60
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#define PATH1_TSSI_OFST_C_M 0x1F00
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#define PATH1_TXAGC_C 0x3C60
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#define PATH1_TXAGC_C_M 0xFF0000
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#define PATH1_TXAGC_ORIG_C 0x3C64
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#define PATH1_TXAGC_ORIG_C_M 0x1FF
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#define PATH1_TXAGC_ORIG_RAW_C 0x3C64
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#define PATH1_TXAGC_ORIG_RAW_C_M 0x1FF000
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#define PATH1_TXAGC_OFST_SEL_NONRFC_RPT_C 0x3C64
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#define PATH1_TXAGC_OFST_SEL_NONRFC_RPT_C_M 0xFF000000
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#define PATH1_TXAGC_TO_TSSI_CW_RPT_C 0x3C68
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#define PATH1_TXAGC_TO_TSSI_CW_RPT_C_M 0xFFFFFFFF
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#define PATH1_TSSI_C_RAW1_C 0x3C6C
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#define PATH1_TSSI_C_RAW1_C_M 0x1FF
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#define PATH1_DAC_GAIN_COMP_MX_C 0x3C70
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#define PATH1_DAC_GAIN_COMP_MX_C_M 0xFF0000
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#define PATH1_TSSI_CW_COMP_MX_C 0x3C70
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#define PATH1_TSSI_CW_COMP_MX_C_M 0xFF000000
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#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_C 0x3C74
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#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_C_M 0x1FF
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#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_C 0x3C74
|
#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_C_M 0x1FF000
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#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x3C74
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#define PATH1_TXAGC_OFDM_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x1000000
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#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C 0x3C74
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#define PATH1_TXAGC_CCK_REF_CW_REVISED_POS_O_WIERD_FLAG_C_M 0x2000000
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#define PATH1_RFC_PREAMLE_PW_TYPE_C 0x3C74
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#define PATH1_RFC_PREAMLE_PW_TYPE_C_M 0x70000000
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#define PATH1_TXPW_C 0x3C78
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#define PATH1_TXPW_C_M 0x1FF
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#define PATH1_TXAGCSWING_C 0x3C78
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#define PATH1_TXAGCSWING_C_M 0x1E00
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#define PATH1_HE_ER_SU_EN_C 0x3C78
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#define PATH1_HE_ER_SU_EN_C_M 0x2000
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#define PATH1_HE_TB_EN_C 0x3C78
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#define PATH1_HE_TB_EN_C_M 0x4000
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#define PATH1_CCK_PPDU_C 0x3C78
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#define PATH1_CCK_PPDU_C_M 0x8000
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#define PATH1_TXINFO_CH_WITH_DATA_C 0x3C78
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#define PATH1_TXINFO_CH_WITH_DATA_C_M 0xFF0000
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#define PATH1_TXSC_C 0x3C78
|
#define PATH1_TXSC_C_M 0xF000000
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#define PATH1_RF_BW_IDX_C 0x3C78
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#define PATH1_RF_BW_IDX_C_M 0x30000000
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#define PATH1_ISOFDM_PREAMBLE_C 0x3C78
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#define PATH1_ISOFDM_PREAMBLE_C_M 0x40000000
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#define PATH1_ISCCK_PREAMBLE_C 0x3C78
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#define PATH1_ISCCK_PREAMBLE_C_M 0x80000000
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#define PATH1_TXAGC_OFST_MX_C 0x3C7C
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#define PATH1_TXAGC_OFST_MX_C_M 0xFF
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#define PATH1_TXAGC_OFST_C 0x3C7C
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#define PATH1_TXAGC_OFST_C_M 0xFF00
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#define PATH1_TXAGC_OFST_VARIATION_POS_FLAG_C 0x3C7C
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#define PATH1_TXAGC_OFST_VARIATION_POS_FLAG_C_M 0x10000
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#define PATH1_TXAGC_OFST_VARIATION_NEG_FLAG_C 0x3C7C
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#define PATH1_TXAGC_OFST_VARIATION_NEG_FLAG_C_M 0x20000
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#define PATH1_BYPASS_TSSI_BY_C_C 0x3C7C
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#define PATH1_BYPASS_TSSI_BY_C_C_M 0x40000
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#define PATH1_ADC_VARIATION_C 0x3C7C
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#define PATH1_ADC_VARIATION_C_M 0xFFF00000
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#define PATH1_DBG_IQK_PATH_C 0x3C80
|
#define PATH1_DBG_IQK_PATH_C_M 0xFFFFFFFF
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#define PATH1_FTM_RFLBK_BYPASS_C 0x3C84
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#define PATH1_FTM_RFLBK_BYPASS_C_M 0x1
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#define PATH1_FTM_LBK_BYPASS_C 0x3C84
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#define PATH1_FTM_LBK_BYPASS_C_M 0x2
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#define PATH1_FTM_A2A_AFELBK_BYPASS_C 0x3C84
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#define PATH1_FTM_A2A_AFELBK_BYPASS_C_M 0x4
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#define PATH1_GNT_BT_TX_BYPASS_C 0x3C84
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#define PATH1_GNT_BT_TX_BYPASS_C_M 0x8
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#define PATH1_GNT_BT_BYPASS_C 0x3C84
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#define PATH1_GNT_BT_BYPASS_C_M 0x10
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#define PATH1_GNT_WL_BYPASS_C 0x3C84
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#define PATH1_GNT_WL_BYPASS_C_M 0x20
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#define PATH1_LTE_RX_BYPASS_C 0x3C84
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#define PATH1_LTE_RX_BYPASS_C_M 0x40
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#define PATH1_TSSI_BYPASS_TXPW_MIN_C 0x3C84
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#define PATH1_TSSI_BYPASS_TXPW_MIN_C_M 0x80
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#define PATH1_TSSI_BYPASS_TXPW_MAX_C 0x3C84
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#define PATH1_TSSI_BYPASS_TXPW_MAX_C_M 0x100
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#define PATH1_BYPASS_TSSI_BY_RATE_CCK_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_CCK_C_M 0x200
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#define PATH1_BYPASS_TSSI_BY_RATE_LEGACY_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_LEGACY_C_M 0x400
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#define PATH1_BYPASS_TSSI_BY_RATE_HT_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_HT_C_M 0x800
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#define PATH1_BYPASS_TSSI_BY_RATE_VHT_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_VHT_C_M 0x1000
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_SU_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_SU_C_M 0x2000
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_ER_SU_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_ER_SU_C_M 0x4000
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_TB_EN_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_TB_EN_C_M 0x8000
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#define PATH1_BYPASS_TSSI_BY_RATE_VHT_MU_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_VHT_MU_C_M 0x10000
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_MU_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_MU_C_M 0x20000
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_RU_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RATE_HE_RU_C_M 0x40000
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#define PATH1_BYPASS_TSSI_BY_TXBF_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_TXBF_C_M 0x80000
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#define PATH1_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x3C84
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#define PATH1_CCK_CCA_AND_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x100000
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#define PATH1_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x3C84
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#define PATH1_VHT_AND_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x200000
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#define PATH1_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C 0x3C84
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#define PATH1_HE_AND_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x400000
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#define PATH1_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C 0x3C84
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#define PATH1_HT_AND_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x800000
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#define PATH1_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C 0x3C84
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#define PATH1_BYPASS_TSSI_BY_RST_DAC_FIFO_SEL_C_M 0x40000000
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#define PATH1_BYPASS_TSSI_C 0x3C84
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#define PATH1_BYPASS_TSSI_C_M 0x80000000
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#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_C 0x3C88
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#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_C_M 0xF
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#define PATH1_DIGI_AGC_C 0x3C88
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#define PATH1_DIGI_AGC_C_M 0x3FF0
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#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_MX_C 0x3C88
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#define PATH1_WLS_WL_GAIN_TX_GAPK_BUF_MX_C_M 0xF0000
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#define PATH1_WLS_WL_GAIN_TX_PAD_BUF_MX_C 0x3C88
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#define PATH1_WLS_WL_GAIN_TX_PAD_BUF_MX_C_M 0x1F00000
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#define PATH1_WLS_WL_GAIN_TX_BUF_MX_C 0x3C88
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#define PATH1_WLS_WL_GAIN_TX_BUF_MX_C_M 0x3E000000
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#define PATH1_RX_CFIR_TAP_DEC_C 0x3C88
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#define PATH1_RX_CFIR_TAP_DEC_C_M 0x40000000
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#define PATH1_CLK_HIGH_RATE_MX_C 0x3C88
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#define PATH1_CLK_HIGH_RATE_MX_C_M 0x80000000
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#define PATH1_CFIR_OUT_IM_DBG_C 0x3C8C
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#define PATH1_CFIR_OUT_IM_DBG_C_M 0xFFF
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#define PATH1_CFIR_OUT_RE_DBG_C 0x3C8C
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#define PATH1_CFIR_OUT_RE_DBG_C_M 0xFFF000
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#define PATH1_EN_RX_CFIR_C 0x3C8C
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#define PATH1_EN_RX_CFIR_C_M 0x1000000
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#define PATH1_CLK_HIGH_RATE_C 0x3C8C
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#define PATH1_CLK_HIGH_RATE_C_M 0x2000000
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#define PATH1_EN_TX_CFIR_C 0x3C8C
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#define PATH1_EN_TX_CFIR_C_M 0x4000000
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#define PATH1_TX_CCK_IND_C 0x3C8C
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#define PATH1_TX_CCK_IND_C_M 0x8000000
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#define PATH1_CFIR_IN_IM_DBG_C 0x3C90
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#define PATH1_CFIR_IN_IM_DBG_C_M 0xFFF
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#define PATH1_CFIR_IN_RE_DBG_C 0x3C90
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#define PATH1_CFIR_IN_RE_DBG_C_M 0xFFF000
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#define PATH1_CCK_CCA_C 0x3C90
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#define PATH1_CCK_CCA_C_M 0x80000000
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#define PATH1_RX_C 0x3C94
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#define PATH1_RX_C_M 0x1F
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#define PATH1_LNA_SETTING_C 0x3C94
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#define PATH1_LNA_SETTING_C_M 0x700
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#define PATH1_TIA_C 0x3C94
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#define PATH1_TIA_C_M 0x1000
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#define PATH1_DB2FLT_O_C 0x3C94
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#define PATH1_DB2FLT_O_C_M 0x7FF8000
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#define PATH1_LSTF_SUM_LINEAR_PW_C 0x3C98
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#define PATH1_LSTF_SUM_LINEAR_PW_C_M 0xFFFFFFFF
|
#define PATH1_LSTF_MAX_LINEAR_PW_C 0x3C9C
|
#define PATH1_LSTF_MAX_LINEAR_PW_C_M 0x7FFFFF
|
#define PATH1_TSSI_C_C 0x3CA0
|
#define PATH1_TSSI_C_C_M 0x1FF
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#define PATH1_TSSI_C_SRC_C 0x3CA0
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#define PATH1_TSSI_C_SRC_C_M 0x3FF000
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#define PATH1_TXAGC_TP_C 0x3CA0
|
#define PATH1_TXAGC_TP_C_M 0xFF000000
|
#define PATH1_LOG_VAL_O_C 0x3CA4
|
#define PATH1_LOG_VAL_O_C_M 0xFFFFF
|
#define PATH1_TXAGC_OFST_ADJ_C 0x3CA4
|
#define PATH1_TXAGC_OFST_ADJ_C_M 0xFF000000
|
#define PATH1_TX_GAIN_FOR_DPD_DB2FLOAT_C 0x3CA8
|
#define PATH1_TX_GAIN_FOR_DPD_DB2FLOAT_C_M 0xFF
|
#define PATH1_TX_GAIN_FOR_DPD_DBAGC_COMB_C 0x3CA8
|
#define PATH1_TX_GAIN_FOR_DPD_DBAGC_COMB_C_M 0xFF00
|
#define PATH1_TMETER_TX_C 0x3CAC
|
#define PATH1_TMETER_TX_C_M 0x3F
|
#define PATH1_TMETER_CCA_POS_C 0x3CAC
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#define PATH1_TMETER_CCA_POS_C_M 0x3F00
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#define PATH1_TMETER_CCA_NEG_C 0x3CAC
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#define PATH1_TMETER_CCA_NEG_C_M 0x3F0000
|
#define PATH1_AFE_ANAPAR_PW_O_C 0x3CB0
|
#define PATH1_AFE_ANAPAR_PW_O_C_M 0xFF
|
#define PATH1_AFE_ANAPAR_CTRL_O_C 0x3CB0
|
#define PATH1_AFE_ANAPAR_CTRL_O_C_M 0xFFFF00
|
#define PATH1_MUX_ST_PATH_C 0x3CB0
|
#define PATH1_MUX_ST_PATH_C_M 0xF000000
|
#define PATH1_TSSI_J_CCK_C 0x3CB4
|
#define PATH1_TSSI_J_CCK_C_M 0x3FF
|
#define PATH1_TSSI_J_OFDM_C 0x3CB4
|
#define PATH1_TSSI_J_OFDM_C_M 0xFFC00
|
#define PATH1_TSSI_CURVE_C 0x3CB4
|
#define PATH1_TSSI_CURVE_C_M 0x70000000
|
#define PATH1_R_TXAGC_OFDM_REF_CW_CMB_C 0x3CB8
|
#define PATH1_R_TXAGC_OFDM_REF_CW_CMB_C_M 0x1FF
|
#define PATH1_R_TXAGC_CCK_REF_CW_CMB_C 0x3CB8
|
#define PATH1_R_TXAGC_CCK_REF_CW_CMB_C_M 0x1FF000
|
#define PATH1_AFE_ANAPAR_CTSDM_OUT_I_C 0x3E00
|
#define PATH1_AFE_ANAPAR_CTSDM_OUT_I_C_M 0xFFFFF
|
#define PATH1_RO_SI_R_DATA_P_C 0x3E04
|
#define PATH1_RO_SI_R_DATA_P_C_M 0xFFFFF
|
#define PATH1_NLGC_STEP_CNT_AT_AGC_RDY_C 0x3E08
|
#define PATH1_NLGC_STEP_CNT_AT_AGC_RDY_C_M 0x7
|
#define PATH1_POST_PD_STEP_CNT_AT_AGC_RDY_C 0x3E08
|
#define PATH1_POST_PD_STEP_CNT_AT_AGC_RDY_C_M 0x38
|
#define PATH1_LINEAR_STEP_CNT_AT_AGC_RDY_C 0x3E08
|
#define PATH1_LINEAR_STEP_CNT_AT_AGC_RDY_C_M 0x1C0
|
#define PATH1_PRE_PD_STEP_CNT_AT_AGC_RDY_C 0x3E08
|
#define PATH1_PRE_PD_STEP_CNT_AT_AGC_RDY_C_M 0xE00
|
#define PATH1_TIA_SAT_DET_AT_AGC_RDY_C 0x3E08
|
#define PATH1_TIA_SAT_DET_AT_AGC_RDY_C_M 0x1000
|
#define PATH1_LNA_SAT_DET_AT_AGC_RDY_C 0x3E08
|
#define PATH1_LNA_SAT_DET_AT_AGC_RDY_C_M 0x2000
|
#define PATH1_NRBW_AT_AGC_RDY_C 0x3E08
|
#define PATH1_NRBW_AT_AGC_RDY_C_M 0x4000
|
#define PATH1_TIA_SHRINK_AT_AGC_RDY_C 0x3E08
|
#define PATH1_TIA_SHRINK_AT_AGC_RDY_C_M 0x8000
|
#define PATH1_P_DIFF_AT_AGC_RDY_C 0x3E08
|
#define PATH1_P_DIFF_AT_AGC_RDY_C_M 0xFF0000
|
#define PATH1_ELNA_IDX_AT_AGC_RDY_C 0x3E0C
|
#define PATH1_ELNA_IDX_AT_AGC_RDY_C_M 0x1
|
#define PATH1_ELNA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_ELNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x2
|
#define PATH1_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_TIA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x4
|
#define PATH1_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_LNA_SAT_DET_AT_PRE_PD_AGC_RDY_C_M 0x8
|
#define PATH1_NRBW_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_NRBW_AT_PRE_PD_AGC_RDY_C_M 0x10
|
#define PATH1_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_TIA_SHRINK_AT_PRE_PD_AGC_RDY_C_M 0x20
|
#define PATH1_P_DIFF_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_P_DIFF_AT_PRE_PD_AGC_RDY_C_M 0x7FC0
|
#define PATH1_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_G_NLGC_DAGC_AT_PRE_PD_AGC_RDY_C_M 0x7F8000
|
#define PATH1_RXIDX_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_RXIDX_AT_PRE_PD_AGC_RDY_C_M 0xF800000
|
#define PATH1_TIA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_TIA_IDX_AT_PRE_PD_AGC_RDY_C_M 0x10000000
|
#define PATH1_LNA_IDX_AT_PRE_PD_AGC_RDY_C 0x3E0C
|
#define PATH1_LNA_IDX_AT_PRE_PD_AGC_RDY_C_M 0xE0000000
|
#define PATH1_ELNA_IDX_AT_PD_HIT_C 0x3E10
|
#define PATH1_ELNA_IDX_AT_PD_HIT_C_M 0x2
|
#define PATH1_TIA_SAT_DET_AT_PD_HIT_C 0x3E10
|
#define PATH1_TIA_SAT_DET_AT_PD_HIT_C_M 0x4
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#define PATH1_LNA_SAT_DET_AT_PD_HIT_C 0x3E10
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#define PATH1_LNA_SAT_DET_AT_PD_HIT_C_M 0x8
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#define PATH1_NRBW_AT_PD_HIT_C 0x3E10
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#define PATH1_NRBW_AT_PD_HIT_C_M 0x10
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#define PATH1_TIA_SHRINK_AT_PD_HIT_C 0x3E10
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#define PATH1_TIA_SHRINK_AT_PD_HIT_C_M 0x20
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#define PATH1_P_DIFF_AT_PD_HIT_C 0x3E10
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#define PATH1_P_DIFF_AT_PD_HIT_C_M 0x7FC0
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#define PATH1_G_NLGC_DAGC_AT_PD_HIT_C 0x3E10
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#define PATH1_G_NLGC_DAGC_AT_PD_HIT_C_M 0x7F8000
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#define PATH1_RXIDX_AT_PD_HIT_C 0x3E10
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#define PATH1_RXIDX_AT_PD_HIT_C_M 0xF800000
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#define PATH1_TIA_IDX_AT_PD_HIT_C 0x3E10
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#define PATH1_TIA_IDX_AT_PD_HIT_C_M 0x10000000
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#define PATH1_LNA_IDX_AT_PD_HIT_C 0x3E10
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#define PATH1_LNA_IDX_AT_PD_HIT_C_M 0xE0000000
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#define PATH1_ELNA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_ELNA_IDX_AT_POST_PD_AGC_RDY_C_M 0x2
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#define PATH1_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_TIA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x4
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#define PATH1_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_LNA_SAT_DET_AT_POST_PD_AGC_RDY_C_M 0x8
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#define PATH1_NRBW_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_NRBW_AT_POST_PD_AGC_RDY_C_M 0x10
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#define PATH1_TIA_SHRINK_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_TIA_SHRINK_AT_POST_PD_AGC_RDY_C_M 0x20
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#define PATH1_P_DIFF_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_P_DIFF_AT_POST_PD_AGC_RDY_C_M 0x7FC0
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#define PATH1_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_G_NLGC_DAGC_AT_POST_PD_AGC_RDY_C_M 0x7F8000
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#define PATH1_RXIDX_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_RXIDX_AT_POST_PD_AGC_RDY_C_M 0xF800000
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#define PATH1_TIA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_TIA_IDX_AT_POST_PD_AGC_RDY_C_M 0x10000000
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#define PATH1_LNA_IDX_AT_POST_PD_AGC_RDY_C 0x3E14
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#define PATH1_LNA_IDX_AT_POST_PD_AGC_RDY_C_M 0xE0000000
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#define PATH1_ELNA_IDX_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_ELNA_IDX_AT_NLGC_AGC_RDY_C_M 0x2
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#define PATH1_TIA_SAT_DET_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_TIA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x4
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#define PATH1_LNA_SAT_DET_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_LNA_SAT_DET_AT_NLGC_AGC_RDY_C_M 0x8
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#define PATH1_NRBW_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_NRBW_AT_NLGC_AGC_RDY_C_M 0x10
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#define PATH1_TIA_SHRINK_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_TIA_SHRINK_AT_NLGC_AGC_RDY_C_M 0x20
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#define PATH1_P_DIFF_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_P_DIFF_AT_NLGC_AGC_RDY_C_M 0x7FC0
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#define PATH1_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_G_NLGC_DAGC_AT_NLGC_AGC_RDY_C_M 0x7F8000
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#define PATH1_RXIDX_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_RXIDX_AT_NLGC_AGC_RDY_C_M 0xF800000
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#define PATH1_TIA_IDX_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_TIA_IDX_AT_NLGC_AGC_RDY_C_M 0x10000000
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#define PATH1_LNA_IDX_AT_NLGC_AGC_RDY_C 0x3E18
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#define PATH1_LNA_IDX_AT_NLGC_AGC_RDY_C_M 0xE0000000
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#define PATH1_RSSI_AT_AGC_RDY_C 0x3E1C
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#define PATH1_RSSI_AT_AGC_RDY_C_M 0x3FF
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#define PATH1_G_TOTAL_AT_AGC_RDY_C 0x3E1C
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#define PATH1_G_TOTAL_AT_AGC_RDY_C_M 0x7FC00
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#define PATH1_P_DFIR_DBM_AT_AGC_RDY_C 0x3E1C
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#define PATH1_P_DFIR_DBM_AT_AGC_RDY_C_M 0xFF80000
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#define PATH1_TIA_IDX_AT_AGC_RDY_C 0x3E1C
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#define PATH1_TIA_IDX_AT_AGC_RDY_C_M 0x10000000
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#define PATH1_LNA_IDX_AT_AGC_RDY_C 0x3E1C
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#define PATH1_LNA_IDX_AT_AGC_RDY_C_M 0xE0000000
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#define PATH1_RSSI_ALWAYS_RUN_C 0x3E20
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#define PATH1_RSSI_ALWAYS_RUN_C_M 0x3FF
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#define PATH1_TIA_SAT_DET_C 0x3E20
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#define PATH1_TIA_SAT_DET_C_M 0x400
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#define PATH1_LNA_SAT_DET_C 0x3E20
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#define PATH1_LNA_SAT_DET_C_M 0x800
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#define PATH1_NRBW_C 0x3E20
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#define PATH1_NRBW_C_M 0x1000
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#define PATH1_TIA_SHRINK_C 0x3E20
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#define PATH1_TIA_SHRINK_C_M 0x2000
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#define PATH1_G_LGC_DAGC_C 0x3E20
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#define PATH1_G_LGC_DAGC_C_M 0x3FC000
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#define PATH1_G_TOTAL_C 0x3E20
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#define PATH1_G_TOTAL_C_M 0xFFC00000
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#define PATH1_HW_SI_READ_DATA_C 0x3E24
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#define PATH1_HW_SI_READ_DATA_C_M 0xFFFFF
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_ALL_C_M 0x1
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_L_STF_C_M 0x2
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_FFT_C_M 0x4
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_PW_NORM_C_M 0x8
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_WIN_C_M 0x10
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_GAIN_C_M 0x20
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_CFO_C_M 0x40
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_DFIR_C_M 0x80
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR1_C_M 0x100
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IFMOD_C_M 0x200
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_B_IFMOD_C_M 0x400
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C 0x3E28
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#define PATH1_TD_RW_TXOV_RPT_PATH_OV_TX_IMFIR2_C_M 0x800
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#define PATH1_CNT_HW_SI_W_TX_CMD_START_PATH_C 0x3E2C
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#define PATH1_CNT_HW_SI_W_TX_CMD_START_PATH_C_M 0xFFFF
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#define PATH1_CNT_HW_SI_W_RX_CMD_START_PATH_C 0x3E2C
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#define PATH1_CNT_HW_SI_W_RX_CMD_START_PATH_C_M 0xFFFF0000
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#define PATH1_CNT_HW_SI_R_CMD_START_PATH_C 0x3E30
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#define PATH1_CNT_HW_SI_R_CMD_START_PATH_C_M 0xFFFF
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#define TX_ACC_EN_C 0x4000
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#define TX_ACC_EN_C_M 0x1
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#define BWD_SNR_THD_1_C 0x4004
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#define BWD_SNR_THD_1_C_M 0x3FF
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#define BWD_SNR_THD_2_C 0x4004
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#define BWD_SNR_THD_2_C_M 0xFFC00
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#define BWD_SNR_THD_3_C 0x4004
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#define BWD_SNR_THD_3_C_M 0x3FF00000
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#define BWD_SEL_CONSERVE_EN_C 0x4004
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#define BWD_SEL_CONSERVE_EN_C_M 0x40000000
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#define DATA_BW_FLAG_S0_C 0x4004
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#define DATA_BW_FLAG_S0_C_M 0x80000000
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#define BWD_SNR_THD_4_C 0x4008
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#define BWD_SNR_THD_4_C_M 0x3FF
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#define BWD_THD_1_C 0x4008
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#define BWD_THD_1_C_M 0xFFC00
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#define BWD_THD_2_C 0x4008
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#define BWD_THD_2_C_M 0x3FF00000
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#define DATA_BW_FLAG_S1_C 0x4008
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#define DATA_BW_FLAG_S1_C_M 0x40000000
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#define DATA_BW_FLAG_S2_C 0x4008
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#define DATA_BW_FLAG_S2_C_M 0x80000000
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#define BWD_THD_3_C 0x400C
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#define BWD_THD_3_C_M 0x3FF
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#define BWD_THD_4_C 0x400C
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#define BWD_THD_4_C_M 0xFFC00
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#define BWD_THD_5_C 0x400C
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#define BWD_THD_5_C_M 0x3FF00000
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#define DATA_BW_FLAG_S3_C 0x400C
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#define DATA_BW_FLAG_S3_C_M 0x40000000
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#define MANUAL_DATA_BW_EN_C 0x400C
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#define MANUAL_DATA_BW_EN_C_M 0x80000000
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#define BWD_RESERVED_1_C 0x4010
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#define BWD_RESERVED_1_C_M 0x3FF
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#define BWD_RESERVED_2_C 0x4010
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#define BWD_RESERVED_2_C_M 0xFFC00
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#define BWD_RESERVED_3_C 0x4010
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#define BWD_RESERVED_3_C_M 0x3FF00000
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#define BWD_RESERVED_4_C 0x4014
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#define BWD_RESERVED_4_C_M 0x3FF
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#define BWD_RESERVED_5_C 0x4014
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#define BWD_RESERVED_5_C_M 0xFFC00
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#define BWD_RESERVED_6_C 0x4014
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#define BWD_RESERVED_6_C_M 0x3FF00000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR0_C 0x4018
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR1_C 0x4018
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR2_C 0x4018
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR3_C 0x4018
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR4_C 0x401C
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR5_C 0x401C
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU0_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR0_C 0x401C
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR1_C 0x401C
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR2_C 0x4020
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR3_C 0x4020
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR4_C 0x4020
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR5_C 0x4020
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU1_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR0_C 0x4024
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR1_C 0x4024
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR2_C 0x4024
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR3_C 0x4024
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR4_C 0x4028
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR5_C 0x4028
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU2_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR0_C 0x4028
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR1_C 0x4028
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR2_C 0x402C
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR3_C 0x402C
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR4_C 0x402C
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR5_C 0x402C
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU3_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR0_C 0x4030
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR1_C 0x4030
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR2_C 0x4030
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR2_C_M 0xFF0000
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR3_C 0x4030
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR3_C_M 0xFF000000
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR4_C 0x4034
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR5_C 0x4034
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU4_SNR5_C_M 0xFF00
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR0_C 0x4034
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#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR0_C_M 0xFF0000
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR1_C 0x4034
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR1_C_M 0xFF000000
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR2_C 0x4038
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR2_C_M 0xFF
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR3_C 0x4038
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR3_C_M 0xFF00
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR4_C 0x4038
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR4_C_M 0xFF0000
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR5_C 0x4038
|
#define NOISE_SCAL_FCTR_5TAP_1X_TAU5_SNR5_C_M 0xFF000000
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR0_C 0x403C
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR0_C_M 0xFF
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR1_C 0x403C
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR1_C_M 0xFF00
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR2_C 0x403C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR2_C_M 0xFF0000
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR3_C 0x403C
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR3_C_M 0xFF000000
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR4_C 0x4040
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR4_C_M 0xFF
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR5_C 0x4040
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU0_SNR5_C_M 0xFF00
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR0_C 0x4040
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR0_C_M 0xFF0000
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR1_C 0x4040
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR1_C_M 0xFF000000
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR2_C 0x4044
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR2_C_M 0xFF
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR3_C 0x4044
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR3_C_M 0xFF00
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR4_C 0x4044
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR4_C_M 0xFF0000
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR5_C 0x4044
|
#define NOISE_SCAL_FCTR_5TAP_2X_TAU1_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR0_C 0x4048
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR1_C 0x4048
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR2_C 0x4048
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR3_C 0x4048
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR4_C 0x404C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR5_C 0x404C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU2_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR0_C 0x404C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR1_C 0x404C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR2_C 0x4050
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR3_C 0x4050
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR4_C 0x4050
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR5_C 0x4050
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU3_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR0_C 0x4054
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR1_C 0x4054
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR2_C 0x4054
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR3_C 0x4054
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR4_C 0x4058
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR5_C 0x4058
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU4_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR0_C 0x4058
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR1_C 0x4058
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR2_C 0x405C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR3_C 0x405C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR4_C 0x405C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR5_C 0x405C
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#define NOISE_SCAL_FCTR_5TAP_2X_TAU5_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR0_C 0x4060
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR1_C 0x4060
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR2_C 0x4060
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR3_C 0x4060
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR4_C 0x4064
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR5_C 0x4064
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU0_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR0_C 0x4064
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR1_C 0x4064
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR2_C 0x4068
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR3_C 0x4068
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR4_C 0x4068
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR5_C 0x4068
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU1_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR0_C 0x406C
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR1_C 0x406C
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR2_C 0x406C
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR3_C 0x406C
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR4_C 0x4070
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR5_C 0x4070
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU2_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR0_C 0x4070
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR1_C 0x4070
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR2_C 0x4074
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR3_C 0x4074
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR4_C 0x4074
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR5_C 0x4074
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU3_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR0_C 0x4078
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR1_C 0x4078
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR2_C 0x4078
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR3_C 0x4078
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR4_C 0x407C
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR5_C 0x407C
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU4_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR0_C 0x407C
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR1_C 0x407C
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR2_C 0x4080
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR3_C 0x4080
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR4_C 0x4080
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR5_C 0x4080
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#define NOISE_SCAL_FCTR_5TAP_4X_TAU5_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR0_C 0x4084
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR1_C 0x4084
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR2_C 0x4084
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR3_C 0x4084
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR4_C 0x4088
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR5_C 0x4088
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU0_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR0_C 0x4088
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR1_C 0x4088
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR2_C 0x408C
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR3_C 0x408C
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR4_C 0x408C
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR5_C 0x408C
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU1_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR0_C 0x4090
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR1_C 0x4090
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR2_C 0x4090
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR3_C 0x4090
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR4_C 0x4094
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR5_C 0x4094
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU2_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR0_C 0x4094
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR1_C 0x4094
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR2_C 0x4098
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR3_C 0x4098
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR4_C 0x4098
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR5_C 0x4098
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU3_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR0_C 0x409C
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR1_C 0x409C
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR2_C 0x409C
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR3_C 0x409C
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR4_C 0x40A0
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR5_C 0x40A0
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU4_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR0_C 0x40A0
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR1_C 0x40A0
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR2_C 0x40A4
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR3_C 0x40A4
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR4_C 0x40A4
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR5_C 0x40A4
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#define NOISE_SCAL_FCTR_9TAP_1X_TAU5_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR0_C 0x40A8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR1_C 0x40A8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR2_C 0x40A8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR3_C 0x40A8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR4_C 0x40AC
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR5_C 0x40AC
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU0_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR0_C 0x40AC
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR1_C 0x40AC
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR2_C 0x40B0
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR3_C 0x40B0
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR4_C 0x40B0
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR5_C 0x40B0
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU1_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR0_C 0x40B4
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR1_C 0x40B4
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR2_C 0x40B4
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR3_C 0x40B4
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR4_C 0x40B8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR5_C 0x40B8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU2_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR0_C 0x40B8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR1_C 0x40B8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR2_C 0x40BC
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR3_C 0x40BC
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR4_C 0x40BC
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR5_C 0x40BC
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU3_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR0_C 0x40C0
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR1_C 0x40C0
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR2_C 0x40C0
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR3_C 0x40C0
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR4_C 0x40C4
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR5_C 0x40C4
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU4_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR0_C 0x40C4
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR1_C 0x40C4
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR2_C 0x40C8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR3_C 0x40C8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR4_C 0x40C8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR5_C 0x40C8
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#define NOISE_SCAL_FCTR_9TAP_2X_TAU5_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR0_C 0x40CC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR1_C 0x40CC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR2_C 0x40CC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR3_C 0x40CC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR4_C 0x40D0
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR5_C 0x40D0
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU0_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR0_C 0x40D0
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR1_C 0x40D0
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR2_C 0x40D4
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR3_C 0x40D4
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR4_C 0x40D4
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR5_C 0x40D4
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU1_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR0_C 0x40D8
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR1_C 0x40D8
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR2_C 0x40D8
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR3_C 0x40D8
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR4_C 0x40DC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR5_C 0x40DC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU2_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR0_C 0x40DC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR1_C 0x40DC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR2_C 0x40E0
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR3_C 0x40E0
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR4_C 0x40E0
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR5_C 0x40E0
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU3_SNR5_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR0_C 0x40E4
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR0_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR1_C 0x40E4
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR1_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR2_C 0x40E4
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR2_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR3_C 0x40E4
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR3_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR4_C 0x40E8
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR4_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR5_C 0x40E8
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU4_SNR5_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR0_C 0x40E8
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR0_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR1_C 0x40E8
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR1_C_M 0xFF000000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR2_C 0x40EC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR2_C_M 0xFF
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR3_C 0x40EC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR3_C_M 0xFF00
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR4_C 0x40EC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR4_C_M 0xFF0000
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR5_C 0x40EC
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#define NOISE_SCAL_FCTR_9TAP_4X_TAU5_SNR5_C_M 0xFF000000
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#define NOISE_EST_COUNT_THR_C 0x40F0
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#define NOISE_EST_COUNT_THR_C_M 0x3F
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#define ZERO_HOLD_FOR_1X_EN_C 0x40F0
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#define ZERO_HOLD_FOR_1X_EN_C_M 0x40
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#define ZERO_HOLD_FOR_2X_EN_C 0x40F0
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#define ZERO_HOLD_FOR_2X_EN_C_M 0x80
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#define SMOOTH_COEFF_SEL_C 0x40F4
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#define SMOOTH_COEFF_SEL_C_M 0x3
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#define V_MATRIX_INTPL_EN_C 0x40F4
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#define V_MATRIX_INTPL_EN_C_M 0x4
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#define V_MATRIX_SMO_EN_C 0x40F4
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#define V_MATRIX_SMO_EN_C_M 0x8
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#define MUIC_EN_C 0x40F8
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#define MUIC_EN_C_M 0x1
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#define DEV1_TH_NG1_BW20_C 0x40FC
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#define DEV1_TH_NG1_BW20_C_M 0x3F
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#define DEV1_TH_NG1_BW40_C 0x40FC
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#define DEV1_TH_NG1_BW40_C_M 0xFC0
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#define DEV1_TH_NG1_BW80_C 0x40FC
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#define DEV1_TH_NG1_BW80_C_M 0x3F000
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#define DEV1_TH_NG2_BW20_C 0x40FC
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#define DEV1_TH_NG2_BW20_C_M 0xFC0000
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#define DEV1_TH_NG2_BW40_C 0x40FC
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#define DEV1_TH_NG2_BW40_C_M 0x3F000000
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#define NONCON160M_C 0x40FC
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#define NONCON160M_C_M 0x40000000
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#define AVGSNR_DIFF_EN_C 0x40FC
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#define AVGSNR_DIFF_EN_C_M 0x80000000
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#define DEV1_TH_NG2_BW80_C 0x4100
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#define DEV1_TH_NG2_BW80_C_M 0x3F
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#define DEV1_TH_NG4_BW20_C 0x4100
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#define DEV1_TH_NG4_BW20_C_M 0xFC0
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#define DEV1_TH_NG4_BW40_C 0x4100
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#define DEV1_TH_NG4_BW40_C_M 0x3F000
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#define DEV1_TH_NG4_BW80_C 0x4100
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#define DEV1_TH_NG4_BW80_C_M 0xFC0000
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#define DEV2_TH_NG1_BW20_C 0x4100
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#define DEV2_TH_NG1_BW20_C_M 0x3F000000
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#define BADTONE_COUNT_TH_SRC_GRPING_C 0x4100
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#define BADTONE_COUNT_TH_SRC_GRPING_C_M 0x40000000
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#define DEV2_TH_NG1_BW40_C 0x4104
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#define DEV2_TH_NG1_BW40_C_M 0x3F
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#define DEV2_TH_NG1_BW80_C 0x4104
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#define DEV2_TH_NG1_BW80_C_M 0xFC0
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#define DEV2_TH_NG2_BW20_C 0x4104
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#define DEV2_TH_NG2_BW20_C_M 0x3F000
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#define DEV2_TH_NG2_BW40_C 0x4104
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#define DEV2_TH_NG2_BW40_C_M 0xFC0000
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#define DEV2_TH_NG2_BW80_C 0x4104
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#define DEV2_TH_NG2_BW80_C_M 0x3F000000
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#define DEV2_TH_NG4_BW20_C 0x4108
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#define DEV2_TH_NG4_BW20_C_M 0x3F
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#define DEV2_TH_NG4_BW40_C 0x4108
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#define DEV2_TH_NG4_BW40_C_M 0xFC0
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#define DEV2_TH_NG4_BW80_C 0x4108
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#define DEV2_TH_NG4_BW80_C_M 0x3F000
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#define HE_DEV1_TH_NG16_BW20_C 0x4108
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#define HE_DEV1_TH_NG16_BW20_C_M 0xFC0000
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#define HE_DEV1_TH_NG16_BW40_C 0x4108
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#define HE_DEV1_TH_NG16_BW40_C_M 0x3F000000
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#define HE_DEV1_TH_NG16_BW80_C 0x410C
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#define HE_DEV1_TH_NG16_BW80_C_M 0x3F
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#define HE_DEV1_TH_NG4_BW20_C 0x410C
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#define HE_DEV1_TH_NG4_BW20_C_M 0xFC0
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#define HE_DEV1_TH_NG4_BW40_C 0x410C
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#define HE_DEV1_TH_NG4_BW40_C_M 0x3F000
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#define HE_DEV1_TH_NG4_BW80_C 0x410C
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#define HE_DEV1_TH_NG4_BW80_C_M 0xFC0000
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#define HE_DEV2_TH_NG16_BW20_C 0x410C
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#define HE_DEV2_TH_NG16_BW20_C_M 0x3F000000
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#define HE_DEV2_TH_NG16_BW40_C 0x4110
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#define HE_DEV2_TH_NG16_BW40_C_M 0x3F
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#define HE_DEV2_TH_NG16_BW80_C 0x4110
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#define HE_DEV2_TH_NG16_BW80_C_M 0xFC0
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#define HE_DEV2_TH_NG4_BW20_C 0x4110
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#define HE_DEV2_TH_NG4_BW20_C_M 0x3F000
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#define HE_DEV2_TH_NG4_BW40_C 0x4110
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#define HE_DEV2_TH_NG4_BW40_C_M 0xFC0000
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#define HE_DEV2_TH_NG4_BW80_C 0x4110
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#define HE_DEV2_TH_NG4_BW80_C_M 0x3F000000
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#define HE_SNR1_MIN_CNT_TH_NG16_BW20_C 0x4114
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#define HE_SNR1_MIN_CNT_TH_NG16_BW20_C_M 0x3F
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#define HE_SNR1_MIN_CNT_TH_NG16_BW40_C 0x4114
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#define HE_SNR1_MIN_CNT_TH_NG16_BW40_C_M 0xFC0
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#define HE_SNR1_MIN_CNT_TH_NG16_BW80_C 0x4114
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#define HE_SNR1_MIN_CNT_TH_NG16_BW80_C_M 0x3F000
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#define HE_SNR1_MIN_CNT_TH_NG4_BW20_C 0x4114
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#define HE_SNR1_MIN_CNT_TH_NG4_BW20_C_M 0xFC0000
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#define HE_SNR1_MIN_CNT_TH_NG4_BW40_C 0x4114
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#define HE_SNR1_MIN_CNT_TH_NG4_BW40_C_M 0x3F000000
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#define HE_SNR1_MIN_CNT_TH_NG4_BW80_C 0x4118
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#define HE_SNR1_MIN_CNT_TH_NG4_BW80_C_M 0x3F
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#define HE_SNR2_MIN_CNT_TH_NG16_BW20_C 0x4118
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#define HE_SNR2_MIN_CNT_TH_NG16_BW20_C_M 0xFC0
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#define HE_SNR2_MIN_CNT_TH_NG16_BW40_C 0x4118
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#define HE_SNR2_MIN_CNT_TH_NG16_BW40_C_M 0x3F000
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#define HE_SNR2_MIN_CNT_TH_NG16_BW80_C 0x4118
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#define HE_SNR2_MIN_CNT_TH_NG16_BW80_C_M 0xFC0000
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#define HE_SNR2_MIN_CNT_TH_NG4_BW20_C 0x4118
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#define HE_SNR2_MIN_CNT_TH_NG4_BW20_C_M 0x3F000000
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#define HE_SNR2_MIN_CNT_TH_NG4_BW40_C 0x411C
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#define HE_SNR2_MIN_CNT_TH_NG4_BW40_C_M 0x3F
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#define HE_SNR2_MIN_CNT_TH_NG4_BW80_C 0x411C
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#define HE_SNR2_MIN_CNT_TH_NG4_BW80_C_M 0xFC0
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#define SNR1_MIN_CNT_TH_NG1_BW20_C 0x411C
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#define SNR1_MIN_CNT_TH_NG1_BW20_C_M 0x3F000
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#define SNR1_MIN_CNT_TH_NG1_BW40_C 0x411C
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#define SNR1_MIN_CNT_TH_NG1_BW40_C_M 0xFC0000
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#define SNR1_MIN_CNT_TH_NG1_BW80_C 0x411C
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#define SNR1_MIN_CNT_TH_NG1_BW80_C_M 0x3F000000
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#define SNR1_MIN_CNT_TH_NG2_BW20_C 0x4120
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#define SNR1_MIN_CNT_TH_NG2_BW20_C_M 0x3F
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#define SNR1_MIN_CNT_TH_NG2_BW40_C 0x4120
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#define SNR1_MIN_CNT_TH_NG2_BW40_C_M 0xFC0
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#define SNR1_MIN_CNT_TH_NG2_BW80_C 0x4120
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#define SNR1_MIN_CNT_TH_NG2_BW80_C_M 0x3F000
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#define SNR1_MIN_CNT_TH_NG4_BW20_C 0x4120
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#define SNR1_MIN_CNT_TH_NG4_BW20_C_M 0xFC0000
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#define SNR1_MIN_CNT_TH_NG4_BW40_C 0x4120
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#define SNR1_MIN_CNT_TH_NG4_BW40_C_M 0x3F000000
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#define SNR1_MIN_CNT_TH_NG4_BW80_C 0x4124
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#define SNR1_MIN_CNT_TH_NG4_BW80_C_M 0x3F
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#define SNR2_MIN_CNT_TH_NG1_BW20_C 0x4124
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#define SNR2_MIN_CNT_TH_NG1_BW20_C_M 0xFC0
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#define SNR2_MIN_CNT_TH_NG1_BW40_C 0x4124
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#define SNR2_MIN_CNT_TH_NG1_BW40_C_M 0x3F000
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#define SNR2_MIN_CNT_TH_NG1_BW80_C 0x4124
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#define SNR2_MIN_CNT_TH_NG1_BW80_C_M 0xFC0000
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#define SNR2_MIN_CNT_TH_NG2_BW20_C 0x4124
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#define SNR2_MIN_CNT_TH_NG2_BW20_C_M 0x3F000000
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#define SNR2_MIN_CNT_TH_NG2_BW40_C 0x4128
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#define SNR2_MIN_CNT_TH_NG2_BW40_C_M 0x3F
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#define SNR2_MIN_CNT_TH_NG2_BW80_C 0x4128
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#define SNR2_MIN_CNT_TH_NG2_BW80_C_M 0xFC0
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#define SNR2_MIN_CNT_TH_NG4_BW20_C 0x4128
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#define SNR2_MIN_CNT_TH_NG4_BW20_C_M 0x3F000
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#define SNR2_MIN_CNT_TH_NG4_BW40_C 0x4128
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#define SNR2_MIN_CNT_TH_NG4_BW40_C_M 0xFC0000
|
#define SNR2_MIN_CNT_TH_NG4_BW80_C 0x4128
|
#define SNR2_MIN_CNT_TH_NG4_BW80_C_M 0x3F000000
|
#define SNRLOSS_WGT_C 0x412C
|
#define SNRLOSS_WGT_C_M 0x1F
|
#define HE_SNR1_TH_NG16_BW20_C 0x412C
|
#define HE_SNR1_TH_NG16_BW20_C_M 0x1E0
|
#define HE_SNR1_TH_NG16_BW40_C 0x412C
|
#define HE_SNR1_TH_NG16_BW40_C_M 0x1E00
|
#define HE_SNR1_TH_NG16_BW80_C 0x412C
|
#define HE_SNR1_TH_NG16_BW80_C_M 0x1E000
|
#define HE_SNR1_TH_NG4_BW20_C 0x412C
|
#define HE_SNR1_TH_NG4_BW20_C_M 0x1E0000
|
#define HE_SNR1_TH_NG4_BW40_C 0x412C
|
#define HE_SNR1_TH_NG4_BW40_C_M 0x1E00000
|
#define HE_SNR1_TH_NG4_BW80_C 0x412C
|
#define HE_SNR1_TH_NG4_BW80_C_M 0x1E000000
|
#define HE_SNR2_TH_NG16_BW20_C 0x4130
|
#define HE_SNR2_TH_NG16_BW20_C_M 0xF
|
#define HE_SNR2_TH_NG16_BW40_C 0x4130
|
#define HE_SNR2_TH_NG16_BW40_C_M 0xF0
|
#define HE_SNR2_TH_NG16_BW80_C 0x4130
|
#define HE_SNR2_TH_NG16_BW80_C_M 0xF00
|
#define HE_SNR2_TH_NG4_BW20_C 0x4130
|
#define HE_SNR2_TH_NG4_BW20_C_M 0xF000
|
#define HE_SNR2_TH_NG4_BW40_C 0x4130
|
#define HE_SNR2_TH_NG4_BW40_C_M 0xF0000
|
#define HE_SNR2_TH_NG4_BW80_C 0x4130
|
#define HE_SNR2_TH_NG4_BW80_C_M 0xF00000
|
#define SNR1_TH_NG1_BW20_C 0x4130
|
#define SNR1_TH_NG1_BW20_C_M 0xF000000
|
#define SNR1_TH_NG1_BW40_C 0x4130
|
#define SNR1_TH_NG1_BW40_C_M 0xF0000000
|
#define SNR1_TH_NG1_BW80_C 0x4134
|
#define SNR1_TH_NG1_BW80_C_M 0xF
|
#define SNR1_TH_NG2_BW20_C 0x4134
|
#define SNR1_TH_NG2_BW20_C_M 0xF0
|
#define SNR1_TH_NG2_BW40_C 0x4134
|
#define SNR1_TH_NG2_BW40_C_M 0xF00
|
#define SNR1_TH_NG2_BW80_C 0x4134
|
#define SNR1_TH_NG2_BW80_C_M 0xF000
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#define SNR1_TH_NG4_BW20_C 0x4134
|
#define SNR1_TH_NG4_BW20_C_M 0xF0000
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#define SNR1_TH_NG4_BW40_C 0x4134
|
#define SNR1_TH_NG4_BW40_C_M 0xF00000
|
#define SNR1_TH_NG4_BW80_C 0x4134
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#define SNR1_TH_NG4_BW80_C_M 0xF000000
|
#define SNR2_TH_NG1_BW20_C 0x4134
|
#define SNR2_TH_NG1_BW20_C_M 0xF0000000
|
#define SNR2_TH_NG1_BW40_C 0x4138
|
#define SNR2_TH_NG1_BW40_C_M 0xF
|
#define SNR2_TH_NG1_BW80_C 0x4138
|
#define SNR2_TH_NG1_BW80_C_M 0xF0
|
#define SNR2_TH_NG2_BW20_C 0x4138
|
#define SNR2_TH_NG2_BW20_C_M 0xF00
|
#define SNR2_TH_NG2_BW40_C 0x4138
|
#define SNR2_TH_NG2_BW40_C_M 0xF000
|
#define SNR2_TH_NG2_BW80_C 0x4138
|
#define SNR2_TH_NG2_BW80_C_M 0xF0000
|
#define SNR2_TH_NG4_BW20_C 0x4138
|
#define SNR2_TH_NG4_BW20_C_M 0xF00000
|
#define SNR2_TH_NG4_BW40_C 0x4138
|
#define SNR2_TH_NG4_BW40_C_M 0xF000000
|
#define SNR2_TH_NG4_BW80_C 0x4138
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#define SNR2_TH_NG4_BW80_C_M 0xF0000000
|
#define AVGSNR_DIFF_TH_C 0x413C
|
#define AVGSNR_DIFF_TH_C_M 0xF
|
#define OTHERSNR_WGT_C 0x413C
|
#define OTHERSNR_WGT_C_M 0xF0
|
#define PDP_AWGN_FLAG_SUB_TUNE_C 0x4140
|
#define PDP_AWGN_FLAG_SUB_TUNE_C_M 0x3FF
|
#define PDP_SNR_SHIFT_FOR_NONLEGACY_C 0x4140
|
#define PDP_SNR_SHIFT_FOR_NONLEGACY_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W0_C 0x4140
|
#define PDP_CORR_DIST1_W0_C_M 0x3FF00000
|
#define GI_COMB_EN_C 0x4140
|
#define GI_COMB_EN_C_M 0x40000000
|
#define PDP_ALL_COMBINE_EN_C 0x4140
|
#define PDP_ALL_COMBINE_EN_C_M 0x80000000
|
#define PDP_CORR_DIST1_W1_C 0x4144
|
#define PDP_CORR_DIST1_W1_C_M 0x3FF
|
#define PDP_CORR_DIST1_W10_C 0x4144
|
#define PDP_CORR_DIST1_W10_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W11_C 0x4144
|
#define PDP_CORR_DIST1_W11_C_M 0x3FF00000
|
#define MANUAL_GD_PHASE_EN_C 0x4144
|
#define MANUAL_GD_PHASE_EN_C_M 0x40000000
|
#define MANUAL_SNR_IDX_EN_C 0x4144
|
#define MANUAL_SNR_IDX_EN_C_M 0x80000000
|
#define PDP_CORR_DIST1_W12_C 0x4148
|
#define PDP_CORR_DIST1_W12_C_M 0x3FF
|
#define PDP_CORR_DIST1_W13_C 0x4148
|
#define PDP_CORR_DIST1_W13_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W14_C 0x4148
|
#define PDP_CORR_DIST1_W14_C_M 0x3FF00000
|
#define MANUAL_TMAX_IDX_EN_C 0x4148
|
#define MANUAL_TMAX_IDX_EN_C_M 0x40000000
|
#define PDP_CORR_DIST1_W15_C 0x414C
|
#define PDP_CORR_DIST1_W15_C_M 0x3FF
|
#define PDP_CORR_DIST1_W16_C 0x414C
|
#define PDP_CORR_DIST1_W16_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W17_C 0x414C
|
#define PDP_CORR_DIST1_W17_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W18_C 0x4150
|
#define PDP_CORR_DIST1_W18_C_M 0x3FF
|
#define PDP_CORR_DIST1_W19_C 0x4150
|
#define PDP_CORR_DIST1_W19_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W2_C 0x4150
|
#define PDP_CORR_DIST1_W2_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W20_C 0x4154
|
#define PDP_CORR_DIST1_W20_C_M 0x3FF
|
#define PDP_CORR_DIST1_W21_C 0x4154
|
#define PDP_CORR_DIST1_W21_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W22_C 0x4154
|
#define PDP_CORR_DIST1_W22_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W23_C 0x4158
|
#define PDP_CORR_DIST1_W23_C_M 0x3FF
|
#define PDP_CORR_DIST1_W24_C 0x4158
|
#define PDP_CORR_DIST1_W24_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W25_C 0x4158
|
#define PDP_CORR_DIST1_W25_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W26_C 0x415C
|
#define PDP_CORR_DIST1_W26_C_M 0x3FF
|
#define PDP_CORR_DIST1_W27_C 0x415C
|
#define PDP_CORR_DIST1_W27_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W28_C 0x415C
|
#define PDP_CORR_DIST1_W28_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W29_C 0x4160
|
#define PDP_CORR_DIST1_W29_C_M 0x3FF
|
#define PDP_CORR_DIST1_W3_C 0x4160
|
#define PDP_CORR_DIST1_W3_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W30_C 0x4160
|
#define PDP_CORR_DIST1_W30_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W31_C 0x4164
|
#define PDP_CORR_DIST1_W31_C_M 0x3FF
|
#define PDP_CORR_DIST1_W32_C 0x4164
|
#define PDP_CORR_DIST1_W32_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W33_C 0x4164
|
#define PDP_CORR_DIST1_W33_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W34_C 0x4168
|
#define PDP_CORR_DIST1_W34_C_M 0x3FF
|
#define PDP_CORR_DIST1_W35_C 0x4168
|
#define PDP_CORR_DIST1_W35_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W36_C 0x4168
|
#define PDP_CORR_DIST1_W36_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W37_C 0x416C
|
#define PDP_CORR_DIST1_W37_C_M 0x3FF
|
#define PDP_CORR_DIST1_W38_C 0x416C
|
#define PDP_CORR_DIST1_W38_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W39_C 0x416C
|
#define PDP_CORR_DIST1_W39_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W4_C 0x4170
|
#define PDP_CORR_DIST1_W4_C_M 0x3FF
|
#define PDP_CORR_DIST1_W40_C 0x4170
|
#define PDP_CORR_DIST1_W40_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W41_C 0x4170
|
#define PDP_CORR_DIST1_W41_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W42_C 0x4174
|
#define PDP_CORR_DIST1_W42_C_M 0x3FF
|
#define PDP_CORR_DIST1_W43_C 0x4174
|
#define PDP_CORR_DIST1_W43_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W44_C 0x4174
|
#define PDP_CORR_DIST1_W44_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W45_C 0x4178
|
#define PDP_CORR_DIST1_W45_C_M 0x3FF
|
#define PDP_CORR_DIST1_W46_C 0x4178
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#define PDP_CORR_DIST1_W46_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W47_C 0x4178
|
#define PDP_CORR_DIST1_W47_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W5_C 0x417C
|
#define PDP_CORR_DIST1_W5_C_M 0x3FF
|
#define PDP_CORR_DIST1_W6_C 0x417C
|
#define PDP_CORR_DIST1_W6_C_M 0xFFC00
|
#define PDP_CORR_DIST1_W7_C 0x417C
|
#define PDP_CORR_DIST1_W7_C_M 0x3FF00000
|
#define PDP_CORR_DIST1_W8_C 0x4180
|
#define PDP_CORR_DIST1_W8_C_M 0x3FF
|
#define PDP_CORR_DIST1_W9_C 0x4180
|
#define PDP_CORR_DIST1_W9_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W0_C 0x4180
|
#define PDP_CORR_DIST2_W0_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W1_C 0x4184
|
#define PDP_CORR_DIST2_W1_C_M 0x3FF
|
#define PDP_CORR_DIST2_W10_C 0x4184
|
#define PDP_CORR_DIST2_W10_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W11_C 0x4184
|
#define PDP_CORR_DIST2_W11_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W12_C 0x4188
|
#define PDP_CORR_DIST2_W12_C_M 0x3FF
|
#define PDP_CORR_DIST2_W13_C 0x4188
|
#define PDP_CORR_DIST2_W13_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W14_C 0x4188
|
#define PDP_CORR_DIST2_W14_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W15_C 0x418C
|
#define PDP_CORR_DIST2_W15_C_M 0x3FF
|
#define PDP_CORR_DIST2_W16_C 0x418C
|
#define PDP_CORR_DIST2_W16_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W17_C 0x418C
|
#define PDP_CORR_DIST2_W17_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W18_C 0x4190
|
#define PDP_CORR_DIST2_W18_C_M 0x3FF
|
#define PDP_CORR_DIST2_W19_C 0x4190
|
#define PDP_CORR_DIST2_W19_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W2_C 0x4190
|
#define PDP_CORR_DIST2_W2_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W20_C 0x4194
|
#define PDP_CORR_DIST2_W20_C_M 0x3FF
|
#define PDP_CORR_DIST2_W21_C 0x4194
|
#define PDP_CORR_DIST2_W21_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W22_C 0x4194
|
#define PDP_CORR_DIST2_W22_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W23_C 0x4198
|
#define PDP_CORR_DIST2_W23_C_M 0x3FF
|
#define PDP_CORR_DIST2_W24_C 0x4198
|
#define PDP_CORR_DIST2_W24_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W25_C 0x4198
|
#define PDP_CORR_DIST2_W25_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W26_C 0x419C
|
#define PDP_CORR_DIST2_W26_C_M 0x3FF
|
#define PDP_CORR_DIST2_W27_C 0x419C
|
#define PDP_CORR_DIST2_W27_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W28_C 0x419C
|
#define PDP_CORR_DIST2_W28_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W29_C 0x41A0
|
#define PDP_CORR_DIST2_W29_C_M 0x3FF
|
#define PDP_CORR_DIST2_W3_C 0x41A0
|
#define PDP_CORR_DIST2_W3_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W30_C 0x41A0
|
#define PDP_CORR_DIST2_W30_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W31_C 0x41A4
|
#define PDP_CORR_DIST2_W31_C_M 0x3FF
|
#define PDP_CORR_DIST2_W32_C 0x41A4
|
#define PDP_CORR_DIST2_W32_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W33_C 0x41A4
|
#define PDP_CORR_DIST2_W33_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W34_C 0x41A8
|
#define PDP_CORR_DIST2_W34_C_M 0x3FF
|
#define PDP_CORR_DIST2_W35_C 0x41A8
|
#define PDP_CORR_DIST2_W35_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W36_C 0x41A8
|
#define PDP_CORR_DIST2_W36_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W37_C 0x41AC
|
#define PDP_CORR_DIST2_W37_C_M 0x3FF
|
#define PDP_CORR_DIST2_W38_C 0x41AC
|
#define PDP_CORR_DIST2_W38_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W39_C 0x41AC
|
#define PDP_CORR_DIST2_W39_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W4_C 0x41B0
|
#define PDP_CORR_DIST2_W4_C_M 0x3FF
|
#define PDP_CORR_DIST2_W40_C 0x41B0
|
#define PDP_CORR_DIST2_W40_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W41_C 0x41B0
|
#define PDP_CORR_DIST2_W41_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W42_C 0x41B4
|
#define PDP_CORR_DIST2_W42_C_M 0x3FF
|
#define PDP_CORR_DIST2_W43_C 0x41B4
|
#define PDP_CORR_DIST2_W43_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W44_C 0x41B4
|
#define PDP_CORR_DIST2_W44_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W45_C 0x41B8
|
#define PDP_CORR_DIST2_W45_C_M 0x3FF
|
#define PDP_CORR_DIST2_W46_C 0x41B8
|
#define PDP_CORR_DIST2_W46_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W47_C 0x41B8
|
#define PDP_CORR_DIST2_W47_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W5_C 0x41BC
|
#define PDP_CORR_DIST2_W5_C_M 0x3FF
|
#define PDP_CORR_DIST2_W6_C 0x41BC
|
#define PDP_CORR_DIST2_W6_C_M 0xFFC00
|
#define PDP_CORR_DIST2_W7_C 0x41BC
|
#define PDP_CORR_DIST2_W7_C_M 0x3FF00000
|
#define PDP_CORR_DIST2_W8_C 0x41C0
|
#define PDP_CORR_DIST2_W8_C_M 0x3FF
|
#define PDP_CORR_DIST2_W9_C 0x41C0
|
#define PDP_CORR_DIST2_W9_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W0_C 0x41C0
|
#define PDP_CORR_DIST3_W0_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W1_C 0x41C4
|
#define PDP_CORR_DIST3_W1_C_M 0x3FF
|
#define PDP_CORR_DIST3_W10_C 0x41C4
|
#define PDP_CORR_DIST3_W10_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W11_C 0x41C4
|
#define PDP_CORR_DIST3_W11_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W12_C 0x41C8
|
#define PDP_CORR_DIST3_W12_C_M 0x3FF
|
#define PDP_CORR_DIST3_W13_C 0x41C8
|
#define PDP_CORR_DIST3_W13_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W14_C 0x41C8
|
#define PDP_CORR_DIST3_W14_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W15_C 0x41CC
|
#define PDP_CORR_DIST3_W15_C_M 0x3FF
|
#define PDP_CORR_DIST3_W16_C 0x41CC
|
#define PDP_CORR_DIST3_W16_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W17_C 0x41CC
|
#define PDP_CORR_DIST3_W17_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W18_C 0x41D0
|
#define PDP_CORR_DIST3_W18_C_M 0x3FF
|
#define PDP_CORR_DIST3_W19_C 0x41D0
|
#define PDP_CORR_DIST3_W19_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W2_C 0x41D0
|
#define PDP_CORR_DIST3_W2_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W20_C 0x41D4
|
#define PDP_CORR_DIST3_W20_C_M 0x3FF
|
#define PDP_CORR_DIST3_W21_C 0x41D4
|
#define PDP_CORR_DIST3_W21_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W22_C 0x41D4
|
#define PDP_CORR_DIST3_W22_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W23_C 0x41D8
|
#define PDP_CORR_DIST3_W23_C_M 0x3FF
|
#define PDP_CORR_DIST3_W24_C 0x41D8
|
#define PDP_CORR_DIST3_W24_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W25_C 0x41D8
|
#define PDP_CORR_DIST3_W25_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W26_C 0x41DC
|
#define PDP_CORR_DIST3_W26_C_M 0x3FF
|
#define PDP_CORR_DIST3_W27_C 0x41DC
|
#define PDP_CORR_DIST3_W27_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W28_C 0x41DC
|
#define PDP_CORR_DIST3_W28_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W29_C 0x41E0
|
#define PDP_CORR_DIST3_W29_C_M 0x3FF
|
#define PDP_CORR_DIST3_W3_C 0x41E0
|
#define PDP_CORR_DIST3_W3_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W30_C 0x41E0
|
#define PDP_CORR_DIST3_W30_C_M 0x3FF00000
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#define PDP_CORR_DIST3_W31_C 0x41E4
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#define PDP_CORR_DIST3_W31_C_M 0x3FF
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#define PDP_CORR_DIST3_W32_C 0x41E4
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#define PDP_CORR_DIST3_W32_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W33_C 0x41E4
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#define PDP_CORR_DIST3_W33_C_M 0x3FF00000
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#define PDP_CORR_DIST3_W34_C 0x41E8
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#define PDP_CORR_DIST3_W34_C_M 0x3FF
|
#define PDP_CORR_DIST3_W35_C 0x41E8
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#define PDP_CORR_DIST3_W35_C_M 0xFFC00
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#define PDP_CORR_DIST3_W36_C 0x41E8
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#define PDP_CORR_DIST3_W36_C_M 0x3FF00000
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#define PDP_CORR_DIST3_W37_C 0x41EC
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#define PDP_CORR_DIST3_W37_C_M 0x3FF
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#define PDP_CORR_DIST3_W38_C 0x41EC
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#define PDP_CORR_DIST3_W38_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W39_C 0x41EC
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#define PDP_CORR_DIST3_W39_C_M 0x3FF00000
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#define PDP_CORR_DIST3_W4_C 0x41F0
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#define PDP_CORR_DIST3_W4_C_M 0x3FF
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#define PDP_CORR_DIST3_W40_C 0x41F0
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#define PDP_CORR_DIST3_W40_C_M 0xFFC00
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#define PDP_CORR_DIST3_W41_C 0x41F0
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#define PDP_CORR_DIST3_W41_C_M 0x3FF00000
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#define PDP_CORR_DIST3_W42_C 0x41F4
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#define PDP_CORR_DIST3_W42_C_M 0x3FF
|
#define PDP_CORR_DIST3_W43_C 0x41F4
|
#define PDP_CORR_DIST3_W43_C_M 0xFFC00
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#define PDP_CORR_DIST3_W44_C 0x41F4
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#define PDP_CORR_DIST3_W44_C_M 0x3FF00000
|
#define PDP_CORR_DIST3_W45_C 0x41F8
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#define PDP_CORR_DIST3_W45_C_M 0x3FF
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#define PDP_CORR_DIST3_W46_C 0x41F8
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#define PDP_CORR_DIST3_W46_C_M 0xFFC00
|
#define PDP_CORR_DIST3_W47_C 0x41F8
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#define PDP_CORR_DIST3_W47_C_M 0x3FF00000
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#define PDP_CORR_DIST3_W5_C 0x41FC
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#define PDP_CORR_DIST3_W5_C_M 0x3FF
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#define PDP_CORR_DIST3_W6_C 0x41FC
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#define PDP_CORR_DIST3_W6_C_M 0xFFC00
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#define PDP_CORR_DIST3_W7_C 0x41FC
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#define PDP_CORR_DIST3_W7_C_M 0x3FF00000
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#define PDP_CORR_DIST3_W8_C 0x4200
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#define PDP_CORR_DIST3_W8_C_M 0x3FF
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#define PDP_CORR_DIST3_W9_C 0x4200
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#define PDP_CORR_DIST3_W9_C_M 0xFFC00
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#define GD_PHASE_LEG_R0S0_C 0x4200
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#define GD_PHASE_LEG_R0S0_C_M 0xFF00000
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#define TMAX_IDX_LEG_R0_C 0x4200
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#define TMAX_IDX_LEG_R0_C_M 0xF0000000
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#define GD_PHASE_LEG_R0S1_C 0x4204
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#define GD_PHASE_LEG_R0S1_C_M 0xFF
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#define GD_PHASE_LEG_R0S2_C 0x4204
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#define GD_PHASE_LEG_R0S2_C_M 0xFF00
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#define GD_PHASE_LEG_R0S3_C 0x4204
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#define GD_PHASE_LEG_R0S3_C_M 0xFF0000
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#define GD_PHASE_LEG_R1S0_C 0x4204
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#define GD_PHASE_LEG_R1S0_C_M 0xFF000000
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#define GD_PHASE_LEG_R1S1_C 0x4208
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#define GD_PHASE_LEG_R1S1_C_M 0xFF
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#define GD_PHASE_LEG_R1S2_C 0x4208
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#define GD_PHASE_LEG_R1S2_C_M 0xFF00
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#define GD_PHASE_LEG_R1S3_C 0x4208
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#define GD_PHASE_LEG_R1S3_C_M 0xFF0000
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#define GD_PHASE_NON_LEG_R0S0_C 0x4208
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#define GD_PHASE_NON_LEG_R0S0_C_M 0xFF000000
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#define GD_PHASE_NON_LEG_R0S1_C 0x420C
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#define GD_PHASE_NON_LEG_R0S1_C_M 0xFF
|
#define GD_PHASE_NON_LEG_R1S0_C 0x420C
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#define GD_PHASE_NON_LEG_R1S0_C_M 0xFF00
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#define GD_PHASE_NON_LEG_R1S1_C 0x420C
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#define GD_PHASE_NON_LEG_R1S1_C_M 0xFF0000
|
#define GI_FCTR_LEGACY_0_C 0x420C
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#define GI_FCTR_LEGACY_0_C_M 0x7F000000
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#define GI_FCTR_LEGACY_1_C 0x4210
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#define GI_FCTR_LEGACY_1_C_M 0x7F
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#define GI_FCTR_LEGACY_2_C 0x4210
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#define GI_FCTR_LEGACY_2_C_M 0x3F80
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#define GI_FCTR_LEGACY_3_C 0x4210
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#define GI_FCTR_LEGACY_3_C_M 0x1FC000
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#define GI_FCTR_LEGACY_4_C 0x4210
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#define GI_FCTR_LEGACY_4_C_M 0xFE00000
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#define TMAX_IDX_LEG_R1_C 0x4210
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#define TMAX_IDX_LEG_R1_C_M 0xF0000000
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#define GI_FCTR_LEGACY_5_C 0x4214
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#define GI_FCTR_LEGACY_5_C_M 0x7F
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#define GI_FCTR_NONLEGACY_0_C 0x4214
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#define GI_FCTR_NONLEGACY_0_C_M 0x3F80
|
#define GI_FCTR_NONLEGACY_1_C 0x4214
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#define GI_FCTR_NONLEGACY_1_C_M 0x1FC000
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#define GI_FCTR_NONLEGACY_2_C 0x4214
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#define GI_FCTR_NONLEGACY_2_C_M 0xFE00000
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#define TMAX_IDX_NON_LEG_R0_C 0x4214
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#define TMAX_IDX_NON_LEG_R0_C_M 0xF0000000
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#define GI_FCTR_NONLEGACY_3_C 0x4218
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#define GI_FCTR_NONLEGACY_3_C_M 0x7F
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#define GI_FCTR_NONLEGACY_4_C 0x4218
|
#define GI_FCTR_NONLEGACY_4_C_M 0x3F80
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#define GI_FCTR_NONLEGACY_5_C 0x4218
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#define GI_FCTR_NONLEGACY_5_C_M 0x1FC000
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#define SNR_LVL_0_C 0x4218
|
#define SNR_LVL_0_C_M 0x7E00000
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#define HE_NUM_BAND_EDGE_TONE_C 0x4218
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#define HE_NUM_BAND_EDGE_TONE_C_M 0xF8000000
|
#define SNR_LVL_1_C 0x421C
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#define SNR_LVL_1_C_M 0x3F
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#define SNR_LVL_2_C 0x421C
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#define SNR_LVL_2_C_M 0xFC0
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#define SNR_LVL_3_C 0x421C
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#define SNR_LVL_3_C_M 0x3F000
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#define SNR_LVL_4_C 0x421C
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#define SNR_LVL_4_C_M 0xFC0000
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#define SNR_LVL_5_C 0x421C
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#define SNR_LVL_5_C_M 0x3F000000
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#define SNR_SMO_THR_C 0x4220
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#define SNR_SMO_THR_C_M 0x3F
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#define SNR_SMO_THR_1XLTF_C 0x4220
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#define SNR_SMO_THR_1XLTF_C_M 0xFC0
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#define SNR_SMO_THR_2XLTF_C 0x4220
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#define SNR_SMO_THR_2XLTF_C_M 0x3F000
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#define PDP_INSIDE_PHASE_ROTATE_C 0x4220
|
#define PDP_INSIDE_PHASE_ROTATE_C_M 0x7C0000
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#define PDP_WGT_DIST_1X_C 0x4220
|
#define PDP_WGT_DIST_1X_C_M 0xF800000
|
#define TMAX_IDX_NON_LEG_R0S0_C 0x4220
|
#define TMAX_IDX_NON_LEG_R0S0_C_M 0xF0000000
|
#define PDP_WGT_DIST_2X_C 0x4224
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#define PDP_WGT_DIST_2X_C_M 0x1F
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#define PDP_WGT_DIST_3X_C 0x4224
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#define PDP_WGT_DIST_3X_C_M 0x3E0
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#define TMAX_IDX_NON_LEG_R0S1_C 0x4224
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#define TMAX_IDX_NON_LEG_R0S1_C_M 0x3C00
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#define TMAX_IDX_NON_LEG_R1S0_C 0x4224
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#define TMAX_IDX_NON_LEG_R1S0_C_M 0x3C000
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#define TMAX_IDX_NON_LEG_R1S1_C 0x4224
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#define TMAX_IDX_NON_LEG_R1S1_C_M 0x3C0000
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#define SNR_IDX_LEG_R0_C 0x4224
|
#define SNR_IDX_LEG_R0_C_M 0x1C00000
|
#define SNR_IDX_LEG_R1_C 0x4224
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#define SNR_IDX_LEG_R1_C_M 0xE000000
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#define SNR_IDX_NON_LEG_R0S0_C 0x4224
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#define SNR_IDX_NON_LEG_R0S0_C_M 0x70000000
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#define SNR_IDX_NON_LEG_R0S1_C 0x4228
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#define SNR_IDX_NON_LEG_R0S1_C_M 0x7
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#define SNR_IDX_NON_LEG_R1S0_C 0x4228
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#define SNR_IDX_NON_LEG_R1S0_C_M 0x38
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#define SNR_IDX_NON_LEG_R1S1_C 0x4228
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#define SNR_IDX_NON_LEG_R1S1_C_M 0x1C0
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#define NUM_BAND_EDGE_TONE_C 0x4228
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#define NUM_BAND_EDGE_TONE_C_M 0xE00
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#define PHYSTS_PDP_HE_AND_GI_TYPE_0_C 0x4228
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#define PHYSTS_PDP_HE_AND_GI_TYPE_0_C_M 0x7000
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#define PHYSTS_PDP_HE_AND_GI_TYPE_1_C 0x4228
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#define PHYSTS_PDP_HE_AND_GI_TYPE_1_C_M 0x38000
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#define PHYSTS_PDP_HE_AND_GI_TYPE_2_C 0x4228
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#define PHYSTS_PDP_HE_AND_GI_TYPE_2_C_M 0x1C0000
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#define PHYSTS_PDP_HE_AND_GI_TYPE_3_C 0x4228
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#define PHYSTS_PDP_HE_AND_GI_TYPE_3_C_M 0xE00000
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#define PHYSTS_PDP_HE_AND_GI_TYPE_4_C 0x4228
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#define PHYSTS_PDP_HE_AND_GI_TYPE_4_C_M 0x7000000
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#define PSD_FFT_IDX_C 0x422C
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#define PSD_FFT_IDX_C_M 0x7FF
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#define PSD_IQ_SEL_C 0x422C
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#define PSD_IQ_SEL_C_M 0x1800
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#define PSD_L_AVG_C 0x422C
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#define PSD_L_AVG_C_M 0x6000
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#define PSD_N_DFT_C 0x422C
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#define PSD_N_DFT_C_M 0x18000
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#define PSD_IN_PATH_SEL_C 0x422C
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#define PSD_IN_PATH_SEL_C_M 0x60000
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#define PSD_IN_SOURCE_SEL_C 0x422C
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#define PSD_IN_SOURCE_SEL_C_M 0x180000
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#define PSD_START_C 0x422C
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#define PSD_START_C_M 0x200000
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#define PSD_ENABLE_C 0x422C
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#define PSD_ENABLE_C_M 0x400000
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#define K_SEL_1024QAM_SNR_TH1_C 0x4230
|
#define K_SEL_1024QAM_SNR_TH1_C_M 0x3F
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#define K_SEL_1024QAM_SNR_TH2_C 0x4230
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#define K_SEL_1024QAM_SNR_TH2_C_M 0xFC0
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#define K_SEL_1024QAM_SNR_TH3_C 0x4230
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#define K_SEL_1024QAM_SNR_TH3_C_M 0x3F000
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#define K_SEL_1024QAM_SNR_TH4_C 0x4230
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#define K_SEL_1024QAM_SNR_TH4_C_M 0xFC0000
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#define K_SEL_1024QAM_SNR_TH5_C 0x4230
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#define K_SEL_1024QAM_SNR_TH5_C_M 0x3F000000
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#define K_SEL_EN_C 0x4230
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#define K_SEL_EN_C_M 0x40000000
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#define K_SEL_USE_CONDNUM_EN_C 0x4230
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#define K_SEL_USE_CONDNUM_EN_C_M 0x80000000
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#define K_SEL_16QAM_SNR_TH1_C 0x4234
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#define K_SEL_16QAM_SNR_TH1_C_M 0x3F
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#define K_SEL_16QAM_SNR_TH2_C 0x4234
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#define K_SEL_16QAM_SNR_TH2_C_M 0xFC0
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#define K_SEL_16QAM_SNR_TH3_C 0x4234
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#define K_SEL_16QAM_SNR_TH3_C_M 0x3F000
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#define K_SEL_256QAM_SNR_TH1_C 0x4234
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#define K_SEL_256QAM_SNR_TH1_C_M 0xFC0000
|
#define K_SEL_256QAM_SNR_TH2_C 0x4234
|
#define K_SEL_256QAM_SNR_TH2_C_M 0x3F000000
|
#define MANUAL_SET_K_FCTR_C 0x4234
|
#define MANUAL_SET_K_FCTR_C_M 0x40000000
|
#define K_SEL_256QAM_SNR_TH3_C 0x4238
|
#define K_SEL_256QAM_SNR_TH3_C_M 0x3F
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#define K_SEL_256QAM_SNR_TH4_C 0x4238
|
#define K_SEL_256QAM_SNR_TH4_C_M 0xFC0
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#define K_SEL_256QAM_SNR_TH5_C 0x4238
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#define K_SEL_256QAM_SNR_TH5_C_M 0x3F000
|
#define K_SEL_64QAM_SNR_TH1_C 0x4238
|
#define K_SEL_64QAM_SNR_TH1_C_M 0xFC0000
|
#define K_SEL_64QAM_SNR_TH2_C 0x4238
|
#define K_SEL_64QAM_SNR_TH2_C_M 0x3F000000
|
#define K_SEL_64QAM_SNR_TH3_C 0x423C
|
#define K_SEL_64QAM_SNR_TH3_C_M 0x3F
|
#define K_SEL_64QAM_SNR_TH4_C 0x423C
|
#define K_SEL_64QAM_SNR_TH4_C_M 0xFC0
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#define K_SEL_64QAM_SNR_TH5_C 0x423C
|
#define K_SEL_64QAM_SNR_TH5_C_M 0x3F000
|
#define K_SEL_1024QAM_CH_C 0x423C
|
#define K_SEL_1024QAM_CH_C_M 0x1C0000
|
#define K_SEL_1024QAM_L1_C 0x423C
|
#define K_SEL_1024QAM_L1_C_M 0xE00000
|
#define K_SEL_1024QAM_L2_C 0x423C
|
#define K_SEL_1024QAM_L2_C_M 0x7000000
|
#define K_SEL_1024QAM_L3_C 0x423C
|
#define K_SEL_1024QAM_L3_C_M 0x38000000
|
#define K_SEL_1024QAM_L4_C 0x4240
|
#define K_SEL_1024QAM_L4_C_M 0x7
|
#define K_SEL_1024QAM_L5_C 0x4240
|
#define K_SEL_1024QAM_L5_C_M 0x38
|
#define K_SEL_1024QAM_CONDNUM_TH_C 0x4240
|
#define K_SEL_1024QAM_CONDNUM_TH_C_M 0x1C0
|
#define K_SEL_16QAM_CH_C 0x4240
|
#define K_SEL_16QAM_CH_C_M 0xE00
|
#define K_SEL_16QAM_L1_C 0x4240
|
#define K_SEL_16QAM_L1_C_M 0x7000
|
#define K_SEL_16QAM_L2_C 0x4240
|
#define K_SEL_16QAM_L2_C_M 0x38000
|
#define K_SEL_16QAM_L3_C 0x4240
|
#define K_SEL_16QAM_L3_C_M 0x1C0000
|
#define K_SEL_16QAM_CONDNUM_TH_C 0x4240
|
#define K_SEL_16QAM_CONDNUM_TH_C_M 0xE00000
|
#define K_SEL_256QAM_CH_C 0x4240
|
#define K_SEL_256QAM_CH_C_M 0x7000000
|
#define K_SEL_256QAM_L1_C 0x4240
|
#define K_SEL_256QAM_L1_C_M 0x38000000
|
#define K_SEL_256QAM_L2_C 0x4244
|
#define K_SEL_256QAM_L2_C_M 0x7
|
#define K_SEL_256QAM_L3_C 0x4244
|
#define K_SEL_256QAM_L3_C_M 0x38
|
#define K_SEL_256QAM_L4_C 0x4244
|
#define K_SEL_256QAM_L4_C_M 0x1C0
|
#define K_SEL_256QAM_L5_C 0x4244
|
#define K_SEL_256QAM_L5_C_M 0xE00
|
#define K_SEL_256QAM_CONDNUM_TH_C 0x4244
|
#define K_SEL_256QAM_CONDNUM_TH_C_M 0x7000
|
#define K_SEL_64QAM_CH_C 0x4244
|
#define K_SEL_64QAM_CH_C_M 0x38000
|
#define K_SEL_64QAM_L1_C 0x4244
|
#define K_SEL_64QAM_L1_C_M 0x1C0000
|
#define K_SEL_64QAM_L2_C 0x4244
|
#define K_SEL_64QAM_L2_C_M 0xE00000
|
#define K_SEL_64QAM_L3_C 0x4244
|
#define K_SEL_64QAM_L3_C_M 0x7000000
|
#define K_SEL_64QAM_L4_C 0x4244
|
#define K_SEL_64QAM_L4_C_M 0x38000000
|
#define K_SEL_64QAM_L5_C 0x4248
|
#define K_SEL_64QAM_L5_C_M 0x7
|
#define K_SEL_64QAM_CONDNUM_TH_C 0x4248
|
#define K_SEL_64QAM_CONDNUM_TH_C_M 0x38
|
#define INDI_QBPSK_CHK_EN_C 0x424C
|
#define INDI_QBPSK_CHK_EN_C_M 0x1
|
#define CHK_BFSNR_QUANTIZATION_ERROR_EN_C 0x4250
|
#define CHK_BFSNR_QUANTIZATION_ERROR_EN_C_M 0x1
|
#define MPDU_OK_CNT_USR0_TAR_CONTENT_C 0x4258
|
#define MPDU_OK_CNT_USR0_TAR_CONTENT_C_M 0xFFFF
|
#define MPDU_OK_CNT_USR1_TAR_CONTENT_C 0x4258
|
#define MPDU_OK_CNT_USR1_TAR_CONTENT_C_M 0xFFFF0000
|
#define MPDU_OK_CNT_USR2_TAR_CONTENT_C 0x425C
|
#define MPDU_OK_CNT_USR2_TAR_CONTENT_C_M 0xFFFF
|
#define MPDU_OK_CNT_USR3_TAR_CONTENT_C 0x425C
|
#define MPDU_OK_CNT_USR3_TAR_CONTENT_C_M 0xFFFF0000
|
#define TARGET_FRAME_TYPE_C 0x4260
|
#define TARGET_FRAME_TYPE_C_M 0xFF
|
#define TARGET_MAC_ADDRESS_8BITS_C 0x4260
|
#define TARGET_MAC_ADDRESS_8BITS_C_M 0xFF00
|
#define MPDU_OK_CNT_MODE_C 0x4260
|
#define MPDU_OK_CNT_MODE_C_M 0x70000
|
#define VHT_USR_POSITION_C 0x4260
|
#define VHT_USR_POSITION_C_M 0x180000
|
#define MPDU_OK_CNT_USR0_EN_C 0x4260
|
#define MPDU_OK_CNT_USR0_EN_C_M 0x200000
|
#define MPDU_OK_CNT_USR1_EN_C 0x4260
|
#define MPDU_OK_CNT_USR1_EN_C_M 0x400000
|
#define MPDU_OK_CNT_USR2_EN_C 0x4260
|
#define MPDU_OK_CNT_USR2_EN_C_M 0x800000
|
#define MPDU_OK_CNT_USR3_EN_C 0x4260
|
#define MPDU_OK_CNT_USR3_EN_C_M 0x1000000
|
#define TARGET_FRAME_TYPE_EN_C 0x4260
|
#define TARGET_FRAME_TYPE_EN_C_M 0x2000000
|
#define TARGET_MAC_ADDRESS_LSB_EN_C 0x4260
|
#define TARGET_MAC_ADDRESS_LSB_EN_C_M 0x4000000
|
#define MANUAL_TD_CFO_SEG0_C 0x426C
|
#define MANUAL_TD_CFO_SEG0_C_M 0xFFF
|
#define MANUAL_TD_CFO_SEG1_C 0x426C
|
#define MANUAL_TD_CFO_SEG1_C_M 0xFFF000
|
#define SBDRDY_WINDOW_LEN_C 0x426C
|
#define SBDRDY_WINDOW_LEN_C_M 0x7000000
|
#define MANUAL_TD_CFO_EN_C 0x426C
|
#define MANUAL_TD_CFO_EN_C_M 0x8000000
|
#define EARLY_TERMINATION_TH_0_C 0x4270
|
#define EARLY_TERMINATION_TH_0_C_M 0xF
|
#define EARLY_TERMINATION_TH_1_C 0x4270
|
#define EARLY_TERMINATION_TH_1_C_M 0xF0
|
#define EARLY_TERMINATION_TH_2_C 0x4270
|
#define EARLY_TERMINATION_TH_2_C_M 0xF00
|
#define EARLY_TERMINATION_TH_3_C 0x4270
|
#define EARLY_TERMINATION_TH_3_C_M 0xF000
|
#define ED_C1_TH_C 0x4270
|
#define ED_C1_TH_C_M 0xF0000
|
#define ED_C0_TH_C 0x4270
|
#define ED_C0_TH_C_M 0x700000
|
#define LDPC_SCAL_FCTR_C 0x4270
|
#define LDPC_SCAL_FCTR_C_M 0x1800000
|
#define EARLY_TERMINATION_BACKWARD_STEP_C 0x4270
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#define EARLY_TERMINATION_BACKWARD_STEP_C_M 0x6000000
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#define EARLY_TERMINATION_FORWARD_STEP_C 0x4270
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#define EARLY_TERMINATION_FORWARD_STEP_C_M 0x18000000
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#define LLR_SYNDROME_CHK_EN_C 0x4270
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#define LLR_SYNDROME_CHK_EN_C_M 0x20000000
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#define EARLY_DROP_C0_EN_C 0x4270
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#define EARLY_DROP_C0_EN_C_M 0x40000000
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#define EARLY_DROP_C1_EN_C 0x4270
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#define EARLY_DROP_C1_EN_C_M 0x80000000
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#define EARLY_DROP_C2_EN_C 0x4274
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#define EARLY_DROP_C2_EN_C_M 0x1
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#define EARLY_TERMINATION_EN_C 0x4274
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#define EARLY_TERMINATION_EN_C_M 0x2
|
#define TBCOMCT_RXTIME_C 0x4278
|
#define TBCOMCT_RXTIME_C_M 0x7FFF
|
#define TBCOMCT_N_SYM_C 0x4278
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#define TBCOMCT_N_SYM_C_M 0x3FF8000
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#define TBUSRCT0_MCS_C 0x4278
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#define TBUSRCT0_MCS_C_M 0x3C000000
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#define TBCOMCT_DBW_IDX_C 0x4278
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#define TBCOMCT_DBW_IDX_C_M 0xC0000000
|
#define TBCOMCT_N_USR_C 0x427C
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#define TBCOMCT_N_USR_C_M 0xFF
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#define TBUSRCT0_RU_ALLOC_C 0x427C
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#define TBUSRCT0_RU_ALLOC_C_M 0xFF00
|
#define TBUSRCT0_U_ID_C 0x427C
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#define TBUSRCT0_U_ID_C_M 0xFF0000
|
#define TBUSRCT1_RU_ALLOC_C 0x427C
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#define TBUSRCT1_RU_ALLOC_C_M 0xFF000000
|
#define TBUSRCT1_U_ID_C 0x4280
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#define TBUSRCT1_U_ID_C_M 0xFF
|
#define TBUSRCT2_RU_ALLOC_C 0x4280
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#define TBUSRCT2_RU_ALLOC_C_M 0xFF00
|
#define TBUSRCT2_U_ID_C 0x4280
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#define TBUSRCT2_U_ID_C_M 0xFF0000
|
#define TBUSRCT3_RU_ALLOC_C 0x4280
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#define TBUSRCT3_RU_ALLOC_C_M 0xFF000000
|
#define TBUSRCT3_U_ID_C 0x4284
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#define TBUSRCT3_U_ID_C_M 0xFF
|
#define TBUSRCT1_MCS_C 0x4284
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#define TBUSRCT1_MCS_C_M 0xF00
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#define TBUSRCT2_MCS_C 0x4284
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#define TBUSRCT2_MCS_C_M 0xF000
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#define TBUSRCT3_MCS_C 0x4284
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#define TBUSRCT3_MCS_C_M 0xF0000
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#define TBCOMCT_N_LTF_C 0x4284
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#define TBCOMCT_N_LTF_C_M 0x700000
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#define TBCOMCT_PKT_EXT_IDX_C 0x4284
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#define TBCOMCT_PKT_EXT_IDX_C_M 0x3800000
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#define TBUSRCT0_N_STS_C 0x4284
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#define TBUSRCT0_N_STS_C_M 0x1C000000
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#define TBUSRCT0_N_STS_RU_TOT_C 0x4284
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#define TBUSRCT0_N_STS_RU_TOT_C_M 0xE0000000
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#define TBUSRCT0_STRT_STS_C 0x4288
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#define TBUSRCT0_STRT_STS_C_M 0x7
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#define TBUSRCT1_N_STS_C 0x4288
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#define TBUSRCT1_N_STS_C_M 0x38
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#define TBUSRCT1_N_STS_RU_TOT_C 0x4288
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#define TBUSRCT1_N_STS_RU_TOT_C_M 0x1C0
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#define TBUSRCT1_STRT_STS_C 0x4288
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#define TBUSRCT1_STRT_STS_C_M 0xE00
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#define TBUSRCT2_N_STS_C 0x4288
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#define TBUSRCT2_N_STS_C_M 0x7000
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#define TBUSRCT2_N_STS_RU_TOT_C 0x4288
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#define TBUSRCT2_N_STS_RU_TOT_C_M 0x38000
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#define TBUSRCT2_STRT_STS_C 0x4288
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#define TBUSRCT2_STRT_STS_C_M 0x1C0000
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#define TBUSRCT3_N_STS_C 0x4288
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#define TBUSRCT3_N_STS_C_M 0xE00000
|
#define TBUSRCT3_N_STS_RU_TOT_C 0x4288
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#define TBUSRCT3_N_STS_RU_TOT_C_M 0x7000000
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#define TBUSRCT3_STRT_STS_C 0x4288
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#define TBUSRCT3_STRT_STS_C_M 0x38000000
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#define TBCOMCT_GI_TYPE_C 0x4288
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#define TBCOMCT_GI_TYPE_C_M 0xC0000000
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#define TBCOMCT_LTF_TYPE_C 0x428C
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#define TBCOMCT_LTF_TYPE_C_M 0x3
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#define TBCOMCT_PRE_FEC_FCTR_C 0x428C
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#define TBCOMCT_PRE_FEC_FCTR_C_M 0xC
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#define PPDU_STANDBY_C 0x428C
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#define PPDU_STANDBY_C_M 0x10
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#define TBCOMCT_DOPPLER_EN_C 0x428C
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#define TBCOMCT_DOPPLER_EN_C_M 0x20
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#define TBCOMCT_LDPC_EXTR_C 0x428C
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#define TBCOMCT_LDPC_EXTR_C_M 0x40
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#define TBCOMCT_MIDAMBLE_MODE_C 0x428C
|
#define TBCOMCT_MIDAMBLE_MODE_C_M 0x80
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#define TBCOMCT_MUMIMO_LTF_MODE_EN_C 0x428C
|
#define TBCOMCT_MUMIMO_LTF_MODE_EN_C_M 0x100
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#define TBCOMCT_NDP_C 0x428C
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#define TBCOMCT_NDP_C_M 0x200
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#define TBCOMCT_STBC_EN_C 0x428C
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#define TBCOMCT_STBC_EN_C_M 0x400
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#define TBUSRCT0_DCM_EN_C 0x428C
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#define TBUSRCT0_DCM_EN_C_M 0x800
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#define TBUSRCT0_FEC_TYPE_C 0x428C
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#define TBUSRCT0_FEC_TYPE_C_M 0x1000
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#define TBUSRCT1_DCM_EN_C 0x428C
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#define TBUSRCT1_DCM_EN_C_M 0x2000
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#define TBUSRCT1_FEC_TYPE_C 0x428C
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#define TBUSRCT1_FEC_TYPE_C_M 0x4000
|
#define TBUSRCT2_DCM_EN_C 0x428C
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#define TBUSRCT2_DCM_EN_C_M 0x8000
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#define TBUSRCT2_FEC_TYPE_C 0x428C
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#define TBUSRCT2_FEC_TYPE_C_M 0x10000
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#define TBUSRCT3_DCM_EN_C 0x428C
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#define TBUSRCT3_DCM_EN_C_M 0x20000
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#define TBUSRCT3_FEC_TYPE_C 0x428C
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#define TBUSRCT3_FEC_TYPE_C_M 0x40000
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#define COLLISION_USR_SNR_DET_TH_C 0x429C
|
#define COLLISION_USR_SNR_DET_TH_C_M 0x3FF
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#define COLLISION_USR_PW_DET_TH_C 0x429C
|
#define COLLISION_USR_PW_DET_TH_C_M 0x7FC00
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#define EMPTY_USR_PW_DET_TH_C 0x429C
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#define EMPTY_USR_PW_DET_TH_C_M 0xFF80000
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#define HESIGB_EXTRA_PHASE_SCAL_FCTR_C 0x429C
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#define HESIGB_EXTRA_PHASE_SCAL_FCTR_C_M 0xF0000000
|
#define LLR_NVAR_SCAL_C 0x42A0
|
#define LLR_NVAR_SCAL_C_M 0x3F
|
#define HE_20M_STA_CH_ALLOC_C 0x42A0
|
#define HE_20M_STA_CH_ALLOC_C_M 0x3C0
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#define BWD_S80_THD_C 0x42A0
|
#define BWD_S80_THD_C_M 0x1C00
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#define LLR_NVAR_SEL_C 0x42A0
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#define LLR_NVAR_SEL_C_M 0x6000
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#define CHSMO_EN_C 0x42A0
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#define CHSMO_EN_C_M 0x8000
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#define CHSMO_IDX_MOD_EN_C 0x42A0
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#define CHSMO_IDX_MOD_EN_C_M 0x10000
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#define HE_20M_STA_EN_C 0x42A0
|
#define HE_20M_STA_EN_C_M 0x20000
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#define HE_TB_STF_CFO_EST_EN_C 0x42A0
|
#define HE_TB_STF_CFO_EST_EN_C_M 0x40000
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#define L2_CFO_TRACKING_EN_C 0x42A0
|
#define L2_CFO_TRACKING_EN_C_M 0x80000
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#define LNA_BASED_TRK_UPD_EN_C 0x42A0
|
#define LNA_BASED_TRK_UPD_EN_C_M 0x100000
|
#define COLLISION_USR_STAT_DET_EN_C 0x42A0
|
#define COLLISION_USR_STAT_DET_EN_C_M 0x200000
|
#define EMPTY_USR_PW_DET_NON_TB_EN_C 0x42A0
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#define EMPTY_USR_PW_DET_NON_TB_EN_C_M 0x400000
|
#define SIGVAL_RPT_EN_C 0x42A0
|
#define SIGVAL_RPT_EN_C_M 0x800000
|
#define STBC_CH_CONSIST_EN_C 0x42A0
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#define STBC_CH_CONSIST_EN_C_M 0x1000000
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#define TRK_UPD_EN_PLCP_FORCE_ON_C 0x42A0
|
#define TRK_UPD_EN_PLCP_FORCE_ON_C_M 0x2000000
|
#define RU_END_IDX_C 0x42A4
|
#define RU_END_IDX_C_M 0x7F
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#define RU_START_IDX_C 0x42A4
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#define RU_START_IDX_C_M 0x3F80
|
#define RX_NR_C 0x42A4
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#define RX_NR_C_M 0x1C000
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#define HT_CB_C 0x42A4
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#define HT_CB_C_M 0x60000
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#define NDPA_FEEDBACK_TYPE_C 0x42A4
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#define NDPA_FEEDBACK_TYPE_C_M 0x180000
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#define RX_NG_C 0x42A4
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#define RX_NG_C_M 0x600000
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#define RX_NC_C 0x42A4
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#define RX_NC_C_M 0x800000
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#define VHT_HE_CB_C 0x42A4
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#define VHT_HE_CB_C_M 0x1000000
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#define CSI_PARA_EN_C 0x42A4
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#define CSI_PARA_EN_C_M 0x2000000
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#define SEG0_SET1_CSI_WGT_TONE_IDX_C 0x42B0
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#define SEG0_SET1_CSI_WGT_TONE_IDX_C_M 0x7FF
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#define SEG0_SET2_CSI_WGT_TONE_IDX_C 0x42B0
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#define SEG0_SET2_CSI_WGT_TONE_IDX_C_M 0x3FF800
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#define CFO_CSI_WGT_TH_C 0x42B0
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#define CFO_CSI_WGT_TH_C_M 0x1C00000
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#define CFO_CSI_WGT_VAL_C 0x42B0
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#define CFO_CSI_WGT_VAL_C_M 0xE000000
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#define CSI_MASK_TH_C 0x42B0
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#define CSI_MASK_TH_C_M 0x70000000
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#define CFO_CSI_WGT_EN_C 0x42B0
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#define CFO_CSI_WGT_EN_C_M 0x80000000
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#define SEG1_SET1_CSI_WGT_TONE_IDX_C 0x42B4
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#define SEG1_SET1_CSI_WGT_TONE_IDX_C_M 0x7FF
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#define SEG1_SET2_CSI_WGT_TONE_IDX_C 0x42B4
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#define SEG1_SET2_CSI_WGT_TONE_IDX_C_M 0x3FF800
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#define CSI_WGT_RSSI_TH_C 0x42B4
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#define CSI_WGT_RSSI_TH_C_M 0x1C00000
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#define SEG0_SET1_CSI_WGT_1X_VAL_TONE0_C 0x42B4
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#define SEG0_SET1_CSI_WGT_1X_VAL_TONE0_C_M 0xE000000
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#define SEG0_SET1_CSI_WGT_1X_VAL_TONE1_C 0x42B4
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#define SEG0_SET1_CSI_WGT_1X_VAL_TONE1_C_M 0x70000000
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#define CSI_WGT_4X_MORE_EN_C 0x42B4
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#define CSI_WGT_4X_MORE_EN_C_M 0x80000000
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#define SEG0_SET1_CSI_WGT_1X_VAL_TONE2_C 0x42B8
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#define SEG0_SET1_CSI_WGT_1X_VAL_TONE2_C_M 0x7
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#define SEG0_SET1_CSI_WGT_1X_VAL_TONE3_C 0x42B8
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#define SEG0_SET1_CSI_WGT_1X_VAL_TONE3_C_M 0x38
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#define SEG0_SET1_CSI_WGT_2X_VAL_TONE0_C 0x42B8
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#define SEG0_SET1_CSI_WGT_2X_VAL_TONE0_C_M 0x1C0
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#define SEG0_SET1_CSI_WGT_2X_VAL_TONE1_C 0x42B8
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#define SEG0_SET1_CSI_WGT_2X_VAL_TONE1_C_M 0xE00
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#define SEG0_SET1_CSI_WGT_2X_VAL_TONE2_C 0x42B8
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#define SEG0_SET1_CSI_WGT_2X_VAL_TONE2_C_M 0x7000
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#define SEG0_SET1_CSI_WGT_2X_VAL_TONE3_C 0x42B8
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#define SEG0_SET1_CSI_WGT_2X_VAL_TONE3_C_M 0x38000
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#define SEG0_SET1_CSI_WGT_4X_MORE_LFT_TONES_C 0x42B8
|
#define SEG0_SET1_CSI_WGT_4X_MORE_LFT_TONES_C_M 0x1C0000
|
#define SEG0_SET1_CSI_WGT_4X_MORE_RHT_TONES_C 0x42B8
|
#define SEG0_SET1_CSI_WGT_4X_MORE_RHT_TONES_C_M 0xE00000
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#define SEG0_SET1_CSI_WGT_VAL_TONE0_C 0x42B8
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#define SEG0_SET1_CSI_WGT_VAL_TONE0_C_M 0x7000000
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#define SEG0_SET1_CSI_WGT_VAL_TONE1_C 0x42B8
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#define SEG0_SET1_CSI_WGT_VAL_TONE1_C_M 0x38000000
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#define SEG0_SET1_CSI_WGT_1X_LFT_TONES_C 0x42B8
|
#define SEG0_SET1_CSI_WGT_1X_LFT_TONES_C_M 0xC0000000
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#define SEG0_SET1_CSI_WGT_VAL_TONE2_C 0x42BC
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#define SEG0_SET1_CSI_WGT_VAL_TONE2_C_M 0x7
|
#define SEG0_SET1_CSI_WGT_VAL_TONE3_C 0x42BC
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#define SEG0_SET1_CSI_WGT_VAL_TONE3_C_M 0x38
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#define SEG0_SET2_CSI_WGT_1X_VAL_TONE0_C 0x42BC
|
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE0_C_M 0x1C0
|
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE1_C 0x42BC
|
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE1_C_M 0xE00
|
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE2_C 0x42BC
|
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE2_C_M 0x7000
|
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE3_C 0x42BC
|
#define SEG0_SET2_CSI_WGT_1X_VAL_TONE3_C_M 0x38000
|
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE0_C 0x42BC
|
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE0_C_M 0x1C0000
|
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE1_C 0x42BC
|
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE1_C_M 0xE00000
|
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE2_C 0x42BC
|
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE2_C_M 0x7000000
|
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE3_C 0x42BC
|
#define SEG0_SET2_CSI_WGT_2X_VAL_TONE3_C_M 0x38000000
|
#define SEG0_SET1_CSI_WGT_1X_RHT_TONES_C 0x42BC
|
#define SEG0_SET1_CSI_WGT_1X_RHT_TONES_C_M 0xC0000000
|
#define SEG0_SET2_CSI_WGT_4X_MORE_LFT_TONES_C 0x42C0
|
#define SEG0_SET2_CSI_WGT_4X_MORE_LFT_TONES_C_M 0x7
|
#define SEG0_SET2_CSI_WGT_4X_MORE_RHT_TONES_C 0x42C0
|
#define SEG0_SET2_CSI_WGT_4X_MORE_RHT_TONES_C_M 0x38
|
#define SEG0_SET2_CSI_WGT_VAL_TONE0_C 0x42C0
|
#define SEG0_SET2_CSI_WGT_VAL_TONE0_C_M 0x1C0
|
#define SEG0_SET2_CSI_WGT_VAL_TONE1_C 0x42C0
|
#define SEG0_SET2_CSI_WGT_VAL_TONE1_C_M 0xE00
|
#define SEG0_SET2_CSI_WGT_VAL_TONE2_C 0x42C0
|
#define SEG0_SET2_CSI_WGT_VAL_TONE2_C_M 0x7000
|
#define SEG0_SET2_CSI_WGT_VAL_TONE3_C 0x42C0
|
#define SEG0_SET2_CSI_WGT_VAL_TONE3_C_M 0x38000
|
#define SEG1_SET1_CSI_WGT_VAL_TONE0_C 0x42C0
|
#define SEG1_SET1_CSI_WGT_VAL_TONE0_C_M 0x1C0000
|
#define SEG1_SET1_CSI_WGT_VAL_TONE1_C 0x42C0
|
#define SEG1_SET1_CSI_WGT_VAL_TONE1_C_M 0xE00000
|
#define SEG1_SET1_CSI_WGT_VAL_TONE2_C 0x42C0
|
#define SEG1_SET1_CSI_WGT_VAL_TONE2_C_M 0x7000000
|
#define SEG1_SET1_CSI_WGT_VAL_TONE3_C 0x42C0
|
#define SEG1_SET1_CSI_WGT_VAL_TONE3_C_M 0x38000000
|
#define SEG0_SET1_CSI_WGT_2X_LFT_TONES_C 0x42C0
|
#define SEG0_SET1_CSI_WGT_2X_LFT_TONES_C_M 0xC0000000
|
#define SEG1_SET2_CSI_WGT_VAL_TONE0_C 0x42C4
|
#define SEG1_SET2_CSI_WGT_VAL_TONE0_C_M 0x7
|
#define SEG1_SET2_CSI_WGT_VAL_TONE1_C 0x42C4
|
#define SEG1_SET2_CSI_WGT_VAL_TONE1_C_M 0x38
|
#define SEG1_SET2_CSI_WGT_VAL_TONE2_C 0x42C4
|
#define SEG1_SET2_CSI_WGT_VAL_TONE2_C_M 0x1C0
|
#define SEG1_SET2_CSI_WGT_VAL_TONE3_C 0x42C4
|
#define SEG1_SET2_CSI_WGT_VAL_TONE3_C_M 0xE00
|
#define SEG0_SET1_CSI_WGT_2X_RHT_TONES_C 0x42C4
|
#define SEG0_SET1_CSI_WGT_2X_RHT_TONES_C_M 0x3000
|
#define SEG0_SET1_CSI_WGT_LFT_TONES_C 0x42C4
|
#define SEG0_SET1_CSI_WGT_LFT_TONES_C_M 0xC000
|
#define SEG0_SET1_CSI_WGT_RHT_TONES_C 0x42C4
|
#define SEG0_SET1_CSI_WGT_RHT_TONES_C_M 0x30000
|
#define SEG0_SET2_CSI_WGT_1X_LFT_TONES_C 0x42C4
|
#define SEG0_SET2_CSI_WGT_1X_LFT_TONES_C_M 0xC0000
|
#define SEG0_SET2_CSI_WGT_1X_RHT_TONES_C 0x42C4
|
#define SEG0_SET2_CSI_WGT_1X_RHT_TONES_C_M 0x300000
|
#define SEG0_SET2_CSI_WGT_2X_LFT_TONES_C 0x42C4
|
#define SEG0_SET2_CSI_WGT_2X_LFT_TONES_C_M 0xC00000
|
#define SEG0_SET2_CSI_WGT_2X_RHT_TONES_C 0x42C4
|
#define SEG0_SET2_CSI_WGT_2X_RHT_TONES_C_M 0x3000000
|
#define SEG0_SET2_CSI_WGT_LFT_TONES_C 0x42C4
|
#define SEG0_SET2_CSI_WGT_LFT_TONES_C_M 0xC000000
|
#define SEG0_SET2_CSI_WGT_RHT_TONES_C 0x42C4
|
#define SEG0_SET2_CSI_WGT_RHT_TONES_C_M 0x30000000
|
#define SEG1_SET1_CSI_WGT_1X_LFT_TONES_C 0x42C4
|
#define SEG1_SET1_CSI_WGT_1X_LFT_TONES_C_M 0xC0000000
|
#define SEG1_SET1_CSI_WGT_1X_RHT_TONES_C 0x42C8
|
#define SEG1_SET1_CSI_WGT_1X_RHT_TONES_C_M 0x3
|
#define SEG1_SET1_CSI_WGT_2X_LFT_TONES_C 0x42C8
|
#define SEG1_SET1_CSI_WGT_2X_LFT_TONES_C_M 0xC
|
#define SEG1_SET1_CSI_WGT_2X_RHT_TONES_C 0x42C8
|
#define SEG1_SET1_CSI_WGT_2X_RHT_TONES_C_M 0x30
|
#define SEG1_SET1_CSI_WGT_LFT_TONES_C 0x42C8
|
#define SEG1_SET1_CSI_WGT_LFT_TONES_C_M 0xC0
|
#define SEG1_SET1_CSI_WGT_RHT_TONES_C 0x42C8
|
#define SEG1_SET1_CSI_WGT_RHT_TONES_C_M 0x300
|
#define SEG1_SET2_CSI_WGT_1X_LFT_TONES_C 0x42C8
|
#define SEG1_SET2_CSI_WGT_1X_LFT_TONES_C_M 0xC00
|
#define SEG1_SET2_CSI_WGT_1X_RHT_TONES_C 0x42C8
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#define SEG1_SET2_CSI_WGT_1X_RHT_TONES_C_M 0x3000
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#define SEG1_SET2_CSI_WGT_2X_LFT_TONES_C 0x42C8
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#define SEG1_SET2_CSI_WGT_2X_LFT_TONES_C_M 0xC000
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#define SEG1_SET2_CSI_WGT_2X_RHT_TONES_C 0x42C8
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#define SEG1_SET2_CSI_WGT_2X_RHT_TONES_C_M 0x30000
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#define SEG1_SET2_CSI_WGT_LFT_TONES_C 0x42C8
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#define SEG1_SET2_CSI_WGT_LFT_TONES_C_M 0xC0000
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#define SEG1_SET2_CSI_WGT_RHT_TONES_C 0x42C8
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#define SEG1_SET2_CSI_WGT_RHT_TONES_C_M 0x300000
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#define CSI_WGT_RSSI_BYPASS_EN_C 0x42C8
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#define CSI_WGT_RSSI_BYPASS_EN_C_M 0x400000
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#define SEG0_SET1_CSI_WGT_EN_C 0x42C8
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#define SEG0_SET1_CSI_WGT_EN_C_M 0x800000
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#define SEG0_SET2_CSI_WGT_EN_C 0x42C8
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#define SEG0_SET2_CSI_WGT_EN_C_M 0x1000000
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#define SEG1_SET1_CSI_WGT_EN_C 0x42C8
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#define SEG1_SET1_CSI_WGT_EN_C_M 0x2000000
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#define SEG1_SET2_CSI_WGT_EN_C 0x42C8
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#define SEG1_SET2_CSI_WGT_EN_C_M 0x4000000
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#define PROCR_MAX_NSTS_SMO_HW_C 0x42D4
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#define PROCR_MAX_NSTS_SMO_HW_C_M 0x3
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#define PROCR_NOISE_RE_EST_HE_TB_EN_C 0x42D4
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#define PROCR_NOISE_RE_EST_HE_TB_EN_C_M 0x4
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#define PROCR_NOISE_RE_EST_HE_EN_C 0x42D4
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#define PROCR_NOISE_RE_EST_HE_EN_C_M 0x8
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#define PROCR_NOISE_RE_EST_HT_EN_C 0x42D4
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#define PROCR_NOISE_RE_EST_HT_EN_C_M 0x10
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#define PROCR_NOISE_RE_EST_VHT_EN_C 0x42D4
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#define PROCR_NOISE_RE_EST_VHT_EN_C_M 0x20
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#define HE_EXTRA_TONE_CHSMO_EN_C 0x42D8
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#define HE_EXTRA_TONE_CHSMO_EN_C_M 0x1
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#define RPT_TONE_EVM_IDX_C 0x42DC
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#define RPT_TONE_EVM_IDX_C_M 0x7FF
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#define SFCTR_AWGN_BCC_1SS_MCS0_C 0x42DC
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#define SFCTR_AWGN_BCC_1SS_MCS0_C_M 0x1F800
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#define SFCTR_AWGN_BCC_1SS_MCS1_C 0x42DC
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#define SFCTR_AWGN_BCC_1SS_MCS1_C_M 0x7E0000
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#define SFCTR_AWGN_BCC_1SS_MCS2_C 0x42DC
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#define SFCTR_AWGN_BCC_1SS_MCS2_C_M 0x1F800000
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#define LLR_COEF_C 0x42DC
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#define LLR_COEF_C_M 0xE0000000
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#define SFCTR_AWGN_BCC_1SS_MCS3_C 0x42E0
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#define SFCTR_AWGN_BCC_1SS_MCS3_C_M 0x3F
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#define SFCTR_AWGN_BCC_1SS_MCS4_C 0x42E0
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#define SFCTR_AWGN_BCC_1SS_MCS4_C_M 0xFC0
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#define SFCTR_AWGN_BCC_1SS_MCS5_C 0x42E0
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#define SFCTR_AWGN_BCC_1SS_MCS5_C_M 0x3F000
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#define SFCTR_AWGN_BCC_1SS_MCS6_C 0x42E0
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#define SFCTR_AWGN_BCC_1SS_MCS6_C_M 0xFC0000
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#define SFCTR_AWGN_BCC_1SS_MCS7_C 0x42E0
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#define SFCTR_AWGN_BCC_1SS_MCS7_C_M 0x3F000000
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#define UPD_SYM_EVM_C 0x42E0
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#define UPD_SYM_EVM_C_M 0xC0000000
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#define SFCTR_AWGN_BCC_1SS_MCS8_C 0x42E4
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#define SFCTR_AWGN_BCC_1SS_MCS8_C_M 0x3F
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#define SFCTR_AWGN_BCC_1SS_MCS9_C 0x42E4
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#define SFCTR_AWGN_BCC_1SS_MCS9_C_M 0xFC0
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#define SFCTR_AWGN_BCC_2SS_MCS0_C 0x42E4
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#define SFCTR_AWGN_BCC_2SS_MCS0_C_M 0x3F000
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#define SFCTR_AWGN_BCC_2SS_MCS1_C 0x42E4
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#define SFCTR_AWGN_BCC_2SS_MCS1_C_M 0xFC0000
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#define SFCTR_AWGN_BCC_2SS_MCS2_C 0x42E4
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#define SFCTR_AWGN_BCC_2SS_MCS2_C_M 0x3F000000
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#define DCM_BINARY_CSI_WGT_C 0x42E4
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#define DCM_BINARY_CSI_WGT_C_M 0x40000000
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#define DCM_COMBINE_EN_C 0x42E4
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#define DCM_COMBINE_EN_C_M 0x80000000
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#define SFCTR_AWGN_BCC_2SS_MCS3_C 0x42E8
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#define SFCTR_AWGN_BCC_2SS_MCS3_C_M 0x3F
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#define SFCTR_AWGN_BCC_2SS_MCS4_C 0x42E8
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#define SFCTR_AWGN_BCC_2SS_MCS4_C_M 0xFC0
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#define SFCTR_AWGN_BCC_2SS_MCS5_C 0x42E8
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#define SFCTR_AWGN_BCC_2SS_MCS5_C_M 0x3F000
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#define SFCTR_AWGN_BCC_2SS_MCS6_C 0x42E8
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#define SFCTR_AWGN_BCC_2SS_MCS6_C_M 0xFC0000
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#define SFCTR_AWGN_BCC_2SS_MCS7_C 0x42E8
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#define SFCTR_AWGN_BCC_2SS_MCS7_C_M 0x3F000000
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#define EVM_RPT_OFST_EN_C 0x42E8
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#define EVM_RPT_OFST_EN_C_M 0x40000000
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#define LEGACY_2R_ANOTHER_SFCTR_EN_C 0x42E8
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#define LEGACY_2R_ANOTHER_SFCTR_EN_C_M 0x80000000
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#define SFCTR_AWGN_BCC_2SS_MCS8_C 0x42EC
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#define SFCTR_AWGN_BCC_2SS_MCS8_C_M 0x3F
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#define SFCTR_AWGN_BCC_2SS_MCS9_C 0x42EC
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#define SFCTR_AWGN_BCC_2SS_MCS9_C_M 0xFC0
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#define SFCTR_AWGN_BCC_3SS_MCS0_C 0x42EC
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#define SFCTR_AWGN_BCC_3SS_MCS0_C_M 0x3F000
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#define SFCTR_AWGN_BCC_3SS_MCS1_C 0x42EC
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#define SFCTR_AWGN_BCC_3SS_MCS1_C_M 0xFC0000
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#define SFCTR_AWGN_BCC_3SS_MCS2_C 0x42EC
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#define SFCTR_AWGN_BCC_3SS_MCS2_C_M 0x3F000000
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#define DIFF_NLM_FOR_CHANNEL_EN_C 0x42EC
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#define DIFF_NLM_FOR_CHANNEL_EN_C_M 0x40000000
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#define SFCTR_AWGN_BCC_3SS_MCS3_C 0x42F0
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#define SFCTR_AWGN_BCC_3SS_MCS3_C_M 0x3F
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#define SFCTR_AWGN_BCC_3SS_MCS4_C 0x42F0
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#define SFCTR_AWGN_BCC_3SS_MCS4_C_M 0xFC0
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#define SFCTR_AWGN_BCC_3SS_MCS5_C 0x42F0
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#define SFCTR_AWGN_BCC_3SS_MCS5_C_M 0x3F000
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#define SFCTR_AWGN_BCC_3SS_MCS6_C 0x42F0
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#define SFCTR_AWGN_BCC_3SS_MCS6_C_M 0xFC0000
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#define SFCTR_AWGN_BCC_3SS_MCS7_C 0x42F0
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#define SFCTR_AWGN_BCC_3SS_MCS7_C_M 0x3F000000
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#define SFCTR_AWGN_BCC_3SS_MCS8_C 0x42F4
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#define SFCTR_AWGN_BCC_3SS_MCS8_C_M 0x3F
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#define SFCTR_AWGN_BCC_3SS_MCS9_C 0x42F4
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#define SFCTR_AWGN_BCC_3SS_MCS9_C_M 0xFC0
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#define SFCTR_AWGN_BCC_4SS_MCS0_C 0x42F4
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#define SFCTR_AWGN_BCC_4SS_MCS0_C_M 0x3F000
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#define SFCTR_AWGN_BCC_4SS_MCS1_C 0x42F4
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#define SFCTR_AWGN_BCC_4SS_MCS1_C_M 0xFC0000
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#define SFCTR_AWGN_BCC_4SS_MCS2_C 0x42F4
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#define SFCTR_AWGN_BCC_4SS_MCS2_C_M 0x3F000000
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#define SFCTR_AWGN_BCC_4SS_MCS3_C 0x42F8
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#define SFCTR_AWGN_BCC_4SS_MCS3_C_M 0x3F
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#define SFCTR_AWGN_BCC_4SS_MCS4_C 0x42F8
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#define SFCTR_AWGN_BCC_4SS_MCS4_C_M 0xFC0
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#define SFCTR_AWGN_BCC_4SS_MCS5_C 0x42F8
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#define SFCTR_AWGN_BCC_4SS_MCS5_C_M 0x3F000
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#define SFCTR_AWGN_BCC_4SS_MCS6_C 0x42F8
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#define SFCTR_AWGN_BCC_4SS_MCS6_C_M 0xFC0000
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#define SFCTR_AWGN_BCC_4SS_MCS7_C 0x42F8
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#define SFCTR_AWGN_BCC_4SS_MCS7_C_M 0x3F000000
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#define SFCTR_AWGN_BCC_4SS_MCS8_C 0x42FC
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#define SFCTR_AWGN_BCC_4SS_MCS8_C_M 0x3F
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#define SFCTR_AWGN_BCC_4SS_MCS9_C 0x42FC
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#define SFCTR_AWGN_BCC_4SS_MCS9_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_1SS_MCS0_C 0x42FC
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#define SFCTR_AWGN_LDPC_1SS_MCS0_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_1SS_MCS1_C 0x42FC
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#define SFCTR_AWGN_LDPC_1SS_MCS1_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_1SS_MCS10_C 0x42FC
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#define SFCTR_AWGN_LDPC_1SS_MCS10_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_1SS_MCS11_C 0x4300
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#define SFCTR_AWGN_LDPC_1SS_MCS11_C_M 0x3F
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#define SFCTR_AWGN_LDPC_1SS_MCS2_C 0x4300
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#define SFCTR_AWGN_LDPC_1SS_MCS2_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_1SS_MCS3_C 0x4300
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#define SFCTR_AWGN_LDPC_1SS_MCS3_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_1SS_MCS4_C 0x4300
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#define SFCTR_AWGN_LDPC_1SS_MCS4_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_1SS_MCS5_C 0x4300
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#define SFCTR_AWGN_LDPC_1SS_MCS5_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_1SS_MCS6_C 0x4304
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#define SFCTR_AWGN_LDPC_1SS_MCS6_C_M 0x3F
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#define SFCTR_AWGN_LDPC_1SS_MCS7_C 0x4304
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#define SFCTR_AWGN_LDPC_1SS_MCS7_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_1SS_MCS8_C 0x4304
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#define SFCTR_AWGN_LDPC_1SS_MCS8_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_1SS_MCS9_C 0x4304
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#define SFCTR_AWGN_LDPC_1SS_MCS9_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_2SS_MCS0_C 0x4304
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#define SFCTR_AWGN_LDPC_2SS_MCS0_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_2SS_MCS1_C 0x4308
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#define SFCTR_AWGN_LDPC_2SS_MCS1_C_M 0x3F
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#define SFCTR_AWGN_LDPC_2SS_MCS10_C 0x4308
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#define SFCTR_AWGN_LDPC_2SS_MCS10_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_2SS_MCS11_C 0x4308
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#define SFCTR_AWGN_LDPC_2SS_MCS11_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_2SS_MCS2_C 0x4308
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#define SFCTR_AWGN_LDPC_2SS_MCS2_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_2SS_MCS3_C 0x4308
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#define SFCTR_AWGN_LDPC_2SS_MCS3_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_2SS_MCS4_C 0x430C
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#define SFCTR_AWGN_LDPC_2SS_MCS4_C_M 0x3F
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#define SFCTR_AWGN_LDPC_2SS_MCS5_C 0x430C
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#define SFCTR_AWGN_LDPC_2SS_MCS5_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_2SS_MCS6_C 0x430C
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#define SFCTR_AWGN_LDPC_2SS_MCS6_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_2SS_MCS7_C 0x430C
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#define SFCTR_AWGN_LDPC_2SS_MCS7_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_2SS_MCS8_C 0x430C
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#define SFCTR_AWGN_LDPC_2SS_MCS8_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_2SS_MCS9_C 0x4310
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#define SFCTR_AWGN_LDPC_2SS_MCS9_C_M 0x3F
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#define SFCTR_AWGN_LDPC_3SS_MCS0_C 0x4310
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#define SFCTR_AWGN_LDPC_3SS_MCS0_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_3SS_MCS1_C 0x4310
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#define SFCTR_AWGN_LDPC_3SS_MCS1_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_3SS_MCS10_C 0x4310
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#define SFCTR_AWGN_LDPC_3SS_MCS10_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_3SS_MCS11_C 0x4310
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#define SFCTR_AWGN_LDPC_3SS_MCS11_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_3SS_MCS2_C 0x4314
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#define SFCTR_AWGN_LDPC_3SS_MCS2_C_M 0x3F
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#define SFCTR_AWGN_LDPC_3SS_MCS3_C 0x4314
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#define SFCTR_AWGN_LDPC_3SS_MCS3_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_3SS_MCS4_C 0x4314
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#define SFCTR_AWGN_LDPC_3SS_MCS4_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_3SS_MCS5_C 0x4314
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#define SFCTR_AWGN_LDPC_3SS_MCS5_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_3SS_MCS6_C 0x4314
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#define SFCTR_AWGN_LDPC_3SS_MCS6_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_3SS_MCS7_C 0x4318
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#define SFCTR_AWGN_LDPC_3SS_MCS7_C_M 0x3F
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#define SFCTR_AWGN_LDPC_3SS_MCS8_C 0x4318
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#define SFCTR_AWGN_LDPC_3SS_MCS8_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_3SS_MCS9_C 0x4318
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#define SFCTR_AWGN_LDPC_3SS_MCS9_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_4SS_MCS0_C 0x4318
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#define SFCTR_AWGN_LDPC_4SS_MCS0_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_4SS_MCS1_C 0x4318
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#define SFCTR_AWGN_LDPC_4SS_MCS1_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_4SS_MCS10_C 0x431C
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#define SFCTR_AWGN_LDPC_4SS_MCS10_C_M 0x3F
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#define SFCTR_AWGN_LDPC_4SS_MCS11_C 0x431C
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#define SFCTR_AWGN_LDPC_4SS_MCS11_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_4SS_MCS2_C 0x431C
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#define SFCTR_AWGN_LDPC_4SS_MCS2_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_4SS_MCS3_C 0x431C
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#define SFCTR_AWGN_LDPC_4SS_MCS3_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_4SS_MCS4_C 0x431C
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#define SFCTR_AWGN_LDPC_4SS_MCS4_C_M 0x3F000000
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#define SFCTR_AWGN_LDPC_4SS_MCS5_C 0x4320
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#define SFCTR_AWGN_LDPC_4SS_MCS5_C_M 0x3F
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#define SFCTR_AWGN_LDPC_4SS_MCS6_C 0x4320
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#define SFCTR_AWGN_LDPC_4SS_MCS6_C_M 0xFC0
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#define SFCTR_AWGN_LDPC_4SS_MCS7_C 0x4320
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#define SFCTR_AWGN_LDPC_4SS_MCS7_C_M 0x3F000
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#define SFCTR_AWGN_LDPC_4SS_MCS8_C 0x4320
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#define SFCTR_AWGN_LDPC_4SS_MCS8_C_M 0xFC0000
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#define SFCTR_AWGN_LDPC_4SS_MCS9_C 0x4320
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#define SFCTR_AWGN_LDPC_4SS_MCS9_C_M 0x3F000000
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#define SFCTR_AWGN_LAGCY_12M_C 0x4324
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#define SFCTR_AWGN_LAGCY_12M_C_M 0x3F
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#define SFCTR_AWGN_LAGCY_18M_C 0x4324
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#define SFCTR_AWGN_LAGCY_18M_C_M 0xFC0
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#define SFCTR_AWGN_LAGCY_24M_C 0x4324
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#define SFCTR_AWGN_LAGCY_24M_C_M 0x3F000
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#define SFCTR_AWGN_LAGCY_36M_C 0x4324
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#define SFCTR_AWGN_LAGCY_36M_C_M 0xFC0000
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#define SFCTR_AWGN_LAGCY_48M_C 0x4324
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#define SFCTR_AWGN_LAGCY_48M_C_M 0x3F000000
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#define SFCTR_AWGN_LAGCY_54M_C 0x4328
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#define SFCTR_AWGN_LAGCY_54M_C_M 0x3F
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#define SFCTR_AWGN_LAGCY_6M_C 0x4328
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#define SFCTR_AWGN_LAGCY_6M_C_M 0xFC0
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#define SFCTR_AWGN_LAGCY_9M_C 0x4328
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#define SFCTR_AWGN_LAGCY_9M_C_M 0x3F000
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#define SFCTR_CH_BCC_1SS_MCS0_C 0x4328
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#define SFCTR_CH_BCC_1SS_MCS0_C_M 0xFC0000
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#define SFCTR_CH_BCC_1SS_MCS1_C 0x4328
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#define SFCTR_CH_BCC_1SS_MCS1_C_M 0x3F000000
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#define SFCTR_CH_BCC_1SS_MCS2_C 0x432C
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#define SFCTR_CH_BCC_1SS_MCS2_C_M 0x3F
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#define SFCTR_CH_BCC_1SS_MCS3_C 0x432C
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#define SFCTR_CH_BCC_1SS_MCS3_C_M 0xFC0
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#define SFCTR_CH_BCC_1SS_MCS4_C 0x432C
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#define SFCTR_CH_BCC_1SS_MCS4_C_M 0x3F000
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#define SFCTR_CH_BCC_1SS_MCS5_C 0x432C
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#define SFCTR_CH_BCC_1SS_MCS5_C_M 0xFC0000
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#define SFCTR_CH_BCC_1SS_MCS6_C 0x432C
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#define SFCTR_CH_BCC_1SS_MCS6_C_M 0x3F000000
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#define SFCTR_CH_BCC_1SS_MCS7_C 0x4330
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#define SFCTR_CH_BCC_1SS_MCS7_C_M 0x3F
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#define SFCTR_CH_BCC_1SS_MCS8_C 0x4330
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#define SFCTR_CH_BCC_1SS_MCS8_C_M 0xFC0
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#define SFCTR_CH_BCC_1SS_MCS9_C 0x4330
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#define SFCTR_CH_BCC_1SS_MCS9_C_M 0x3F000
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#define SFCTR_CH_BCC_2SS_MCS0_C 0x4330
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#define SFCTR_CH_BCC_2SS_MCS0_C_M 0xFC0000
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#define SFCTR_CH_BCC_2SS_MCS1_C 0x4330
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#define SFCTR_CH_BCC_2SS_MCS1_C_M 0x3F000000
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#define SFCTR_CH_BCC_2SS_MCS2_C 0x4334
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#define SFCTR_CH_BCC_2SS_MCS2_C_M 0x3F
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#define SFCTR_CH_BCC_2SS_MCS3_C 0x4334
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#define SFCTR_CH_BCC_2SS_MCS3_C_M 0xFC0
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#define SFCTR_CH_BCC_2SS_MCS4_C 0x4334
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#define SFCTR_CH_BCC_2SS_MCS4_C_M 0x3F000
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#define SFCTR_CH_BCC_2SS_MCS5_C 0x4334
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#define SFCTR_CH_BCC_2SS_MCS5_C_M 0xFC0000
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#define SFCTR_CH_BCC_2SS_MCS6_C 0x4334
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#define SFCTR_CH_BCC_2SS_MCS6_C_M 0x3F000000
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#define SFCTR_CH_BCC_2SS_MCS7_C 0x4338
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#define SFCTR_CH_BCC_2SS_MCS7_C_M 0x3F
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#define SFCTR_CH_BCC_2SS_MCS8_C 0x4338
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#define SFCTR_CH_BCC_2SS_MCS8_C_M 0xFC0
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#define SFCTR_CH_BCC_2SS_MCS9_C 0x4338
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#define SFCTR_CH_BCC_2SS_MCS9_C_M 0x3F000
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#define SFCTR_CH_BCC_3SS_MCS0_C 0x4338
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#define SFCTR_CH_BCC_3SS_MCS0_C_M 0xFC0000
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#define SFCTR_CH_BCC_3SS_MCS1_C 0x4338
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#define SFCTR_CH_BCC_3SS_MCS1_C_M 0x3F000000
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#define SFCTR_CH_BCC_3SS_MCS2_C 0x433C
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#define SFCTR_CH_BCC_3SS_MCS2_C_M 0x3F
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#define SFCTR_CH_BCC_3SS_MCS3_C 0x433C
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#define SFCTR_CH_BCC_3SS_MCS3_C_M 0xFC0
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#define SFCTR_CH_BCC_3SS_MCS4_C 0x433C
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#define SFCTR_CH_BCC_3SS_MCS4_C_M 0x3F000
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#define SFCTR_CH_BCC_3SS_MCS5_C 0x433C
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#define SFCTR_CH_BCC_3SS_MCS5_C_M 0xFC0000
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#define SFCTR_CH_BCC_3SS_MCS6_C 0x433C
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#define SFCTR_CH_BCC_3SS_MCS6_C_M 0x3F000000
|
#define SFCTR_CH_BCC_3SS_MCS7_C 0x4340
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#define SFCTR_CH_BCC_3SS_MCS7_C_M 0x3F
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#define SFCTR_CH_BCC_3SS_MCS8_C 0x4340
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#define SFCTR_CH_BCC_3SS_MCS8_C_M 0xFC0
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#define SFCTR_CH_BCC_3SS_MCS9_C 0x4340
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#define SFCTR_CH_BCC_3SS_MCS9_C_M 0x3F000
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#define SFCTR_CH_BCC_4SS_MCS0_C 0x4340
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#define SFCTR_CH_BCC_4SS_MCS0_C_M 0xFC0000
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#define SFCTR_CH_BCC_4SS_MCS1_C 0x4340
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#define SFCTR_CH_BCC_4SS_MCS1_C_M 0x3F000000
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#define SFCTR_CH_BCC_4SS_MCS2_C 0x4344
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#define SFCTR_CH_BCC_4SS_MCS2_C_M 0x3F
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#define SFCTR_CH_BCC_4SS_MCS3_C 0x4344
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#define SFCTR_CH_BCC_4SS_MCS3_C_M 0xFC0
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#define SFCTR_CH_BCC_4SS_MCS4_C 0x4344
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#define SFCTR_CH_BCC_4SS_MCS4_C_M 0x3F000
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#define SFCTR_CH_BCC_4SS_MCS5_C 0x4344
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#define SFCTR_CH_BCC_4SS_MCS5_C_M 0xFC0000
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#define SFCTR_CH_BCC_4SS_MCS6_C 0x4344
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#define SFCTR_CH_BCC_4SS_MCS6_C_M 0x3F000000
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#define SFCTR_CH_BCC_4SS_MCS7_C 0x4348
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#define SFCTR_CH_BCC_4SS_MCS7_C_M 0x3F
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#define SFCTR_CH_BCC_4SS_MCS8_C 0x4348
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#define SFCTR_CH_BCC_4SS_MCS8_C_M 0xFC0
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#define SFCTR_CH_BCC_4SS_MCS9_C 0x4348
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#define SFCTR_CH_BCC_4SS_MCS9_C_M 0x3F000
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#define SFCTR_CH_LDPC_1SS_MCS0_C 0x4348
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#define SFCTR_CH_LDPC_1SS_MCS0_C_M 0xFC0000
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#define SFCTR_CH_LDPC_1SS_MCS1_C 0x4348
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#define SFCTR_CH_LDPC_1SS_MCS1_C_M 0x3F000000
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#define SFCTR_CH_LDPC_1SS_MCS10_C 0x434C
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#define SFCTR_CH_LDPC_1SS_MCS10_C_M 0x3F
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#define SFCTR_CH_LDPC_1SS_MCS11_C 0x434C
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#define SFCTR_CH_LDPC_1SS_MCS11_C_M 0xFC0
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#define SFCTR_CH_LDPC_1SS_MCS2_C 0x434C
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#define SFCTR_CH_LDPC_1SS_MCS2_C_M 0x3F000
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#define SFCTR_CH_LDPC_1SS_MCS3_C 0x434C
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#define SFCTR_CH_LDPC_1SS_MCS3_C_M 0xFC0000
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#define SFCTR_CH_LDPC_1SS_MCS4_C 0x434C
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#define SFCTR_CH_LDPC_1SS_MCS4_C_M 0x3F000000
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#define SFCTR_CH_LDPC_1SS_MCS5_C 0x4350
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#define SFCTR_CH_LDPC_1SS_MCS5_C_M 0x3F
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#define SFCTR_CH_LDPC_1SS_MCS6_C 0x4350
|
#define SFCTR_CH_LDPC_1SS_MCS6_C_M 0xFC0
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#define SFCTR_CH_LDPC_1SS_MCS7_C 0x4350
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#define SFCTR_CH_LDPC_1SS_MCS7_C_M 0x3F000
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#define SFCTR_CH_LDPC_1SS_MCS8_C 0x4350
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#define SFCTR_CH_LDPC_1SS_MCS8_C_M 0xFC0000
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#define SFCTR_CH_LDPC_1SS_MCS9_C 0x4350
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#define SFCTR_CH_LDPC_1SS_MCS9_C_M 0x3F000000
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#define SFCTR_CH_LDPC_2SS_MCS0_C 0x4354
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#define SFCTR_CH_LDPC_2SS_MCS0_C_M 0x3F
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#define SFCTR_CH_LDPC_2SS_MCS1_C 0x4354
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#define SFCTR_CH_LDPC_2SS_MCS1_C_M 0xFC0
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#define SFCTR_CH_LDPC_2SS_MCS10_C 0x4354
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#define SFCTR_CH_LDPC_2SS_MCS10_C_M 0x3F000
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#define SFCTR_CH_LDPC_2SS_MCS11_C 0x4354
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#define SFCTR_CH_LDPC_2SS_MCS11_C_M 0xFC0000
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#define SFCTR_CH_LDPC_2SS_MCS2_C 0x4354
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#define SFCTR_CH_LDPC_2SS_MCS2_C_M 0x3F000000
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#define SFCTR_CH_LDPC_2SS_MCS3_C 0x4358
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#define SFCTR_CH_LDPC_2SS_MCS3_C_M 0x3F
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#define SFCTR_CH_LDPC_2SS_MCS4_C 0x4358
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#define SFCTR_CH_LDPC_2SS_MCS4_C_M 0xFC0
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#define SFCTR_CH_LDPC_2SS_MCS5_C 0x4358
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#define SFCTR_CH_LDPC_2SS_MCS5_C_M 0x3F000
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#define SFCTR_CH_LDPC_2SS_MCS6_C 0x4358
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#define SFCTR_CH_LDPC_2SS_MCS6_C_M 0xFC0000
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#define SFCTR_CH_LDPC_2SS_MCS7_C 0x4358
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#define SFCTR_CH_LDPC_2SS_MCS7_C_M 0x3F000000
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#define SFCTR_CH_LDPC_2SS_MCS8_C 0x435C
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#define SFCTR_CH_LDPC_2SS_MCS8_C_M 0x3F
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#define SFCTR_CH_LDPC_2SS_MCS9_C 0x435C
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#define SFCTR_CH_LDPC_2SS_MCS9_C_M 0xFC0
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#define SFCTR_CH_LDPC_3SS_MCS0_C 0x435C
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#define SFCTR_CH_LDPC_3SS_MCS0_C_M 0x3F000
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#define SFCTR_CH_LDPC_3SS_MCS1_C 0x435C
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#define SFCTR_CH_LDPC_3SS_MCS1_C_M 0xFC0000
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#define SFCTR_CH_LDPC_3SS_MCS10_C 0x435C
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#define SFCTR_CH_LDPC_3SS_MCS10_C_M 0x3F000000
|
#define SFCTR_CH_LDPC_3SS_MCS11_C 0x4360
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#define SFCTR_CH_LDPC_3SS_MCS11_C_M 0x3F
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#define SFCTR_CH_LDPC_3SS_MCS2_C 0x4360
|
#define SFCTR_CH_LDPC_3SS_MCS2_C_M 0xFC0
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#define SFCTR_CH_LDPC_3SS_MCS3_C 0x4360
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#define SFCTR_CH_LDPC_3SS_MCS3_C_M 0x3F000
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#define SFCTR_CH_LDPC_3SS_MCS4_C 0x4360
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#define SFCTR_CH_LDPC_3SS_MCS4_C_M 0xFC0000
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#define SFCTR_CH_LDPC_3SS_MCS5_C 0x4360
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#define SFCTR_CH_LDPC_3SS_MCS5_C_M 0x3F000000
|
#define SFCTR_CH_LDPC_3SS_MCS6_C 0x4364
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#define SFCTR_CH_LDPC_3SS_MCS6_C_M 0x3F
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#define SFCTR_CH_LDPC_3SS_MCS7_C 0x4364
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#define SFCTR_CH_LDPC_3SS_MCS7_C_M 0xFC0
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#define SFCTR_CH_LDPC_3SS_MCS8_C 0x4364
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#define SFCTR_CH_LDPC_3SS_MCS8_C_M 0x3F000
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#define SFCTR_CH_LDPC_3SS_MCS9_C 0x4364
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#define SFCTR_CH_LDPC_3SS_MCS9_C_M 0xFC0000
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#define SFCTR_CH_LDPC_4SS_MCS0_C 0x4364
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#define SFCTR_CH_LDPC_4SS_MCS0_C_M 0x3F000000
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#define SFCTR_CH_LDPC_4SS_MCS1_C 0x4368
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#define SFCTR_CH_LDPC_4SS_MCS1_C_M 0x3F
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#define SFCTR_CH_LDPC_4SS_MCS10_C 0x4368
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#define SFCTR_CH_LDPC_4SS_MCS10_C_M 0xFC0
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#define SFCTR_CH_LDPC_4SS_MCS11_C 0x4368
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#define SFCTR_CH_LDPC_4SS_MCS11_C_M 0x3F000
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#define SFCTR_CH_LDPC_4SS_MCS2_C 0x4368
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#define SFCTR_CH_LDPC_4SS_MCS2_C_M 0xFC0000
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#define SFCTR_CH_LDPC_4SS_MCS3_C 0x4368
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#define SFCTR_CH_LDPC_4SS_MCS3_C_M 0x3F000000
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#define SFCTR_CH_LDPC_4SS_MCS4_C 0x436C
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#define SFCTR_CH_LDPC_4SS_MCS4_C_M 0x3F
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#define SFCTR_CH_LDPC_4SS_MCS5_C 0x436C
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#define SFCTR_CH_LDPC_4SS_MCS5_C_M 0xFC0
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#define SFCTR_CH_LDPC_4SS_MCS6_C 0x436C
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#define SFCTR_CH_LDPC_4SS_MCS6_C_M 0x3F000
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#define SFCTR_CH_LDPC_4SS_MCS7_C 0x436C
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#define SFCTR_CH_LDPC_4SS_MCS7_C_M 0xFC0000
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#define SFCTR_CH_LDPC_4SS_MCS8_C 0x436C
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#define SFCTR_CH_LDPC_4SS_MCS8_C_M 0x3F000000
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#define SFCTR_CH_LDPC_4SS_MCS9_C 0x4370
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#define SFCTR_CH_LDPC_4SS_MCS9_C_M 0x3F
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#define SFCTR_CH_LAGCY_12M_C 0x4370
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#define SFCTR_CH_LAGCY_12M_C_M 0xFC0
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#define SFCTR_CH_LAGCY_18M_C 0x4370
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#define SFCTR_CH_LAGCY_18M_C_M 0x3F000
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#define SFCTR_CH_LAGCY_24M_C 0x4370
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#define SFCTR_CH_LAGCY_24M_C_M 0xFC0000
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#define SFCTR_CH_LAGCY_36M_C 0x4370
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#define SFCTR_CH_LAGCY_36M_C_M 0x3F000000
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#define SFCTR_CH_LAGCY_48M_C 0x4374
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#define SFCTR_CH_LAGCY_48M_C_M 0x3F
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#define SFCTR_CH_LAGCY_54M_C 0x4374
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#define SFCTR_CH_LAGCY_54M_C_M 0xFC0
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#define SFCTR_CH_LAGCY_6M_C 0x4374
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#define SFCTR_CH_LAGCY_6M_C_M 0x3F000
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#define SFCTR_CH_LAGCY_9M_C 0x4374
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#define SFCTR_CH_LAGCY_9M_C_M 0xFC0000
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#define FCTR_AWGN_LAGCY_2R_C 0x4374
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#define FCTR_AWGN_LAGCY_2R_C_M 0xF000000
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#define FCTR_CH_LAGCY_2R_C 0x4374
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#define FCTR_CH_LAGCY_2R_C_M 0xF0000000
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#define FCTR_BCC_STBC_CH_16QAM_C 0x4378
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#define FCTR_BCC_STBC_CH_16QAM_C_M 0xF
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#define FCTR_BCC_STBC_CH_256QAM_C 0x4378
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#define FCTR_BCC_STBC_CH_256QAM_C_M 0xF0
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#define FCTR_BCC_STBC_CH_64QAM_C 0x4378
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#define FCTR_BCC_STBC_CH_64QAM_C_M 0xF00
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#define FCTR_BCC_STBC_CH_BPSK_C 0x4378
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#define FCTR_BCC_STBC_CH_BPSK_C_M 0xF000
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#define FCTR_BCC_STBC_CH_QPSK_C 0x4378
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#define FCTR_BCC_STBC_CH_QPSK_C_M 0xF0000
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#define FCTR_BCC_STBC_I_16QAM_C 0x4378
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#define FCTR_BCC_STBC_I_16QAM_C_M 0xF00000
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#define FCTR_BCC_STBC_I_256QAM_C 0x4378
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#define FCTR_BCC_STBC_I_256QAM_C_M 0xF000000
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#define FCTR_BCC_STBC_I_64QAM_C 0x4378
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#define FCTR_BCC_STBC_I_64QAM_C_M 0xF0000000
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#define FCTR_BCC_STBC_I_BPSK_C 0x437C
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#define FCTR_BCC_STBC_I_BPSK_C_M 0xF
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#define FCTR_BCC_STBC_I_QPSK_C 0x437C
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#define FCTR_BCC_STBC_I_QPSK_C_M 0xF0
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#define FCTR_HE_BCC_1SS_CH_16QAM_C 0x437C
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#define FCTR_HE_BCC_1SS_CH_16QAM_C_M 0xF00
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#define FCTR_HE_BCC_1SS_CH_256QAM_C 0x437C
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#define FCTR_HE_BCC_1SS_CH_256QAM_C_M 0xF000
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#define FCTR_HE_BCC_1SS_CH_64QAM_C 0x437C
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#define FCTR_HE_BCC_1SS_CH_64QAM_C_M 0xF0000
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#define FCTR_HE_BCC_1SS_CH_BPSK_C 0x437C
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#define FCTR_HE_BCC_1SS_CH_BPSK_C_M 0xF00000
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#define FCTR_HE_BCC_1SS_CH_QPSK_C 0x437C
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#define FCTR_HE_BCC_1SS_CH_QPSK_C_M 0xF000000
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#define FCTR_HE_BCC_1SS_I_16QAM_C 0x437C
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#define FCTR_HE_BCC_1SS_I_16QAM_C_M 0xF0000000
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#define FCTR_HE_BCC_1SS_I_256QAM_C 0x4380
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#define FCTR_HE_BCC_1SS_I_256QAM_C_M 0xF
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#define FCTR_HE_BCC_1SS_I_64QAM_C 0x4380
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#define FCTR_HE_BCC_1SS_I_64QAM_C_M 0xF0
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#define FCTR_HE_BCC_1SS_I_BPSK_C 0x4380
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#define FCTR_HE_BCC_1SS_I_BPSK_C_M 0xF00
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#define FCTR_HE_BCC_1SS_I_QPSK_C 0x4380
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#define FCTR_HE_BCC_1SS_I_QPSK_C_M 0xF000
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#define FCTR_HE_BCC_2SS_CH_16QAM_C 0x4380
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#define FCTR_HE_BCC_2SS_CH_16QAM_C_M 0xF0000
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#define FCTR_HE_BCC_2SS_CH_256QAM_C 0x4380
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#define FCTR_HE_BCC_2SS_CH_256QAM_C_M 0xF00000
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#define FCTR_HE_BCC_2SS_CH_64QAM_C 0x4380
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#define FCTR_HE_BCC_2SS_CH_64QAM_C_M 0xF000000
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#define FCTR_HE_BCC_2SS_CH_BPSK_C 0x4380
|
#define FCTR_HE_BCC_2SS_CH_BPSK_C_M 0xF0000000
|
#define FCTR_HE_BCC_2SS_CH_QPSK_C 0x4384
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#define FCTR_HE_BCC_2SS_CH_QPSK_C_M 0xF
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#define FCTR_HE_BCC_2SS_I_16QAM_C 0x4384
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#define FCTR_HE_BCC_2SS_I_16QAM_C_M 0xF0
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#define FCTR_HE_BCC_2SS_I_256QAM_C 0x4384
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#define FCTR_HE_BCC_2SS_I_256QAM_C_M 0xF00
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#define FCTR_HE_BCC_2SS_I_64QAM_C 0x4384
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#define FCTR_HE_BCC_2SS_I_64QAM_C_M 0xF000
|
#define FCTR_HE_BCC_2SS_I_BPSK_C 0x4384
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#define FCTR_HE_BCC_2SS_I_BPSK_C_M 0xF0000
|
#define FCTR_HE_BCC_2SS_I_QPSK_C 0x4384
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#define FCTR_HE_BCC_2SS_I_QPSK_C_M 0xF00000
|
#define FCTR_HE_BCC_STBC_CH_16QAM_C 0x4384
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#define FCTR_HE_BCC_STBC_CH_16QAM_C_M 0xF000000
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#define FCTR_HE_BCC_STBC_CH_256QAM_C 0x4384
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#define FCTR_HE_BCC_STBC_CH_256QAM_C_M 0xF0000000
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#define FCTR_HE_BCC_STBC_CH_64QAM_C 0x4388
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#define FCTR_HE_BCC_STBC_CH_64QAM_C_M 0xF
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#define FCTR_HE_BCC_STBC_CH_BPSK_C 0x4388
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#define FCTR_HE_BCC_STBC_CH_BPSK_C_M 0xF0
|
#define FCTR_HE_BCC_STBC_CH_QPSK_C 0x4388
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#define FCTR_HE_BCC_STBC_CH_QPSK_C_M 0xF00
|
#define FCTR_HE_BCC_STBC_I_16QAM_C 0x4388
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#define FCTR_HE_BCC_STBC_I_16QAM_C_M 0xF000
|
#define FCTR_HE_BCC_STBC_I_256QAM_C 0x4388
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#define FCTR_HE_BCC_STBC_I_256QAM_C_M 0xF0000
|
#define FCTR_HE_BCC_STBC_I_64QAM_C 0x4388
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#define FCTR_HE_BCC_STBC_I_64QAM_C_M 0xF00000
|
#define FCTR_HE_BCC_STBC_I_BPSK_C 0x4388
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#define FCTR_HE_BCC_STBC_I_BPSK_C_M 0xF000000
|
#define FCTR_HE_BCC_STBC_I_QPSK_C 0x4388
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#define FCTR_HE_BCC_STBC_I_QPSK_C_M 0xF0000000
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#define FCTR_HE_LDPC_1SS_CH_C 0x438C
|
#define FCTR_HE_LDPC_1SS_CH_C_M 0xF
|
#define FCTR_HE_LDPC_1SS_I_C 0x438C
|
#define FCTR_HE_LDPC_1SS_I_C_M 0xF0
|
#define FCTR_HE_LDPC_2SS_CH_C 0x438C
|
#define FCTR_HE_LDPC_2SS_CH_C_M 0xF00
|
#define FCTR_HE_LDPC_2SS_I_C 0x438C
|
#define FCTR_HE_LDPC_2SS_I_C_M 0xF000
|
#define FCTR_HE_LDPC_STBC_CH_C 0x438C
|
#define FCTR_HE_LDPC_STBC_CH_C_M 0xF0000
|
#define FCTR_HE_LDPC_STBC_I_C 0x438C
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#define FCTR_HE_LDPC_STBC_I_C_M 0xF00000
|
#define FCTR_HE_MU_BCC_CH_C 0x438C
|
#define FCTR_HE_MU_BCC_CH_C_M 0xF000000
|
#define FCTR_HE_MU_BCC_I_C 0x438C
|
#define FCTR_HE_MU_BCC_I_C_M 0xF0000000
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#define FCTR_HE_MU_LDPC_CH_C 0x4390
|
#define FCTR_HE_MU_LDPC_CH_C_M 0xF
|
#define FCTR_HE_MU_LDPC_I_C 0x4390
|
#define FCTR_HE_MU_LDPC_I_C_M 0xF0
|
#define FCTR_HE_MU_NOMUIC_BCC_CH_C 0x4390
|
#define FCTR_HE_MU_NOMUIC_BCC_CH_C_M 0xF00
|
#define FCTR_HE_MU_NOMUIC_BCC_I_C 0x4390
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#define FCTR_HE_MU_NOMUIC_BCC_I_C_M 0xF000
|
#define FCTR_HE_MU_NOMUIC_LDPC_CH_C 0x4390
|
#define FCTR_HE_MU_NOMUIC_LDPC_CH_C_M 0xF0000
|
#define FCTR_HE_MU_NOMUIC_LDPC_I_C 0x4390
|
#define FCTR_HE_MU_NOMUIC_LDPC_I_C_M 0xF00000
|
#define FCTR_LDPC_STBC_CH_C 0x4390
|
#define FCTR_LDPC_STBC_CH_C_M 0xF000000
|
#define FCTR_LDPC_STBC_I_C 0x4390
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#define FCTR_LDPC_STBC_I_C_M 0xF0000000
|
#define LLR_COEF_H_DELAY_SPREAD_C 0x4394
|
#define LLR_COEF_H_DELAY_SPREAD_C_M 0x7
|
#define LLR_COEF_L_DELAY_SPREAD_C 0x4394
|
#define LLR_COEF_L_DELAY_SPREAD_C_M 0x38
|
#define LLR_COEF_TH_C 0x4394
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#define LLR_COEF_TH_C_M 0x1C0
|
#define LLR_SCAL_MODE_C 0x4394
|
#define LLR_SCAL_MODE_C_M 0xE00
|
#define LDPC_R12_MAX_ITER_C 0x4398
|
#define LDPC_R12_MAX_ITER_C_M 0xF
|
#define LDPC_R23_MAX_ITER_C 0x4398
|
#define LDPC_R23_MAX_ITER_C_M 0xF0
|
#define LDPC_R34_MAX_ITER_C 0x4398
|
#define LDPC_R34_MAX_ITER_C_M 0xF00
|
#define LDPC_R56_MAX_ITER_C 0x4398
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#define LDPC_R56_MAX_ITER_C_M 0xF000
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#define LDPC_STBC_MAX_ITER_C 0x4398
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#define LDPC_STBC_MAX_ITER_C_M 0xF0000
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#define SEL_DEFAULT_ITER_C 0x4398
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#define SEL_DEFAULT_ITER_C_M 0x100000
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#define PACKET_FMT_C 0x43A0
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#define PACKET_FMT_C_M 0x7
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#define PFD_EN_C 0x43A0
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#define PFD_EN_C_M 0x8
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#define PFD_HE_ER_BLOCK_C 0x43A0
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#define PFD_HE_ER_BLOCK_C_M 0x10
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#define PFD_HE_MU_BLOCK_C 0x43A0
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#define PFD_HE_MU_BLOCK_C_M 0x20
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#define PFD_HE_SU_BLOCK_C 0x43A0
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#define PFD_HE_SU_BLOCK_C_M 0x40
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#define PFD_HE_TB_BLOCK_C 0x43A0
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#define PFD_HE_TB_BLOCK_C_M 0x80
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#define PFD_HT_BLOCK_C 0x43A0
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#define PFD_HT_BLOCK_C_M 0x100
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#define PFD_LEG_BLOCK_C 0x43A0
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#define PFD_LEG_BLOCK_C_M 0x200
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#define PFD_VHT_BLOCK_C 0x43A0
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#define PFD_VHT_BLOCK_C_M 0x400
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#define MANUAL_SIMI_FLAG_EN_C 0x43A0
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#define MANUAL_SIMI_FLAG_EN_C_M 0x800
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#define SIMI_FLAG_C 0x43A0
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#define SIMI_FLAG_C_M 0x1000
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#define LDPC_SU_SHARE_ITER_EN_C 0x43A8
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#define LDPC_SU_SHARE_ITER_EN_C_M 0x1
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#define BOARDCAST_STA_ID_C 0x43B0
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#define BOARDCAST_STA_ID_C_M 0x7FF
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#define TARGET_STA_ID_0_C 0x43B0
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#define TARGET_STA_ID_0_C_M 0x3FF800
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#define TARGET_BSS_COLOR_0_C 0x43B0
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#define TARGET_BSS_COLOR_0_C_M 0xFC00000
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#define BSS_COLOR_MAP_VLD_0_C 0x43B0
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#define BSS_COLOR_MAP_VLD_0_C_M 0x10000000
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#define BSS_COLOR_MAP_VLD_1_C 0x43B0
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#define BSS_COLOR_MAP_VLD_1_C_M 0x20000000
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#define BSS_COLOR_MAP_VLD_2_C 0x43B0
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#define BSS_COLOR_MAP_VLD_2_C_M 0x40000000
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#define BSS_COLOR_MAP_VLD_3_C 0x43B0
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#define BSS_COLOR_MAP_VLD_3_C_M 0x80000000
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#define TARGET_STA_ID_1_C 0x43B4
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#define TARGET_STA_ID_1_C_M 0x7FF
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#define TARGET_STA_ID_2_C 0x43B4
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#define TARGET_STA_ID_2_C_M 0x3FF800
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#define TARGET_BSS_COLOR_1_C 0x43B4
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#define TARGET_BSS_COLOR_1_C_M 0xFC00000
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#define VHT_SIGB_NDP_CHK_EN_C 0x43B4
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#define VHT_SIGB_NDP_CHK_EN_C_M 0x10000000
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#define SNIFFER_MODE_EN_C 0x43B4
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#define SNIFFER_MODE_EN_C_M 0x20000000
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#define TARGET_STA_ID_3_C 0x43B8
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#define TARGET_STA_ID_3_C_M 0x7FF
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#define TARGET_BSS_COLOR_2_C 0x43B8
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#define TARGET_BSS_COLOR_2_C_M 0x1F800
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#define TARGET_BSS_COLOR_3_C 0x43B8
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#define TARGET_BSS_COLOR_3_C_M 0x7E0000
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#define MIN_SIVAL_TH_C 0x43BC
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#define MIN_SIVAL_TH_C_M 0xFF
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#define COND_TH_C 0x43BC
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#define COND_TH_C_M 0x3F00
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#define COND_NUM_COUNT_NORM_FCTR_C 0x43BC
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#define COND_NUM_COUNT_NORM_FCTR_C_M 0x4000
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#define MIN_SIGVAL_COUNT_NORM_FCTR_C 0x43BC
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#define MIN_SIGVAL_COUNT_NORM_FCTR_C_M 0x8000
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#define SIG_RPT_GRP_FCTR_C 0x43BC
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#define SIG_RPT_GRP_FCTR_C_M 0x10000
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#define TRACKING_RSV_C 0x43C0
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#define TRACKING_RSV_C_M 0xFFFFFFFF
|
#define NOISE_VAR_TH_0_C 0x43C4
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#define NOISE_VAR_TH_0_C_M 0xFFFFFF
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#define USER_EXIST_N1_C 0x43C4
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#define USER_EXIST_N1_C_M 0xFF000000
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#define NOISE_VAR_TH_1_C 0x43C8
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#define NOISE_VAR_TH_1_C_M 0xFFFFFF
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#define USER_EXIST_N2_C 0x43C8
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#define USER_EXIST_N2_C_M 0xFF000000
|
#define FORCE_RCFO_VAL_C 0x43CC
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#define FORCE_RCFO_VAL_C_M 0xFFFF
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#define LPBW_KI_E_C 0x43CC
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#define LPBW_KI_E_C_M 0xFFFF0000
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#define LPBW_KP_E_C 0x43D0
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#define LPBW_KP_E_C_M 0xFFF
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#define CH_TRACKING_NST_C 0x43D0
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#define CH_TRACKING_NST_C_M 0x3FF000
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#define EVM_RPT_SCIDX_C 0x43D0
|
#define EVM_RPT_SCIDX_C_M 0xFFC00000
|
#define LPBW_OUT_LMT_C 0x43D4
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#define LPBW_OUT_LMT_C_M 0x3FF
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#define USER_EXIST_CSI_C 0x43D4
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#define USER_EXIST_CSI_C_M 0xFFC00
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#define USER_EXIST_N3_C 0x43D4
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#define USER_EXIST_N3_C_M 0xFF00000
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#define USER_EXIST_T1_C 0x43D4
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#define USER_EXIST_T1_C_M 0xF0000000
|
#define USER_EXIST_N4_C 0x43D8
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#define USER_EXIST_N4_C_M 0xFF
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#define USER_EXIST_N9_C 0x43D8
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#define USER_EXIST_N9_C_M 0xFF00
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#define USER_EXIST_NU_C 0x43D8
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#define USER_EXIST_NU_C_M 0xFF0000
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#define ALPHA_FOR_CFO_DATA_00_C 0x43D8
|
#define ALPHA_FOR_CFO_DATA_00_C_M 0x3F000000
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#define EVM_RPT_NSC0_C 0x43D8
|
#define EVM_RPT_NSC0_C_M 0xC0000000
|
#define ALPHA_FOR_CFO_DATA_01_C 0x43DC
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#define ALPHA_FOR_CFO_DATA_01_C_M 0x3F
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#define ALPHA_FOR_CFO_DATA_02_C 0x43DC
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#define ALPHA_FOR_CFO_DATA_02_C_M 0xFC0
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#define ALPHA_FOR_CFO_DATA_03_C 0x43DC
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#define ALPHA_FOR_CFO_DATA_03_C_M 0x3F000
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#define ALPHA_FOR_CFO_DATA_10_C 0x43DC
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#define ALPHA_FOR_CFO_DATA_10_C_M 0xFC0000
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#define ALPHA_FOR_CFO_DATA_11_C 0x43DC
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#define ALPHA_FOR_CFO_DATA_11_C_M 0x3F000000
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#define EVM_RPT_NSC1_C 0x43DC
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#define EVM_RPT_NSC1_C_M 0xC0000000
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#define ALPHA_FOR_CFO_DATA_12_C 0x43E0
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#define ALPHA_FOR_CFO_DATA_12_C_M 0x3F
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#define ALPHA_FOR_CFO_DATA_13_C 0x43E0
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#define ALPHA_FOR_CFO_DATA_13_C_M 0xFC0
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#define ALPHA_FOR_CFO_DATA_20_C 0x43E0
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#define ALPHA_FOR_CFO_DATA_20_C_M 0x3F000
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#define ALPHA_FOR_CFO_DATA_21_C 0x43E0
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#define ALPHA_FOR_CFO_DATA_21_C_M 0xFC0000
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#define ALPHA_FOR_CFO_DATA_22_C 0x43E0
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#define ALPHA_FOR_CFO_DATA_22_C_M 0x3F000000
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#define EVM_RPT_ALPHA0_C 0x43E0
|
#define EVM_RPT_ALPHA0_C_M 0xC0000000
|
#define ALPHA_FOR_CFO_DATA_23_C 0x43E4
|
#define ALPHA_FOR_CFO_DATA_23_C_M 0x3F
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#define ALPHA_FOR_CFO_PILOT_00_C 0x43E4
|
#define ALPHA_FOR_CFO_PILOT_00_C_M 0xFC0
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#define ALPHA_FOR_CFO_PILOT_01_C 0x43E4
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#define ALPHA_FOR_CFO_PILOT_01_C_M 0x3F000
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#define ALPHA_FOR_CFO_PILOT_02_C 0x43E4
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#define ALPHA_FOR_CFO_PILOT_02_C_M 0xFC0000
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#define ALPHA_FOR_CFO_PILOT_03_C 0x43E4
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#define ALPHA_FOR_CFO_PILOT_03_C_M 0x3F000000
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#define EVM_RPT_ALPHA1_C 0x43E4
|
#define EVM_RPT_ALPHA1_C_M 0xC0000000
|
#define ALPHA_FOR_CFO_PILOT_10_C 0x43E8
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#define ALPHA_FOR_CFO_PILOT_10_C_M 0x3F
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#define ALPHA_FOR_CFO_PILOT_11_C 0x43E8
|
#define ALPHA_FOR_CFO_PILOT_11_C_M 0xFC0
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#define ALPHA_FOR_CFO_PILOT_12_C 0x43E8
|
#define ALPHA_FOR_CFO_PILOT_12_C_M 0x3F000
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#define ALPHA_FOR_CFO_PILOT_13_C 0x43E8
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#define ALPHA_FOR_CFO_PILOT_13_C_M 0xFC0000
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#define ALPHA_FOR_CFO_PILOT_20_C 0x43E8
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#define ALPHA_FOR_CFO_PILOT_20_C_M 0x3F000000
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#define N_HESYM_EXT_EN_C 0x43E8
|
#define N_HESYM_EXT_EN_C_M 0x40000000
|
#define CH_TRACKING_COEF_SEL_C 0x43E8
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#define CH_TRACKING_COEF_SEL_C_M 0x80000000
|
#define ALPHA_FOR_CFO_PILOT_21_C 0x43EC
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#define ALPHA_FOR_CFO_PILOT_21_C_M 0x3F
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#define ALPHA_FOR_CFO_PILOT_22_C 0x43EC
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#define ALPHA_FOR_CFO_PILOT_22_C_M 0xFC0
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#define ALPHA_FOR_CFO_PILOT_23_C 0x43EC
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#define ALPHA_FOR_CFO_PILOT_23_C_M 0x3F000
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#define ALPHA_FOR_H_00_C 0x43EC
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#define ALPHA_FOR_H_00_C_M 0xFC0000
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#define ALPHA_FOR_H_01_C 0x43EC
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#define ALPHA_FOR_H_01_C_M 0x3F000000
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#define CH_TRACKING_EN_C 0x43EC
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#define CH_TRACKING_EN_C_M 0x40000000
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#define CSI_WGT_BYPASS_CPE_EN_C 0x43EC
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#define CSI_WGT_BYPASS_CPE_EN_C_M 0x80000000
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#define ALPHA_FOR_H_02_C 0x43F0
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#define ALPHA_FOR_H_02_C_M 0x3F
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#define ALPHA_FOR_H_03_C 0x43F0
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#define ALPHA_FOR_H_03_C_M 0xFC0
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#define ALPHA_FOR_H_10_C 0x43F0
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#define ALPHA_FOR_H_10_C_M 0x3F000
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#define ALPHA_FOR_H_11_C 0x43F0
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#define ALPHA_FOR_H_11_C_M 0xFC0000
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#define ALPHA_FOR_H_12_C 0x43F0
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#define ALPHA_FOR_H_12_C_M 0x3F000000
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#define DATA_TRACKING_EN_C 0x43F0
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#define DATA_TRACKING_EN_C_M 0x40000000
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#define EVM_RPT_MODE_C 0x43F0
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#define EVM_RPT_MODE_C_M 0x80000000
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#define ALPHA_FOR_H_13_C 0x43F4
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#define ALPHA_FOR_H_13_C_M 0x3F
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#define ALPHA_FOR_H_20_C 0x43F4
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#define ALPHA_FOR_H_20_C_M 0xFC0
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#define ALPHA_FOR_H_21_C 0x43F4
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#define ALPHA_FOR_H_21_C_M 0x3F000
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#define ALPHA_FOR_H_22_C 0x43F4
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#define ALPHA_FOR_H_22_C_M 0xFC0000
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#define ALPHA_FOR_H_23_C 0x43F4
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#define ALPHA_FOR_H_23_C_M 0x3F000000
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#define FORCE_RCFO_EN_C 0x43F4
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#define FORCE_RCFO_EN_C_M 0x40000000
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#define LGY80_TRACKING_EN_C 0x43F4
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#define LGY80_TRACKING_EN_C_M 0x80000000
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#define ALPHA_FOR_NOISE_VAR_0_C 0x43F8
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#define ALPHA_FOR_NOISE_VAR_0_C_M 0x3F
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#define ALPHA_FOR_NOISE_VAR_1_C 0x43F8
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#define ALPHA_FOR_NOISE_VAR_1_C_M 0xFC0
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#define CH_TRACKING_A0_C 0x43F8
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#define CH_TRACKING_A0_C_M 0x3F000
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#define CH_TRACKING_A1_C 0x43F8
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#define CH_TRACKING_A1_C_M 0xFC0000
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#define CH_TRACKING_A1_LGY80_C 0x43F8
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#define CH_TRACKING_A1_LGY80_C_M 0x3F000000
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#define LOOP_DATA_EN_C 0x43F8
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#define LOOP_DATA_EN_C_M 0x40000000
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#define LOOP_FILTER_EN_C 0x43F8
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#define LOOP_FILTER_EN_C_M 0x80000000
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#define CH_TRACKING_A1_STBC_C 0x43FC
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#define CH_TRACKING_A1_STBC_C_M 0x3F
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#define CH_TRACKING_A2_C 0x43FC
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#define CH_TRACKING_A2_C_M 0xFC0
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#define CH_TRACKING_A2_LGY80_C 0x43FC
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#define CH_TRACKING_A2_LGY80_C_M 0x3F000
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#define CH_TRACKING_A2_STBC_C 0x43FC
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#define CH_TRACKING_A2_STBC_C_M 0xFC0000
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#define USER_EXIST_R1_C 0x43FC
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#define USER_EXIST_R1_C_M 0x3F000000
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#define NOISE_TRACKING_EN_C 0x43FC
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#define NOISE_TRACKING_EN_C_M 0x40000000
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#define SYMBOL_COUNT_SEL_C 0x43FC
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#define SYMBOL_COUNT_SEL_C_M 0x80000000
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#define USER_EXIST_R2_C 0x4400
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#define USER_EXIST_R2_C_M 0x3F
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#define USER_EXIST_R3_C 0x4400
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#define USER_EXIST_R3_C_M 0xFC0
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#define USER_EXIST_R4_C 0x4400
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#define USER_EXIST_R4_C_M 0x3F000
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#define USER_EXIST_R9_C 0x4400
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#define USER_EXIST_R9_C_M 0xFC0000
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#define CH_TRACKING_SYMB0_C 0x4400
|
#define CH_TRACKING_SYMB0_C_M 0x1F000000
|
#define CSI_WGT_BYPASS_CPE_TH_C 0x4400
|
#define CSI_WGT_BYPASS_CPE_TH_C_M 0xE0000000
|
#define CH_TRACKING_SYMB1_C 0x4404
|
#define CH_TRACKING_SYMB1_C_M 0x1F
|
#define LPBW_SEL_D0_C 0x4404
|
#define LPBW_SEL_D0_C_M 0x3E0
|
#define LPBW_SEL_D0_TB_C 0x4404
|
#define LPBW_SEL_D0_TB_C_M 0x7C00
|
#define LPBW_SEL_D1_C 0x4404
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#define LPBW_SEL_D1_C_M 0xF8000
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#define LPBW_SEL_D1_HESU_C 0x4404
|
#define LPBW_SEL_D1_HESU_C_M 0x1F00000
|
#define LPBW_SEL_D1_TB_C 0x4404
|
#define LPBW_SEL_D1_TB_C_M 0x3E000000
|
#define LPBW_SEL_D1_LGY_C 0x4408
|
#define LPBW_SEL_D1_LGY_C_M 0x1F
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#define LPBW_SEL_D1_STBC_C 0x4408
|
#define LPBW_SEL_D1_STBC_C_M 0x3E0
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#define LPBW_SEL_D2_C 0x4408
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#define LPBW_SEL_D2_C_M 0x7C00
|
#define LPBW_SEL_D2_HESU_C 0x4408
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#define LPBW_SEL_D2_HESU_C_M 0xF8000
|
#define LPBW_SEL_D2_TB_C 0x4408
|
#define LPBW_SEL_D2_TB_C_M 0x1F00000
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#define LPBW_SEL_D2_LGY_C 0x4408
|
#define LPBW_SEL_D2_LGY_C_M 0x3E000000
|
#define LPBW_SEL_D2_STBC_C 0x440C
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#define LPBW_SEL_D2_STBC_C_M 0x1F
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#define LPBW_SEL_P0_C 0x440C
|
#define LPBW_SEL_P0_C_M 0x3E0
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#define LPBW_SEL_P0_TB_C 0x440C
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#define LPBW_SEL_P0_TB_C_M 0x7C00
|
#define LPBW_SEL_P1_C 0x440C
|
#define LPBW_SEL_P1_C_M 0xF8000
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#define LPBW_SEL_P1_HESU_C 0x440C
|
#define LPBW_SEL_P1_HESU_C_M 0x1F00000
|
#define LPBW_SEL_P1_TB_C 0x440C
|
#define LPBW_SEL_P1_TB_C_M 0x3E000000
|
#define LPBW_SEL_P1_LGY_C 0x4410
|
#define LPBW_SEL_P1_LGY_C_M 0x1F
|
#define LPBW_SEL_P1_STBC_C 0x4410
|
#define LPBW_SEL_P1_STBC_C_M 0x3E0
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#define LPBW_SEL_P2_C 0x4410
|
#define LPBW_SEL_P2_C_M 0x7C00
|
#define LPBW_SEL_P2_HESU_C 0x4410
|
#define LPBW_SEL_P2_HESU_C_M 0xF8000
|
#define LPBW_SEL_P2_TB_C 0x4410
|
#define LPBW_SEL_P2_TB_C_M 0x1F00000
|
#define LPBW_SEL_P2_LGY_C 0x4410
|
#define LPBW_SEL_P2_LGY_C_M 0x3E000000
|
#define LPBW_SEL_P2_STBC_C 0x4414
|
#define LPBW_SEL_P2_STBC_C_M 0x1F
|
#define LPBW_SW_SYMB0_C 0x4414
|
#define LPBW_SW_SYMB0_C_M 0x3E0
|
#define LPBW_SW_SYMB1_C 0x4414
|
#define LPBW_SW_SYMB1_C_M 0x7C00
|
#define USER_EXIST_T4_C 0x4414
|
#define USER_EXIST_T4_C_M 0x78000
|
#define EVM_RPT_RUIDX_C 0x4414
|
#define EVM_RPT_RUIDX_C_M 0x380000
|
#define T2F_R_DC_EST_FORCE_I_C 0x4420
|
#define T2F_R_DC_EST_FORCE_I_C_M 0xFFF
|
#define T2F_R_DC_EST_FORCE_Q_C 0x4420
|
#define T2F_R_DC_EST_FORCE_Q_C_M 0xFFF000
|
#define T2F_R_GI2_COMB_THR_C 0x4420
|
#define T2F_R_GI2_COMB_THR_C_M 0x7F000000
|
#define T2F_R_BT_DYN_DC_EST_EN_C 0x4420
|
#define T2F_R_BT_DYN_DC_EST_EN_C_M 0x80000000
|
#define T2F_R_MANUAL_N_GI2_COMB_C 0x4424
|
#define T2F_R_MANUAL_N_GI2_COMB_C_M 0x7F
|
#define T2F_R_MANUAL_N_GI_COMB_C 0x4424
|
#define T2F_R_MANUAL_N_GI_COMB_C_M 0x1F80
|
#define T2F_R_MANUAL_N_SGI_COMB_C 0x4424
|
#define T2F_R_MANUAL_N_SGI_COMB_C_M 0x3E000
|
#define T2F_R_EXTRA_CH_LEN_C 0x4424
|
#define T2F_R_EXTRA_CH_LEN_C_M 0x3C0000
|
#define T2F_R_MANUAL_N_CDD_OFST_C 0x4424
|
#define T2F_R_MANUAL_N_CDD_OFST_C_M 0x3C00000
|
#define T2F_R_SBDRDY_WINDOW_LEN_C 0x4424
|
#define T2F_R_SBDRDY_WINDOW_LEN_C_M 0x1C000000
|
#define T2F_R_DC_EST_VHT_L1_C 0x4424
|
#define T2F_R_DC_EST_VHT_L1_C_M 0x20000000
|
#define T2F_R_GI2_COMB_LVL_C 0x4424
|
#define T2F_R_GI2_COMB_LVL_C_M 0x40000000
|
#define T2F_R_LNA_BASED_DC_UPD_EN_C 0x4424
|
#define T2F_R_LNA_BASED_DC_UPD_EN_C_M 0x80000000
|
#define T2F_R_VHT_LTF_DCCL_MODE_C 0x4428
|
#define T2F_R_VHT_LTF_DCCL_MODE_C_M 0x1
|
#define T2F_R_DC_EST_FORCE_EN_C 0x4428
|
#define T2F_R_DC_EST_FORCE_EN_C_M 0x2
|
#define T2F_R_MANUAL_GI_COMB_EN_C 0x4428
|
#define T2F_R_MANUAL_GI_COMB_EN_C_M 0x4
|
#define T2F_R_MANUAL_CDD_OFST_EN_C 0x4428
|
#define T2F_R_MANUAL_CDD_OFST_EN_C_M 0x8
|
#define T2F_R_RXFIR_COMP_BW20_FIR0_EN_C 0x4428
|
#define T2F_R_RXFIR_COMP_BW20_FIR0_EN_C_M 0x10
|
#define T2F_R_RXFIR_COMP_BW20_FIR1_EN_C 0x4428
|
#define T2F_R_RXFIR_COMP_BW20_FIR1_EN_C_M 0x20
|
#define T2F_R_RXFIR_COMP_BW20_FIR2_EN_C 0x4428
|
#define T2F_R_RXFIR_COMP_BW20_FIR2_EN_C_M 0x40
|
#define T2F_R_RXFIR_COMP_BW40_FIR0_EN_C 0x4428
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#define T2F_R_RXFIR_COMP_BW40_FIR0_EN_C_M 0x80
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#define T2F_R_RXFIR_COMP_BW40_FIR1_EN_C 0x4428
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#define T2F_R_RXFIR_COMP_BW40_FIR1_EN_C_M 0x100
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#define T2F_R_RXFIR_COMP_BW40_FIR2_EN_C 0x4428
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#define T2F_R_RXFIR_COMP_BW40_FIR2_EN_C_M 0x200
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#define T2F_R_RXFIR_COMP_BW80_FIR0_EN_C 0x4428
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#define T2F_R_RXFIR_COMP_BW80_FIR0_EN_C_M 0x400
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#define T2F_R_RXFIR_COMP_BW80_FIR1_EN_C 0x4428
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#define T2F_R_RXFIR_COMP_BW80_FIR1_EN_C_M 0x800
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#define T2F_R_RXFIR_COMP_EN_C 0x4428
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#define T2F_R_RXFIR_COMP_EN_C_M 0x1000
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#define DUMMY_0_C 0x442C
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#define DUMMY_0_C_M 0xFFFFFFFF
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#define DUMMY_1_C 0x4430
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#define DUMMY_1_C_M 0xFFFFFFFF
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#define DUMMY_2_C 0x4434
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#define DUMMY_2_C_M 0xFFFFFFFF
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#define DUMMY_3_C 0x4438
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#define DUMMY_3_C_M 0xFFFFFFFF
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#define HE_TB_CCA_END_C 0x443C
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#define HE_TB_CCA_END_C_M 0x3FF
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#define HE_TB_CCA_ON_C 0x443C
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#define HE_TB_CCA_ON_C_M 0xFFC00
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#define HE_TB_PD_COUNT_C 0x443C
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#define HE_TB_PD_COUNT_C_M 0x3FF00000
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#define MIMO_PS_OPT_C 0x443C
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#define MIMO_PS_OPT_C_M 0xC0000000
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#define HE_TB_RX_ON_C 0x4440
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#define HE_TB_RX_ON_C_M 0x3FF
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#define HE_TB_SBD_COUNT_C 0x4440
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#define HE_TB_SBD_COUNT_C_M 0xFFC00
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#define MAXOFST_C 0x4440
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#define MAXOFST_C_M 0x3FF00000
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#define R11RCCA_EN_C 0x4440
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#define R11RCCA_EN_C_M 0x40000000
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#define R55M_DET_EN_C 0x4440
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#define R55M_DET_EN_C_M 0x80000000
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#define MINOFST_C 0x4444
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#define MINOFST_C_M 0xFF
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#define FGT_FCTR_C 0x4444
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#define FGT_FCTR_C_M 0x7F00
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#define OFDMA_STF_OFST_C 0x4444
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#define OFDMA_STF_OFST_C_M 0x1F8000
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#define RF2SYNC_DLY_C 0x4444
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#define RF2SYNC_DLY_C_M 0x7E00000
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#define DFEDLY_BW20_C 0x4444
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#define DFEDLY_BW20_C_M 0xF8000000
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#define DFEDLY_BW40_C 0x4448
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#define DFEDLY_BW40_C_M 0x1F
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#define DFEDLY_BW80_C 0x4448
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#define DFEDLY_BW80_C_M 0x3E0
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#define OPPDLY_C 0x4448
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#define OPPDLY_C_M 0x7C00
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#define SYNCDLY_BW20_C 0x4448
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#define SYNCDLY_BW20_C_M 0xF8000
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#define SYNCDLY_BW40_C 0x4448
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#define SYNCDLY_BW40_C_M 0x1F00000
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#define SYNCDLY_BW80_C 0x4448
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#define SYNCDLY_BW80_C_M 0x3E000000
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#define PSD_TOP_EN_C 0x4448
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#define PSD_TOP_EN_C_M 0x40000000
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#define ACI_DET_EN_C 0x4448
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#define ACI_DET_EN_C_M 0x80000000
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#define NBIDLY_C 0x444C
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#define NBIDLY_C_M 0xF
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#define WAIT_SBD_TIME_C 0x444C
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#define WAIT_SBD_TIME_C_M 0xF0
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#define WAIT_SEG0_PD_TIME_C 0x444C
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#define WAIT_SEG0_PD_TIME_C_M 0xF00
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#define WAIT_SEG1_PD_TIME_C 0x444C
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#define WAIT_SEG1_PD_TIME_C_M 0xF000
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#define CCX_SOURCE_SEL_C 0x444C
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#define CCX_SOURCE_SEL_C_M 0x70000
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#define DATADLY_BW20_C 0x444C
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#define DATADLY_BW20_C_M 0x380000
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#define DATADLY_BW40_C 0x444C
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#define DATADLY_BW40_C_M 0x1C00000
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#define DATADLY_BW80_C 0x444C
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#define DATADLY_BW80_C_M 0xE000000
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#define SNR_REQ_1SS_MCS0_C 0x444C
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#define SNR_REQ_1SS_MCS0_C_M 0x70000000
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#define AGC_LPW_C 0x444C
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#define AGC_LPW_C_M 0x80000000
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#define SNR_REQ_1SS_MCS1_C 0x4450
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#define SNR_REQ_1SS_MCS1_C_M 0x7
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#define SNR_REQ_1SS_MCS10_C 0x4450
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#define SNR_REQ_1SS_MCS10_C_M 0x38
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#define SNR_REQ_1SS_MCS11_C 0x4450
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#define SNR_REQ_1SS_MCS11_C_M 0x1C0
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#define SNR_REQ_1SS_MCS2_C 0x4450
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#define SNR_REQ_1SS_MCS2_C_M 0xE00
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#define SNR_REQ_1SS_MCS3_C 0x4450
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#define SNR_REQ_1SS_MCS3_C_M 0x7000
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#define SNR_REQ_1SS_MCS4_C 0x4450
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#define SNR_REQ_1SS_MCS4_C_M 0x38000
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#define SNR_REQ_1SS_MCS5_C 0x4450
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#define SNR_REQ_1SS_MCS5_C_M 0x1C0000
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#define SNR_REQ_1SS_MCS6_C 0x4450
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#define SNR_REQ_1SS_MCS6_C_M 0xE00000
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#define SNR_REQ_1SS_MCS7_C 0x4450
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#define SNR_REQ_1SS_MCS7_C_M 0x7000000
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#define SNR_REQ_1SS_MCS8_C 0x4450
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#define SNR_REQ_1SS_MCS8_C_M 0x38000000
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#define ASSIGN_SBD_OPT_C 0x4450
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#define ASSIGN_SBD_OPT_C_M 0x40000000
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#define DCCL4SYNC_EN_C 0x4450
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#define DCCL4SYNC_EN_C_M 0x80000000
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#define SNR_REQ_1SS_MCS9_C 0x4454
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#define SNR_REQ_1SS_MCS9_C_M 0x7
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#define DFIR_EN_C 0x4454
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#define DFIR_EN_C_M 0x8
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#define HE_TB_CFO_EN_C 0x4454
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#define HE_TB_CFO_EN_C_M 0x10
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#define HE_TB_SYNC_FREE_C 0x4454
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#define HE_TB_SYNC_FREE_C_M 0x20
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#define I_ONLY_C 0x4454
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#define I_ONLY_C_M 0x40
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#define I_ONLY_S_C 0x4454
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#define I_ONLY_S_C_M 0x80
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#define IF_SEG0_PRIM80_C 0x4454
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#define IF_SEG0_PRIM80_C_M 0x100
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#define MIMO_PS_EN_C 0x4454
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#define MIMO_PS_EN_C_M 0x200
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#define NBI_EN_C 0x4454
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#define NBI_EN_C_M 0x400
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#define OFDMA_COMB_EN_C 0x4454
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#define OFDMA_COMB_EN_C_M 0x800
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#define POP_PD_FIRST_EN_C 0x4454
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#define POP_PD_FIRST_EN_C_M 0x1000
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#define SBDSEL_C 0x4454
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#define SBDSEL_C_M 0x2000
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#define SBDSEL_OFDMA_C 0x4454
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#define SBDSEL_OFDMA_C_M 0x4000
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#define SBF_EN_C 0x4454
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#define SBF_EN_C_M 0x8000
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#define SIMI_THD_0_C 0x445C
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#define SIMI_THD_0_C_M 0x3FF
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#define SIMI_THD_1_C 0x445C
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#define SIMI_THD_1_C_M 0xFFC00
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#define SIMI_THD_2_C 0x445C
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#define SIMI_THD_2_C_M 0x3FF00000
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#define EXTRATONE_PW_WGT_C 0x445C
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#define EXTRATONE_PW_WGT_C_M 0xC0000000
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#define SIMI_THD_3_C 0x4460
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#define SIMI_THD_3_C_M 0x3FF
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#define COMBINE_GAIN_GAP_DB_C 0x4460
|
#define COMBINE_GAIN_GAP_DB_C_M 0x7C00
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#define EXTRATONE_PW_CHK_SNR_THR_C 0x4460
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#define EXTRATONE_PW_CHK_SNR_THR_C_M 0x38000
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#define SNR_COMB_IDX_C 0x4460
|
#define SNR_COMB_IDX_C_M 0xC0000
|
#define EXTRATONE_PW_CHK_EN_C 0x4460
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#define EXTRATONE_PW_CHK_EN_C_M 0x100000
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#define MANUL_SNR_COMB_IDX_EN_C 0x4460
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#define MANUL_SNR_COMB_IDX_EN_C_M 0x200000
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#define POSITIVE_SIMI_DET_EN_C 0x4460
|
#define POSITIVE_SIMI_DET_EN_C_M 0x400000
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#define REAL_OR_ABS_SIMI_DET_C 0x4460
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#define REAL_OR_ABS_SIMI_DET_C_M 0x800000
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#define PATHA_T2F_R_DCCL_DATA_BKP1_C 0x4464
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#define PATHA_T2F_R_DCCL_DATA_BKP1_C_M 0xFFFFFFFF
|
#define PATHA_T2F_R_DCCL_DATA_BKP2_C 0x4468
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#define PATHA_T2F_R_DCCL_DATA_BKP2_C_M 0xFFFFFFFF
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#define PATHA_T2F_R_DC_EST_FILT_EN_C 0x446C
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#define PATHA_T2F_R_DC_EST_FILT_EN_C_M 0x1
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#define PATHB_T2F_R_DCCL_DATA_BKP1_C 0x4470
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#define PATHB_T2F_R_DCCL_DATA_BKP1_C_M 0xFFFFFFFF
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#define PATHB_T2F_R_DCCL_DATA_BKP2_C 0x4474
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#define PATHB_T2F_R_DCCL_DATA_BKP2_C_M 0xFFFFFFFF
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#define PATHB_T2F_R_DC_EST_FILT_EN_C 0x4478
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#define PATHB_T2F_R_DC_EST_FILT_EN_C_M 0x1
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#define SNR_LOSS_RPT_BUFFER_IDX_SEL_C 0x447C
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#define SNR_LOSS_RPT_BUFFER_IDX_SEL_C_M 0x3F
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#define SNR_LOSS_RPT_TYPE_C 0x447C
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#define SNR_LOSS_RPT_TYPE_C_M 0xC0
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#define NV_TYPE_C 0x447C
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#define NV_TYPE_C_M 0x100
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#define PRECODING_SCHEME_C 0x447C
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#define PRECODING_SCHEME_C_M 0x200
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#define TXBF_PL_2NSTS_TH0_STS0_C 0x4480
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#define TXBF_PL_2NSTS_TH0_STS0_C_M 0x7F
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#define TXBF_PL_2NSTS_TH0_STS1_C 0x4480
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#define TXBF_PL_2NSTS_TH0_STS1_C_M 0x3F80
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#define TXBF_PL_2NSTS_TH1_STS0_C 0x4480
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#define TXBF_PL_2NSTS_TH1_STS0_C_M 0x1FC000
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#define TXBF_PL_2NSTS_TH1_STS1_C 0x4480
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#define TXBF_PL_2NSTS_TH1_STS1_C_M 0xFE00000
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#define TXBF_PL_TH_SCAL_C 0x4480
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#define TXBF_PL_TH_SCAL_C_M 0x10000000
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#define TXBF_PL_EN_C 0x4480
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#define TXBF_PL_EN_C_M 0x20000000
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#define TXBF_PL_2NSTS_TH2_STS0_C 0x4484
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#define TXBF_PL_2NSTS_TH2_STS0_C_M 0x7F
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#define TXBF_PL_2NSTS_TH2_STS1_C 0x4484
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#define TXBF_PL_2NSTS_TH2_STS1_C_M 0x3F80
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#define TXBF_PL_2NSTS_TH3_STS0_C 0x4484
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#define TXBF_PL_2NSTS_TH3_STS0_C_M 0x1FC000
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#define TXBF_PL_2NSTS_TH3_STS1_C 0x4484
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#define TXBF_PL_2NSTS_TH3_STS1_C_M 0xFE00000
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#define STEER_MATRIX_INTERPOLATION_EN_C 0x4488
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#define STEER_MATRIX_INTERPOLATION_EN_C_M 0x4
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#define CFO_COMP_SEG0_312P5KHZ_0_C 0x448C
|
#define CFO_COMP_SEG0_312P5KHZ_0_C_M 0xFFF
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#define CFO_COMP_SEG0_312P5KHZ_1_C 0x448C
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#define CFO_COMP_SEG0_312P5KHZ_1_C_M 0xFFF000
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#define TX_TIMING_C 0x448C
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#define TX_TIMING_C_M 0xFF000000
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#define CFO_COMP_SEG0_312P5KHZ_2_C 0x4490
|
#define CFO_COMP_SEG0_312P5KHZ_2_C_M 0xFFF
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#define CFO_COMP_SEG0_312P5KHZ_3_C 0x4490
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#define CFO_COMP_SEG0_312P5KHZ_3_C_M 0xFFF000
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#define CFO_WGTING_C 0x4490
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#define CFO_WGTING_C_M 0xF000000
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#define PRIM_CH_C 0x4490
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#define PRIM_CH_C_M 0x70000000
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#define DAC_CLK_IDX_C 0x4490
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#define DAC_CLK_IDX_C_M 0x80000000
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#define CFO_COMP_SEG1_312P5KHZ_0_C 0x4494
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#define CFO_COMP_SEG1_312P5KHZ_0_C_M 0xFFF
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#define CFO_COMP_SEG1_312P5KHZ_1_C 0x4494
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#define CFO_COMP_SEG1_312P5KHZ_1_C_M 0xFFF000
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#define TX_BANDEDGE_CFG_C 0x4494
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#define TX_BANDEDGE_CFG_C_M 0x3000000
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#define SPATIAL_MAP_MODE_IDX_C 0x4494
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#define SPATIAL_MAP_MODE_IDX_C_M 0xC000000
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#define TXBF_BYPASS_EN_C 0x4494
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#define TXBF_BYPASS_EN_C_M 0x10000000
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#define CFO_COMP_SEG0_VLD_0_C 0x4494
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#define CFO_COMP_SEG0_VLD_0_C_M 0x20000000
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#define CFO_COMP_SEG0_VLD_1_C 0x4494
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#define CFO_COMP_SEG0_VLD_1_C_M 0x40000000
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#define CFO_COMP_SEG0_VLD_2_C 0x4494
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#define CFO_COMP_SEG0_VLD_2_C_M 0x80000000
|
#define CFO_COMP_SEG1_312P5KHZ_2_C 0x4498
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#define CFO_COMP_SEG1_312P5KHZ_2_C_M 0xFFF
|
#define CFO_COMP_SEG1_312P5KHZ_3_C 0x4498
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#define CFO_COMP_SEG1_312P5KHZ_3_C_M 0xFFF000
|
#define CFO_COMP_SEG0_VLD_3_C 0x4498
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#define CFO_COMP_SEG0_VLD_3_C_M 0x1000000
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#define CFO_COMP_SEG1_VLD_0_C 0x4498
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#define CFO_COMP_SEG1_VLD_0_C_M 0x2000000
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#define CFO_COMP_SEG1_VLD_1_C 0x4498
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#define CFO_COMP_SEG1_VLD_1_C_M 0x4000000
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#define CFO_COMP_SEG1_VLD_2_C 0x4498
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#define CFO_COMP_SEG1_VLD_2_C_M 0x8000000
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#define CFO_COMP_SEG1_VLD_3_C 0x4498
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#define CFO_COMP_SEG1_VLD_3_C_M 0x10000000
|
#define IDFT_OVER_SAMPLING_EN_C 0x4498
|
#define IDFT_OVER_SAMPLING_EN_C_M 0x20000000
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#define IF_BANDEDGE_C 0x4498
|
#define IF_BANDEDGE_C_M 0x40000000
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#define L_STF_TD_MODE_EN_C 0x4498
|
#define L_STF_TD_MODE_EN_C_M 0x80000000
|
#define TX_DAGC_PW_TOR_DB_C 0x449C
|
#define TX_DAGC_PW_TOR_DB_C_M 0x7
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#define TX_DAGC_EN_C 0x449C
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#define TX_DAGC_EN_C_M 0x8
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#define TX_DAGC_MODE_IDX_C 0x449C
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#define TX_DAGC_MODE_IDX_C_M 0x10
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#define TX_SCALE_C 0x44A0
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#define TX_SCALE_C_M 0x7F
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#define TX_CCK_BACKOFF_C 0x44A0
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#define TX_CCK_BACKOFF_C_M 0xF80
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#define TX_NORMAL_BACKOFF_C 0x44A0
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#define TX_NORMAL_BACKOFF_C_M 0x1F000
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#define TX_BACKOFF_OFST1_C 0x44A0
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#define TX_BACKOFF_OFST1_C_M 0xE0000
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#define TX_BACKOFF_OFST2_C 0x44A0
|
#define TX_BACKOFF_OFST2_C_M 0x700000
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#define TX_BACKOFF_OFST3_C 0x44A0
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#define TX_BACKOFF_OFST3_C_M 0x3800000
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#define TX_BACKOFF_BITMAP0_C 0x44A0
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#define TX_BACKOFF_BITMAP0_C_M 0xC000000
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#define TX_BACKOFF_BITMAP1_C 0x44A0
|
#define TX_BACKOFF_BITMAP1_C_M 0x30000000
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#define TX_BACKOFF_BITMAP2_C 0x44A0
|
#define TX_BACKOFF_BITMAP2_C_M 0xC0000000
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#define TX_BACKOFF_BITMAP3_C 0x44A4
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#define TX_BACKOFF_BITMAP3_C_M 0x3
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#define TX_BACKOFF_BITMAP4_C 0x44A4
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#define TX_BACKOFF_BITMAP4_C_M 0xC
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#define TX_BACKOFF_BITMAP5_C 0x44A4
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#define TX_BACKOFF_BITMAP5_C_M 0x30
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#define TX_BACKOFF_BITMAP6_C 0x44A4
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#define TX_BACKOFF_BITMAP6_C_M 0xC0
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#define TX_BACKOFF_BITMAP7_C 0x44A4
|
#define TX_BACKOFF_BITMAP7_C_M 0x300
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#define OV_RPT_RST_C 0x44A4
|
#define OV_RPT_RST_C_M 0x400
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#define OBW_TX_EN_C 0x44A8
|
#define OBW_TX_EN_C_M 0x1
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#define TX_N_PACKET_C 0x44AC
|
#define TX_N_PACKET_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_0_C 0x44B0
|
#define TXD_HE_SIGB_CH1_0_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_1_C 0x44B4
|
#define TXD_HE_SIGB_CH1_1_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_10_C 0x44B8
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#define TXD_HE_SIGB_CH1_10_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH1_11_C 0x44BC
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#define TXD_HE_SIGB_CH1_11_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_12_C 0x44C0
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#define TXD_HE_SIGB_CH1_12_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_13_C 0x44C4
|
#define TXD_HE_SIGB_CH1_13_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_14_C 0x44C8
|
#define TXD_HE_SIGB_CH1_14_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_15_C 0x44CC
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#define TXD_HE_SIGB_CH1_15_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH1_2_C 0x44D0
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#define TXD_HE_SIGB_CH1_2_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_3_C 0x44D4
|
#define TXD_HE_SIGB_CH1_3_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_4_C 0x44D8
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#define TXD_HE_SIGB_CH1_4_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_5_C 0x44DC
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#define TXD_HE_SIGB_CH1_5_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_6_C 0x44E0
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#define TXD_HE_SIGB_CH1_6_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH1_7_C 0x44E4
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#define TXD_HE_SIGB_CH1_7_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_8_C 0x44E8
|
#define TXD_HE_SIGB_CH1_8_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH1_9_C 0x44EC
|
#define TXD_HE_SIGB_CH1_9_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_0_C 0x44F0
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#define TXD_HE_SIGB_CH2_0_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_1_C 0x44F4
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#define TXD_HE_SIGB_CH2_1_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH2_10_C 0x44F8
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#define TXD_HE_SIGB_CH2_10_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH2_11_C 0x44FC
|
#define TXD_HE_SIGB_CH2_11_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_12_C 0x4500
|
#define TXD_HE_SIGB_CH2_12_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH2_13_C 0x4504
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#define TXD_HE_SIGB_CH2_13_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH2_14_C 0x4508
|
#define TXD_HE_SIGB_CH2_14_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH2_15_C 0x450C
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#define TXD_HE_SIGB_CH2_15_C_M 0xFFFFFFFF
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#define TXD_HE_SIGB_CH2_2_C 0x4510
|
#define TXD_HE_SIGB_CH2_2_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_3_C 0x4514
|
#define TXD_HE_SIGB_CH2_3_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_4_C 0x4518
|
#define TXD_HE_SIGB_CH2_4_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_5_C 0x451C
|
#define TXD_HE_SIGB_CH2_5_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_6_C 0x4520
|
#define TXD_HE_SIGB_CH2_6_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_7_C 0x4524
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#define TXD_HE_SIGB_CH2_7_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_8_C 0x4528
|
#define TXD_HE_SIGB_CH2_8_C_M 0xFFFFFFFF
|
#define TXD_HE_SIGB_CH2_9_C 0x452C
|
#define TXD_HE_SIGB_CH2_9_C_M 0xFFFFFFFF
|
#define USER0_DELMTER_C 0x4530
|
#define USER0_DELMTER_C_M 0xFFFFFFFF
|
#define USER0_EOF_PADDING_LEN_C 0x4534
|
#define USER0_EOF_PADDING_LEN_C_M 0xFFFFFFFF
|
#define USER0_INIT_SEED_C 0x4538
|
#define USER0_INIT_SEED_C_M 0xFFFFFFFF
|
#define USER1_DELMTER_C 0x453C
|
#define USER1_DELMTER_C_M 0xFFFFFFFF
|
#define USER1_EOF_PADDING_LEN_C 0x4540
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#define USER1_EOF_PADDING_LEN_C_M 0xFFFFFFFF
|
#define USER1_INIT_SEED_C 0x4544
|
#define USER1_INIT_SEED_C_M 0xFFFFFFFF
|
#define USER2_DELMTER_C 0x4548
|
#define USER2_DELMTER_C_M 0xFFFFFFFF
|
#define USER2_EOF_PADDING_LEN_C 0x454C
|
#define USER2_EOF_PADDING_LEN_C_M 0xFFFFFFFF
|
#define USER2_INIT_SEED_C 0x4550
|
#define USER2_INIT_SEED_C_M 0xFFFFFFFF
|
#define USER3_DELMTER_C 0x4554
|
#define USER3_DELMTER_C_M 0xFFFFFFFF
|
#define USER3_EOF_PADDING_LEN_C 0x4558
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#define USER3_EOF_PADDING_LEN_C_M 0xFFFFFFFF
|
#define USER3_INIT_SEED_C 0x455C
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#define USER3_INIT_SEED_C_M 0xFFFFFFFF
|
#define TXD_VHT_SIGB0_C 0x4560
|
#define TXD_VHT_SIGB0_C_M 0x1FFFFFFF
|
#define MAC_TDRDY_EXT_CNT_I_C 0x4560
|
#define MAC_TDRDY_EXT_CNT_I_C_M 0xE0000000
|
#define TXD_VHT_SIGB1_C 0x4564
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#define TXD_VHT_SIGB1_C_M 0x1FFFFFFF
|
#define MAC_TX_INFO_DLY_CNT_I_C 0x4564
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#define MAC_TX_INFO_DLY_CNT_I_C_M 0xE0000000
|
#define TXD_VHT_SIGB2_C 0x4568
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#define TXD_VHT_SIGB2_C_M 0x1FFFFFFF
|
#define TXCOMCT_HE_SIGB_MCS_C 0x4568
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#define TXCOMCT_HE_SIGB_MCS_C_M 0xE0000000
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#define TXD_VHT_SIGB3_C 0x456C
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#define TXD_VHT_SIGB3_C_M 0x1FFFFFFF
|
#define TXCOMCT_N_LTF_C 0x456C
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#define TXCOMCT_N_LTF_C_M 0xE0000000
|
#define TXD_SIGA1_C 0x4570
|
#define TXD_SIGA1_C_M 0x3FFFFFF
|
#define TAR_TXINFO_TXTP_C 0x4570
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#define TAR_TXINFO_TXTP_C_M 0xFC000000
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#define TXD_SIGA2_C 0x4574
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#define TXD_SIGA2_C_M 0x3FFFFFF
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#define TXINFO_RATE_BIAS_C 0x4574
|
#define TXINFO_RATE_BIAS_C_M 0xFC000000
|
#define TXD_LSIG_C 0x4578
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#define TXD_LSIG_C_M 0xFFFFFF
|
#define TXINFO_CCA_PW_TH_C 0x4578
|
#define TXINFO_CCA_PW_TH_C_M 0xFF000000
|
#define TX_PADDING_ZEROS_50NS_C 0x457C
|
#define TX_PADDING_ZEROS_50NS_C_M 0x1FFFFF
|
#define TXTIMCT_N_SYM_C 0x457C
|
#define TXTIMCT_N_SYM_C_M 0xFFE00000
|
#define USER0_SERVICE_C 0x4580
|
#define USER0_SERVICE_C_M 0xFFFF
|
#define USER1_SERVICE_C 0x4580
|
#define USER1_SERVICE_C_M 0xFFFF0000
|
#define USER2_SERVICE_C 0x4584
|
#define USER2_SERVICE_C_M 0xFFFF
|
#define USER3_SERVICE_C 0x4584
|
#define USER3_SERVICE_C_M 0xFFFF0000
|
#define USER0_MDPU_LEN_BYTE_C 0x4588
|
#define USER0_MDPU_LEN_BYTE_C_M 0x3FFF
|
#define USER1_MDPU_LEN_BYTE_C 0x4588
|
#define USER1_MDPU_LEN_BYTE_C_M 0xFFFC000
|
#define TXINFO_OBW_CTS2SELF_DUP_TYPE_C 0x4588
|
#define TXINFO_OBW_CTS2SELF_DUP_TYPE_C_M 0xF0000000
|
#define USER2_MDPU_LEN_BYTE_C 0x458C
|
#define USER2_MDPU_LEN_BYTE_C_M 0x3FFF
|
#define USER3_MDPU_LEN_BYTE_C 0x458C
|
#define USER3_MDPU_LEN_BYTE_C_M 0xFFFC000
|
#define TXINFO_PATH_EN_C 0x458C
|
#define TXINFO_PATH_EN_C_M 0xF0000000
|
#define TXUSRCT0_CSI_BUF_ID_C 0x4590
|
#define TXUSRCT0_CSI_BUF_ID_C_M 0x7FF
|
#define TXUSRCT1_CSI_BUF_ID_C 0x4590
|
#define TXUSRCT1_CSI_BUF_ID_C_M 0x3FF800
|
#define TXINFO_RF_GAIN_IDX_C 0x4590
|
#define TXINFO_RF_GAIN_IDX_C_M 0xFFC00000
|
#define TXUSRCT2_CSI_BUF_ID_C 0x4594
|
#define TXUSRCT2_CSI_BUF_ID_C_M 0x7FF
|
#define TXUSRCT3_CSI_BUF_ID_C 0x4594
|
#define TXUSRCT3_CSI_BUF_ID_C_M 0x3FF800
|
#define TXINFO_TX_PW_DBM_C 0x4594
|
#define TXINFO_TX_PW_DBM_C_M 0x7FC00000
|
#define AMPDU_4BYTES_ALIGN_EN_C 0x4594
|
#define AMPDU_4BYTES_ALIGN_EN_C_M 0x80000000
|
#define USER0_N_MPDU_C 0x4598
|
#define USER0_N_MPDU_C_M 0x1FF
|
#define USER1_N_MPDU_C 0x4598
|
#define USER1_N_MPDU_C_M 0x3FE00
|
#define USER2_N_MPDU_C 0x4598
|
#define USER2_N_MPDU_C_M 0x7FC0000
|
#define TXUSRCT0_PW_BOOST_FCTR_DB_C 0x4598
|
#define TXUSRCT0_PW_BOOST_FCTR_DB_C_M 0xF8000000
|
#define USER3_N_MPDU_C 0x459C
|
#define USER3_N_MPDU_C_M 0x1FF
|
#define TXINFO_CH20_WITH_DATA_C 0x459C
|
#define TXINFO_CH20_WITH_DATA_C_M 0x1FE00
|
#define TXINFO_N_USR_C 0x459C
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#define TXINFO_N_USR_C_M 0x1FE0000
|
#define TXINFO_TXCMD_TXTP_C 0x459C
|
#define TXINFO_TXCMD_TXTP_C_M 0x7E000000
|
#define BMODE_LOCKED_CLK_EN_C 0x459C
|
#define BMODE_LOCKED_CLK_EN_C_M 0x80000000
|
#define TXUSRCT0_RU_ALLOC_C 0x45A0
|
#define TXUSRCT0_RU_ALLOC_C_M 0xFF
|
#define TXUSRCT0_U_ID_C 0x45A0
|
#define TXUSRCT0_U_ID_C_M 0xFF00
|
#define TXUSRCT1_RU_ALLOC_C 0x45A0
|
#define TXUSRCT1_RU_ALLOC_C_M 0xFF0000
|
#define TXUSRCT1_U_ID_C 0x45A0
|
#define TXUSRCT1_U_ID_C_M 0xFF000000
|
#define TXUSRCT2_RU_ALLOC_C 0x45A4
|
#define TXUSRCT2_RU_ALLOC_C_M 0xFF
|
#define TXUSRCT2_U_ID_C 0x45A4
|
#define TXUSRCT2_U_ID_C_M 0xFF00
|
#define TXUSRCT3_RU_ALLOC_C 0x45A4
|
#define TXUSRCT3_RU_ALLOC_C_M 0xFF0000
|
#define TXUSRCT3_U_ID_C 0x45A4
|
#define TXUSRCT3_U_ID_C_M 0xFF000000
|
#define TXTIMCT_N_SYM_HESIGB_C 0x45A8
|
#define TXTIMCT_N_SYM_HESIGB_C_M 0x3F
|
#define TXUSRCT0_MCS_C 0x45A8
|
#define TXUSRCT0_MCS_C_M 0xFC0
|
#define TXUSRCT1_MCS_C 0x45A8
|
#define TXUSRCT1_MCS_C_M 0x3F000
|
#define TXUSRCT2_MCS_C 0x45A8
|
#define TXUSRCT2_MCS_C_M 0xFC0000
|
#define TXUSRCT3_MCS_C 0x45A8
|
#define TXUSRCT3_MCS_C_M 0x3F000000
|
#define BMODE_RATE_IDX_C 0x45A8
|
#define BMODE_RATE_IDX_C_M 0xC0000000
|
#define TXUSRCT1_PW_BOOST_FCTR_DB_C 0x45AC
|
#define TXUSRCT1_PW_BOOST_FCTR_DB_C_M 0x1F
|
#define TXUSRCT2_PW_BOOST_FCTR_DB_C 0x45AC
|
#define TXUSRCT2_PW_BOOST_FCTR_DB_C_M 0x3E0
|
#define TXUSRCT3_PW_BOOST_FCTR_DB_C 0x45AC
|
#define TXUSRCT3_PW_BOOST_FCTR_DB_C_M 0x7C00
|
#define TXINFO_PPDU_TYPE_C 0x45AC
|
#define TXINFO_PPDU_TYPE_C_M 0x78000
|
#define TXINFO_TX_SWING_C 0x45AC
|
#define TXINFO_TX_SWING_C_M 0x780000
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#define TXINFO_TXSC_C 0x45AC
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#define TXINFO_TXSC_C_M 0x7800000
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#define TXINFO_CFO_COMP_C 0x45AC
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#define TXINFO_CFO_COMP_C_M 0x38000000
|
#define MAC_TX_U_ID_PHASE_OPT_T_C 0x45AC
|
#define MAC_TX_U_ID_PHASE_OPT_T_C_M 0xC0000000
|
#define TXTIMCT_PKT_EXT_IDX_C 0x45B0
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#define TXTIMCT_PKT_EXT_IDX_C_M 0x7
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#define TXUSRCT0_N_STS_C 0x45B0
|
#define TXUSRCT0_N_STS_C_M 0x38
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#define TXUSRCT0_N_STS_RU_TOT_C 0x45B0
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#define TXUSRCT0_N_STS_RU_TOT_C_M 0x1C0
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#define TXUSRCT0_STRT_STS_C 0x45B0
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#define TXUSRCT0_STRT_STS_C_M 0xE00
|
#define TXUSRCT1_N_STS_C 0x45B0
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#define TXUSRCT1_N_STS_C_M 0x7000
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#define TXUSRCT1_N_STS_RU_TOT_C 0x45B0
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#define TXUSRCT1_N_STS_RU_TOT_C_M 0x38000
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#define TXUSRCT1_STRT_STS_C 0x45B0
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#define TXUSRCT1_STRT_STS_C_M 0x1C0000
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#define TXUSRCT2_N_STS_C 0x45B0
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#define TXUSRCT2_N_STS_C_M 0xE00000
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#define TXUSRCT2_N_STS_RU_TOT_C 0x45B0
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#define TXUSRCT2_N_STS_RU_TOT_C_M 0x7000000
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#define TXUSRCT2_STRT_STS_C 0x45B0
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#define TXUSRCT2_STRT_STS_C_M 0x38000000
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#define MAC_TXD_PHASE_OPT_I_C 0x45B0
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#define MAC_TXD_PHASE_OPT_I_C_M 0xC0000000
|
#define TXUSRCT3_N_STS_C 0x45B4
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#define TXUSRCT3_N_STS_C_M 0x7
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#define TXUSRCT3_N_STS_RU_TOT_C 0x45B4
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#define TXUSRCT3_N_STS_RU_TOT_C_M 0x38
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#define TXUSRCT3_STRT_STS_C 0x45B4
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#define TXUSRCT3_STRT_STS_C_M 0x1C0
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#define SOURCE_GEN_MODE_IDX_C 0x45B4
|
#define SOURCE_GEN_MODE_IDX_C_M 0x600
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#define TXCOMCT_GI_TYPE_C 0x45B4
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#define TXCOMCT_GI_TYPE_C_M 0x1800
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#define TXCOMCT_LTF_TYPE_C 0x45B4
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#define TXCOMCT_LTF_TYPE_C_M 0x6000
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#define TXINFO_DBW_IDX_C 0x45B4
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#define TXINFO_DBW_IDX_C_M 0x18000
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#define TXINFO_PATH_MAP_A_C 0x45B4
|
#define TXINFO_PATH_MAP_A_C_M 0x60000
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#define TXINFO_PATH_MAP_B_C 0x45B4
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#define TXINFO_PATH_MAP_B_C_M 0x180000
|
#define TXINFO_PATH_MAP_C_C 0x45B4
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#define TXINFO_PATH_MAP_C_C_M 0x600000
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#define TXINFO_PATH_MAP_D_C 0x45B4
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#define TXINFO_PATH_MAP_D_C_M 0x1800000
|
#define TXTIMCT_PRE_FEC_FCTR_C 0x45B4
|
#define TXTIMCT_PRE_FEC_FCTR_C_M 0x6000000
|
#define BMODE_LONG_PREAMBLE_EN_C 0x45B4
|
#define BMODE_LONG_PREAMBLE_EN_C_M 0x8000000
|
#define MAC_TX_PMAC_EN_I_C 0x45B4
|
#define MAC_TX_PMAC_EN_I_C_M 0x10000000
|
#define TAR_TXINFO_TXTP_EN_C 0x45B4
|
#define TAR_TXINFO_TXTP_EN_C_M 0x20000000
|
#define TX_N_PACKET_EN_C 0x45B4
|
#define TX_N_PACKET_EN_C_M 0x40000000
|
#define TX_CONTINUOUS_C 0x45B4
|
#define TX_CONTINUOUS_C_M 0x80000000
|
#define TX_EN_C 0x45B8
|
#define TX_EN_C_M 0x1
|
#define TXCOMCT_BEAM_CHANGE_EN_C 0x45B8
|
#define TXCOMCT_BEAM_CHANGE_EN_C_M 0x2
|
#define TXCOMCT_DOPPLER_EN_C 0x45B8
|
#define TXCOMCT_DOPPLER_EN_C_M 0x4
|
#define TXCOMCT_FB_MUMIMO_EN_C 0x45B8
|
#define TXCOMCT_FB_MUMIMO_EN_C_M 0x8
|
#define TXCOMCT_FEEDBACK_STATUS_C 0x45B8
|
#define TXCOMCT_FEEDBACK_STATUS_C_M 0x10
|
#define TXCOMCT_HE_SIGB_DCM_EN_C 0x45B8
|
#define TXCOMCT_HE_SIGB_DCM_EN_C_M 0x20
|
#define TXCOMCT_MIDAMBLE_MODE_C 0x45B8
|
#define TXCOMCT_MIDAMBLE_MODE_C_M 0x40
|
#define TXCOMCT_MUMIMO_LTF_MODE_EN_C 0x45B8
|
#define TXCOMCT_MUMIMO_LTF_MODE_EN_C_M 0x80
|
#define TXCOMCT_NDP_C 0x45B8
|
#define TXCOMCT_NDP_C_M 0x100
|
#define TXCOMCT_STBC_EN_C 0x45B8
|
#define TXCOMCT_STBC_EN_C_M 0x200
|
#define TXINFO_ANT_SEL_A_C 0x45B8
|
#define TXINFO_ANT_SEL_A_C_M 0x400
|
#define TXINFO_ANT_SEL_B_C 0x45B8
|
#define TXINFO_ANT_SEL_B_C_M 0x800
|
#define TXINFO_ANT_SEL_C_C 0x45B8
|
#define TXINFO_ANT_SEL_C_C_M 0x1000
|
#define TXINFO_ANT_SEL_D_C 0x45B8
|
#define TXINFO_ANT_SEL_D_C_M 0x2000
|
#define TXINFO_CCA_PW_TH_EN_C 0x45B8
|
#define TXINFO_CCA_PW_TH_EN_C_M 0x4000
|
#define TXINFO_CFIR_BY_RATE_OFF_C 0x45B8
|
#define TXINFO_CFIR_BY_RATE_OFF_C_M 0x8000
|
#define TXINFO_DPD_BY_RATE_OFF_C 0x45B8
|
#define TXINFO_DPD_BY_RATE_OFF_C_M 0x10000
|
#define TXINFO_RF_FIXED_GAIN_EN_C 0x45B8
|
#define TXINFO_RF_FIXED_GAIN_EN_C_M 0x20000
|
#define TXINFO_UL_CQI_RPT_TRI_C 0x45B8
|
#define TXINFO_UL_CQI_RPT_TRI_C_M 0x40000
|
#define TXTIMCT_LDPC_EXTR_C 0x45B8
|
#define TXTIMCT_LDPC_EXTR_C_M 0x80000
|
#define TXUSRCT0_DCM_EN_C 0x45B8
|
#define TXUSRCT0_DCM_EN_C_M 0x100000
|
#define TXUSRCT0_FEC_TYPE_C 0x45B8
|
#define TXUSRCT0_FEC_TYPE_C_M 0x200000
|
#define TXUSRCT0_TXBF_EN_C 0x45B8
|
#define TXUSRCT0_TXBF_EN_C_M 0x400000
|
#define TXUSRCT1_DCM_EN_C 0x45B8
|
#define TXUSRCT1_DCM_EN_C_M 0x800000
|
#define TXUSRCT1_FEC_TYPE_C 0x45B8
|
#define TXUSRCT1_FEC_TYPE_C_M 0x1000000
|
#define TXUSRCT1_TXBF_EN_C 0x45B8
|
#define TXUSRCT1_TXBF_EN_C_M 0x2000000
|
#define TXUSRCT2_DCM_EN_C 0x45B8
|
#define TXUSRCT2_DCM_EN_C_M 0x4000000
|
#define TXUSRCT2_FEC_TYPE_C 0x45B8
|
#define TXUSRCT2_FEC_TYPE_C_M 0x8000000
|
#define TXUSRCT2_TXBF_EN_C 0x45B8
|
#define TXUSRCT2_TXBF_EN_C_M 0x10000000
|
#define TXUSRCT3_DCM_EN_C 0x45B8
|
#define TXUSRCT3_DCM_EN_C_M 0x20000000
|
#define TXUSRCT3_FEC_TYPE_C 0x45B8
|
#define TXUSRCT3_FEC_TYPE_C_M 0x40000000
|
#define TXUSRCT3_TXBF_EN_C 0x45B8
|
#define TXUSRCT3_TXBF_EN_C_M 0x80000000
|
#define PCOEFF0_C 0x45BC
|
#define PCOEFF0_C_M 0xFFF
|
#define PCOEFF1_C 0x45BC
|
#define PCOEFF1_C_M 0xFFF000
|
#define NORM_FCTR_C 0x45BC
|
#define NORM_FCTR_C_M 0x3F000000
|
#define DELAY_SAMPLE0_C 0x45BC
|
#define DELAY_SAMPLE0_C_M 0xC0000000
|
#define PCOEFF10_C 0x45C0
|
#define PCOEFF10_C_M 0xFFF
|
#define PCOEFF11_C 0x45C0
|
#define PCOEFF11_C_M 0xFFF000
|
#define DELAY_SAMPLE1_C 0x45C0
|
#define DELAY_SAMPLE1_C_M 0x3000000
|
#define DELAY_SAMPLE2_C 0x45C0
|
#define DELAY_SAMPLE2_C_M 0xC000000
|
#define DELAY_SAMPLE3_C 0x45C0
|
#define DELAY_SAMPLE3_C_M 0x30000000
|
#define TXPSF_SCALE_OPT_C 0x45C0
|
#define TXPSF_SCALE_OPT_C_M 0xC0000000
|
#define PCOEFF12_C 0x45C4
|
#define PCOEFF12_C_M 0xFFF
|
#define PCOEFF13_C 0x45C4
|
#define PCOEFF13_C_M 0xFFF000
|
#define PCOEFF14_C 0x45C8
|
#define PCOEFF14_C_M 0xFFF
|
#define PCOEFF15_C 0x45C8
|
#define PCOEFF15_C_M 0xFFF000
|
#define PCOEFF2_C 0x45CC
|
#define PCOEFF2_C_M 0xFFF
|
#define PCOEFF3_C 0x45CC
|
#define PCOEFF3_C_M 0xFFF000
|
#define PCOEFF4_C 0x45D0
|
#define PCOEFF4_C_M 0xFFF
|
#define PCOEFF5_C 0x45D0
|
#define PCOEFF5_C_M 0xFFF000
|
#define PCOEFF6_C 0x45D4
|
#define PCOEFF6_C_M 0xFFF
|
#define PCOEFF7_C 0x45D4
|
#define PCOEFF7_C_M 0xFFF000
|
#define PCOEFF8_C 0x45D8
|
#define PCOEFF8_C_M 0xFFF
|
#define PCOEFF9_C 0x45D8
|
#define PCOEFF9_C_M 0xFFF000
|
#define PATH0_R_A_G_ELNA0_C 0x45DC
|
#define PATH0_R_A_G_ELNA0_C_M 0xFF
|
#define PATH0_R_A_G_ELNA1_C 0x45DC
|
#define PATH0_R_A_G_ELNA1_C_M 0xFF00
|
#define PATH0_R_A_G_LNA0_C 0x45DC
|
#define PATH0_R_A_G_LNA0_C_M 0xFF0000
|
#define PATH0_R_A_G_LNA1_C 0x45DC
|
#define PATH0_R_A_G_LNA1_C_M 0xFF000000
|
#define FTM_1ST_SPA_C 0x4638
|
#define FTM_1ST_SPA_C_M 0xF
|
#define FTM_ALPHA_RATIO_C 0x4638
|
#define FTM_ALPHA_RATIO_C_M 0xF0
|
#define FTM_SEARCH_MP_C 0x4638
|
#define FTM_SEARCH_MP_C_M 0xF00
|
#define FTM_SIR_C 0x4638
|
#define FTM_SIR_C_M 0x7000
|
#define FTM_L_C 0x4638
|
#define FTM_L_C_M 0xC0000
|
#define FTM_N_PRO_C 0x4638
|
#define FTM_N_PRO_C_M 0x300000
|
#define FTM_1ST_MODE_C 0x4638
|
#define FTM_1ST_MODE_C_M 0x800000
|
#define FTM_MASK_C 0x4638
|
#define FTM_MASK_C_M 0x1000000
|
#define FTM_SEARCH_RANGE_20_C 0x4638
|
#define FTM_SEARCH_RANGE_20_C_M 0x2000000
|
#define FTM_SEARCH_RANGE_40_C 0x4638
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#define FTM_SEARCH_RANGE_40_C_M 0x4000000
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#define FTM_SEARCH_RANGE_80_C 0x4638
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#define FTM_SEARCH_RANGE_80_C_M 0x8000000
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#define PATH0_R_ACI_DET_BKP1_C 0x463C
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#define PATH0_R_ACI_DET_BKP1_C_M 0xFFFFFFFF
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#define PATH0_R_ACI_DET_BKP2_C 0x4640
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#define PATH0_R_ACI_DET_BKP2_C_M 0xFFFFFFFF
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#define PATH0_R_ACI_TH_DB_BW20_C 0x4644
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#define PATH0_R_ACI_TH_DB_BW20_C_M 0xFF
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#define PATH0_R_ACI_TH_DB_BW40_C 0x4644
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#define PATH0_R_ACI_TH_DB_BW40_C_M 0xFF00
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#define PATH0_R_ACI_TH_DB_BW80_C 0x4644
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#define PATH0_R_ACI_TH_DB_BW80_C_M 0xFF0000
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#define PATH0_R_LARGE_ACI_ACT_TH_BW20_C 0x4644
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#define PATH0_R_LARGE_ACI_ACT_TH_BW20_C_M 0xFF000000
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#define PATH0_R_LARGE_ACI_ACT_TH_BW40_C 0x4648
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#define PATH0_R_LARGE_ACI_ACT_TH_BW40_C_M 0xFF
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#define PATH0_R_LARGE_ACI_ACT_TH_BW80_C 0x4648
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#define PATH0_R_LARGE_ACI_ACT_TH_BW80_C_M 0xFF00
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#define PATH0_R_NORMAL_ACI_ACT_TH_BW20_C 0x4648
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#define PATH0_R_NORMAL_ACI_ACT_TH_BW20_C_M 0xFF0000
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#define PATH0_R_NORMAL_ACI_ACT_TH_BW40_C 0x4648
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#define PATH0_R_NORMAL_ACI_ACT_TH_BW40_C_M 0xFF000000
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#define PATH0_R_NORMAL_ACI_ACT_TH_BW80_C 0x464C
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#define PATH0_R_NORMAL_ACI_ACT_TH_BW80_C_M 0xFF
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#define PATH0_R_LARGE_ACI_DB_C 0x464C
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#define PATH0_R_LARGE_ACI_DB_C_M 0x7F00
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#define PATH0_R_ACI_NRBW_OFST_BW20_C 0x464C
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#define PATH0_R_ACI_NRBW_OFST_BW20_C_M 0x78000
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#define PATH0_R_ACI_NRBW_OFST_BW40_C 0x464C
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#define PATH0_R_ACI_NRBW_OFST_BW40_C_M 0x780000
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#define PATH0_R_ACI_NRBW_OFST_BW80_C 0x464C
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#define PATH0_R_ACI_NRBW_OFST_BW80_C_M 0x7800000
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#define PATH0_R_ACI_HIT_CNT_TH_C 0x464C
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#define PATH0_R_ACI_HIT_CNT_TH_C_M 0x38000000
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#define PATH0_R_ACI_NRBW_OFST_EN_C 0x464C
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#define PATH0_R_ACI_NRBW_OFST_EN_C_M 0x40000000
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#define PATH0_R_BYPASS_RFGC_EN_C 0x464C
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#define PATH0_R_BYPASS_RFGC_EN_C_M 0x80000000
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#define PATH0_R_ADC_DC_OFST_RXLOW_IM_C 0x4650
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#define PATH0_R_ADC_DC_OFST_RXLOW_IM_C_M 0x3FFF
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#define PATH0_R_ADC_DC_OFST_RXLOW_RE_C 0x4650
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#define PATH0_R_ADC_DC_OFST_RXLOW_RE_C_M 0xFFFC000
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#define PATH0_R_DC_COMP_EN_C 0x4650
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#define PATH0_R_DC_COMP_EN_C_M 0x10000000
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#define PATH0_R_ADC_DC_OFST_RXMID_IM_C 0x4654
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#define PATH0_R_ADC_DC_OFST_RXMID_IM_C_M 0x3FFF
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#define PATH0_R_ADC_DC_OFST_RXMID_RE_C 0x4654
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#define PATH0_R_ADC_DC_OFST_RXMID_RE_C_M 0xFFFC000
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#define PATH0_R_DC_OFST_IM_C 0x4658
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#define PATH0_R_DC_OFST_IM_C_M 0x3FFF
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#define PATH0_R_DC_OFST_RE_C 0x4658
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#define PATH0_R_DC_OFST_RE_C_M 0xFFFC000
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#define PATH0_R_RXTH1_C 0x465C
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#define PATH0_R_RXTH1_C_M 0x1F
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#define PATH0_R_RXTH2_C 0x465C
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#define PATH0_R_RXTH2_C_M 0x3E0
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#define PATH0_R_A_G_LNA2_C 0x4660
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#define PATH0_R_A_G_LNA2_C_M 0xFF
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#define PATH0_R_A_G_LNA3_C 0x4660
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#define PATH0_R_A_G_LNA3_C_M 0xFF00
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#define PATH0_R_A_G_LNA4_C 0x4660
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#define PATH0_R_A_G_LNA4_C_M 0xFF0000
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#define PATH0_R_A_G_LNA5_C 0x4660
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#define PATH0_R_A_G_LNA5_C_M 0xFF000000
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#define PATH0_R_A_G_LNA6_C 0x4664
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#define PATH0_R_A_G_LNA6_C_M 0xFF
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#define PATH0_R_A_G_RX0_C 0x4664
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#define PATH0_R_A_G_RX0_C_M 0xFF00
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#define PATH0_R_A_G_TIA0_C 0x4664
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#define PATH0_R_A_G_TIA0_C_M 0xFF0000
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#define PATH0_R_A_G_TIA1_C 0x4664
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#define PATH0_R_A_G_TIA1_C_M 0xFF000000
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#define PATH0_R_A_LNA0_OP1DB_C 0x4668
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#define PATH0_R_A_LNA0_OP1DB_C_M 0xFF
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#define PATH0_R_A_LNA1_OP1DB_C 0x4668
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#define PATH0_R_A_LNA1_OP1DB_C_M 0xFF00
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#define PATH0_R_A_LNA2_OP1DB_C 0x4668
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#define PATH0_R_A_LNA2_OP1DB_C_M 0xFF0000
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#define PATH0_R_A_LNA3_OP1DB_C 0x4668
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#define PATH0_R_A_LNA3_OP1DB_C_M 0xFF000000
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#define PATH0_R_A_LNA4_OP1DB_C 0x466C
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#define PATH0_R_A_LNA4_OP1DB_C_M 0xFF
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#define PATH0_R_A_LNA5_OP1DB_C 0x466C
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#define PATH0_R_A_LNA5_OP1DB_C_M 0xFF00
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#define PATH0_R_A_LNA6_OP1DB_C 0x466C
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#define PATH0_R_A_LNA6_OP1DB_C_M 0xFF0000
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#define PATH0_R_A_RXOP1DB_C 0x466C
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#define PATH0_R_A_RXOP1DB_C_M 0xFF000000
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#define PATH0_R_A_TIA0_LNA0_OP1DB_C 0x4670
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#define PATH0_R_A_TIA0_LNA0_OP1DB_C_M 0xFF
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#define PATH0_R_A_TIA0_LNA1_OP1DB_C 0x4670
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#define PATH0_R_A_TIA0_LNA1_OP1DB_C_M 0xFF00
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#define PATH0_R_A_TIA0_LNA2_OP1DB_C 0x4670
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#define PATH0_R_A_TIA0_LNA2_OP1DB_C_M 0xFF0000
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#define PATH0_R_A_TIA0_LNA3_OP1DB_C 0x4670
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#define PATH0_R_A_TIA0_LNA3_OP1DB_C_M 0xFF000000
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#define PATH0_R_A_TIA0_LNA4_OP1DB_C 0x4674
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#define PATH0_R_A_TIA0_LNA4_OP1DB_C_M 0xFF
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#define PATH0_R_A_TIA0_LNA5_OP1DB_C 0x4674
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#define PATH0_R_A_TIA0_LNA5_OP1DB_C_M 0xFF00
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#define PATH0_R_A_TIA0_LNA6_OP1DB_C 0x4674
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#define PATH0_R_A_TIA0_LNA6_OP1DB_C_M 0xFF0000
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#define PATH0_R_A_TIA1_LNA6_OP1DB_C 0x4674
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#define PATH0_R_A_TIA1_LNA6_OP1DB_C_M 0xFF000000
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#define PATH0_R_G_G_ELNA0_C 0x4678
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#define PATH0_R_G_G_ELNA0_C_M 0xFF
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#define PATH0_R_G_G_ELNA1_C 0x4678
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#define PATH0_R_G_G_ELNA1_C_M 0xFF00
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#define PATH0_R_G_G_LNA0_C 0x4678
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#define PATH0_R_G_G_LNA0_C_M 0xFF0000
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#define PATH0_R_G_G_LNA1_C 0x4678
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#define PATH0_R_G_G_LNA1_C_M 0xFF000000
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#define PATH0_R_G_G_LNA2_C 0x467C
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#define PATH0_R_G_G_LNA2_C_M 0xFF
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#define PATH0_R_G_G_LNA3_C 0x467C
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#define PATH0_R_G_G_LNA3_C_M 0xFF00
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#define PATH0_R_G_G_LNA4_C 0x467C
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#define PATH0_R_G_G_LNA4_C_M 0xFF0000
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#define PATH0_R_G_G_LNA5_C 0x467C
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#define PATH0_R_G_G_LNA5_C_M 0xFF000000
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#define PATH0_R_G_G_LNA6_C 0x4680
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#define PATH0_R_G_G_LNA6_C_M 0xFF
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#define PATH0_R_G_G_RX0_C 0x4680
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#define PATH0_R_G_G_RX0_C_M 0xFF00
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#define PATH0_R_G_G_TIA0_C 0x4680
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#define PATH0_R_G_G_TIA0_C_M 0xFF0000
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#define PATH0_R_G_G_TIA1_C 0x4680
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#define PATH0_R_G_G_TIA1_C_M 0xFF000000
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#define PATH0_R_G_LGC_DAGC_C 0x4684
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#define PATH0_R_G_LGC_DAGC_C_M 0xFF
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#define PATH0_R_G_LNA0_OP1DB_C 0x4684
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#define PATH0_R_G_LNA0_OP1DB_C_M 0xFF00
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#define PATH0_R_G_LNA1_OP1DB_C 0x4684
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#define PATH0_R_G_LNA1_OP1DB_C_M 0xFF0000
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#define PATH0_R_G_LNA2_OP1DB_C 0x4684
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#define PATH0_R_G_LNA2_OP1DB_C_M 0xFF000000
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#define PATH0_R_G_LNA3_OP1DB_C 0x4688
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#define PATH0_R_G_LNA3_OP1DB_C_M 0xFF
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#define PATH0_R_G_LNA4_OP1DB_C 0x4688
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#define PATH0_R_G_LNA4_OP1DB_C_M 0xFF00
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#define PATH0_R_G_LNA5_OP1DB_C 0x4688
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#define PATH0_R_G_LNA5_OP1DB_C_M 0xFF0000
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#define PATH0_R_G_LNA6_OP1DB_C 0x4688
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#define PATH0_R_G_LNA6_OP1DB_C_M 0xFF000000
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#define PATH0_R_G_NLGC_DAGC_C 0x468C
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#define PATH0_R_G_NLGC_DAGC_C_M 0xFF
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#define PATH0_R_G_RXOP1DB_C 0x468C
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#define PATH0_R_G_RXOP1DB_C_M 0xFF00
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#define PATH0_R_G_TIA0_LNA0_OP1DB_C 0x468C
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#define PATH0_R_G_TIA0_LNA0_OP1DB_C_M 0xFF0000
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#define PATH0_R_G_TIA0_LNA1_OP1DB_C 0x468C
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#define PATH0_R_G_TIA0_LNA1_OP1DB_C_M 0xFF000000
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#define PATH0_R_G_TIA0_LNA2_OP1DB_C 0x4690
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#define PATH0_R_G_TIA0_LNA2_OP1DB_C_M 0xFF
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#define PATH0_R_G_TIA0_LNA3_OP1DB_C 0x4690
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#define PATH0_R_G_TIA0_LNA3_OP1DB_C_M 0xFF00
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#define PATH0_R_G_TIA0_LNA4_OP1DB_C 0x4690
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#define PATH0_R_G_TIA0_LNA4_OP1DB_C_M 0xFF0000
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#define PATH0_R_G_TIA0_LNA5_OP1DB_C 0x4690
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#define PATH0_R_G_TIA0_LNA5_OP1DB_C_M 0xFF000000
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#define PATH0_R_G_TIA0_LNA6_OP1DB_C 0x4694
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#define PATH0_R_G_TIA0_LNA6_OP1DB_C_M 0xFF
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#define PATH0_R_G_TIA1_LNA6_OP1DB_C 0x4694
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#define PATH0_R_G_TIA1_LNA6_OP1DB_C_M 0xFF00
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#define PATH0_R_G_OFST_C 0x4694
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#define PATH0_R_G_OFST_C_M 0xFF0000
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#define PATH0_R_IBADC_SAT_TH_C 0x4694
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#define PATH0_R_IBADC_SAT_TH_C_M 0xFF000000
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#define PATH0_R_IBADC_UNDER_TH_C 0x4698
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#define PATH0_R_IBADC_UNDER_TH_C_M 0xFF
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#define PATH0_R_WBADC_SAT_TH_C 0x4698
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#define PATH0_R_WBADC_SAT_TH_C_M 0xFF00
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#define PATH0_R_WBADC_SAT_TH_ANTWGT_C 0x4698
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#define PATH0_R_WBADC_SAT_TH_ANTWGT_C_M 0xFF0000
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#define PATH0_R_WBADC_UNDER_TH_C 0x4698
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#define PATH0_R_WBADC_UNDER_TH_C_M 0xFF000000
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#define PATH0_R_P_PEAK_IBADC_DBM_C 0x469C
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#define PATH0_R_P_PEAK_IBADC_DBM_C_M 0x7F
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#define PATH0_R_P_PEAK_WBADC_DBM_C 0x469C
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#define PATH0_R_P_PEAK_WBADC_DBM_C_M 0x3F80
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#define PATH0_R_ACI_NRBW_TH_C 0x469C
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#define PATH0_R_ACI_NRBW_TH_C_M 0xFC000
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#define PATH0_R_BACKOFF_BMODE_C 0x469C
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#define PATH0_R_BACKOFF_BMODE_C_M 0x3F00000
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#define PATH0_R_BACKOFF_IBADC_C 0x469C
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#define PATH0_R_BACKOFF_IBADC_C_M 0xFC000000
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#define PATH0_R_BACKOFF_LNA_C 0x46A0
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#define PATH0_R_BACKOFF_LNA_C_M 0x3F
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#define PATH0_R_BACKOFF_TIA_C 0x46A0
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#define PATH0_R_BACKOFF_TIA_C_M 0xFC0
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#define PATH0_R_BACKOFF_WBADC_C 0x46A0
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#define PATH0_R_BACKOFF_WBADC_C_M 0x3F000
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#define PATH0_R_G_IBADC_IN_C 0x46A0
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#define PATH0_R_G_IBADC_IN_C_M 0xFC0000
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#define PATH0_R_A_GS_SAT_IDX_RX_C 0x46A0
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#define PATH0_R_A_GS_SAT_IDX_RX_C_M 0x1F000000
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#define PATH0_R_A_WB_GIDX_00_LNA_TIA_C 0x46A0
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#define PATH0_R_A_WB_GIDX_00_LNA_TIA_C_M 0xE0000000
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#define PATH0_R_A_GS_UND_IDX_RX_C 0x46A4
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#define PATH0_R_A_GS_UND_IDX_RX_C_M 0x1F
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#define PATH0_R_G_GS_SAT_IDX_RX_C 0x46A4
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#define PATH0_R_G_GS_SAT_IDX_RX_C_M 0x3E0
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#define PATH0_R_G_GS_UND_IDX_RX_C 0x46A4
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#define PATH0_R_G_GS_UND_IDX_RX_C_M 0x7C00
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#define PATH0_R_DLY_DCCL_C 0x46A4
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#define PATH0_R_DLY_DCCL_C_M 0x1F00000
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#define PATH0_R_DLY_DFE_C 0x46A4
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#define PATH0_R_DLY_DFE_C_M 0x3E000000
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#define PATH0_R_G_MIXER_C 0x46A4
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#define PATH0_R_G_MIXER_C_M 0xC0000000
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#define PATH0_R_DLY_PRIM_C 0x46A8
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#define PATH0_R_DLY_PRIM_C_M 0x1F
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#define PATH0_R_DLY_SYNC_C 0x46A8
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#define PATH0_R_DLY_SYNC_C_M 0x3E0
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#define PATH0_R_RXIDX_INIT_C 0x46A8
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#define PATH0_R_RXIDX_INIT_C_M 0x7C00
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#define PATH0_R_A_GS_SAT_IDX_H_C 0x46A8
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#define PATH0_R_A_GS_SAT_IDX_H_C_M 0x78000
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#define PATH0_R_A_GS_SAT_IDX_L_C 0x46A8
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#define PATH0_R_A_GS_SAT_IDX_L_C_M 0x780000
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#define PATH0_R_A_GS_SAT_IDX_PP1_C 0x46A8
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#define PATH0_R_A_GS_SAT_IDX_PP1_C_M 0x7800000
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#define PATH0_R_A_GS_SAT_IDX_PP2_C 0x46A8
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#define PATH0_R_A_GS_SAT_IDX_PP2_C_M 0x78000000
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#define PATH0_R_1RCCA_PRE_PD_MODE_C 0x46A8
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#define PATH0_R_1RCCA_PRE_PD_MODE_C_M 0x80000000
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#define PATH0_R_A_GS_SAT_TH_H_C 0x46AC
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#define PATH0_R_A_GS_SAT_TH_H_C_M 0xF
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#define PATH0_R_A_GS_SAT_TH_L_C 0x46AC
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#define PATH0_R_A_GS_SAT_TH_L_C_M 0xF0
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#define PATH0_R_A_GS_UND_IDX_C 0x46AC
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#define PATH0_R_A_GS_UND_IDX_C_M 0xF00
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#define PATH0_R_A_GS_UND_IDX_PP1_C 0x46AC
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#define PATH0_R_A_GS_UND_IDX_PP1_C_M 0xF000
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#define PATH0_R_A_GS_UND_IDX_PP2_C 0x46AC
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#define PATH0_R_A_GS_UND_IDX_PP2_C_M 0xF0000
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#define PATH0_R_A_GS_UND_TH_H_C 0x46AC
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#define PATH0_R_A_GS_UND_TH_H_C_M 0xF00000
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#define PATH0_R_A_GS_UND_TH_L_C 0x46AC
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#define PATH0_R_A_GS_UND_TH_L_C_M 0xF000000
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#define PATH0_R_GC1_TIME_C 0x46AC
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#define PATH0_R_GC1_TIME_C_M 0xF0000000
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#define PATH0_R_GC1_TIME_NLGC_C 0x46B0
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#define PATH0_R_GC1_TIME_NLGC_C_M 0xF
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#define PATH0_R_GC2_TIME_C 0x46B0
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#define PATH0_R_GC2_TIME_C_M 0xF0
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#define PATH0_R_GC2_TIME_NLGC_C 0x46B0
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#define PATH0_R_GC2_TIME_NLGC_C_M 0xF00
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#define PATH0_R_GC3_TIME_C 0x46B0
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#define PATH0_R_GC3_TIME_C_M 0xF000
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#define PATH0_R_GC4_TIME_C 0x46B0
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#define PATH0_R_GC4_TIME_C_M 0xF0000
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#define PATH0_R_GC5_TIME_C 0x46B0
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#define PATH0_R_GC5_TIME_C_M 0xF00000
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#define PATH0_R_GC_TIME_LESS_80M_C 0x46B0
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#define PATH0_R_GC_TIME_LESS_80M_C_M 0xF000000
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#define PATH0_R_GC_TIME_LESS_NLINEAR_C 0x46B0
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#define PATH0_R_GC_TIME_LESS_NLINEAR_C_M 0xF0000000
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#define PATH0_R_G_GS_SAT_IDX_H_C 0x46B4
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#define PATH0_R_G_GS_SAT_IDX_H_C_M 0xF
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#define PATH0_R_G_GS_SAT_IDX_L_C 0x46B4
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#define PATH0_R_G_GS_SAT_IDX_L_C_M 0xF0
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#define PATH0_R_G_GS_SAT_IDX_PP1_C 0x46B4
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#define PATH0_R_G_GS_SAT_IDX_PP1_C_M 0xF00
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#define PATH0_R_G_GS_SAT_IDX_PP2_C 0x46B4
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#define PATH0_R_G_GS_SAT_IDX_PP2_C_M 0xF000
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#define PATH0_R_G_GS_SAT_TH_H_C 0x46B4
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#define PATH0_R_G_GS_SAT_TH_H_C_M 0xF0000
|
#define PATH0_R_G_GS_SAT_TH_L_C 0x46B4
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#define PATH0_R_G_GS_SAT_TH_L_C_M 0xF00000
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#define PATH0_R_G_GS_UND_IDX_C 0x46B4
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#define PATH0_R_G_GS_UND_IDX_C_M 0xF000000
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#define PATH0_R_G_GS_UND_IDX_PP1_C 0x46B4
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#define PATH0_R_G_GS_UND_IDX_PP1_C_M 0xF0000000
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#define PATH0_R_G_GS_UND_IDX_PP2_C 0x46B8
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#define PATH0_R_G_GS_UND_IDX_PP2_C_M 0xF
|
#define PATH0_R_G_GS_UND_TH_H_C 0x46B8
|
#define PATH0_R_G_GS_UND_TH_H_C_M 0xF0
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#define PATH0_R_G_GS_UND_TH_L_C 0x46B8
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#define PATH0_R_G_GS_UND_TH_L_C_M 0xF00
|
#define PATH0_R_ACI_NRBW_RATIO_C 0x46B8
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#define PATH0_R_ACI_NRBW_RATIO_C_M 0xF000
|
#define PATH0_R_AGC_RESTART_TH_IB_C 0x46B8
|
#define PATH0_R_AGC_RESTART_TH_IB_C_M 0xF0000
|
#define PATH0_R_AGC_RESTART_TH_WB_C 0x46B8
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#define PATH0_R_AGC_RESTART_TH_WB_C_M 0xF00000
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#define PATH0_R_DCCL_ALPHA_80_C 0x46B8
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#define PATH0_R_DCCL_ALPHA_80_C_M 0xF000000
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#define PATH0_R_DCCL_ALPHA_N80_C 0x46B8
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#define PATH0_R_DCCL_ALPHA_N80_C_M 0xF0000000
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#define PATH0_R_LGC_FREEZE_TH_H_C 0x46BC
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#define PATH0_R_LGC_FREEZE_TH_H_C_M 0xF
|
#define PATH0_R_LGC_FREEZE_TH_L_C 0x46BC
|
#define PATH0_R_LGC_FREEZE_TH_L_C_M 0xF0
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#define PATH0_R_NLGC_FREEZE_TH_H_C 0x46BC
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#define PATH0_R_NLGC_FREEZE_TH_H_C_M 0xF00
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#define PATH0_R_NLGC_FREEZE_TH_L_C 0x46BC
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#define PATH0_R_NLGC_FREEZE_TH_L_C_M 0xF000
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#define PATH0_R_WB_GAIN_IDX_INIT_C 0x46BC
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#define PATH0_R_WB_GAIN_IDX_INIT_C_M 0xF0000
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#define PATH0_R_A_WB_GIDX_01_LNA_TIA_C 0x46BC
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#define PATH0_R_A_WB_GIDX_01_LNA_TIA_C_M 0x7000000
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#define PATH0_R_A_WB_GIDX_02_LNA_TIA_C 0x46BC
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#define PATH0_R_A_WB_GIDX_02_LNA_TIA_C_M 0x38000000
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#define PATH0_R_G_WBADC_IN_C 0x46BC
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#define PATH0_R_G_WBADC_IN_C_M 0xC0000000
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#define PATH0_R_DCCL_SYNC_BKP1_C 0x46C0
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#define PATH0_R_DCCL_SYNC_BKP1_C_M 0xFFFFFFFF
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#define PATH0_R_DCCL_SYNC_BKP2_C 0x46C4
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#define PATH0_R_DCCL_SYNC_BKP2_C_M 0xFFFFFFFF
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#define PATH0_R_ALPHA_END_IDX_C 0x46C8
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#define PATH0_R_ALPHA_END_IDX_C_M 0xF
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#define PATH0_R_ALPHA_START_IDX_C 0x46C8
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#define PATH0_R_ALPHA_START_IDX_C_M 0xF0
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#define PATH0_R_TIME_CONST_IDX_C 0x46C8
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#define PATH0_R_TIME_CONST_IDX_C_M 0x700
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#define PATH0_R_RXFIR_BKP_C 0x46CC
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#define PATH0_R_RXFIR_BKP_C_M 0xFFFFFFFF
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#define PATH0_R_FORCE_FIR_TYPE_C 0x46D0
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#define PATH0_R_FORCE_FIR_TYPE_C_M 0x3
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#define PATH0_R_CCK_CCA_SHRINK_EN_C 0x46D0
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#define PATH0_R_CCK_CCA_SHRINK_EN_C_M 0x4
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#define PATH0_P20_R_L1_CFO_CMP_EN_C 0x46D4
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#define PATH0_P20_R_L1_CFO_CMP_EN_C_M 0x1
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#define PATH0_S20_R_L1_CFO_CMP_EN_C 0x46D8
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#define PATH0_S20_R_L1_CFO_CMP_EN_C_M 0x1
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#define PATH0_R_NBI_NOTCH_BKP1_C 0x46DC
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#define PATH0_R_NBI_NOTCH_BKP1_C_M 0xFFFFFFFF
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#define PATH0_R_NBI_NOTCH_BKP2_C 0x46E0
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#define PATH0_R_NBI_NOTCH_BKP2_C_M 0xFFFFFFFF
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#define PATH0_R_NBI_IDX_C 0x46E4
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#define PATH0_R_NBI_IDX_C_M 0xFF
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#define PATH0_R_CORNER_IDX_C 0x46E4
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#define PATH0_R_CORNER_IDX_C_M 0x300
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#define PATH0_R_NBI_FRAC_IDX_C 0x46E4
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#define PATH0_R_NBI_FRAC_IDX_C_M 0xC00
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#define PATH0_R_NBI_NOTCH_EN_C 0x46E4
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#define PATH0_R_NBI_NOTCH_EN_C_M 0x1000
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#define PATH0_P20_R_DAGC_EXTRA_SETTLING_TIME_C 0x46E8
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#define PATH0_P20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7
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#define PATH0_P20_R_DAGC_SETTLING_TIME_C 0x46E8
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#define PATH0_P20_R_DAGC_SETTLING_TIME_C_M 0x18
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#define PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C 0x46E8
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#define PATH0_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20
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#define PATH0_P20_R_PW_EST_SHORT_TIME_FAGC_C 0x46E8
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#define PATH0_P20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40
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#define PATH0_P20_R_PW_EST_TIME_FAGC_C 0x46E8
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#define PATH0_P20_R_PW_EST_TIME_FAGC_C_M 0x80
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#define PATH0_P20_R_PW_EST_TIME_PAGC_C 0x46E8
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#define PATH0_P20_R_PW_EST_TIME_PAGC_C_M 0x100
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#define PATH0_P20_R_PW_EST_TIME_RFGC_C 0x46E8
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#define PATH0_P20_R_PW_EST_TIME_RFGC_C_M 0x200
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#define PATH0_P20_R_SDAGC_EN_C 0x46E8
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#define PATH0_P20_R_SDAGC_EN_C_M 0x400
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#define PATH0_S20_R_DAGC_EXTRA_SETTLING_TIME_C 0x46EC
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#define PATH0_S20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7
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#define PATH0_S20_R_DAGC_SETTLING_TIME_C 0x46EC
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#define PATH0_S20_R_DAGC_SETTLING_TIME_C_M 0x18
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#define PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C 0x46EC
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#define PATH0_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20
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#define PATH0_S20_R_PW_EST_SHORT_TIME_FAGC_C 0x46EC
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#define PATH0_S20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40
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#define PATH0_S20_R_PW_EST_TIME_FAGC_C 0x46EC
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#define PATH0_S20_R_PW_EST_TIME_FAGC_C_M 0x80
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#define PATH0_S20_R_PW_EST_TIME_PAGC_C 0x46EC
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#define PATH0_S20_R_PW_EST_TIME_PAGC_C_M 0x100
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#define PATH0_S20_R_PW_EST_TIME_RFGC_C 0x46EC
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#define PATH0_S20_R_PW_EST_TIME_RFGC_C_M 0x200
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#define PATH0_S20_R_SDAGC_EN_C 0x46EC
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#define PATH0_S20_R_SDAGC_EN_C_M 0x400
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#define PATH0_R_5MDET_BKP1_C 0x46F0
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#define PATH0_R_5MDET_BKP1_C_M 0xFFFFFFFF
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#define PATH0_R_5MDET_BKP2_C 0x46F4
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#define PATH0_R_5MDET_BKP2_C_M 0xFFFFFFFF
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#define PATH0_R_5MDET_TH_DB_C 0x46F8
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#define PATH0_R_5MDET_TH_DB_C_M 0x3F
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#define PATH0_R_5MDET_MASK_SB0_C 0x46F8
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#define PATH0_R_5MDET_MASK_SB0_C_M 0x40
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#define PATH0_R_5MDET_MASK_SB1_C 0x46F8
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#define PATH0_R_5MDET_MASK_SB1_C_M 0x80
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#define PATH0_R_5MDET_MASK_SB2_C 0x46F8
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#define PATH0_R_5MDET_MASK_SB2_C_M 0x100
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#define PATH0_R_5MDET_MASK_SB3_C 0x46F8
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#define PATH0_R_5MDET_MASK_SB3_C_M 0x200
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#define PATH0_R_5MDET_MODE_C 0x46F8
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#define PATH0_R_5MDET_MODE_C_M 0x400
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#define PATH0_R_IIR_PW_AVG_EN_C 0x46F8
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#define PATH0_R_IIR_PW_AVG_EN_C_M 0x800
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#define PATH0_R_SBF5M_EN_C 0x46F8
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#define PATH0_R_SBF5M_EN_C_M 0x1000
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#define PATH1_R_ACI_DET_BKP1_C 0x46FC
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#define PATH1_R_ACI_DET_BKP1_C_M 0xFFFFFFFF
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#define PATH1_R_ACI_DET_BKP2_C 0x4700
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#define PATH1_R_ACI_DET_BKP2_C_M 0xFFFFFFFF
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#define PATH1_R_ACI_TH_DB_BW20_C 0x4704
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#define PATH1_R_ACI_TH_DB_BW20_C_M 0xFF
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#define PATH1_R_ACI_TH_DB_BW40_C 0x4704
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#define PATH1_R_ACI_TH_DB_BW40_C_M 0xFF00
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#define PATH1_R_ACI_TH_DB_BW80_C 0x4704
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#define PATH1_R_ACI_TH_DB_BW80_C_M 0xFF0000
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#define PATH1_R_LARGE_ACI_ACT_TH_BW20_C 0x4704
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#define PATH1_R_LARGE_ACI_ACT_TH_BW20_C_M 0xFF000000
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#define PATH1_R_LARGE_ACI_ACT_TH_BW40_C 0x4708
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#define PATH1_R_LARGE_ACI_ACT_TH_BW40_C_M 0xFF
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#define PATH1_R_LARGE_ACI_ACT_TH_BW80_C 0x4708
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#define PATH1_R_LARGE_ACI_ACT_TH_BW80_C_M 0xFF00
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#define PATH1_R_NORMAL_ACI_ACT_TH_BW20_C 0x4708
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#define PATH1_R_NORMAL_ACI_ACT_TH_BW20_C_M 0xFF0000
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#define PATH1_R_NORMAL_ACI_ACT_TH_BW40_C 0x4708
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#define PATH1_R_NORMAL_ACI_ACT_TH_BW40_C_M 0xFF000000
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#define PATH1_R_NORMAL_ACI_ACT_TH_BW80_C 0x470C
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#define PATH1_R_NORMAL_ACI_ACT_TH_BW80_C_M 0xFF
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#define PATH1_R_LARGE_ACI_DB_C 0x470C
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#define PATH1_R_LARGE_ACI_DB_C_M 0x7F00
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#define PATH1_R_ACI_NRBW_OFST_BW20_C 0x470C
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#define PATH1_R_ACI_NRBW_OFST_BW20_C_M 0x78000
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#define PATH1_R_ACI_NRBW_OFST_BW40_C 0x470C
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#define PATH1_R_ACI_NRBW_OFST_BW40_C_M 0x780000
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#define PATH1_R_ACI_NRBW_OFST_BW80_C 0x470C
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#define PATH1_R_ACI_NRBW_OFST_BW80_C_M 0x7800000
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#define PATH1_R_ACI_HIT_CNT_TH_C 0x470C
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#define PATH1_R_ACI_HIT_CNT_TH_C_M 0x38000000
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#define PATH1_R_ACI_NRBW_OFST_EN_C 0x470C
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#define PATH1_R_ACI_NRBW_OFST_EN_C_M 0x40000000
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#define PATH1_R_BYPASS_RFGC_EN_C 0x470C
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#define PATH1_R_BYPASS_RFGC_EN_C_M 0x80000000
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#define PATH1_R_ADC_DC_OFST_RXLOW_IM_C 0x4710
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#define PATH1_R_ADC_DC_OFST_RXLOW_IM_C_M 0x3FFF
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#define PATH1_R_ADC_DC_OFST_RXLOW_RE_C 0x4710
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#define PATH1_R_ADC_DC_OFST_RXLOW_RE_C_M 0xFFFC000
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#define PATH1_R_DC_COMP_EN_C 0x4710
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#define PATH1_R_DC_COMP_EN_C_M 0x10000000
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#define PATH1_R_ADC_DC_OFST_RXMID_IM_C 0x4714
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#define PATH1_R_ADC_DC_OFST_RXMID_IM_C_M 0x3FFF
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#define PATH1_R_ADC_DC_OFST_RXMID_RE_C 0x4714
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#define PATH1_R_ADC_DC_OFST_RXMID_RE_C_M 0xFFFC000
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#define PATH1_R_DC_OFST_IM_C 0x4718
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#define PATH1_R_DC_OFST_IM_C_M 0x3FFF
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#define PATH1_R_DC_OFST_RE_C 0x4718
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#define PATH1_R_DC_OFST_RE_C_M 0xFFFC000
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#define PATH1_R_RXTH1_C 0x471C
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#define PATH1_R_RXTH1_C_M 0x1F
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#define PATH1_R_RXTH2_C 0x471C
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#define PATH1_R_RXTH2_C_M 0x3E0
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#define PATH0_R_A_WB_GIDX_03_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_03_LNA_TIA_C_M 0x7
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#define PATH0_R_A_WB_GIDX_04_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_04_LNA_TIA_C_M 0x38
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#define PATH0_R_A_WB_GIDX_05_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_05_LNA_TIA_C_M 0x1C0
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#define PATH0_R_A_WB_GIDX_06_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_06_LNA_TIA_C_M 0xE00
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#define PATH0_R_A_WB_GIDX_07_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_07_LNA_TIA_C_M 0x7000
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#define PATH0_R_A_WB_GIDX_08_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_08_LNA_TIA_C_M 0x38000
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#define PATH0_R_A_WB_GIDX_09_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_09_LNA_TIA_C_M 0x1C0000
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#define PATH0_R_A_WB_GIDX_10_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_10_LNA_TIA_C_M 0xE00000
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#define PATH0_R_A_WB_GIDX_11_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_11_LNA_TIA_C_M 0x7000000
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#define PATH0_R_A_WB_GIDX_12_LNA_TIA_C 0x4720
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#define PATH0_R_A_WB_GIDX_12_LNA_TIA_C_M 0x38000000
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#define PATH0_R_IBADC_PW_ALPHA_H_C 0x4720
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#define PATH0_R_IBADC_PW_ALPHA_H_C_M 0xC0000000
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#define PATH0_R_A_WB_GIDX_13_LNA_TIA_C 0x4724
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#define PATH0_R_A_WB_GIDX_13_LNA_TIA_C_M 0x7
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#define PATH0_R_A_WB_GIDX_14_LNA_TIA_C 0x4724
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#define PATH0_R_A_WB_GIDX_14_LNA_TIA_C_M 0x38
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#define PATH0_R_A_WB_GIDX_15_LNA_TIA_C 0x4724
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#define PATH0_R_A_WB_GIDX_15_LNA_TIA_C_M 0x1C0
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#define PATH0_R_G_WB_GIDX_00_LNA_TIA_C 0x4724
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#define PATH0_R_G_WB_GIDX_00_LNA_TIA_C_M 0xE00
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#define PATH0_R_G_WB_GIDX_01_LNA_TIA_C 0x4724
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#define PATH0_R_G_WB_GIDX_01_LNA_TIA_C_M 0x7000
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#define PATH0_R_G_WB_GIDX_02_LNA_TIA_C 0x4724
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#define PATH0_R_G_WB_GIDX_02_LNA_TIA_C_M 0x38000
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#define PATH0_R_G_WB_GIDX_03_LNA_TIA_C 0x4724
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#define PATH0_R_G_WB_GIDX_03_LNA_TIA_C_M 0x1C0000
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#define PATH0_R_G_WB_GIDX_04_LNA_TIA_C 0x4724
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#define PATH0_R_G_WB_GIDX_04_LNA_TIA_C_M 0xE00000
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#define PATH0_R_G_WB_GIDX_05_LNA_TIA_C 0x4724
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#define PATH0_R_G_WB_GIDX_05_LNA_TIA_C_M 0x7000000
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#define PATH0_R_G_WB_GIDX_06_LNA_TIA_C 0x4724
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#define PATH0_R_G_WB_GIDX_06_LNA_TIA_C_M 0x38000000
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#define PATH0_R_IBADC_PW_ALPHA_L_C 0x4724
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#define PATH0_R_IBADC_PW_ALPHA_L_C_M 0xC0000000
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#define PATH0_R_G_WB_GIDX_07_LNA_TIA_C 0x4728
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#define PATH0_R_G_WB_GIDX_07_LNA_TIA_C_M 0x7
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#define PATH0_R_G_WB_GIDX_08_LNA_TIA_C 0x4728
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#define PATH0_R_G_WB_GIDX_08_LNA_TIA_C_M 0x38
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#define PATH0_R_G_WB_GIDX_09_LNA_TIA_C 0x4728
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#define PATH0_R_G_WB_GIDX_09_LNA_TIA_C_M 0x1C0
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#define PATH0_R_G_WB_GIDX_10_LNA_TIA_C 0x4728
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#define PATH0_R_G_WB_GIDX_10_LNA_TIA_C_M 0xE00
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#define PATH0_R_G_WB_GIDX_11_LNA_TIA_C 0x4728
|
#define PATH0_R_G_WB_GIDX_11_LNA_TIA_C_M 0x7000
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#define PATH0_R_G_WB_GIDX_12_LNA_TIA_C 0x4728
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#define PATH0_R_G_WB_GIDX_12_LNA_TIA_C_M 0x38000
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#define PATH0_R_G_WB_GIDX_13_LNA_TIA_C 0x4728
|
#define PATH0_R_G_WB_GIDX_13_LNA_TIA_C_M 0x1C0000
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#define PATH0_R_G_WB_GIDX_14_LNA_TIA_C 0x4728
|
#define PATH0_R_G_WB_GIDX_14_LNA_TIA_C_M 0xE00000
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#define PATH0_R_G_WB_GIDX_15_LNA_TIA_C 0x4728
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#define PATH0_R_G_WB_GIDX_15_LNA_TIA_C_M 0x7000000
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#define PATH0_R_BT_LNA_IDX0_C 0x4728
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#define PATH0_R_BT_LNA_IDX0_C_M 0x38000000
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#define PATH0_R_LINEAR_STEP_LIM_C 0x4728
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#define PATH0_R_LINEAR_STEP_LIM_C_M 0xC0000000
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#define PATH0_R_BT_LNA_IDX1_C 0x472C
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#define PATH0_R_BT_LNA_IDX1_C_M 0x7
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#define PATH0_R_BT_LNA_IDX2_C 0x472C
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#define PATH0_R_BT_LNA_IDX2_C_M 0x38
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#define PATH0_R_BT_LNA_IDX3_C 0x472C
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#define PATH0_R_BT_LNA_IDX3_C_M 0x1C0
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#define PATH0_R_ELNA_SEL_MARGIN_LGC_C 0x472C
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#define PATH0_R_ELNA_SEL_MARGIN_LGC_C_M 0xE00
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#define PATH0_R_ELNA_SEL_MARGIN_NLGC_C 0x472C
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#define PATH0_R_ELNA_SEL_MARGIN_NLGC_C_M 0x7000
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#define PATH0_R_IBADC_CLIP_RATIO_C 0x472C
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#define PATH0_R_IBADC_CLIP_RATIO_C_M 0x38000
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#define PATH0_R_IBADC_CLIP_TH_C 0x472C
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#define PATH0_R_IBADC_CLIP_TH_C_M 0x1C0000
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#define PATH0_R_LGC_STEP_LIM_C 0x472C
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#define PATH0_R_LGC_STEP_LIM_C_M 0xE00000
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#define PATH0_R_LNA_IDX_INIT_C 0x472C
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#define PATH0_R_LNA_IDX_INIT_C_M 0x7000000
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#define PATH0_R_LNA_SEL_MARGIN_LGC_C 0x472C
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#define PATH0_R_LNA_SEL_MARGIN_LGC_C_M 0x38000000
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#define PATH0_R_LINEAR_STEP_MIN_C 0x472C
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#define PATH0_R_LINEAR_STEP_MIN_C_M 0xC0000000
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#define PATH0_R_LNA_SEL_MARGIN_NLGC_C 0x4730
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#define PATH0_R_LNA_SEL_MARGIN_NLGC_C_M 0x7
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#define PATH0_R_RXSEL_MARGIN_LGC_C 0x4730
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#define PATH0_R_RXSEL_MARGIN_LGC_C_M 0x38
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#define PATH0_R_RXSEL_MARGIN_NLGC_C 0x4730
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#define PATH0_R_RXSEL_MARGIN_NLGC_C_M 0x1C0
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#define PATH0_R_TIA_SEL_MARGIN_LGC_C 0x4730
|
#define PATH0_R_TIA_SEL_MARGIN_LGC_C_M 0xE00
|
#define PATH0_R_TIA_SEL_MARGIN_NLGC_C 0x4730
|
#define PATH0_R_TIA_SEL_MARGIN_NLGC_C_M 0x7000
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#define PATH0_R_WBADC_CLIP_RATIO_C 0x4730
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#define PATH0_R_WBADC_CLIP_RATIO_C_M 0x38000
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#define PATH0_R_WBADC_CLIP_TH_C 0x4730
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#define PATH0_R_WBADC_CLIP_TH_C_M 0x1C0000
|
#define PATH0_R_NLGC_STEP_LIM_C 0x4730
|
#define PATH0_R_NLGC_STEP_LIM_C_M 0x600000
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#define PATH0_R_NLGC_STEP_MIN_C 0x4730
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#define PATH0_R_NLGC_STEP_MIN_C_M 0x1800000
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#define PATH0_R_POST_PD_STEP_LIM_C 0x4730
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#define PATH0_R_POST_PD_STEP_LIM_C_M 0x6000000
|
#define PATH0_R_POST_PD_STEP_MIN_C 0x4730
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#define PATH0_R_POST_PD_STEP_MIN_C_M 0x18000000
|
#define PATH0_R_PRE_PD_STEP_LIM_C 0x4730
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#define PATH0_R_PRE_PD_STEP_LIM_C_M 0x60000000
|
#define PATH0_R_AGC_EN_C 0x4730
|
#define PATH0_R_AGC_EN_C_M 0x80000000
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#define PATH0_R_PRE_PD_STEP_MIN_C 0x4734
|
#define PATH0_R_PRE_PD_STEP_MIN_C_M 0x3
|
#define PATH0_R_WBADC_PW_ALPHA_H_C 0x4734
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#define PATH0_R_WBADC_PW_ALPHA_H_C_M 0xC
|
#define PATH0_R_WBADC_PW_ALPHA_L_C 0x4734
|
#define PATH0_R_WBADC_PW_ALPHA_L_C_M 0x30
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#define PATH0_R_A_WB_GIDX_00_ELNA_C 0x4734
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#define PATH0_R_A_WB_GIDX_00_ELNA_C_M 0x40
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#define PATH0_R_A_WB_GIDX_01_ELNA_C 0x4734
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#define PATH0_R_A_WB_GIDX_01_ELNA_C_M 0x80
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#define PATH0_R_A_WB_GIDX_02_ELNA_C 0x4734
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#define PATH0_R_A_WB_GIDX_02_ELNA_C_M 0x100
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#define PATH0_R_A_WB_GIDX_03_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_03_ELNA_C_M 0x200
|
#define PATH0_R_A_WB_GIDX_04_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_04_ELNA_C_M 0x400
|
#define PATH0_R_A_WB_GIDX_05_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_05_ELNA_C_M 0x800
|
#define PATH0_R_A_WB_GIDX_06_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_06_ELNA_C_M 0x1000
|
#define PATH0_R_A_WB_GIDX_07_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_07_ELNA_C_M 0x2000
|
#define PATH0_R_A_WB_GIDX_08_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_08_ELNA_C_M 0x4000
|
#define PATH0_R_A_WB_GIDX_09_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_09_ELNA_C_M 0x8000
|
#define PATH0_R_A_WB_GIDX_10_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_10_ELNA_C_M 0x10000
|
#define PATH0_R_A_WB_GIDX_11_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_11_ELNA_C_M 0x20000
|
#define PATH0_R_A_WB_GIDX_12_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_12_ELNA_C_M 0x40000
|
#define PATH0_R_A_WB_GIDX_13_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_13_ELNA_C_M 0x80000
|
#define PATH0_R_A_WB_GIDX_14_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_14_ELNA_C_M 0x100000
|
#define PATH0_R_A_WB_GIDX_15_ELNA_C 0x4734
|
#define PATH0_R_A_WB_GIDX_15_ELNA_C_M 0x200000
|
#define PATH0_R_GC_TIME_1T_MORE_C 0x4734
|
#define PATH0_R_GC_TIME_1T_MORE_C_M 0x400000
|
#define PATH0_R_G_WB_GIDX_00_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_00_ELNA_C_M 0x800000
|
#define PATH0_R_G_WB_GIDX_01_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_01_ELNA_C_M 0x1000000
|
#define PATH0_R_G_WB_GIDX_02_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_02_ELNA_C_M 0x2000000
|
#define PATH0_R_G_WB_GIDX_03_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_03_ELNA_C_M 0x4000000
|
#define PATH0_R_G_WB_GIDX_04_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_04_ELNA_C_M 0x8000000
|
#define PATH0_R_G_WB_GIDX_05_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_05_ELNA_C_M 0x10000000
|
#define PATH0_R_G_WB_GIDX_06_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_06_ELNA_C_M 0x20000000
|
#define PATH0_R_G_WB_GIDX_07_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_07_ELNA_C_M 0x40000000
|
#define PATH0_R_G_WB_GIDX_08_ELNA_C 0x4734
|
#define PATH0_R_G_WB_GIDX_08_ELNA_C_M 0x80000000
|
#define PATH0_R_G_WB_GIDX_09_ELNA_C 0x4738
|
#define PATH0_R_G_WB_GIDX_09_ELNA_C_M 0x1
|
#define PATH0_R_G_WB_GIDX_10_ELNA_C 0x4738
|
#define PATH0_R_G_WB_GIDX_10_ELNA_C_M 0x2
|
#define PATH0_R_G_WB_GIDX_11_ELNA_C 0x4738
|
#define PATH0_R_G_WB_GIDX_11_ELNA_C_M 0x4
|
#define PATH0_R_G_WB_GIDX_12_ELNA_C 0x4738
|
#define PATH0_R_G_WB_GIDX_12_ELNA_C_M 0x8
|
#define PATH0_R_G_WB_GIDX_13_ELNA_C 0x4738
|
#define PATH0_R_G_WB_GIDX_13_ELNA_C_M 0x10
|
#define PATH0_R_G_WB_GIDX_14_ELNA_C 0x4738
|
#define PATH0_R_G_WB_GIDX_14_ELNA_C_M 0x20
|
#define PATH0_R_G_WB_GIDX_15_ELNA_C 0x4738
|
#define PATH0_R_G_WB_GIDX_15_ELNA_C_M 0x40
|
#define PATH0_R_SE1_TIME_C 0x4738
|
#define PATH0_R_SE1_TIME_C_M 0x80
|
#define PATH0_R_SE1_TIME_NLGC_C 0x4738
|
#define PATH0_R_SE1_TIME_NLGC_C_M 0x100
|
#define PATH0_R_SE2_TIME_C 0x4738
|
#define PATH0_R_SE2_TIME_C_M 0x200
|
#define PATH0_R_SE2_TIME_NLGC_C 0x4738
|
#define PATH0_R_SE2_TIME_NLGC_C_M 0x400
|
#define PATH0_R_SE3_TIME_C 0x4738
|
#define PATH0_R_SE3_TIME_C_M 0x800
|
#define PATH0_R_SE4_TIME_C 0x4738
|
#define PATH0_R_SE4_TIME_C_M 0x1000
|
#define PATH0_R_SE5_TIME_C 0x4738
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#define PATH0_R_SE5_TIME_C_M 0x2000
|
#define PATH0_R_SE_TIME_DONE_C 0x4738
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#define PATH0_R_SE_TIME_DONE_C_M 0x4000
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#define PATH0_R_SE_TIME_LINEAR_EXT_C 0x4738
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#define PATH0_R_SE_TIME_LINEAR_EXT_C_M 0x8000
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#define PATH0_R_ACI_NRBW_EN_C 0x4738
|
#define PATH0_R_ACI_NRBW_EN_C_M 0x10000
|
#define PATH0_R_BAND_SEL_C 0x4738
|
#define PATH0_R_BAND_SEL_C_M 0x20000
|
#define PATH0_R_BT_RX_MODE_EN_C 0x4738
|
#define PATH0_R_BT_RX_MODE_EN_C_M 0x40000
|
#define PATH0_R_BT_SHARE_C 0x4738
|
#define PATH0_R_BT_SHARE_C_M 0x80000
|
#define PATH0_R_BT_TX_FORCE_NRBW_C 0x4738
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#define PATH0_R_BT_TX_FORCE_NRBW_C_M 0x100000
|
#define PATH0_R_BT_TX_MODE_EN_C 0x4738
|
#define PATH0_R_BT_TX_MODE_EN_C_M 0x200000
|
#define PATH0_R_BTG_PATH_C 0x4738
|
#define PATH0_R_BTG_PATH_C_M 0x400000
|
#define PATH0_R_CCK_FORCE_NRBW_C 0x4738
|
#define PATH0_R_CCK_FORCE_NRBW_C_M 0x800000
|
#define PATH0_R_DCCL_EN_C 0x4738
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#define PATH0_R_DCCL_EN_C_M 0x1000000
|
#define PATH0_R_ELNA_BYPASS_EN_C 0x4738
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#define PATH0_R_ELNA_BYPASS_EN_C_M 0x2000000
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#define PATH0_R_ELNA_EN_C 0x4738
|
#define PATH0_R_ELNA_EN_C_M 0x4000000
|
#define PATH0_R_ELNA_IDX_INIT_C 0x4738
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#define PATH0_R_ELNA_IDX_INIT_C_M 0x8000000
|
#define PATH0_R_FORCE_BT_COEX_C 0x4738
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#define PATH0_R_FORCE_BT_COEX_C_M 0x10000000
|
#define PATH0_R_FORCE_NRBW_C 0x4738
|
#define PATH0_R_FORCE_NRBW_C_M 0x20000000
|
#define PATH0_R_I_ONLY_C 0x4738
|
#define PATH0_R_I_ONLY_C_M 0x40000000
|
#define PATH0_R_LGC_DAGC_EN_C 0x4738
|
#define PATH0_R_LGC_DAGC_EN_C_M 0x80000000
|
#define PATH0_R_LINEAR_AGC_EN_C 0x473C
|
#define PATH0_R_LINEAR_AGC_EN_C_M 0x1
|
#define PATH0_R_LINEAR_MARGIN_MODE_C 0x473C
|
#define PATH0_R_LINEAR_MARGIN_MODE_C_M 0x2
|
#define PATH0_R_NLGC_AGC_EN_C 0x473C
|
#define PATH0_R_NLGC_AGC_EN_C_M 0x4
|
#define PATH0_R_NLGC_DAGC_EN_C 0x473C
|
#define PATH0_R_NLGC_DAGC_EN_C_M 0x8
|
#define PATH0_R_NRBW_DEF_C 0x473C
|
#define PATH0_R_NRBW_DEF_C_M 0x10
|
#define PATH0_R_POST_PD_AGC_EN_C 0x473C
|
#define PATH0_R_POST_PD_AGC_EN_C_M 0x20
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#define PATH0_R_PRE_PD_AGC_EN_C 0x473C
|
#define PATH0_R_PRE_PD_AGC_EN_C_M 0x40
|
#define PATH0_R_PURE_POST_PD_MODE_C 0x473C
|
#define PATH0_R_PURE_POST_PD_MODE_C_M 0x80
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#define PATH0_R_SYNC_PRE_PD_STEP_C 0x473C
|
#define PATH0_R_SYNC_PRE_PD_STEP_C_M 0x100
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#define PATH0_R_TIA_IDX_INIT_C 0x473C
|
#define PATH0_R_TIA_IDX_INIT_C_M 0x200
|
#define PATH0_R_TIA_SHRINK_DEF_C 0x473C
|
#define PATH0_R_TIA_SHRINK_DEF_C_M 0x400
|
#define PATH0_R_TIA_SHRINK_EN_C 0x473C
|
#define PATH0_R_TIA_SHRINK_EN_C_M 0x800
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#define PATH0_R_TIA_SHRINK_INIT_C 0x473C
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#define PATH0_R_TIA_SHRINK_INIT_C_M 0x1000
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#define PATH1_R_A_G_ELNA0_C 0x4740
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#define PATH1_R_A_G_ELNA0_C_M 0xFF
|
#define PATH1_R_A_G_ELNA1_C 0x4740
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#define PATH1_R_A_G_ELNA1_C_M 0xFF00
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#define PATH1_R_A_G_LNA0_C 0x4740
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#define PATH1_R_A_G_LNA0_C_M 0xFF0000
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#define PATH1_R_A_G_LNA1_C 0x4740
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#define PATH1_R_A_G_LNA1_C_M 0xFF000000
|
#define PATH1_R_A_G_LNA2_C 0x4744
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#define PATH1_R_A_G_LNA2_C_M 0xFF
|
#define PATH1_R_A_G_LNA3_C 0x4744
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#define PATH1_R_A_G_LNA3_C_M 0xFF00
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#define PATH1_R_A_G_LNA4_C 0x4744
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#define PATH1_R_A_G_LNA4_C_M 0xFF0000
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#define PATH1_R_A_G_LNA5_C 0x4744
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#define PATH1_R_A_G_LNA5_C_M 0xFF000000
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#define PATH1_R_A_G_LNA6_C 0x4748
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#define PATH1_R_A_G_LNA6_C_M 0xFF
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#define PATH1_R_A_G_RX0_C 0x4748
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#define PATH1_R_A_G_RX0_C_M 0xFF00
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#define PATH1_R_A_G_TIA0_C 0x4748
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#define PATH1_R_A_G_TIA0_C_M 0xFF0000
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#define PATH1_R_A_G_TIA1_C 0x4748
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#define PATH1_R_A_G_TIA1_C_M 0xFF000000
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#define PATH1_R_A_LNA0_OP1DB_C 0x474C
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#define PATH1_R_A_LNA0_OP1DB_C_M 0xFF
|
#define PATH1_R_A_LNA1_OP1DB_C 0x474C
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#define PATH1_R_A_LNA1_OP1DB_C_M 0xFF00
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#define PATH1_R_A_LNA2_OP1DB_C 0x474C
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#define PATH1_R_A_LNA2_OP1DB_C_M 0xFF0000
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#define PATH1_R_A_LNA3_OP1DB_C 0x474C
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#define PATH1_R_A_LNA3_OP1DB_C_M 0xFF000000
|
#define PATH1_R_A_LNA4_OP1DB_C 0x4750
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#define PATH1_R_A_LNA4_OP1DB_C_M 0xFF
|
#define PATH1_R_A_LNA5_OP1DB_C 0x4750
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#define PATH1_R_A_LNA5_OP1DB_C_M 0xFF00
|
#define PATH1_R_A_LNA6_OP1DB_C 0x4750
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#define PATH1_R_A_LNA6_OP1DB_C_M 0xFF0000
|
#define PATH1_R_A_RXOP1DB_C 0x4750
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#define PATH1_R_A_RXOP1DB_C_M 0xFF000000
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#define PATH1_R_A_TIA0_LNA0_OP1DB_C 0x4754
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#define PATH1_R_A_TIA0_LNA0_OP1DB_C_M 0xFF
|
#define PATH1_R_A_TIA0_LNA1_OP1DB_C 0x4754
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#define PATH1_R_A_TIA0_LNA1_OP1DB_C_M 0xFF00
|
#define PATH1_R_A_TIA0_LNA2_OP1DB_C 0x4754
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#define PATH1_R_A_TIA0_LNA2_OP1DB_C_M 0xFF0000
|
#define PATH1_R_A_TIA0_LNA3_OP1DB_C 0x4754
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#define PATH1_R_A_TIA0_LNA3_OP1DB_C_M 0xFF000000
|
#define PATH1_R_A_TIA0_LNA4_OP1DB_C 0x4758
|
#define PATH1_R_A_TIA0_LNA4_OP1DB_C_M 0xFF
|
#define PATH1_R_A_TIA0_LNA5_OP1DB_C 0x4758
|
#define PATH1_R_A_TIA0_LNA5_OP1DB_C_M 0xFF00
|
#define PATH1_R_A_TIA0_LNA6_OP1DB_C 0x4758
|
#define PATH1_R_A_TIA0_LNA6_OP1DB_C_M 0xFF0000
|
#define PATH1_R_A_TIA1_LNA6_OP1DB_C 0x4758
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#define PATH1_R_A_TIA1_LNA6_OP1DB_C_M 0xFF000000
|
#define PATH1_R_G_G_ELNA0_C 0x475C
|
#define PATH1_R_G_G_ELNA0_C_M 0xFF
|
#define PATH1_R_G_G_ELNA1_C 0x475C
|
#define PATH1_R_G_G_ELNA1_C_M 0xFF00
|
#define PATH1_R_G_G_LNA0_C 0x475C
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#define PATH1_R_G_G_LNA0_C_M 0xFF0000
|
#define PATH1_R_G_G_LNA1_C 0x475C
|
#define PATH1_R_G_G_LNA1_C_M 0xFF000000
|
#define PATH1_R_G_G_LNA2_C 0x4760
|
#define PATH1_R_G_G_LNA2_C_M 0xFF
|
#define PATH1_R_G_G_LNA3_C 0x4760
|
#define PATH1_R_G_G_LNA3_C_M 0xFF00
|
#define PATH1_R_G_G_LNA4_C 0x4760
|
#define PATH1_R_G_G_LNA4_C_M 0xFF0000
|
#define PATH1_R_G_G_LNA5_C 0x4760
|
#define PATH1_R_G_G_LNA5_C_M 0xFF000000
|
#define PATH1_R_G_G_LNA6_C 0x4764
|
#define PATH1_R_G_G_LNA6_C_M 0xFF
|
#define PATH1_R_G_G_RX0_C 0x4764
|
#define PATH1_R_G_G_RX0_C_M 0xFF00
|
#define PATH1_R_G_G_TIA0_C 0x4764
|
#define PATH1_R_G_G_TIA0_C_M 0xFF0000
|
#define PATH1_R_G_G_TIA1_C 0x4764
|
#define PATH1_R_G_G_TIA1_C_M 0xFF000000
|
#define PATH1_R_G_LGC_DAGC_C 0x4768
|
#define PATH1_R_G_LGC_DAGC_C_M 0xFF
|
#define PATH1_R_G_LNA0_OP1DB_C 0x4768
|
#define PATH1_R_G_LNA0_OP1DB_C_M 0xFF00
|
#define PATH1_R_G_LNA1_OP1DB_C 0x4768
|
#define PATH1_R_G_LNA1_OP1DB_C_M 0xFF0000
|
#define PATH1_R_G_LNA2_OP1DB_C 0x4768
|
#define PATH1_R_G_LNA2_OP1DB_C_M 0xFF000000
|
#define PATH1_R_G_LNA3_OP1DB_C 0x476C
|
#define PATH1_R_G_LNA3_OP1DB_C_M 0xFF
|
#define PATH1_R_G_LNA4_OP1DB_C 0x476C
|
#define PATH1_R_G_LNA4_OP1DB_C_M 0xFF00
|
#define PATH1_R_G_LNA5_OP1DB_C 0x476C
|
#define PATH1_R_G_LNA5_OP1DB_C_M 0xFF0000
|
#define PATH1_R_G_LNA6_OP1DB_C 0x476C
|
#define PATH1_R_G_LNA6_OP1DB_C_M 0xFF000000
|
#define PATH1_R_G_NLGC_DAGC_C 0x4770
|
#define PATH1_R_G_NLGC_DAGC_C_M 0xFF
|
#define PATH1_R_G_RXOP1DB_C 0x4770
|
#define PATH1_R_G_RXOP1DB_C_M 0xFF00
|
#define PATH1_R_G_TIA0_LNA0_OP1DB_C 0x4770
|
#define PATH1_R_G_TIA0_LNA0_OP1DB_C_M 0xFF0000
|
#define PATH1_R_G_TIA0_LNA1_OP1DB_C 0x4770
|
#define PATH1_R_G_TIA0_LNA1_OP1DB_C_M 0xFF000000
|
#define PATH1_R_G_TIA0_LNA2_OP1DB_C 0x4774
|
#define PATH1_R_G_TIA0_LNA2_OP1DB_C_M 0xFF
|
#define PATH1_R_G_TIA0_LNA3_OP1DB_C 0x4774
|
#define PATH1_R_G_TIA0_LNA3_OP1DB_C_M 0xFF00
|
#define PATH1_R_G_TIA0_LNA4_OP1DB_C 0x4774
|
#define PATH1_R_G_TIA0_LNA4_OP1DB_C_M 0xFF0000
|
#define PATH1_R_G_TIA0_LNA5_OP1DB_C 0x4774
|
#define PATH1_R_G_TIA0_LNA5_OP1DB_C_M 0xFF000000
|
#define PATH1_R_G_TIA0_LNA6_OP1DB_C 0x4778
|
#define PATH1_R_G_TIA0_LNA6_OP1DB_C_M 0xFF
|
#define PATH1_R_G_TIA1_LNA6_OP1DB_C 0x4778
|
#define PATH1_R_G_TIA1_LNA6_OP1DB_C_M 0xFF00
|
#define PATH1_R_G_OFST_C 0x4778
|
#define PATH1_R_G_OFST_C_M 0xFF0000
|
#define PATH1_R_IBADC_SAT_TH_C 0x4778
|
#define PATH1_R_IBADC_SAT_TH_C_M 0xFF000000
|
#define PATH1_R_IBADC_UNDER_TH_C 0x477C
|
#define PATH1_R_IBADC_UNDER_TH_C_M 0xFF
|
#define PATH1_R_WBADC_SAT_TH_C 0x477C
|
#define PATH1_R_WBADC_SAT_TH_C_M 0xFF00
|
#define PATH1_R_WBADC_SAT_TH_ANTWGT_C 0x477C
|
#define PATH1_R_WBADC_SAT_TH_ANTWGT_C_M 0xFF0000
|
#define PATH1_R_WBADC_UNDER_TH_C 0x477C
|
#define PATH1_R_WBADC_UNDER_TH_C_M 0xFF000000
|
#define PATH1_R_DCCL_SYNC_BKP1_C 0x4780
|
#define PATH1_R_DCCL_SYNC_BKP1_C_M 0xFFFFFFFF
|
#define PATH1_R_DCCL_SYNC_BKP2_C 0x4784
|
#define PATH1_R_DCCL_SYNC_BKP2_C_M 0xFFFFFFFF
|
#define PATH1_R_ALPHA_END_IDX_C 0x4788
|
#define PATH1_R_ALPHA_END_IDX_C_M 0xF
|
#define PATH1_R_ALPHA_START_IDX_C 0x4788
|
#define PATH1_R_ALPHA_START_IDX_C_M 0xF0
|
#define PATH1_R_TIME_CONST_IDX_C 0x4788
|
#define PATH1_R_TIME_CONST_IDX_C_M 0x700
|
#define PATH1_R_RXFIR_BKP_C 0x478C
|
#define PATH1_R_RXFIR_BKP_C_M 0xFFFFFFFF
|
#define PATH1_R_FORCE_FIR_TYPE_C 0x4790
|
#define PATH1_R_FORCE_FIR_TYPE_C_M 0x3
|
#define PATH1_R_CCK_CCA_SHRINK_EN_C 0x4790
|
#define PATH1_R_CCK_CCA_SHRINK_EN_C_M 0x4
|
#define PATH1_P20_R_L1_CFO_CMP_EN_C 0x4794
|
#define PATH1_P20_R_L1_CFO_CMP_EN_C_M 0x1
|
#define PATH1_S20_R_L1_CFO_CMP_EN_C 0x4798
|
#define PATH1_S20_R_L1_CFO_CMP_EN_C_M 0x1
|
#define PATH1_R_NBI_NOTCH_BKP1_C 0x479C
|
#define PATH1_R_NBI_NOTCH_BKP1_C_M 0xFFFFFFFF
|
#define PATH1_R_NBI_NOTCH_BKP2_C 0x47A0
|
#define PATH1_R_NBI_NOTCH_BKP2_C_M 0xFFFFFFFF
|
#define PATH1_R_NBI_IDX_C 0x47A4
|
#define PATH1_R_NBI_IDX_C_M 0xFF
|
#define PATH1_R_CORNER_IDX_C 0x47A4
|
#define PATH1_R_CORNER_IDX_C_M 0x300
|
#define PATH1_R_NBI_FRAC_IDX_C 0x47A4
|
#define PATH1_R_NBI_FRAC_IDX_C_M 0xC00
|
#define PATH1_R_NBI_NOTCH_EN_C 0x47A4
|
#define PATH1_R_NBI_NOTCH_EN_C_M 0x1000
|
#define PATH1_P20_R_DAGC_EXTRA_SETTLING_TIME_C 0x47A8
|
#define PATH1_P20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7
|
#define PATH1_P20_R_DAGC_SETTLING_TIME_C 0x47A8
|
#define PATH1_P20_R_DAGC_SETTLING_TIME_C_M 0x18
|
#define PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C 0x47A8
|
#define PATH1_P20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20
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#define PATH1_P20_R_PW_EST_SHORT_TIME_FAGC_C 0x47A8
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#define PATH1_P20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40
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#define PATH1_P20_R_PW_EST_TIME_FAGC_C 0x47A8
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#define PATH1_P20_R_PW_EST_TIME_FAGC_C_M 0x80
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#define PATH1_P20_R_PW_EST_TIME_PAGC_C 0x47A8
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#define PATH1_P20_R_PW_EST_TIME_PAGC_C_M 0x100
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#define PATH1_P20_R_PW_EST_TIME_RFGC_C 0x47A8
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#define PATH1_P20_R_PW_EST_TIME_RFGC_C_M 0x200
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#define PATH1_P20_R_SDAGC_EN_C 0x47A8
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#define PATH1_P20_R_SDAGC_EN_C_M 0x400
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#define PATH1_S20_R_DAGC_EXTRA_SETTLING_TIME_C 0x47AC
|
#define PATH1_S20_R_DAGC_EXTRA_SETTLING_TIME_C_M 0x7
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#define PATH1_S20_R_DAGC_SETTLING_TIME_C 0x47AC
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#define PATH1_S20_R_DAGC_SETTLING_TIME_C_M 0x18
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#define PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C 0x47AC
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#define PATH1_S20_R_FOLLOW_BY_PAGCUGC_EN_C_M 0x20
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#define PATH1_S20_R_PW_EST_SHORT_TIME_FAGC_C 0x47AC
|
#define PATH1_S20_R_PW_EST_SHORT_TIME_FAGC_C_M 0x40
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#define PATH1_S20_R_PW_EST_TIME_FAGC_C 0x47AC
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#define PATH1_S20_R_PW_EST_TIME_FAGC_C_M 0x80
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#define PATH1_S20_R_PW_EST_TIME_PAGC_C 0x47AC
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#define PATH1_S20_R_PW_EST_TIME_PAGC_C_M 0x100
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#define PATH1_S20_R_PW_EST_TIME_RFGC_C 0x47AC
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#define PATH1_S20_R_PW_EST_TIME_RFGC_C_M 0x200
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#define PATH1_S20_R_SDAGC_EN_C 0x47AC
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#define PATH1_S20_R_SDAGC_EN_C_M 0x400
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#define PATH1_R_5MDET_BKP1_C 0x47B0
|
#define PATH1_R_5MDET_BKP1_C_M 0xFFFFFFFF
|
#define PATH1_R_5MDET_BKP2_C 0x47B4
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#define PATH1_R_5MDET_BKP2_C_M 0xFFFFFFFF
|
#define PATH1_R_5MDET_TH_DB_C 0x47B8
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#define PATH1_R_5MDET_TH_DB_C_M 0x3F
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#define PATH1_R_5MDET_MASK_SB0_C 0x47B8
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#define PATH1_R_5MDET_MASK_SB0_C_M 0x40
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#define PATH1_R_5MDET_MASK_SB1_C 0x47B8
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#define PATH1_R_5MDET_MASK_SB1_C_M 0x80
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#define PATH1_R_5MDET_MASK_SB2_C 0x47B8
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#define PATH1_R_5MDET_MASK_SB2_C_M 0x100
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#define PATH1_R_5MDET_MASK_SB3_C 0x47B8
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#define PATH1_R_5MDET_MASK_SB3_C_M 0x200
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#define PATH1_R_5MDET_MODE_C 0x47B8
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#define PATH1_R_5MDET_MODE_C_M 0x400
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#define PATH1_R_IIR_PW_AVG_EN_C 0x47B8
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#define PATH1_R_IIR_PW_AVG_EN_C_M 0x800
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#define PATH1_R_SBF5M_EN_C 0x47B8
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#define PATH1_R_SBF5M_EN_C_M 0x1000
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#define POP_RSV_C 0x47C4
|
#define POP_RSV_C_M 0xFFFFFFFF
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#define CLIPPING_LVL_C 0x47C8
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#define CLIPPING_LVL_C_M 0x3FF
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#define CLIPPING_OBS_C 0x47C8
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#define CLIPPING_OBS_C_M 0x1FC00
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#define CLIPPING_RATIO_C 0x47C8
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#define CLIPPING_RATIO_C_M 0xFE0000
|
#define B_THD_C 0x47C8
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#define B_THD_C_M 0x3F000000
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#define BT_GNT_POP_EN_C 0x47C8
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#define BT_GNT_POP_EN_C_M 0x40000000
|
#define CCK_EN_C 0x47C8
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#define CCK_EN_C_M 0x80000000
|
#define M_THD_C 0x47CC
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#define M_THD_C_M 0x3F
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#define CCK_DROP_TH_C 0x47CC
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#define CCK_DROP_TH_C_M 0x7C0
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#define CCK_POP_H_TH_C 0x47CC
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#define CCK_POP_H_TH_C_M 0xF800
|
#define CCK_POP_L_TH_C 0x47CC
|
#define CCK_POP_L_TH_C_M 0x1F0000
|
#define D_CNT_C 0x47CC
|
#define D_CNT_C_M 0x3E00000
|
#define D_THD_C 0x47CC
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#define D_THD_C_M 0x7C000000
|
#define D_EN_C 0x47CC
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#define D_EN_C_M 0x80000000
|
#define H_THD_C 0x47D0
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#define H_THD_C_M 0x1F
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#define L_THD_C 0x47D0
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#define L_THD_C_M 0x3E0
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#define OFDM_DROP_TH_C 0x47D0
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#define OFDM_DROP_TH_C_M 0x7C00
|
#define OFDM_POP_H_TH_C 0x47D0
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#define OFDM_POP_H_TH_C_M 0xF8000
|
#define OFDM_POP_L_TH_C 0x47D0
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#define OFDM_POP_L_TH_C_M 0x1F00000
|
#define P_CNT_C 0x47D0
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#define P_CNT_C_M 0x3E000000
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#define D_LSIG_RDY_C 0x47D0
|
#define D_LSIG_RDY_C_M 0x40000000
|
#define DL_EN_C 0x47D0
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#define DL_EN_C_M 0x80000000
|
#define O_THD_C 0x47D4
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#define O_THD_C_M 0x7
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#define REFPW_LB_C 0x47D4
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#define REFPW_LB_C_M 0x38
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#define M_40_C 0x47D4
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#define M_40_C_M 0x40
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#define OFDM_EN_C 0x47D4
|
#define OFDM_EN_C_M 0x80
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#define P_EN_C 0x47D4
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#define P_EN_C_M 0x100
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#define P_LSIG_RDY_C 0x47D4
|
#define P_LSIG_RDY_C_M 0x200
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#define REFPW_LB_EN_C 0x47D4
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#define REFPW_LB_EN_C_M 0x400
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#define P20_SEG0R_PINTHD_C 0x47D8
|
#define P20_SEG0R_PINTHD_C_M 0xFF
|
#define P20_SEG0R_PWDIF_C 0x47D8
|
#define P20_SEG0R_PWDIF_C_M 0x3F00
|
#define P20_SEG0R_P20TAR_C 0x47D8
|
#define P20_SEG0R_P20TAR_C_M 0x7C000
|
#define P20_SEG0R_BT_WGT_C 0x47D8
|
#define P20_SEG0R_BT_WGT_C_M 0x380000
|
#define P20_SEG0R_UNIT_WGT_OPT_C 0x47D8
|
#define P20_SEG0R_UNIT_WGT_OPT_C_M 0x400000
|
#define P20_SEG0R_WGT_EN_C 0x47D8
|
#define P20_SEG0R_WGT_EN_C_M 0x800000
|
#define P20_SEG0R_ZERO_WGT_EN_C 0x47D8
|
#define P20_SEG0R_ZERO_WGT_EN_C_M 0x1000000
|
#define S20_SEG0R_PINTHD_C 0x47DC
|
#define S20_SEG0R_PINTHD_C_M 0xFF
|
#define S20_SEG0R_PWDIF_C 0x47DC
|
#define S20_SEG0R_PWDIF_C_M 0x3F00
|
#define S20_SEG0R_P20TAR_C 0x47DC
|
#define S20_SEG0R_P20TAR_C_M 0x7C000
|
#define S20_SEG0R_BT_WGT_C 0x47DC
|
#define S20_SEG0R_BT_WGT_C_M 0x380000
|
#define S20_SEG0R_UNIT_WGT_OPT_C 0x47DC
|
#define S20_SEG0R_UNIT_WGT_OPT_C_M 0x400000
|
#define S20_SEG0R_WGT_EN_C 0x47DC
|
#define S20_SEG0R_WGT_EN_C_M 0x800000
|
#define S20_SEG0R_ZERO_WGT_EN_C 0x47DC
|
#define S20_SEG0R_ZERO_WGT_EN_C_M 0x1000000
|
#define BW_INDSEG0R_BW_GAIN_CHK_THD_C 0x47E0
|
#define BW_INDSEG0R_BW_GAIN_CHK_THD_C_M 0x3F
|
#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_C 0x47E0
|
#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_C_M 0x7C0
|
#define BW_INDSEG0R_CBW20_HIGH_PIN_TH_BWD_C 0x47E0
|
#define BW_INDSEG0R_CBW20_HIGH_PIN_TH_BWD_C_M 0xF800
|
#define BW_INDSEG0R_CBW20_LOW_PIN_TH_BW_C 0x47E0
|
#define BW_INDSEG0R_CBW20_LOW_PIN_TH_BW_C_M 0x1F0000
|
#define BW_INDSEG0R_CBW40_HIGH_PIN_TH_BWD_C 0x47E0
|
#define BW_INDSEG0R_CBW40_HIGH_PIN_TH_BWD_C_M 0x3E00000
|
#define BW_INDSEG0R_CBW40_LOW_PIN_TH_BW_C 0x47E0
|
#define BW_INDSEG0R_CBW40_LOW_PIN_TH_BW_C_M 0x7C000000
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#define BW_INDSEG0R_BW_GAIN_CHK_EN_C 0x47E0
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#define BW_INDSEG0R_BW_GAIN_CHK_EN_C_M 0x80000000
|
#define BW_INDSEG0R_CBW80_HIGH_PIN_TH_BWD_C 0x47E4
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#define BW_INDSEG0R_CBW80_HIGH_PIN_TH_BWD_C_M 0x1F
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#define BW_INDSEG0R_CBW80_LOW_PIN_TH_BW_C 0x47E4
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#define BW_INDSEG0R_CBW80_LOW_PIN_TH_BW_C_M 0x3E0
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX1_C 0x47E4
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX1_C_M 0x7C00
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX2_C 0x47E4
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_20_NRX2_C_M 0xF8000
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX1_C 0x47E4
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX1_C_M 0x1F00000
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX2_C 0x47E4
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_40_NRX2_C_M 0x3E000000
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#define BW_INDSEG0R_BW_START_CHK_EN_C 0x47E4
|
#define BW_INDSEG0R_BW_START_CHK_EN_C_M 0x40000000
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#define BW_INDSEG0R_BW_TIMING_CTRL_OPT_C 0x47E4
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#define BW_INDSEG0R_BW_TIMING_CTRL_OPT_C_M 0x80000000
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX1_C 0x47E8
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX1_C_M 0x1F
|
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX2_C 0x47E8
|
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80_NRX2_C_M 0x3E0
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX1_C 0x47E8
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX1_C_M 0x7C00
|
#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX2_C 0x47E8
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#define BW_INDSEG0R_SUB20_INDICATOR_TH_80P80_NRX2_C_M 0xF8000
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#define BW_INDSEG0R_BW_COUNT_MAX_BY_FALLING_C 0x47E8
|
#define BW_INDSEG0R_BW_COUNT_MAX_BY_FALLING_C_M 0xF00000
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#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_AFTER_L1_IS_FOUND_C 0x47E8
|
#define BW_INDSEG0R_BW_END_HALF_SYM_COUNT_AFTER_L1_IS_FOUND_C_M 0xF000000
|
#define BW_INDSEG0R_BW_START_HALF_SYM_COUNT_C 0x47E8
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#define BW_INDSEG0R_BW_START_HALF_SYM_COUNT_C_M 0xF0000000
|
#define BW_INDSEG0R_INDICATOR_TH_OFST_0_C 0x47EC
|
#define BW_INDSEG0R_INDICATOR_TH_OFST_0_C_M 0xF
|
#define BW_INDSEG0R_INDICATOR_TH_OFST_1_C 0x47EC
|
#define BW_INDSEG0R_INDICATOR_TH_OFST_1_C_M 0xF0
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#define BW_INDSEG0R_INDICATOR_TH_OFST_BY_RSSI_C 0x47EC
|
#define BW_INDSEG0R_INDICATOR_TH_OFST_BY_RSSI_C_M 0xF00
|
#define BW_INDSEG0R_INTF_TH_0_C 0x47EC
|
#define BW_INDSEG0R_INTF_TH_0_C_M 0xF000
|
#define BW_INDSEG0R_INTF_TH_1_C 0x47EC
|
#define BW_INDSEG0R_INTF_TH_1_C_M 0xF0000
|
#define BW_INDSEG0R_START_HALF_SYM_OFST_BY_RSSI_C 0x47EC
|
#define BW_INDSEG0R_START_HALF_SYM_OFST_BY_RSSI_C_M 0xF00000
|
#define BW_INDSEG0R_CR_SWITCH_BY_PIN_C 0x47EC
|
#define BW_INDSEG0R_CR_SWITCH_BY_PIN_C_M 0x7000000
|
#define BW_INDSEG0R_SUB20_SEARCH_TH_C 0x47EC
|
#define BW_INDSEG0R_SUB20_SEARCH_TH_C_M 0x38000000
|
#define BW_INDSEG0R_CR_SWITCH_BY_ACI_EN_C 0x47EC
|
#define BW_INDSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x40000000
|
#define BW_INDSEG0R_CR_SWITCH_BY_RSSI_EN_C 0x47EC
|
#define BW_INDSEG0R_CR_SWITCH_BY_RSSI_EN_C_M 0x80000000
|
#define BW_INDSEG0R_EARLY_DROP_BY_L1_C 0x47F0
|
#define BW_INDSEG0R_EARLY_DROP_BY_L1_C_M 0x1
|
#define BW_INDSEG0R_FORCE_BW_EN_C 0x47F0
|
#define BW_INDSEG0R_FORCE_BW_EN_C_M 0x2
|
#define BW_INDSEG0R_FORCE_BW_MODE_C 0x47F0
|
#define BW_INDSEG0R_FORCE_BW_MODE_C_M 0x4
|
#define SEG0R_HIGH_PIN_TH_CFO_C 0x47F4
|
#define SEG0R_HIGH_PIN_TH_CFO_C_M 0x1F
|
#define SEG0R_HIGH_PIN_TH_CFOE_C 0x47F4
|
#define SEG0R_HIGH_PIN_TH_CFOE_C_M 0x1E0
|
#define SEG0R_CFO_START_OFST_C 0x47F4
|
#define SEG0R_CFO_START_OFST_C_M 0xE00
|
#define SEG0R_CFO_SIZE_OPT_C 0x47F4
|
#define SEG0R_CFO_SIZE_OPT_C_M 0x3000
|
#define SEG0R_COUNT_INI_PH_C 0x47F4
|
#define SEG0R_COUNT_INI_PH_C_M 0xC000
|
#define SEG0R_ZERO_CRO_CNT_DIFF_AVG_TH_C 0x47F8
|
#define SEG0R_ZERO_CRO_CNT_DIFF_AVG_TH_C_M 0x3FF
|
#define SEG0R_ZERO_CRO_CNT_DIFF_VAR_TH_C 0x47F8
|
#define SEG0R_ZERO_CRO_CNT_DIFF_VAR_TH_C_M 0xFFC00
|
#define SEG0R_H2L_TH_C 0x47F8
|
#define SEG0R_H2L_TH_C_M 0xFF00000
|
#define SEG0R_ZERO_CRO_OBS_INTRVL_C 0x47F8
|
#define SEG0R_ZERO_CRO_OBS_INTRVL_C_M 0xF0000000
|
#define SEG0R_L2H_TH_C 0x47FC
|
#define SEG0R_L2H_TH_C_M 0xFF
|
#define SEG0R_RXI_CHK_TH_C 0x47FC
|
#define SEG0R_RXI_CHK_TH_C_M 0xFF00
|
#define SEG0R_ADCPW_C 0x47FC
|
#define SEG0R_ADCPW_C_M 0x7F0000
|
#define SEG0R_ZERO_CRO_HIGH_TH_C 0x47FC
|
#define SEG0R_ZERO_CRO_HIGH_TH_C_M 0x3F800000
|
#define SEG0R_DCRM_EN_C 0x47FC
|
#define SEG0R_DCRM_EN_C_M 0x40000000
|
#define SEG0R_RFGC_EN_C 0x47FC
|
#define SEG0R_RFGC_EN_C_M 0x80000000
|
#define SEG0R_DC_COUNT_MAX_C 0x4800
|
#define SEG0R_DC_COUNT_MAX_C_M 0xF
|
#define SEG0R_DC_HIGH_TH_20_NRX1_C 0x4800
|
#define SEG0R_DC_HIGH_TH_20_NRX1_C_M 0xF0
|
#define SEG0R_DC_HIGH_TH_20_NRX2_C 0x4800
|
#define SEG0R_DC_HIGH_TH_20_NRX2_C_M 0xF00
|
#define SEG0R_DC_HIGH_TH_40_NRX1_C 0x4800
|
#define SEG0R_DC_HIGH_TH_40_NRX1_C_M 0xF000
|
#define SEG0R_DC_HIGH_TH_40_NRX2_C 0x4800
|
#define SEG0R_DC_HIGH_TH_40_NRX2_C_M 0xF0000
|
#define SEG0R_DC_HIGH_TH_80_NRX1_C 0x4800
|
#define SEG0R_DC_HIGH_TH_80_NRX1_C_M 0xF00000
|
#define SEG0R_DC_HIGH_TH_80_NRX2_C 0x4800
|
#define SEG0R_DC_HIGH_TH_80_NRX2_C_M 0xF000000
|
#define SEG0R_DC_HIGH_TH_80P80_NRX1_C 0x4800
|
#define SEG0R_DC_HIGH_TH_80P80_NRX1_C_M 0xF0000000
|
#define SEG0R_DC_HIGH_TH_80P80_NRX2_C 0x4804
|
#define SEG0R_DC_HIGH_TH_80P80_NRX2_C_M 0xF
|
#define SEG0R_DC_LOW_TH_20_NRX1_C 0x4804
|
#define SEG0R_DC_LOW_TH_20_NRX1_C_M 0xF0
|
#define SEG0R_DC_LOW_TH_20_NRX2_C 0x4804
|
#define SEG0R_DC_LOW_TH_20_NRX2_C_M 0xF00
|
#define SEG0R_DC_LOW_TH_40_NRX1_C 0x4804
|
#define SEG0R_DC_LOW_TH_40_NRX1_C_M 0xF000
|
#define SEG0R_DC_LOW_TH_40_NRX2_C 0x4804
|
#define SEG0R_DC_LOW_TH_40_NRX2_C_M 0xF0000
|
#define SEG0R_DC_LOW_TH_80_NRX1_C 0x4804
|
#define SEG0R_DC_LOW_TH_80_NRX1_C_M 0xF00000
|
#define SEG0R_DC_LOW_TH_80_NRX2_C 0x4804
|
#define SEG0R_DC_LOW_TH_80_NRX2_C_M 0xF000000
|
#define SEG0R_DC_LOW_TH_80P80_NRX1_C 0x4804
|
#define SEG0R_DC_LOW_TH_80P80_NRX1_C_M 0xF0000000
|
#define SEG0R_DC_LOW_TH_80P80_NRX2_C 0x4808
|
#define SEG0R_DC_LOW_TH_80P80_NRX2_C_M 0xF
|
#define SEG0R_DC_TH_OFST_C 0x4808
|
#define SEG0R_DC_TH_OFST_C_M 0xF0
|
#define SEG0R_DCFI_COUNT_MAX_C 0x4808
|
#define SEG0R_DCFI_COUNT_MAX_C_M 0xF00
|
#define SEG0R_DCFI_HIGH_TH_20_NRX1_C 0x4808
|
#define SEG0R_DCFI_HIGH_TH_20_NRX1_C_M 0xF000
|
#define SEG0R_DCFI_HIGH_TH_20_NRX2_C 0x4808
|
#define SEG0R_DCFI_HIGH_TH_20_NRX2_C_M 0xF0000
|
#define SEG0R_DCFI_HIGH_TH_40_NRX1_C 0x4808
|
#define SEG0R_DCFI_HIGH_TH_40_NRX1_C_M 0xF00000
|
#define SEG0R_DCFI_HIGH_TH_40_NRX2_C 0x4808
|
#define SEG0R_DCFI_HIGH_TH_40_NRX2_C_M 0xF000000
|
#define SEG0R_DCFI_HIGH_TH_80_NRX1_C 0x4808
|
#define SEG0R_DCFI_HIGH_TH_80_NRX1_C_M 0xF0000000
|
#define SEG0R_DCFI_HIGH_TH_80_NRX2_C 0x480C
|
#define SEG0R_DCFI_HIGH_TH_80_NRX2_C_M 0xF
|
#define SEG0R_DCFI_HIGH_TH_80P80_NRX1_C 0x480C
|
#define SEG0R_DCFI_HIGH_TH_80P80_NRX1_C_M 0xF0
|
#define SEG0R_DCFI_HIGH_TH_80P80_NRX2_C 0x480C
|
#define SEG0R_DCFI_HIGH_TH_80P80_NRX2_C_M 0xF00
|
#define SEG0R_DCFI_LOW_TH_20_NRX1_C 0x480C
|
#define SEG0R_DCFI_LOW_TH_20_NRX1_C_M 0xF000
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#define SEG0R_DCFI_LOW_TH_20_NRX2_C 0x480C
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#define SEG0R_DCFI_LOW_TH_20_NRX2_C_M 0xF0000
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#define SEG0R_DCFI_LOW_TH_40_NRX1_C 0x480C
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#define SEG0R_DCFI_LOW_TH_40_NRX1_C_M 0xF00000
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#define SEG0R_DCFI_LOW_TH_40_NRX2_C 0x480C
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#define SEG0R_DCFI_LOW_TH_40_NRX2_C_M 0xF000000
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#define SEG0R_DCFI_LOW_TH_80_NRX1_C 0x480C
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#define SEG0R_DCFI_LOW_TH_80_NRX1_C_M 0xF0000000
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#define SEG0R_DCFI_LOW_TH_80_NRX2_C 0x4810
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#define SEG0R_DCFI_LOW_TH_80_NRX2_C_M 0xF
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#define SEG0R_DCFI_LOW_TH_80P80_NRX1_C 0x4810
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#define SEG0R_DCFI_LOW_TH_80P80_NRX1_C_M 0xF0
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#define SEG0R_DCFI_LOW_TH_80P80_NRX2_C 0x4810
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#define SEG0R_DCFI_LOW_TH_80P80_NRX2_C_M 0xF00
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#define SEG0R_DCFI_REF_COUNT_MAX_C 0x4810
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#define SEG0R_DCFI_REF_COUNT_MAX_C_M 0xF000
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#define SEG0R_DCFI_TH_OFST_C 0x4810
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#define SEG0R_DCFI_TH_OFST_C_M 0xF0000
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#define SEG0R_DCPR_HIGH_TH_20_NRX1_C 0x4810
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#define SEG0R_DCPR_HIGH_TH_20_NRX1_C_M 0xF00000
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#define SEG0R_DCPR_HIGH_TH_20_NRX2_C 0x4810
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#define SEG0R_DCPR_HIGH_TH_20_NRX2_C_M 0xF000000
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#define SEG0R_DCPR_HIGH_TH_40_NRX1_C 0x4810
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#define SEG0R_DCPR_HIGH_TH_40_NRX1_C_M 0xF0000000
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#define SEG0R_DCPR_HIGH_TH_40_NRX2_C 0x4814
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#define SEG0R_DCPR_HIGH_TH_40_NRX2_C_M 0xF
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#define SEG0R_DCPR_HIGH_TH_80_NRX1_C 0x4814
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#define SEG0R_DCPR_HIGH_TH_80_NRX1_C_M 0xF0
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#define SEG0R_DCPR_HIGH_TH_80_NRX2_C 0x4814
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#define SEG0R_DCPR_HIGH_TH_80_NRX2_C_M 0xF00
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#define SEG0R_DCPR_HIGH_TH_80P80_NRX1_C 0x4814
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#define SEG0R_DCPR_HIGH_TH_80P80_NRX1_C_M 0xF000
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#define SEG0R_DCPR_HIGH_TH_80P80_NRX2_C 0x4814
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#define SEG0R_DCPR_HIGH_TH_80P80_NRX2_C_M 0xF0000
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#define SEG0R_DCPR_LOW_TH_20_NRX1_C 0x4814
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#define SEG0R_DCPR_LOW_TH_20_NRX1_C_M 0xF00000
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#define SEG0R_DCPR_LOW_TH_20_NRX2_C 0x4814
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#define SEG0R_DCPR_LOW_TH_20_NRX2_C_M 0xF000000
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#define SEG0R_DCPR_LOW_TH_40_NRX1_C 0x4814
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#define SEG0R_DCPR_LOW_TH_40_NRX1_C_M 0xF0000000
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#define SEG0R_DCPR_LOW_TH_40_NRX2_C 0x4818
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#define SEG0R_DCPR_LOW_TH_40_NRX2_C_M 0xF
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#define SEG0R_DCPR_LOW_TH_80_NRX1_C 0x4818
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#define SEG0R_DCPR_LOW_TH_80_NRX1_C_M 0xF0
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#define SEG0R_DCPR_LOW_TH_80_NRX2_C 0x4818
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#define SEG0R_DCPR_LOW_TH_80_NRX2_C_M 0xF00
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#define SEG0R_DCPR_LOW_TH_80P80_NRX1_C 0x4818
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#define SEG0R_DCPR_LOW_TH_80P80_NRX1_C_M 0xF000
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#define SEG0R_DCPR_LOW_TH_80P80_NRX2_C 0x4818
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#define SEG0R_DCPR_LOW_TH_80P80_NRX2_C_M 0xF0000
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#define SEG0R_DCPR_RST_TH_C 0x4818
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#define SEG0R_DCPR_RST_TH_C_M 0xF00000
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#define SEG0R_DCPR_COUNT_MAX_C 0x4818
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#define SEG0R_DCPR_COUNT_MAX_C_M 0x3000000
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#define SEG0R_DCPR_RESEARCH_COUNT_MAX_C 0x4818
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#define SEG0R_DCPR_RESEARCH_COUNT_MAX_C_M 0xC000000
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#define SEG0R_DCPR_RST_COUNT_MAX_C 0x4818
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#define SEG0R_DCPR_RST_COUNT_MAX_C_M 0x30000000
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#define SEG0R_CBW20_LOW_PIN_TH_FINE_TUNE_C 0x481C
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#define SEG0R_CBW20_LOW_PIN_TH_FINE_TUNE_C_M 0x1F
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#define SEG0R_CBW40_LOW_PIN_TH_FINE_TUNE_C 0x481C
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#define SEG0R_CBW40_LOW_PIN_TH_FINE_TUNE_C_M 0x3E0
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#define SEG0R_CBW80_LOW_PIN_TH_FINE_TUNE_C 0x481C
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#define SEG0R_CBW80_LOW_PIN_TH_FINE_TUNE_C_M 0x7C00
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#define SEG0R_CBW80P80_LOW_PIN_TH_FINE_TUNE_C 0x481C
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#define SEG0R_CBW80P80_LOW_PIN_TH_FINE_TUNE_C_M 0xF8000
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#define SEG0R_FINE_TUNE_STOP_LMT_C 0x481C
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#define SEG0R_FINE_TUNE_STOP_LMT_C_M 0x1F00000
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#define SEG0R_CBW20_DC_MAX_RATIO_C 0x481C
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#define SEG0R_CBW20_DC_MAX_RATIO_C_M 0x1E000000
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#define SEG0R_FINE_TUNE_DELTA_C 0x481C
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#define SEG0R_FINE_TUNE_DELTA_C_M 0xE0000000
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#define SEG0R_CBW40_DC_MAX_RATIO_C 0x4820
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#define SEG0R_CBW40_DC_MAX_RATIO_C_M 0xF
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#define SEG0R_CBW80_DC_MAX_RATIO_C 0x4820
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#define SEG0R_CBW80_DC_MAX_RATIO_C_M 0xF0
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#define SEG0R_CBW80P80_DC_MAX_RATIO_C 0x4820
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#define SEG0R_CBW80P80_DC_MAX_RATIO_C_M 0xF00
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#define SEG0R_DC_MAX_RATIO_20_NRX1_C 0x4820
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#define SEG0R_DC_MAX_RATIO_20_NRX1_C_M 0xF000
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#define SEG0R_DC_MAX_RATIO_20_NRX2_C 0x4820
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#define SEG0R_DC_MAX_RATIO_20_NRX2_C_M 0xF0000
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#define SEG0R_DC_MAX_RATIO_40_NRX1_C 0x4820
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#define SEG0R_DC_MAX_RATIO_40_NRX1_C_M 0xF00000
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#define SEG0R_DC_MAX_RATIO_40_NRX2_C 0x4820
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#define SEG0R_DC_MAX_RATIO_40_NRX2_C_M 0xF000000
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#define SEG0R_DC_MAX_RATIO_80_NRX1_C 0x4820
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#define SEG0R_DC_MAX_RATIO_80_NRX1_C_M 0xF0000000
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#define SEG0R_DC_MAX_RATIO_80_NRX2_C 0x4824
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#define SEG0R_DC_MAX_RATIO_80_NRX2_C_M 0xF
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#define SEG0R_DC_MAX_RATIO_80P80_NRX1_C 0x4824
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#define SEG0R_DC_MAX_RATIO_80P80_NRX1_C_M 0xF0
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#define SEG0R_DC_MAX_RATIO_80P80_NRX2_C 0x4824
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#define SEG0R_DC_MAX_RATIO_80P80_NRX2_C_M 0xF00
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#define SEG0R_FINE_TUNE_LMT_C 0x4824
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#define SEG0R_FINE_TUNE_LMT_C_M 0xF000
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#define SEG0R_FINE_TUNE_PROCESS_DELAY_C 0x4824
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#define SEG0R_FINE_TUNE_PROCESS_DELAY_C_M 0xF0000
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#define SEG0R_FINE_TUNE_STEP_BY_CDD_DETECT_C 0x4824
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#define SEG0R_FINE_TUNE_STEP_BY_CDD_DETECT_C_M 0xF00000
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#define SEG0R_FINE_TUNE_TRUNC_HIGH_TH_C 0x4824
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#define SEG0R_FINE_TUNE_TRUNC_HIGH_TH_C_M 0xF000000
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#define SEG0R_FINE_TUNE_TRUNC_LOW_TH_C 0x4824
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#define SEG0R_FINE_TUNE_TRUNC_LOW_TH_C_M 0xF0000000
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#define SEG0R_FINE_TUNE_OPT_C 0x4828
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#define SEG0R_FINE_TUNE_OPT_C_M 0x3
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#define SEG0R_FINE_TUNE_TRUNC_EN_C 0x4828
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#define SEG0R_FINE_TUNE_TRUNC_EN_C_M 0x4
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#define SEG0R_FORCE_CDD_REFINE_OFF_C 0x4828
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#define SEG0R_FORCE_CDD_REFINE_OFF_C_M 0x8
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#define P20_SEG0R_L1_L2_AVG_START_TIME_C 0x482C
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#define P20_SEG0R_L1_L2_AVG_START_TIME_C_M 0x3
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#define P20_SEG0R_L1_L2_ALLOW_AVG_EN_C 0x482C
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#define P20_SEG0R_L1_L2_ALLOW_AVG_EN_C_M 0x4
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#define P20_SEG0R_L1_L2_AVG_OPT_C 0x482C
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#define P20_SEG0R_L1_L2_AVG_OPT_C_M 0x8
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#define S20_SEG0R_L1_L2_AVG_START_TIME_C 0x4830
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#define S20_SEG0R_L1_L2_AVG_START_TIME_C_M 0x3
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#define S20_SEG0R_L1_L2_ALLOW_AVG_EN_C 0x4830
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#define S20_SEG0R_L1_L2_ALLOW_AVG_EN_C_M 0x4
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#define S20_SEG0R_L1_L2_AVG_OPT_C 0x4830
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#define S20_SEG0R_L1_L2_AVG_OPT_C_M 0x8
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#define PROCSEG0R_ADV_SINR_WGT_20_NRX1_C 0x4834
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#define PROCSEG0R_ADV_SINR_WGT_20_NRX1_C_M 0x7FF
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#define PROCSEG0R_ADV_SINR_WGT_20_NRX2_C 0x4834
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#define PROCSEG0R_ADV_SINR_WGT_20_NRX2_C_M 0x3FF800
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#define PROCSEG0R_ADV_SINR_TH_C 0x4834
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#define PROCSEG0R_ADV_SINR_TH_C_M 0x3FC00000
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#define PROCSEG0R_CH_AVG_SIZE_C 0x4834
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#define PROCSEG0R_CH_AVG_SIZE_C_M 0xC0000000
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#define PROCSEG0R_ADV_SINR_WGT_40_NRX1_C 0x4838
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#define PROCSEG0R_ADV_SINR_WGT_40_NRX1_C_M 0x7FF
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#define PROCSEG0R_ADV_SINR_WGT_40_NRX2_C 0x4838
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#define PROCSEG0R_ADV_SINR_WGT_40_NRX2_C_M 0x3FF800
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#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX1_C 0x4838
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#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX1_C_M 0x7C00000
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#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX2_C 0x4838
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#define PROCSEG0R_FS_SQUARE_PK_WGT_20_NRX2_C_M 0xF8000000
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#define PROCSEG0R_ADV_SINR_WGT_80_NRX1_C 0x483C
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#define PROCSEG0R_ADV_SINR_WGT_80_NRX1_C_M 0x7FF
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#define PROCSEG0R_ADV_SINR_WGT_80_NRX2_C 0x483C
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#define PROCSEG0R_ADV_SINR_WGT_80_NRX2_C_M 0x3FF800
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#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX1_C 0x483C
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#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX1_C_M 0x7C00000
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#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX2_C 0x483C
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#define PROCSEG0R_FS_SQUARE_PK_WGT_40_NRX2_C_M 0xF8000000
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#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX1_C 0x4840
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#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX1_C_M 0x7FF
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#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX2_C 0x4840
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#define PROCSEG0R_ADV_SINR_WGT_80P80_NRX2_C_M 0x3FF800
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#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX1_C 0x4840
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#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX1_C_M 0x7C00000
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#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX2_C 0x4840
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#define PROCSEG0R_FS_SQUARE_PK_WGT_80_NRX2_C_M 0xF8000000
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#define PROCSEG0R_INT_SINR_WGT_20_NRX1_C 0x4844
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#define PROCSEG0R_INT_SINR_WGT_20_NRX1_C_M 0x7FF
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#define PROCSEG0R_INT_SINR_WGT_20_NRX2_C 0x4844
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#define PROCSEG0R_INT_SINR_WGT_20_NRX2_C_M 0x3FF800
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#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX1_C 0x4844
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#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX1_C_M 0x7C00000
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#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX2_C 0x4844
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#define PROCSEG0R_FS_SQUARE_PK_WGT_80P80_NRX2_C_M 0xF8000000
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#define PROCSEG0R_INT_SINR_WGT_40_NRX1_C 0x4848
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#define PROCSEG0R_INT_SINR_WGT_40_NRX1_C_M 0x7FF
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#define PROCSEG0R_INT_SINR_WGT_40_NRX2_C 0x4848
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#define PROCSEG0R_INT_SINR_WGT_40_NRX2_C_M 0x3FF800
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#define PROCSEG0R_SBD_FAIL_HALF_SYM_COUNT_C 0x4848
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#define PROCSEG0R_SBD_FAIL_HALF_SYM_COUNT_C_M 0x7C00000
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#define PROCSEG0R_CBW20_HIGH_PIN_TH_MAX_SINR_C 0x4848
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#define PROCSEG0R_CBW20_HIGH_PIN_TH_MAX_SINR_C_M 0xF8000000
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#define PROCSEG0R_INT_SINR_WGT_80_NRX1_C 0x484C
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#define PROCSEG0R_INT_SINR_WGT_80_NRX1_C_M 0x7FF
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#define PROCSEG0R_INT_SINR_WGT_80_NRX2_C 0x484C
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#define PROCSEG0R_INT_SINR_WGT_80_NRX2_C_M 0x3FF800
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#define PROCSEG0R_CBW40_HIGH_PIN_TH_MAX_SINR_C 0x484C
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#define PROCSEG0R_CBW40_HIGH_PIN_TH_MAX_SINR_C_M 0x7C00000
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#define PROCSEG0R_CBW80_HIGH_PIN_TH_MAX_SINR_C 0x484C
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#define PROCSEG0R_CBW80_HIGH_PIN_TH_MAX_SINR_C_M 0xF8000000
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#define PROCSEG0R_INT_SINR_WGT_80P80_NRX1_C 0x4850
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#define PROCSEG0R_INT_SINR_WGT_80P80_NRX1_C_M 0x7FF
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#define PROCSEG0R_INT_SINR_WGT_80P80_NRX2_C 0x4850
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#define PROCSEG0R_INT_SINR_WGT_80P80_NRX2_C_M 0x3FF800
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX1_C 0x4850
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX1_C_M 0x7C00000
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX2_C 0x4850
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_20_NRX2_C_M 0xF8000000
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX1_C 0x4854
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX1_C_M 0x1F
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX2_C 0x4854
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_40_NRX2_C_M 0x3E0
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX1_C 0x4854
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX1_C_M 0x7C00
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX2_C 0x4854
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80_NRX2_C_M 0xF8000
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX1_C 0x4854
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX1_C_M 0x1F00000
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX2_C 0x4854
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#define PROCSEG0R_CDD0_SQUARE_PK_WGT_80P80_NRX2_C_M 0x3E000000
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#define PROCSEG0R_CDD0_SUB_TUNE_OPT_C 0x4854
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#define PROCSEG0R_CDD0_SUB_TUNE_OPT_C_M 0x40000000
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#define PROCSEG0R_CR_SWITCH_BY_ACI_EN_C 0x4854
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#define PROCSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x80000000
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#define PROCSEG0R_FS_WGT_OFST_0_C 0x4858
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#define PROCSEG0R_FS_WGT_OFST_0_C_M 0xF
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#define PROCSEG0R_FS_WGT_OFST_1_C 0x4858
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#define PROCSEG0R_FS_WGT_OFST_1_C_M 0xF0
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#define PROCSEG0R_L1_L2_PROCESS_DELAY_C 0x4858
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#define PROCSEG0R_L1_L2_PROCESS_DELAY_C_M 0xF00
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#define PROCSEG0R_SBD_START_HALF_SYM_COUNT_C 0x4858
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#define PROCSEG0R_SBD_START_HALF_SYM_COUNT_C_M 0xF000
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#define PROCSEG0R_CDD0_JUMP_SUB_TUNE_C 0x4858
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#define PROCSEG0R_CDD0_JUMP_SUB_TUNE_C_M 0xF0000
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#define PROCSEG0R_CDD0_WGT_OFST_0_C 0x4858
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#define PROCSEG0R_CDD0_WGT_OFST_0_C_M 0xF00000
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#define PROCSEG0R_CDD0_WGT_OFST_1_C 0x4858
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#define PROCSEG0R_CDD0_WGT_OFST_1_C_M 0xF000000
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#define PROCSEG0R_CH_BEGIN_COUNT_MAX_C 0x4858
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#define PROCSEG0R_CH_BEGIN_COUNT_MAX_C_M 0xF0000000
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#define PROCSEG0R_CH_FALLING_COUNT_MAX_C 0x485C
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#define PROCSEG0R_CH_FALLING_COUNT_MAX_C_M 0xF
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#define PROCSEG0R_INTF_TH_0_C 0x485C
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#define PROCSEG0R_INTF_TH_0_C_M 0xF0
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#define PROCSEG0R_INTF_TH_1_C 0x485C
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#define PROCSEG0R_INTF_TH_1_C_M 0xF00
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#define PROCSEG0R_TARGET_COUNT_MAX_C 0x485C
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#define PROCSEG0R_TARGET_COUNT_MAX_C_M 0xF000
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#define PROCSEG0R_FS_PEAK_WGT_C 0x485C
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#define PROCSEG0R_FS_PEAK_WGT_C_M 0x70000
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#define PROCSEG0R_CDD0_COUNT_LMT_C 0x485C
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#define PROCSEG0R_CDD0_COUNT_LMT_C_M 0x380000
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#define PROCSEG0R_CDD0_DELAY_SPREAD_SIZE_C 0x485C
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#define PROCSEG0R_CDD0_DELAY_SPREAD_SIZE_C_M 0x1C00000
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#define PROCSEG0R_CH_BEGIN_TH_C 0x485C
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#define PROCSEG0R_CH_BEGIN_TH_C_M 0xE000000
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#define PROCSEG0R_CR_SWITCH_BY_PIN_C 0x485C
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#define PROCSEG0R_CR_SWITCH_BY_PIN_C_M 0x70000000
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#define SEG0R_PW_TH_C 0x4860
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#define SEG0R_PW_TH_C_M 0x3F
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#define SEG0R_PD_LOWER_BOUND_C 0x4860
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#define SEG0R_PD_LOWER_BOUND_C_M 0x7C0
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#define SEG0R_PD_UPPER_BOUND_C 0x4860
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#define SEG0R_PD_UPPER_BOUND_C_M 0xF800
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#define SEG0R_HIGH_PIN_TH_DCFI_C 0x4860
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#define SEG0R_HIGH_PIN_TH_DCFI_C_M 0x1F0000
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#define SEG0R_VERY_HIGH_PIN_TH_C 0x4860
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#define SEG0R_VERY_HIGH_PIN_TH_C_M 0x3E00000
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#define SEG0R_DCFI_FALLING_TH_20_C 0x4860
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#define SEG0R_DCFI_FALLING_TH_20_C_M 0x3C000000
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#define SEG0R_PD_SPATIAL_REUSE_EN_C 0x4860
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#define SEG0R_PD_SPATIAL_REUSE_EN_C_M 0x40000000
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#define SEG0R_DCFI_EN_C 0x4860
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#define SEG0R_DCFI_EN_C_M 0x80000000
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#define SEG0R_DCFI_FALLING_TH_40_C 0x4864
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#define SEG0R_DCFI_FALLING_TH_40_C_M 0xF
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#define SEG0R_DCFI_FALLING_TH_80_C 0x4864
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#define SEG0R_DCFI_FALLING_TH_80_C_M 0xF0
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#define SEG0R_DCFI_FALLING_TH_80P80_C 0x4864
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#define SEG0R_DCFI_FALLING_TH_80P80_C_M 0xF00
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#define SEG0R_DCFI_RISING_TH_20_C 0x4864
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#define SEG0R_DCFI_RISING_TH_20_C_M 0xF000
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#define SEG0R_DCFI_RISING_TH_40_C 0x4864
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#define SEG0R_DCFI_RISING_TH_40_C_M 0xF0000
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#define SEG0R_DCFI_RISING_TH_80_C 0x4864
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#define SEG0R_DCFI_RISING_TH_80_C_M 0xF00000
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#define SEG0R_DCFI_RISING_TH_80P80_C 0x4864
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#define SEG0R_DCFI_RISING_TH_80P80_C_M 0xF000000
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#define SEG0R_FALLING_COUNT_MAX_C 0x4864
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#define SEG0R_FALLING_COUNT_MAX_C_M 0xF0000000
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#define SEG0R_FALLING_TH_C 0x4868
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#define SEG0R_FALLING_TH_C_M 0xF
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#define SEG0R_RISING_COUNT_MAX_C 0x4868
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#define SEG0R_RISING_COUNT_MAX_C_M 0xF0
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#define SEG0R_WAIT_SETTLE_PERIOD_C 0x4868
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#define SEG0R_WAIT_SETTLE_PERIOD_C_M 0xF00
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#define SEG0R_DCPR_EN_C 0x4868
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#define SEG0R_DCPR_EN_C_M 0x1000
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#define SEG0R_DYN_PW_EN_C 0x4868
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#define SEG0R_DYN_PW_EN_C_M 0x2000
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#define SEG0R_FALLING_EDGE_OPT_C 0x4868
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#define SEG0R_FALLING_EDGE_OPT_C_M 0x4000
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#define SEG0R_FORCE_DCFI_EN_C 0x4868
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#define SEG0R_FORCE_DCFI_EN_C_M 0x8000
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#define SEG0R_SB5M_BLK_EN_C 0x4868
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#define SEG0R_SB5M_BLK_EN_C_M 0x10000
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#define P20_SEG0R_PW_DBM_TH_C 0x486C
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#define P20_SEG0R_PW_DBM_TH_C_M 0x7F
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#define P20_SEG0R_PW_TH_C 0x486C
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#define P20_SEG0R_PW_TH_C_M 0x1F80
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#define P20_SEG0R_DYN_FALLING_TH_C 0x486C
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#define P20_SEG0R_DYN_FALLING_TH_C_M 0x7E000
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#define P20_SEG0R_DYN_RISING_TH_C 0x486C
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#define P20_SEG0R_DYN_RISING_TH_C_M 0x1F80000
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#define P20_SEG0R_DYN_TH_MAX_C 0x486C
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#define P20_SEG0R_DYN_TH_MAX_C_M 0x7E000000
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#define P20_SEG0R_DYN_TH_EN_C 0x486C
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#define P20_SEG0R_DYN_TH_EN_C_M 0x80000000
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#define P20_SEG0R_DYN_TH_MIN_C 0x4870
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#define P20_SEG0R_DYN_TH_MIN_C_M 0x3F
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#define P20_SEG0R_DYN_COVER_FCTR_C 0x4870
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#define P20_SEG0R_DYN_COVER_FCTR_C_M 0x3C0
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#define P20_SEG0R_DYN_LAMBDA_C 0x4870
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#define P20_SEG0R_DYN_LAMBDA_C_M 0x1C00
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#define P20_SEG0R_DYN_WAIT_PERIOD_C 0x4870
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#define P20_SEG0R_DYN_WAIT_PERIOD_C_M 0xE000
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#define P20_SEG0R_VLD_CHK_COUNT_MAX_C 0x4870
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#define P20_SEG0R_VLD_CHK_COUNT_MAX_C_M 0x70000
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#define P20_SEG0R_DYN_OBSER_SIZE_C 0x4870
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#define P20_SEG0R_DYN_OBSER_SIZE_C_M 0x180000
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#define P20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C 0x4870
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#define P20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C_M 0x600000
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#define P20_SEG0R_PATH_SEL_C 0x4870
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#define P20_SEG0R_PATH_SEL_C_M 0x1800000
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#define P20_SEG0R_PATH_SEL_EN_C 0x4870
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#define P20_SEG0R_PATH_SEL_EN_C_M 0x2000000
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#define S20_SEG0R_PW_DBM_TH_C 0x4874
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#define S20_SEG0R_PW_DBM_TH_C_M 0x7F
|
#define S20_SEG0R_PW_TH_C 0x4874
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#define S20_SEG0R_PW_TH_C_M 0x1F80
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#define S20_SEG0R_DYN_FALLING_TH_C 0x4874
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#define S20_SEG0R_DYN_FALLING_TH_C_M 0x7E000
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#define S20_SEG0R_DYN_RISING_TH_C 0x4874
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#define S20_SEG0R_DYN_RISING_TH_C_M 0x1F80000
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#define S20_SEG0R_DYN_TH_MAX_C 0x4874
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#define S20_SEG0R_DYN_TH_MAX_C_M 0x7E000000
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#define S20_SEG0R_DYN_TH_EN_C 0x4874
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#define S20_SEG0R_DYN_TH_EN_C_M 0x80000000
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#define S20_SEG0R_DYN_TH_MIN_C 0x4878
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#define S20_SEG0R_DYN_TH_MIN_C_M 0x3F
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#define S20_SEG0R_DYN_COVER_FCTR_C 0x4878
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#define S20_SEG0R_DYN_COVER_FCTR_C_M 0x3C0
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#define S20_SEG0R_DYN_LAMBDA_C 0x4878
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#define S20_SEG0R_DYN_LAMBDA_C_M 0x1C00
|
#define S20_SEG0R_DYN_WAIT_PERIOD_C 0x4878
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#define S20_SEG0R_DYN_WAIT_PERIOD_C_M 0xE000
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#define S20_SEG0R_VLD_CHK_COUNT_MAX_C 0x4878
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#define S20_SEG0R_VLD_CHK_COUNT_MAX_C_M 0x70000
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#define S20_SEG0R_DYN_OBSER_SIZE_C 0x4878
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#define S20_SEG0R_DYN_OBSER_SIZE_C_M 0x180000
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#define S20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C 0x4878
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#define S20_SEG0R_DYN_UPD_TO_ZERO_RATIO_C_M 0x600000
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#define S20_SEG0R_PATH_SEL_C 0x4878
|
#define S20_SEG0R_PATH_SEL_C_M 0x1800000
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#define S20_SEG0R_PATH_SEL_EN_C 0x4878
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#define S20_SEG0R_PATH_SEL_EN_C_M 0x2000000
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#define SMFSEG0R_MF_TH_OFST_0_C 0x487C
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#define SMFSEG0R_MF_TH_OFST_0_C_M 0xF
|
#define SMFSEG0R_MF_TH_OFST_1_C 0x487C
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#define SMFSEG0R_MF_TH_OFST_1_C_M 0xF0
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#define SMFSEG0R_MF_TH_20_NRX1_C 0x487C
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#define SMFSEG0R_MF_TH_20_NRX1_C_M 0xF00
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#define SMFSEG0R_MF_TH_20_NRX2_C 0x487C
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#define SMFSEG0R_MF_TH_20_NRX2_C_M 0xF000
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#define SMFSEG0R_MF_TH_40_NRX1_C 0x487C
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#define SMFSEG0R_MF_TH_40_NRX1_C_M 0xF0000
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#define SMFSEG0R_MF_TH_40_NRX2_C 0x487C
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#define SMFSEG0R_MF_TH_40_NRX2_C_M 0xF00000
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#define SMFSEG0R_MF_TH_80_NRX1_C 0x487C
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#define SMFSEG0R_MF_TH_80_NRX1_C_M 0xF000000
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#define SMFSEG0R_MF_TH_80_NRX2_C 0x487C
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#define SMFSEG0R_MF_TH_80_NRX2_C_M 0xF0000000
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#define SMFSEG0R_MF_TH_80P80_NRX1_C 0x4880
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#define SMFSEG0R_MF_TH_80P80_NRX1_C_M 0xF
|
#define SMFSEG0R_MF_TH_80P80_NRX2_C 0x4880
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#define SMFSEG0R_MF_TH_80P80_NRX2_C_M 0xF0
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#define SMFSEG0R_INTF_TH_0_C 0x4880
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#define SMFSEG0R_INTF_TH_0_C_M 0xF00
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#define SMFSEG0R_INTF_TH_1_C 0x4880
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#define SMFSEG0R_INTF_TH_1_C_M 0xF000
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#define SMFSEG0R_MF_HOLD_C 0x4880
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#define SMFSEG0R_MF_HOLD_C_M 0x70000
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#define SMFSEG0R_MF_WIN_L_C 0x4880
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#define SMFSEG0R_MF_WIN_L_C_M 0x380000
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#define SMFSEG0R_CR_SWITCH_BY_PIN_C 0x4880
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#define SMFSEG0R_CR_SWITCH_BY_PIN_C_M 0x1C00000
|
#define SMFSEG0R_MF_PEAK_OPT_C 0x4880
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#define SMFSEG0R_MF_PEAK_OPT_C_M 0x6000000
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#define SMFSEG0R_NULL_POINT_IDX_C 0x4880
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#define SMFSEG0R_NULL_POINT_IDX_C_M 0x18000000
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#define SMFSEG0R_CR_SWITCH_BY_ACI_EN_C 0x4880
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#define SMFSEG0R_CR_SWITCH_BY_ACI_EN_C_M 0x20000000
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#define SEG0R_EDCCA_LVL_C 0x4884
|
#define SEG0R_EDCCA_LVL_C_M 0xFF
|
#define SEG0R_EDCCA_LVL_P_C 0x4884
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#define SEG0R_EDCCA_LVL_P_C_M 0xFF00
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#define SEG0R_OBSS_LVL_C 0x4884
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#define SEG0R_OBSS_LVL_C_M 0xFF0000
|
#define SEG0R_PPDU_LVL_C 0x4884
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#define SEG0R_PPDU_LVL_C_M 0xFF000000
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#define SEG0R_PPDU_LVL_P_C 0x4888
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#define SEG0R_PPDU_LVL_P_C_M 0xFF
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#define SEG0R_DCV_C 0x4888
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#define SEG0R_DCV_C_M 0x7F00
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#define SEG0R_PWLMT_C 0x4888
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#define SEG0R_PWLMT_C_M 0x3F8000
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#define SEG0R_WGTHD_C 0x4888
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#define SEG0R_WGTHD_C_M 0x1FC00000
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#define SEG0R_PATHSEL_C 0x4888
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#define SEG0R_PATHSEL_C_M 0x60000000
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#define SEG0R_DROP_EN_C 0x4888
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#define SEG0R_DROP_EN_C_M 0x80000000
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#define SEG0R_ADCPKPW_C 0x488C
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#define SEG0R_ADCPKPW_C_M 0x3F
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#define SEG0R_LTFTHD_C 0x488C
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#define SEG0R_LTFTHD_C_M 0xFC0
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#define SEG0R_DWN_LVL_C 0x488C
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#define SEG0R_DWN_LVL_C_M 0x1F000
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#define SEG0R_PWOFST_C 0x488C
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#define SEG0R_PWOFST_C_M 0x3E0000
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#define SEG0R_DROP_NC_C 0x488C
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#define SEG0R_DROP_NC_C_M 0x3C00000
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#define SEG0R_FORCE_EN_C 0x488C
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#define SEG0R_FORCE_EN_C_M 0x4000000
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#define SEG0R_FORGETTING_C 0x488C
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#define SEG0R_FORGETTING_C_M 0x8000000
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#define SEG0R_GCRST_C 0x488C
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#define SEG0R_GCRST_C_M 0x10000000
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#define SEG0R_PWSLOT_C 0x488C
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#define SEG0R_PWSLOT_C_M 0x20000000
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#define SEG0R_SND_EN_C 0x488C
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#define SEG0R_SND_EN_C_M 0x40000000
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#define SEG0R_WGTSEL_EN_C 0x488C
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#define SEG0R_WGTSEL_EN_C_M 0x80000000
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#define SEG0R_SDAGC_CHK_PIN_THD_C 0x4890
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#define SEG0R_SDAGC_CHK_PIN_THD_C_M 0x3F
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#define SEG0R_ALPHA_STEP_C 0x4890
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#define SEG0R_ALPHA_STEP_C_M 0xC0
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#define SEG0R_CBW40_RSSI_SHIFT_C 0x4890
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#define SEG0R_CBW40_RSSI_SHIFT_C_M 0x300
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#define SEG0R_CBW80_RSSI_SHIFT_C 0x4890
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#define SEG0R_CBW80_RSSI_SHIFT_C_M 0xC00
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#define SEG0R_ALPHA_FILTER_EN_C 0x4890
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#define SEG0R_ALPHA_FILTER_EN_C_M 0x1000
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#define SEG0R_LTF_RSSI_CMP_EN_C 0x4890
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#define SEG0R_LTF_RSSI_CMP_EN_C_M 0x2000
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#define SEG0R_PD_RSSI_CMP_EN_C 0x4890
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#define SEG0R_PD_RSSI_CMP_EN_C_M 0x4000
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#define SEG0R_SDAGC_CHK_PIN_EN_C 0x4890
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#define SEG0R_SDAGC_CHK_PIN_EN_C_M 0x8000
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#define SEG0R_COMB_WGT_C 0x4894
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#define SEG0R_COMB_WGT_C_M 0xF
|
#define L_NOISE_VAR_PER_RX_R0_C 0x4958
|
#define L_NOISE_VAR_PER_RX_R0_C_M 0x3FFFF
|
#define MANUAL_NOISE_RESCAL_FCTR_R0_C 0x4958
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#define MANUAL_NOISE_RESCAL_FCTR_R0_C_M 0x7FFC0000
|
#define FD_ANT_WGT_EN_C 0x4958
|
#define FD_ANT_WGT_EN_C_M 0x80000000
|
#define L_NOISE_VAR_PER_RX_R1_C 0x495C
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#define L_NOISE_VAR_PER_RX_R1_C_M 0x3FFFF
|
#define MANUAL_NOISE_RESCAL_FCTR_R1_C 0x495C
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#define MANUAL_NOISE_RESCAL_FCTR_R1_C_M 0x7FFC0000
|
#define FD_PW_NORM_EN_C 0x495C
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#define FD_PW_NORM_EN_C_M 0x80000000
|
#define NOISE_VAR_PER_RX_R0_C 0x4960
|
#define NOISE_VAR_PER_RX_R0_C_M 0x3FFFF
|
#define NOISE_VAR_PER_RX_DB_THD_C 0x4960
|
#define NOISE_VAR_PER_RX_DB_THD_C_M 0x3FFC0000
|
#define RPL_CAL_EN_C 0x4960
|
#define RPL_CAL_EN_C_M 0x40000000
|
#define TB_RSSI_M_CAL_EN_C 0x4960
|
#define TB_RSSI_M_CAL_EN_C_M 0x80000000
|
#define NOISE_VAR_PER_RX_R1_C 0x4964
|
#define NOISE_VAR_PER_RX_R1_C_M 0x3FFFF
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#define PER_RX_DIFF_MAX_NOISE_PW_THD_C 0x4964
|
#define PER_RX_DIFF_MAX_NOISE_PW_THD_C_M 0x3FFC0000
|
#define ANT_WGT_MANUAL_EN_C 0x4964
|
#define ANT_WGT_MANUAL_EN_C_M 0x40000000
|
#define ANT_WGT_NORMALIZE_MODE_EN_C 0x4964
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#define ANT_WGT_NORMALIZE_MODE_EN_C_M 0x80000000
|
#define FD_AMP_WGT_LEG_R0_C 0x4968
|
#define FD_AMP_WGT_LEG_R0_C_M 0xFFFF
|
#define FD_AMP_WGT_LEG_R1_C 0x4968
|
#define FD_AMP_WGT_LEG_R1_C_M 0xFFFF0000
|
#define FD_AMP_WGT_NON_LEG_R0_C 0x496C
|
#define FD_AMP_WGT_NON_LEG_R0_C_M 0xFFFF
|
#define FD_AMP_WGT_NON_LEG_R1_C 0x496C
|
#define FD_AMP_WGT_NON_LEG_R1_C_M 0xFFFF0000
|
#define L_SNR_ALL_COMB_C 0x4978
|
#define L_SNR_ALL_COMB_C_M 0x3FF
|
#define L_SNR_PER_RX_R0_C 0x4978
|
#define L_SNR_PER_RX_R0_C_M 0xFFC00
|
#define L_SNR_PER_RX_R1_C 0x4978
|
#define L_SNR_PER_RX_R1_C_M 0x3FF00000
|
#define MANUAL_FD_AMP_WGT_EN_C 0x4978
|
#define MANUAL_FD_AMP_WGT_EN_C_M 0x40000000
|
#define MANUAL_SNR_EN_C 0x4978
|
#define MANUAL_SNR_EN_C_M 0x80000000
|
#define SNR_ALL_COMB_C 0x497C
|
#define SNR_ALL_COMB_C_M 0x3FF
|
#define SNR_PER_RX_STS_R0_S0_C 0x497C
|
#define SNR_PER_RX_STS_R0_S0_C_M 0xFFC00
|
#define SNR_PER_RX_STS_R0_S1_C 0x497C
|
#define SNR_PER_RX_STS_R0_S1_C_M 0x3FF00000
|
#define MANUAL_NOISE_RESCAL_EN_C 0x497C
|
#define MANUAL_NOISE_RESCAL_EN_C_M 0x40000000
|
#define MANUAL_NOISE_VAR_EN_C 0x497C
|
#define MANUAL_NOISE_VAR_EN_C_M 0x80000000
|
#define SNR_PER_RX_STS_R1_S0_C 0x4980
|
#define SNR_PER_RX_STS_R1_S0_C_M 0x3FF
|
#define SNR_PER_RX_STS_R1_S1_C 0x4980
|
#define SNR_PER_RX_STS_R1_S1_C_M 0xFFC00
|
#define SNR_PER_RX_SUB_R0_S0_C 0x4980
|
#define SNR_PER_RX_SUB_R0_S0_C_M 0x3FF00000
|
#define NOISE_RESCAL_EN_C 0x4980
|
#define NOISE_RESCAL_EN_C_M 0x40000000
|
#define SNR_PER_RX_SUB_R0_S1_C 0x4984
|
#define SNR_PER_RX_SUB_R0_S1_C_M 0x3FF
|
#define SNR_PER_RX_SUB_R0_S2_C 0x4984
|
#define SNR_PER_RX_SUB_R0_S2_C_M 0xFFC00
|
#define SNR_PER_RX_SUB_R0_S3_C 0x4984
|
#define SNR_PER_RX_SUB_R0_S3_C_M 0x3FF00000
|
#define SNR_PER_RX_SUB_R1_S0_C 0x4988
|
#define SNR_PER_RX_SUB_R1_S0_C_M 0x3FF
|
#define SNR_PER_RX_SUB_R1_S1_C 0x4988
|
#define SNR_PER_RX_SUB_R1_S1_C_M 0xFFC00
|
#define SNR_PER_RX_SUB_R1_S2_C 0x4988
|
#define SNR_PER_RX_SUB_R1_S2_C_M 0x3FF00000
|
#define SNR_PER_RX_SUB_R1_S3_C 0x498C
|
#define SNR_PER_RX_SUB_R1_S3_C_M 0x3FF
|
#define SNR_PER_STS_S0_C 0x498C
|
#define SNR_PER_STS_S0_C_M 0xFFC00
|
#define SNR_PER_STS_S1_C 0x498C
|
#define SNR_PER_STS_S1_C_M 0x3FF00000
|
#define SNR_PER_SUB_S0_C 0x4990
|
#define SNR_PER_SUB_S0_C_M 0x3FF
|
#define SNR_PER_SUB_S1_C 0x4990
|
#define SNR_PER_SUB_S1_C_M 0xFFC00
|
#define SNR_PER_SUB_S2_C 0x4990
|
#define SNR_PER_SUB_S2_C_M 0x3FF00000
|
#define SNR_PER_SUB_S3_C 0x4994
|
#define SNR_PER_SUB_S3_C_M 0x3FF
|
#define RX_DB_SAME_THD_C 0x4994
|
#define RX_DB_SAME_THD_C_M 0x7FC00
|
#define ANT_WGT_MANUAL_RX0_C 0x4994
|
#define ANT_WGT_MANUAL_RX0_C_M 0xFF80000
|
#define ANT_WGT_MANUAL_RX1_C 0x4998
|
#define ANT_WGT_MANUAL_RX1_C_M 0x1FF
|
#define FORBT_FD_ANT_WGT_OFF_C 0x4998
|
#define FORBT_FD_ANT_WGT_OFF_C_M 0x3FE00
|
#define FORBT_FD_ANT_WGT_ON_C 0x4998
|
#define FORBT_FD_ANT_WGT_ON_C_M 0x7FC0000
|
#define DIFF_SAME_THD_C 0x499C
|
#define DIFF_SAME_THD_C_M 0x7F
|
#define RX_DB_DISCONNECT_THD_0_C 0x499C
|
#define RX_DB_DISCONNECT_THD_0_C_M 0x3F80
|
#define RX_DB_DISCONNECT_THD_1_C 0x499C
|
#define RX_DB_DISCONNECT_THD_1_C_M 0x1FC000
|
#define RX_DB_DISCONNECT_THD_2_C 0x499C
|
#define RX_DB_DISCONNECT_THD_2_C_M 0xFE00000
|
#define RX_DB_DISCONNECT_THD_3_C 0x49A0
|
#define RX_DB_DISCONNECT_THD_3_C_M 0x7F
|
#define RX_DB_DISCONNECT_THD_4_C 0x49A0
|
#define RX_DB_DISCONNECT_THD_4_C_M 0x3F80
|
#define RX_DB_DISCONNECT_THD_5_C 0x49A0
|
#define RX_DB_DISCONNECT_THD_5_C_M 0x1FC000
|
#define RX_DB_DISCONNECT_THD_6_C 0x49A0
|
#define RX_DB_DISCONNECT_THD_6_C_M 0xFE00000
|
#define ANT_WGT_NSS2_LOW_BOUND_C 0x49A4
|
#define ANT_WGT_NSS2_LOW_BOUND_C_M 0x7F
|
#define ANT_WGT_NSS2_LOW_BOUND_THD_C 0x49A4
|
#define ANT_WGT_NSS2_LOW_BOUND_THD_C_M 0x3F80
|
#define DISCONNECT_ANT_WGT_0_C 0x49A4
|
#define DISCONNECT_ANT_WGT_0_C_M 0x1FC000
|
#define DISCONNECT_ANT_WGT_1_C 0x49A4
|
#define DISCONNECT_ANT_WGT_1_C_M 0xFE00000
|
#define DISCONNECT_ANT_WGT_2_C 0x49A8
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#define DISCONNECT_ANT_WGT_2_C_M 0x7F
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#define DISCONNECT_ANT_WGT_3_C 0x49A8
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#define DISCONNECT_ANT_WGT_3_C_M 0x3F80
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#define DISCONNECT_ANT_WGT_4_C 0x49A8
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#define DISCONNECT_ANT_WGT_4_C_M 0x1FC000
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#define DISCONNECT_ANT_WGT_5_C 0x49A8
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#define DISCONNECT_ANT_WGT_5_C_M 0xFE00000
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#define DISCONNECT_ANT_WGT_6_C 0x49AC
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#define DISCONNECT_ANT_WGT_6_C_M 0x7F
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#define DISCONNECT_ANT_WGT_7_C 0x49AC
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#define DISCONNECT_ANT_WGT_7_C_M 0x3F80
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#define L_RPL_BIAS_COMP_C 0x49B0
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#define L_RPL_BIAS_COMP_C_M 0xFF
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#define L_RPL_BIAS_COMP_BW20_C 0x49B0
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#define L_RPL_BIAS_COMP_BW20_C_M 0xFF00
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#define L_RPL_BIAS_COMP_BW40_C 0x49B0
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#define L_RPL_BIAS_COMP_BW40_C_M 0xFF0000
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#define L_RPL_BIAS_COMP_BW40_1_C 0x49B0
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#define L_RPL_BIAS_COMP_BW40_1_C_M 0xFF000000
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#define L_RPL_BIAS_COMP_BW40_2_C 0x49B4
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#define L_RPL_BIAS_COMP_BW40_2_C_M 0xFF
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#define L_RPL_BIAS_COMP_BW80_C 0x49B4
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#define L_RPL_BIAS_COMP_BW80_C_M 0xFF00
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#define L_RPL_BIAS_COMP_BW80_1_C 0x49B4
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#define L_RPL_BIAS_COMP_BW80_1_C_M 0xFF0000
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#define L_RPL_BIAS_COMP_BW80_10_C 0x49B4
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#define L_RPL_BIAS_COMP_BW80_10_C_M 0xFF000000
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#define L_RPL_BIAS_COMP_BW80_2_C 0x49B8
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#define L_RPL_BIAS_COMP_BW80_2_C_M 0xFF
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#define L_RPL_BIAS_COMP_BW80_3_C 0x49B8
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#define L_RPL_BIAS_COMP_BW80_3_C_M 0xFF00
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#define L_RPL_BIAS_COMP_BW80_4_C 0x49B8
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#define L_RPL_BIAS_COMP_BW80_4_C_M 0xFF0000
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#define L_RPL_BIAS_COMP_BW80_9_C 0x49B8
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#define L_RPL_BIAS_COMP_BW80_9_C_M 0xFF000000
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#define DBCC_C 0x49BC
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#define DBCC_C_M 0x1
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#define DBCC_2P4G_BAND_SEL_C 0x49BC
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#define DBCC_2P4G_BAND_SEL_C_M 0x2
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#define NONCON160_C 0x49BC
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#define NONCON160_C_M 0x4
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#define FC0_INV_C 0x49C0
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#define FC0_INV_C_M 0x7F
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#define FC1_INV_C 0x49C0
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#define FC1_INV_C_M 0x3F80
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#define ANT_RX_1RCCA_SEG0_C 0x49C0
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#define ANT_RX_1RCCA_SEG0_C_M 0x3C000
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#define ANT_RX_1RCCA_SEG1_C 0x49C0
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#define ANT_RX_1RCCA_SEG1_C_M 0x3C0000
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#define ANT_RX_BT_SEG0_C 0x49C0
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#define ANT_RX_BT_SEG0_C_M 0x3C00000
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#define ANT_RX_BT_SEG1_C 0x49C0
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#define ANT_RX_BT_SEG1_C_M 0x3C000000
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#define BW_C 0x49C0
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#define BW_C_M 0xC0000000
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#define ANT_RX_SEG0_C 0x49C4
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#define ANT_RX_SEG0_C_M 0xF
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#define ANT_RX_SEG1_C 0x49C4
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#define ANT_RX_SEG1_C_M 0xF0
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#define PRICH_C 0x49C4
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#define PRICH_C_M 0xF00
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#define SMALL_BW_MODE_C 0x49C4
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#define SMALL_BW_MODE_C_M 0x3000
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#define BT_SHARE_C 0x49C4
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#define BT_SHARE_C_M 0x4000
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#define PROC0_PROCQ_MATRIX_00_IM_C 0x49C8
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#define PROC0_PROCQ_MATRIX_00_IM_C_M 0xFFFF
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#define PROC0_PROCQ_MATRIX_00_RE_C 0x49C8
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#define PROC0_PROCQ_MATRIX_00_RE_C_M 0xFFFF0000
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#define PROC0_PROCQ_MATRIX_01_IM_C 0x49CC
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#define PROC0_PROCQ_MATRIX_01_IM_C_M 0xFFFF
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#define PROC0_PROCQ_MATRIX_01_RE_C 0x49CC
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#define PROC0_PROCQ_MATRIX_01_RE_C_M 0xFFFF0000
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#define PROC0_PROCQ_MATRIX_10_IM_C 0x49D0
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#define PROC0_PROCQ_MATRIX_10_IM_C_M 0xFFFF
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#define PROC0_PROCQ_MATRIX_10_RE_C 0x49D0
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#define PROC0_PROCQ_MATRIX_10_RE_C_M 0xFFFF0000
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#define PROC0_PROCQ_MATRIX_11_IM_C 0x49D4
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#define PROC0_PROCQ_MATRIX_11_IM_C_M 0xFFFF
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#define PROC0_PROCQ_MATRIX_11_RE_C 0x49D4
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#define PROC0_PROCQ_MATRIX_11_RE_C_M 0xFFFF0000
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#define PROC0_PROCCUSTOMIZE_Q_MATRIX_EN_C 0x49D8
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#define PROC0_PROCCUSTOMIZE_Q_MATRIX_EN_C_M 0x1
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#define PRPC1_PROCQ_MATRIX_00_IM_C 0x49DC
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#define PRPC1_PROCQ_MATRIX_00_IM_C_M 0xFFFF
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#define PRPC1_PROCQ_MATRIX_00_RE_C 0x49DC
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#define PRPC1_PROCQ_MATRIX_00_RE_C_M 0xFFFF0000
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#define PRPC1_PROCQ_MATRIX_01_IM_C 0x49E0
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#define PRPC1_PROCQ_MATRIX_01_IM_C_M 0xFFFF
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#define PRPC1_PROCQ_MATRIX_01_RE_C 0x49E0
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#define PRPC1_PROCQ_MATRIX_01_RE_C_M 0xFFFF0000
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#define PRPC1_PROCQ_MATRIX_10_IM_C 0x49E4
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#define PRPC1_PROCQ_MATRIX_10_IM_C_M 0xFFFF
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#define PRPC1_PROCQ_MATRIX_10_RE_C 0x49E4
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#define PRPC1_PROCQ_MATRIX_10_RE_C_M 0xFFFF0000
|
#define PRPC1_PROCQ_MATRIX_11_IM_C 0x49E8
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#define PRPC1_PROCQ_MATRIX_11_IM_C_M 0xFFFF
|
#define PRPC1_PROCQ_MATRIX_11_RE_C 0x49E8
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#define PRPC1_PROCQ_MATRIX_11_RE_C_M 0xFFFF0000
|
#define PRPC1_PROCCUSTOMIZE_Q_MATRIX_EN_C 0x49EC
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#define PRPC1_PROCCUSTOMIZE_Q_MATRIX_EN_C_M 0x1
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#define PATH1_R_P_PEAK_IBADC_DBM_C 0x49F0
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#define PATH1_R_P_PEAK_IBADC_DBM_C_M 0x7F
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#define PATH1_R_P_PEAK_WBADC_DBM_C 0x49F0
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#define PATH1_R_P_PEAK_WBADC_DBM_C_M 0x3F80
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#define PATH1_R_ACI_NRBW_TH_C 0x49F0
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#define PATH1_R_ACI_NRBW_TH_C_M 0xFC000
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#define PATH1_R_BACKOFF_BMODE_C 0x49F0
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#define PATH1_R_BACKOFF_BMODE_C_M 0x3F00000
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#define PATH1_R_BACKOFF_IBADC_C 0x49F0
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#define PATH1_R_BACKOFF_IBADC_C_M 0xFC000000
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#define PATH1_R_BACKOFF_LNA_C 0x49F4
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#define PATH1_R_BACKOFF_LNA_C_M 0x3F
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#define PATH1_R_BACKOFF_TIA_C 0x49F4
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#define PATH1_R_BACKOFF_TIA_C_M 0xFC0
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#define PATH1_R_BACKOFF_WBADC_C 0x49F4
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#define PATH1_R_BACKOFF_WBADC_C_M 0x3F000
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#define PATH1_R_G_IBADC_IN_C 0x49F4
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#define PATH1_R_G_IBADC_IN_C_M 0xFC0000
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#define PATH1_R_A_GS_SAT_IDX_RX_C 0x49F4
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#define PATH1_R_A_GS_SAT_IDX_RX_C_M 0x1F000000
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#define PATH1_R_A_WB_GIDX_00_LNA_TIA_C 0x49F4
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#define PATH1_R_A_WB_GIDX_00_LNA_TIA_C_M 0xE0000000
|
#define FTM_EN_C 0x49F8
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#define FTM_EN_C_M 0x1
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#define PATH1_R_A_GS_UND_IDX_RX_C 0x49FC
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#define PATH1_R_A_GS_UND_IDX_RX_C_M 0x1F
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#define PATH1_R_G_GS_SAT_IDX_RX_C 0x49FC
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#define PATH1_R_G_GS_SAT_IDX_RX_C_M 0x3E0
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#define PATH1_R_G_GS_UND_IDX_RX_C 0x49FC
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#define PATH1_R_G_GS_UND_IDX_RX_C_M 0x7C00
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#define PATH1_R_DLY_DCCL_C 0x49FC
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#define PATH1_R_DLY_DCCL_C_M 0x1F00000
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#define PATH1_R_DLY_DFE_C 0x49FC
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#define PATH1_R_DLY_DFE_C_M 0x3E000000
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#define PATH1_R_G_MIXER_C 0x49FC
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#define PATH1_R_G_MIXER_C_M 0xC0000000
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#define TB_RSSI_M_BIAS_COMP_C 0x4A00
|
#define TB_RSSI_M_BIAS_COMP_C_M 0xFF
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#define TB_RSSI_M_BIAS_COMP_BW20_C 0x4A00
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#define TB_RSSI_M_BIAS_COMP_BW20_C_M 0xFF00
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#define TB_RSSI_M_BIAS_COMP_BW40_C 0x4A00
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#define TB_RSSI_M_BIAS_COMP_BW40_C_M 0xFF0000
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#define TB_RSSI_M_BIAS_COMP_BW40_1_C 0x4A00
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#define TB_RSSI_M_BIAS_COMP_BW40_1_C_M 0xFF000000
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#define TB_RSSI_M_BIAS_COMP_BW40_2_C 0x4A04
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#define TB_RSSI_M_BIAS_COMP_BW40_2_C_M 0xFF
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#define TB_RSSI_M_BIAS_COMP_BW80_C 0x4A04
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#define TB_RSSI_M_BIAS_COMP_BW80_C_M 0xFF00
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#define TB_RSSI_M_BIAS_COMP_BW80_1_C 0x4A04
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#define TB_RSSI_M_BIAS_COMP_BW80_1_C_M 0xFF0000
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#define TB_RSSI_M_BIAS_COMP_BW80_10_C 0x4A04
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#define TB_RSSI_M_BIAS_COMP_BW80_10_C_M 0xFF000000
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#define TB_RSSI_M_BIAS_COMP_BW80_2_C 0x4A08
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#define TB_RSSI_M_BIAS_COMP_BW80_2_C_M 0xFF
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#define TB_RSSI_M_BIAS_COMP_BW80_3_C 0x4A08
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#define TB_RSSI_M_BIAS_COMP_BW80_3_C_M 0xFF00
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#define TB_RSSI_M_BIAS_COMP_BW80_4_C 0x4A08
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#define TB_RSSI_M_BIAS_COMP_BW80_4_C_M 0xFF0000
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#define TB_RSSI_M_BIAS_COMP_BW80_9_C 0x4A08
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#define TB_RSSI_M_BIAS_COMP_BW80_9_C_M 0xFF000000
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#define LSIGMRLSIG_NOISE_EST_DIFF_THR_C 0x4A24
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#define LSIGMRLSIG_NOISE_EST_DIFF_THR_C_M 0x3FF
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#define LSIGMRLSIG_NOISE_EST_ORG_THR_C 0x4A24
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#define LSIGMRLSIG_NOISE_EST_ORG_THR_C_M 0xFFC00
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#define LSIGMRLSIG_NOISE_EST_FOR_PFD_EN_C 0x4A24
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#define LSIGMRLSIG_NOISE_EST_FOR_PFD_EN_C_M 0x100000
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#define LSIGMRLSIG_NOISE_EST_FOR_IN_EN_C 0x4A24
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#define LSIGMRLSIG_NOISE_EST_FOR_IN_EN_C_M 0x200000
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#define PDP_TAU_FIX_FOR_LOWSNR_C 0x4A48
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#define PDP_TAU_FIX_FOR_LOWSNR_C_M 0x7
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#define LPBW_SEL_D1_HEER_C 0x4A4C
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#define LPBW_SEL_D1_HEER_C_M 0x1F
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#define LPBW_SEL_D2_HEER_C 0x4A4C
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#define LPBW_SEL_D2_HEER_C_M 0x3E0
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#define LPBW_SEL_P1_HEER_C 0x4A4C
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#define LPBW_SEL_P1_HEER_C_M 0x7C00
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#define LPBW_SEL_P2_HEER_C 0x4A4C
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#define LPBW_SEL_P2_HEER_C_M 0xF8000
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#define PATH1_R_DLY_PRIM_C 0x4A5C
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#define PATH1_R_DLY_PRIM_C_M 0x1F
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#define PATH1_R_DLY_SYNC_C 0x4A5C
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#define PATH1_R_DLY_SYNC_C_M 0x3E0
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#define PATH1_R_RXIDX_INIT_C 0x4A5C
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#define PATH1_R_RXIDX_INIT_C_M 0x7C00
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#define PATH1_R_A_GS_SAT_IDX_H_C 0x4A5C
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#define PATH1_R_A_GS_SAT_IDX_H_C_M 0x78000
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#define PATH1_R_A_GS_SAT_IDX_L_C 0x4A5C
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#define PATH1_R_A_GS_SAT_IDX_L_C_M 0x780000
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#define PATH1_R_A_GS_SAT_IDX_PP1_C 0x4A5C
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#define PATH1_R_A_GS_SAT_IDX_PP1_C_M 0x7800000
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#define PATH1_R_A_GS_SAT_IDX_PP2_C 0x4A5C
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#define PATH1_R_A_GS_SAT_IDX_PP2_C_M 0x78000000
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#define PATH1_R_1RCCA_PRE_PD_MODE_C 0x4A5C
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#define PATH1_R_1RCCA_PRE_PD_MODE_C_M 0x80000000
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#define PATH1_R_A_GS_SAT_TH_H_C 0x4A60
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#define PATH1_R_A_GS_SAT_TH_H_C_M 0xF
|
#define PATH1_R_A_GS_SAT_TH_L_C 0x4A60
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#define PATH1_R_A_GS_SAT_TH_L_C_M 0xF0
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#define PATH1_R_A_GS_UND_IDX_C 0x4A60
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#define PATH1_R_A_GS_UND_IDX_C_M 0xF00
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#define PATH1_R_A_GS_UND_IDX_PP1_C 0x4A60
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#define PATH1_R_A_GS_UND_IDX_PP1_C_M 0xF000
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#define PATH1_R_A_GS_UND_IDX_PP2_C 0x4A60
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#define PATH1_R_A_GS_UND_IDX_PP2_C_M 0xF0000
|
#define PATH1_R_A_GS_UND_TH_H_C 0x4A60
|
#define PATH1_R_A_GS_UND_TH_H_C_M 0xF00000
|
#define PATH1_R_A_GS_UND_TH_L_C 0x4A60
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#define PATH1_R_A_GS_UND_TH_L_C_M 0xF000000
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#define PATH1_R_GC1_TIME_C 0x4A60
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#define PATH1_R_GC1_TIME_C_M 0xF0000000
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#define PATH1_R_GC1_TIME_NLGC_C 0x4A64
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#define PATH1_R_GC1_TIME_NLGC_C_M 0xF
|
#define PATH1_R_GC2_TIME_C 0x4A64
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#define PATH1_R_GC2_TIME_C_M 0xF0
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#define PATH1_R_GC2_TIME_NLGC_C 0x4A64
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#define PATH1_R_GC2_TIME_NLGC_C_M 0xF00
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#define PATH1_R_GC3_TIME_C 0x4A64
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#define PATH1_R_GC3_TIME_C_M 0xF000
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#define PATH1_R_GC4_TIME_C 0x4A64
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#define PATH1_R_GC4_TIME_C_M 0xF0000
|
#define PATH1_R_GC5_TIME_C 0x4A64
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#define PATH1_R_GC5_TIME_C_M 0xF00000
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#define PATH1_R_GC_TIME_LESS_80M_C 0x4A64
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#define PATH1_R_GC_TIME_LESS_80M_C_M 0xF000000
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#define PATH1_R_GC_TIME_LESS_NLINEAR_C 0x4A64
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#define PATH1_R_GC_TIME_LESS_NLINEAR_C_M 0xF0000000
|
#define PATH1_R_G_GS_SAT_IDX_H_C 0x4A68
|
#define PATH1_R_G_GS_SAT_IDX_H_C_M 0xF
|
#define PATH1_R_G_GS_SAT_IDX_L_C 0x4A68
|
#define PATH1_R_G_GS_SAT_IDX_L_C_M 0xF0
|
#define PATH1_R_G_GS_SAT_IDX_PP1_C 0x4A68
|
#define PATH1_R_G_GS_SAT_IDX_PP1_C_M 0xF00
|
#define PATH1_R_G_GS_SAT_IDX_PP2_C 0x4A68
|
#define PATH1_R_G_GS_SAT_IDX_PP2_C_M 0xF000
|
#define PATH1_R_G_GS_SAT_TH_H_C 0x4A68
|
#define PATH1_R_G_GS_SAT_TH_H_C_M 0xF0000
|
#define PATH1_R_G_GS_SAT_TH_L_C 0x4A68
|
#define PATH1_R_G_GS_SAT_TH_L_C_M 0xF00000
|
#define PATH1_R_G_GS_UND_IDX_C 0x4A68
|
#define PATH1_R_G_GS_UND_IDX_C_M 0xF000000
|
#define PATH1_R_G_GS_UND_IDX_PP1_C 0x4A68
|
#define PATH1_R_G_GS_UND_IDX_PP1_C_M 0xF0000000
|
#define PATH1_R_G_GS_UND_IDX_PP2_C 0x4A6C
|
#define PATH1_R_G_GS_UND_IDX_PP2_C_M 0xF
|
#define PATH1_R_G_GS_UND_TH_H_C 0x4A6C
|
#define PATH1_R_G_GS_UND_TH_H_C_M 0xF0
|
#define PATH1_R_G_GS_UND_TH_L_C 0x4A6C
|
#define PATH1_R_G_GS_UND_TH_L_C_M 0xF00
|
#define PATH1_R_ACI_NRBW_RATIO_C 0x4A6C
|
#define PATH1_R_ACI_NRBW_RATIO_C_M 0xF000
|
#define PATH1_R_AGC_RESTART_TH_IB_C 0x4A6C
|
#define PATH1_R_AGC_RESTART_TH_IB_C_M 0xF0000
|
#define PATH1_R_AGC_RESTART_TH_WB_C 0x4A6C
|
#define PATH1_R_AGC_RESTART_TH_WB_C_M 0xF00000
|
#define PATH1_R_DCCL_ALPHA_80_C 0x4A6C
|
#define PATH1_R_DCCL_ALPHA_80_C_M 0xF000000
|
#define PATH1_R_DCCL_ALPHA_N80_C 0x4A6C
|
#define PATH1_R_DCCL_ALPHA_N80_C_M 0xF0000000
|
#define PATH1_R_LGC_FREEZE_TH_H_C 0x4A70
|
#define PATH1_R_LGC_FREEZE_TH_H_C_M 0xF
|
#define PATH1_R_LGC_FREEZE_TH_L_C 0x4A70
|
#define PATH1_R_LGC_FREEZE_TH_L_C_M 0xF0
|
#define PATH1_R_NLGC_FREEZE_TH_H_C 0x4A70
|
#define PATH1_R_NLGC_FREEZE_TH_H_C_M 0xF00
|
#define PATH1_R_NLGC_FREEZE_TH_L_C 0x4A70
|
#define PATH1_R_NLGC_FREEZE_TH_L_C_M 0xF000
|
#define PATH1_R_WB_GAIN_IDX_INIT_C 0x4A70
|
#define PATH1_R_WB_GAIN_IDX_INIT_C_M 0xF0000
|
#define PATH1_R_A_WB_GIDX_01_LNA_TIA_C 0x4A70
|
#define PATH1_R_A_WB_GIDX_01_LNA_TIA_C_M 0x7000000
|
#define PATH1_R_A_WB_GIDX_02_LNA_TIA_C 0x4A70
|
#define PATH1_R_A_WB_GIDX_02_LNA_TIA_C_M 0x38000000
|
#define PATH1_R_G_WBADC_IN_C 0x4A70
|
#define PATH1_R_G_WBADC_IN_C_M 0xC0000000
|
#define PATH1_R_A_WB_GIDX_03_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_03_LNA_TIA_C_M 0x7
|
#define PATH1_R_A_WB_GIDX_04_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_04_LNA_TIA_C_M 0x38
|
#define PATH1_R_A_WB_GIDX_05_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_05_LNA_TIA_C_M 0x1C0
|
#define PATH1_R_A_WB_GIDX_06_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_06_LNA_TIA_C_M 0xE00
|
#define PATH1_R_A_WB_GIDX_07_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_07_LNA_TIA_C_M 0x7000
|
#define PATH1_R_A_WB_GIDX_08_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_08_LNA_TIA_C_M 0x38000
|
#define PATH1_R_A_WB_GIDX_09_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_09_LNA_TIA_C_M 0x1C0000
|
#define PATH1_R_A_WB_GIDX_10_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_10_LNA_TIA_C_M 0xE00000
|
#define PATH1_R_A_WB_GIDX_11_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_11_LNA_TIA_C_M 0x7000000
|
#define PATH1_R_A_WB_GIDX_12_LNA_TIA_C 0x4A74
|
#define PATH1_R_A_WB_GIDX_12_LNA_TIA_C_M 0x38000000
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#define PATH1_R_IBADC_PW_ALPHA_H_C 0x4A74
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#define PATH1_R_IBADC_PW_ALPHA_H_C_M 0xC0000000
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#define PATH1_R_A_WB_GIDX_13_LNA_TIA_C 0x4A78
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#define PATH1_R_A_WB_GIDX_13_LNA_TIA_C_M 0x7
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#define PATH1_R_A_WB_GIDX_14_LNA_TIA_C 0x4A78
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#define PATH1_R_A_WB_GIDX_14_LNA_TIA_C_M 0x38
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#define PATH1_R_A_WB_GIDX_15_LNA_TIA_C 0x4A78
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#define PATH1_R_A_WB_GIDX_15_LNA_TIA_C_M 0x1C0
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#define PATH1_R_G_WB_GIDX_00_LNA_TIA_C 0x4A78
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#define PATH1_R_G_WB_GIDX_00_LNA_TIA_C_M 0xE00
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#define PATH1_R_G_WB_GIDX_01_LNA_TIA_C 0x4A78
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#define PATH1_R_G_WB_GIDX_01_LNA_TIA_C_M 0x7000
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#define PATH1_R_G_WB_GIDX_02_LNA_TIA_C 0x4A78
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#define PATH1_R_G_WB_GIDX_02_LNA_TIA_C_M 0x38000
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#define PATH1_R_G_WB_GIDX_03_LNA_TIA_C 0x4A78
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#define PATH1_R_G_WB_GIDX_03_LNA_TIA_C_M 0x1C0000
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#define PATH1_R_G_WB_GIDX_04_LNA_TIA_C 0x4A78
|
#define PATH1_R_G_WB_GIDX_04_LNA_TIA_C_M 0xE00000
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#define PATH1_R_G_WB_GIDX_05_LNA_TIA_C 0x4A78
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#define PATH1_R_G_WB_GIDX_05_LNA_TIA_C_M 0x7000000
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#define PATH1_R_G_WB_GIDX_06_LNA_TIA_C 0x4A78
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#define PATH1_R_G_WB_GIDX_06_LNA_TIA_C_M 0x38000000
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#define PATH1_R_IBADC_PW_ALPHA_L_C 0x4A78
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#define PATH1_R_IBADC_PW_ALPHA_L_C_M 0xC0000000
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#define PATH1_R_G_WB_GIDX_07_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_07_LNA_TIA_C_M 0x7
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#define PATH1_R_G_WB_GIDX_08_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_08_LNA_TIA_C_M 0x38
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#define PATH1_R_G_WB_GIDX_09_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_09_LNA_TIA_C_M 0x1C0
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#define PATH1_R_G_WB_GIDX_10_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_10_LNA_TIA_C_M 0xE00
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#define PATH1_R_G_WB_GIDX_11_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_11_LNA_TIA_C_M 0x7000
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#define PATH1_R_G_WB_GIDX_12_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_12_LNA_TIA_C_M 0x38000
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#define PATH1_R_G_WB_GIDX_13_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_13_LNA_TIA_C_M 0x1C0000
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#define PATH1_R_G_WB_GIDX_14_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_14_LNA_TIA_C_M 0xE00000
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#define PATH1_R_G_WB_GIDX_15_LNA_TIA_C 0x4A7C
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#define PATH1_R_G_WB_GIDX_15_LNA_TIA_C_M 0x7000000
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#define PATH1_R_BT_LNA_IDX0_C 0x4A7C
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#define PATH1_R_BT_LNA_IDX0_C_M 0x38000000
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#define PATH1_R_LINEAR_STEP_LIM_C 0x4A7C
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#define PATH1_R_LINEAR_STEP_LIM_C_M 0xC0000000
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#define PATH1_R_BT_LNA_IDX1_C 0x4A80
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#define PATH1_R_BT_LNA_IDX1_C_M 0x7
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#define PATH1_R_BT_LNA_IDX2_C 0x4A80
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#define PATH1_R_BT_LNA_IDX2_C_M 0x38
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#define PATH1_R_BT_LNA_IDX3_C 0x4A80
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#define PATH1_R_BT_LNA_IDX3_C_M 0x1C0
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#define PATH1_R_ELNA_SEL_MARGIN_LGC_C 0x4A80
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#define PATH1_R_ELNA_SEL_MARGIN_LGC_C_M 0xE00
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#define PATH1_R_ELNA_SEL_MARGIN_NLGC_C 0x4A80
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#define PATH1_R_ELNA_SEL_MARGIN_NLGC_C_M 0x7000
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#define PATH1_R_IBADC_CLIP_RATIO_C 0x4A80
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#define PATH1_R_IBADC_CLIP_RATIO_C_M 0x38000
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#define PATH1_R_IBADC_CLIP_TH_C 0x4A80
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#define PATH1_R_IBADC_CLIP_TH_C_M 0x1C0000
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#define PATH1_R_LGC_STEP_LIM_C 0x4A80
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#define PATH1_R_LGC_STEP_LIM_C_M 0xE00000
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#define PATH1_R_LNA_IDX_INIT_C 0x4A80
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#define PATH1_R_LNA_IDX_INIT_C_M 0x7000000
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#define PATH1_R_LNA_SEL_MARGIN_LGC_C 0x4A80
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#define PATH1_R_LNA_SEL_MARGIN_LGC_C_M 0x38000000
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#define PATH1_R_LINEAR_STEP_MIN_C 0x4A80
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#define PATH1_R_LINEAR_STEP_MIN_C_M 0xC0000000
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#define SEG0R_DFS_MSKNPW_TH_C 0x4A84
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#define SEG0R_DFS_MSKNPW_TH_C_M 0x7F
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#define SEG0R_DFS_MSKNPW_EN_C 0x4A84
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#define SEG0R_DFS_MSKNPW_EN_C_M 0x80
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#define PATH0_R_IB_PW_DIFF_OFST_BW20_C 0x4A8C
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#define PATH0_R_IB_PW_DIFF_OFST_BW20_C_M 0xF
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#define PATH0_R_IB_PW_DIFF_OFST_BW40_C 0x4A8C
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#define PATH0_R_IB_PW_DIFF_OFST_BW40_C_M 0xF0
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#define PATH0_R_IB_PW_DIFF_OFST_BW80_C 0x4A8C
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#define PATH0_R_IB_PW_DIFF_OFST_BW80_C_M 0xF00
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#define PATH1_R_IB_PW_DIFF_OFST_BW20_C 0x4A90
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#define PATH1_R_IB_PW_DIFF_OFST_BW20_C_M 0xF
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#define PATH1_R_IB_PW_DIFF_OFST_BW40_C 0x4A90
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#define PATH1_R_IB_PW_DIFF_OFST_BW40_C_M 0xF0
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#define PATH1_R_IB_PW_DIFF_OFST_BW80_C 0x4A90
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#define PATH1_R_IB_PW_DIFF_OFST_BW80_C_M 0xF00
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#define SEG0R_SB5M_BLK_PATH_COMB_TYPE_C 0x4A94
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#define SEG0R_SB5M_BLK_PATH_COMB_TYPE_C_M 0x1
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#define PATH1_R_LNA_SEL_MARGIN_NLGC_C 0x4A9C
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#define PATH1_R_LNA_SEL_MARGIN_NLGC_C_M 0x7
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#define PATH1_R_RXSEL_MARGIN_LGC_C 0x4A9C
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#define PATH1_R_RXSEL_MARGIN_LGC_C_M 0x38
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#define PATH1_R_RXSEL_MARGIN_NLGC_C 0x4A9C
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#define PATH1_R_RXSEL_MARGIN_NLGC_C_M 0x1C0
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#define PATH1_R_TIA_SEL_MARGIN_LGC_C 0x4A9C
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#define PATH1_R_TIA_SEL_MARGIN_LGC_C_M 0xE00
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#define PATH1_R_TIA_SEL_MARGIN_NLGC_C 0x4A9C
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#define PATH1_R_TIA_SEL_MARGIN_NLGC_C_M 0x7000
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#define PATH1_R_WBADC_CLIP_RATIO_C 0x4A9C
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#define PATH1_R_WBADC_CLIP_RATIO_C_M 0x38000
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#define PATH1_R_WBADC_CLIP_TH_C 0x4A9C
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#define PATH1_R_WBADC_CLIP_TH_C_M 0x1C0000
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#define PATH1_R_NLGC_STEP_LIM_C 0x4A9C
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#define PATH1_R_NLGC_STEP_LIM_C_M 0x600000
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#define PATH1_R_NLGC_STEP_MIN_C 0x4A9C
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#define PATH1_R_NLGC_STEP_MIN_C_M 0x1800000
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#define PATH1_R_POST_PD_STEP_LIM_C 0x4A9C
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#define PATH1_R_POST_PD_STEP_LIM_C_M 0x6000000
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#define PATH1_R_POST_PD_STEP_MIN_C 0x4A9C
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#define PATH1_R_POST_PD_STEP_MIN_C_M 0x18000000
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#define PATH1_R_PRE_PD_STEP_LIM_C 0x4A9C
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#define PATH1_R_PRE_PD_STEP_LIM_C_M 0x60000000
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#define PATH1_R_AGC_EN_C 0x4A9C
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#define PATH1_R_AGC_EN_C_M 0x80000000
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#define PATH1_R_PRE_PD_STEP_MIN_C 0x4AA0
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#define PATH1_R_PRE_PD_STEP_MIN_C_M 0x3
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#define PATH1_R_WBADC_PW_ALPHA_H_C 0x4AA0
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#define PATH1_R_WBADC_PW_ALPHA_H_C_M 0xC
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#define PATH1_R_WBADC_PW_ALPHA_L_C 0x4AA0
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#define PATH1_R_WBADC_PW_ALPHA_L_C_M 0x30
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#define PATH1_R_A_WB_GIDX_00_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_00_ELNA_C_M 0x40
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#define PATH1_R_A_WB_GIDX_01_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_01_ELNA_C_M 0x80
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#define PATH1_R_A_WB_GIDX_02_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_02_ELNA_C_M 0x100
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#define PATH1_R_A_WB_GIDX_03_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_03_ELNA_C_M 0x200
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#define PATH1_R_A_WB_GIDX_04_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_04_ELNA_C_M 0x400
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#define PATH1_R_A_WB_GIDX_05_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_05_ELNA_C_M 0x800
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#define PATH1_R_A_WB_GIDX_06_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_06_ELNA_C_M 0x1000
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#define PATH1_R_A_WB_GIDX_07_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_07_ELNA_C_M 0x2000
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#define PATH1_R_A_WB_GIDX_08_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_08_ELNA_C_M 0x4000
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#define PATH1_R_A_WB_GIDX_09_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_09_ELNA_C_M 0x8000
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#define PATH1_R_A_WB_GIDX_10_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_10_ELNA_C_M 0x10000
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#define PATH1_R_A_WB_GIDX_11_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_11_ELNA_C_M 0x20000
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#define PATH1_R_A_WB_GIDX_12_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_12_ELNA_C_M 0x40000
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#define PATH1_R_A_WB_GIDX_13_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_13_ELNA_C_M 0x80000
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#define PATH1_R_A_WB_GIDX_14_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_14_ELNA_C_M 0x100000
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#define PATH1_R_A_WB_GIDX_15_ELNA_C 0x4AA0
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#define PATH1_R_A_WB_GIDX_15_ELNA_C_M 0x200000
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#define PATH1_R_GC_TIME_1T_MORE_C 0x4AA0
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#define PATH1_R_GC_TIME_1T_MORE_C_M 0x400000
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#define PATH1_R_G_WB_GIDX_00_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_00_ELNA_C_M 0x800000
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#define PATH1_R_G_WB_GIDX_01_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_01_ELNA_C_M 0x1000000
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#define PATH1_R_G_WB_GIDX_02_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_02_ELNA_C_M 0x2000000
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#define PATH1_R_G_WB_GIDX_03_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_03_ELNA_C_M 0x4000000
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#define PATH1_R_G_WB_GIDX_04_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_04_ELNA_C_M 0x8000000
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#define PATH1_R_G_WB_GIDX_05_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_05_ELNA_C_M 0x10000000
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#define PATH1_R_G_WB_GIDX_06_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_06_ELNA_C_M 0x20000000
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#define PATH1_R_G_WB_GIDX_07_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_07_ELNA_C_M 0x40000000
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#define PATH1_R_G_WB_GIDX_08_ELNA_C 0x4AA0
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#define PATH1_R_G_WB_GIDX_08_ELNA_C_M 0x80000000
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#define PATH1_R_G_WB_GIDX_09_ELNA_C 0x4AA4
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#define PATH1_R_G_WB_GIDX_09_ELNA_C_M 0x1
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#define PATH1_R_G_WB_GIDX_10_ELNA_C 0x4AA4
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#define PATH1_R_G_WB_GIDX_10_ELNA_C_M 0x2
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#define PATH1_R_G_WB_GIDX_11_ELNA_C 0x4AA4
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#define PATH1_R_G_WB_GIDX_11_ELNA_C_M 0x4
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#define PATH1_R_G_WB_GIDX_12_ELNA_C 0x4AA4
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#define PATH1_R_G_WB_GIDX_12_ELNA_C_M 0x8
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#define PATH1_R_G_WB_GIDX_13_ELNA_C 0x4AA4
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#define PATH1_R_G_WB_GIDX_13_ELNA_C_M 0x10
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#define PATH1_R_G_WB_GIDX_14_ELNA_C 0x4AA4
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#define PATH1_R_G_WB_GIDX_14_ELNA_C_M 0x20
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#define PATH1_R_G_WB_GIDX_15_ELNA_C 0x4AA4
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#define PATH1_R_G_WB_GIDX_15_ELNA_C_M 0x40
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#define PATH1_R_SE1_TIME_C 0x4AA4
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#define PATH1_R_SE1_TIME_C_M 0x80
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#define PATH1_R_SE1_TIME_NLGC_C 0x4AA4
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#define PATH1_R_SE1_TIME_NLGC_C_M 0x100
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#define PATH1_R_SE2_TIME_C 0x4AA4
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#define PATH1_R_SE2_TIME_C_M 0x200
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#define PATH1_R_SE2_TIME_NLGC_C 0x4AA4
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#define PATH1_R_SE2_TIME_NLGC_C_M 0x400
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#define PATH1_R_SE3_TIME_C 0x4AA4
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#define PATH1_R_SE3_TIME_C_M 0x800
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#define PATH1_R_SE4_TIME_C 0x4AA4
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#define PATH1_R_SE4_TIME_C_M 0x1000
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#define PATH1_R_SE5_TIME_C 0x4AA4
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#define PATH1_R_SE5_TIME_C_M 0x2000
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#define PATH1_R_SE_TIME_DONE_C 0x4AA4
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#define PATH1_R_SE_TIME_DONE_C_M 0x4000
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#define PATH1_R_SE_TIME_LINEAR_EXT_C 0x4AA4
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#define PATH1_R_SE_TIME_LINEAR_EXT_C_M 0x8000
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#define PATH1_R_ACI_NRBW_EN_C 0x4AA4
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#define PATH1_R_ACI_NRBW_EN_C_M 0x10000
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#define PATH1_R_BAND_SEL_C 0x4AA4
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#define PATH1_R_BAND_SEL_C_M 0x20000
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#define PATH1_R_BT_RX_MODE_EN_C 0x4AA4
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#define PATH1_R_BT_RX_MODE_EN_C_M 0x40000
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#define PATH1_R_BT_SHARE_C 0x4AA4
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#define PATH1_R_BT_SHARE_C_M 0x80000
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#define PATH1_R_BT_TX_FORCE_NRBW_C 0x4AA4
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#define PATH1_R_BT_TX_FORCE_NRBW_C_M 0x100000
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#define PATH1_R_BT_TX_MODE_EN_C 0x4AA4
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#define PATH1_R_BT_TX_MODE_EN_C_M 0x200000
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#define PATH1_R_BTG_PATH_C 0x4AA4
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#define PATH1_R_BTG_PATH_C_M 0x400000
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#define PATH1_R_CCK_FORCE_NRBW_C 0x4AA4
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#define PATH1_R_CCK_FORCE_NRBW_C_M 0x800000
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#define PATH1_R_DCCL_EN_C 0x4AA4
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#define PATH1_R_DCCL_EN_C_M 0x1000000
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#define PATH1_R_ELNA_BYPASS_EN_C 0x4AA4
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#define PATH1_R_ELNA_BYPASS_EN_C_M 0x2000000
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#define PATH1_R_ELNA_EN_C 0x4AA4
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#define PATH1_R_ELNA_EN_C_M 0x4000000
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#define PATH1_R_ELNA_IDX_INIT_C 0x4AA4
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#define PATH1_R_ELNA_IDX_INIT_C_M 0x8000000
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#define PATH1_R_FORCE_BT_COEX_C 0x4AA4
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#define PATH1_R_FORCE_BT_COEX_C_M 0x10000000
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#define PATH1_R_FORCE_NRBW_C 0x4AA4
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#define PATH1_R_FORCE_NRBW_C_M 0x20000000
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#define PATH1_R_I_ONLY_C 0x4AA4
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#define PATH1_R_I_ONLY_C_M 0x40000000
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#define PATH1_R_LGC_DAGC_EN_C 0x4AA4
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#define PATH1_R_LGC_DAGC_EN_C_M 0x80000000
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#define PATH1_R_LINEAR_AGC_EN_C 0x4AA8
|
#define PATH1_R_LINEAR_AGC_EN_C_M 0x1
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#define PATH1_R_LINEAR_MARGIN_MODE_C 0x4AA8
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#define PATH1_R_LINEAR_MARGIN_MODE_C_M 0x2
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#define PATH1_R_NLGC_AGC_EN_C 0x4AA8
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#define PATH1_R_NLGC_AGC_EN_C_M 0x4
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#define PATH1_R_NLGC_DAGC_EN_C 0x4AA8
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#define PATH1_R_NLGC_DAGC_EN_C_M 0x8
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#define PATH1_R_NRBW_DEF_C 0x4AA8
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#define PATH1_R_NRBW_DEF_C_M 0x10
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#define PATH1_R_POST_PD_AGC_EN_C 0x4AA8
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#define PATH1_R_POST_PD_AGC_EN_C_M 0x20
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#define PATH1_R_PRE_PD_AGC_EN_C 0x4AA8
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#define PATH1_R_PRE_PD_AGC_EN_C_M 0x40
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#define PATH1_R_PURE_POST_PD_MODE_C 0x4AA8
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#define PATH1_R_PURE_POST_PD_MODE_C_M 0x80
|
#define PATH1_R_SYNC_PRE_PD_STEP_C 0x4AA8
|
#define PATH1_R_SYNC_PRE_PD_STEP_C_M 0x100
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#define PATH1_R_TIA_IDX_INIT_C 0x4AA8
|
#define PATH1_R_TIA_IDX_INIT_C_M 0x200
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#define PATH1_R_TIA_SHRINK_DEF_C 0x4AA8
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#define PATH1_R_TIA_SHRINK_DEF_C_M 0x400
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#define PATH1_R_TIA_SHRINK_EN_C 0x4AA8
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#define PATH1_R_TIA_SHRINK_EN_C_M 0x800
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#define PATH1_R_TIA_SHRINK_INIT_C 0x4AA8
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#define PATH1_R_TIA_SHRINK_INIT_C_M 0x1000
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#define LDPC_MCS0_MAX_ITER_C 0x4AAC
|
#define LDPC_MCS0_MAX_ITER_C_M 0xF
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#define LDPC_MCS10_MAX_ITER_C 0x4AAC
|
#define LDPC_MCS10_MAX_ITER_C_M 0xF0
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#define LDPC_MCS11_MAX_ITER_C 0x4AAC
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#define LDPC_MCS11_MAX_ITER_C_M 0xF00
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#define LDPC_MCS1_MAX_ITER_C 0x4AAC
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#define LDPC_MCS1_MAX_ITER_C_M 0xF000
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#define LDPC_MCS2_MAX_ITER_C 0x4AAC
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#define LDPC_MCS2_MAX_ITER_C_M 0xF0000
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#define LDPC_MCS3_MAX_ITER_C 0x4AAC
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#define LDPC_MCS3_MAX_ITER_C_M 0xF00000
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#define LDPC_MCS4_MAX_ITER_C 0x4AAC
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#define LDPC_MCS4_MAX_ITER_C_M 0xF000000
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#define LDPC_MCS5_MAX_ITER_C 0x4AAC
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#define LDPC_MCS5_MAX_ITER_C_M 0xF0000000
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#define LDPC_MCS6_MAX_ITER_C 0x4AB0
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#define LDPC_MCS6_MAX_ITER_C_M 0xF
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#define LDPC_MCS7_MAX_ITER_C 0x4AB0
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#define LDPC_MCS7_MAX_ITER_C_M 0xF0
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#define LDPC_MCS8_MAX_ITER_C 0x4AB0
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#define LDPC_MCS8_MAX_ITER_C_M 0xF00
|
#define LDPC_MCS9_MAX_ITER_C 0x4AB0
|
#define LDPC_MCS9_MAX_ITER_C_M 0xF000
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#define CFO_COMP_PHASE_MODE_C 0x4AB4
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#define CFO_COMP_PHASE_MODE_C_M 0x1
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#define T2F_R_HE_1SS_CDDREFINE_TIE_0_C 0x4AC8
|
#define T2F_R_HE_1SS_CDDREFINE_TIE_0_C_M 0x1
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#define PATH0_R_AGC_RESERVED_1_C 0x4ACC
|
#define PATH0_R_AGC_RESERVED_1_C_M 0xFFFFFFFF
|
#define PATH0_R_AGC_RESERVED_2_C 0x4AD0
|
#define PATH0_R_AGC_RESERVED_2_C_M 0xFFFFFFFF
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#define PATH0_R_RXBY_WBADC_TH_C 0x4AD4
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#define PATH0_R_RXBY_WBADC_TH_C_M 0xF
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#define PATH0_R_ALWAYS_RXBY_WBADC_C 0x4AD4
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#define PATH0_R_ALWAYS_RXBY_WBADC_C_M 0x10
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#define PATH0_R_BT_RXBY_WBADC_C 0x4AD4
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#define PATH0_R_BT_RXBY_WBADC_C_M 0x20
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#define PATH0_R_BT_TRACKING_OFF_EN_C 0x4AD4
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#define PATH0_R_BT_TRACKING_OFF_EN_C_M 0x40
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#define PATH1_R_AGC_RESERVED_1_C 0x4AD8
|
#define PATH1_R_AGC_RESERVED_1_C_M 0xFFFFFFFF
|
#define PATH1_R_AGC_RESERVED_2_C 0x4ADC
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#define PATH1_R_AGC_RESERVED_2_C_M 0xFFFFFFFF
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#define PATH1_R_RXBY_WBADC_TH_C 0x4AE0
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#define PATH1_R_RXBY_WBADC_TH_C_M 0xF
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#define PATH1_R_ALWAYS_RXBY_WBADC_C 0x4AE0
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#define PATH1_R_ALWAYS_RXBY_WBADC_C_M 0x10
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#define PATH1_R_BT_RXBY_WBADC_C 0x4AE0
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#define PATH1_R_BT_RXBY_WBADC_C_M 0x20
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#define PATH1_R_BT_TRACKING_OFF_EN_C 0x4AE0
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#define PATH1_R_BT_TRACKING_OFF_EN_C_M 0x40
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#define PATH0_R_BT_BACKOFF_BMODE_C 0x4AE4
|
#define PATH0_R_BT_BACKOFF_BMODE_C_M 0x3F
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#define PATH0_R_BT_BACKOFF_IBADC_C 0x4AE4
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#define PATH0_R_BT_BACKOFF_IBADC_C_M 0xFC0
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#define PATH0_R_BT_BACKOFF_LNA_C 0x4AE4
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#define PATH0_R_BT_BACKOFF_LNA_C_M 0x3F000
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#define PATH0_R_BT_BACKOFF_TIA_C 0x4AE4
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#define PATH0_R_BT_BACKOFF_TIA_C_M 0xFC0000
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#define PATH0_R_GC_TIME_LESS_160M_C 0x4AE4
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#define PATH0_R_GC_TIME_LESS_160M_C_M 0xF000000
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#define PATH0_R_DCCL_ALPHA_160_C 0x4AE4
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#define PATH0_R_DCCL_ALPHA_160_C_M 0xF0000000
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#define PATH0_R_WBADC_DLY_160M_C 0x4AE8
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#define PATH0_R_WBADC_DLY_160M_C_M 0xF
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#define PATH0_R_WBADC_DLY_80M_C 0x4AE8
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#define PATH0_R_WBADC_DLY_80M_C_M 0xF0
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#define PATH0_R_WBADC_DLY_N80M_C 0x4AE8
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#define PATH0_R_WBADC_DLY_N80M_C_M 0xF00
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#define PATH0_R_RSSI_SOURCE_C 0x4AE8
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#define PATH0_R_RSSI_SOURCE_C_M 0x1000
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#define PATH1_R_BT_BACKOFF_BMODE_C 0x4AEC
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#define PATH1_R_BT_BACKOFF_BMODE_C_M 0x3F
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#define PATH1_R_BT_BACKOFF_IBADC_C 0x4AEC
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#define PATH1_R_BT_BACKOFF_IBADC_C_M 0xFC0
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#define PATH1_R_BT_BACKOFF_LNA_C 0x4AEC
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#define PATH1_R_BT_BACKOFF_LNA_C_M 0x3F000
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#define PATH1_R_BT_BACKOFF_TIA_C 0x4AEC
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#define PATH1_R_BT_BACKOFF_TIA_C_M 0xFC0000
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#define PATH1_R_GC_TIME_LESS_160M_C 0x4AEC
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#define PATH1_R_GC_TIME_LESS_160M_C_M 0xF000000
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#define PATH1_R_DCCL_ALPHA_160_C 0x4AEC
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#define PATH1_R_DCCL_ALPHA_160_C_M 0xF0000000
|
#define PATH1_R_WBADC_DLY_160M_C 0x4AF0
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#define PATH1_R_WBADC_DLY_160M_C_M 0xF
|
#define PATH1_R_WBADC_DLY_80M_C 0x4AF0
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#define PATH1_R_WBADC_DLY_80M_C_M 0xF0
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#define PATH1_R_WBADC_DLY_N80M_C 0x4AF0
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#define PATH1_R_WBADC_DLY_N80M_C_M 0xF00
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#define PATH1_R_RSSI_SOURCE_C 0x4AF0
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#define PATH1_R_RSSI_SOURCE_C_M 0x1000
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#define SEG0R_SNDCCA_RSV_C 0x4AFC
|
#define SEG0R_SNDCCA_RSV_C_M 0xFFFFFFFF
|
#define GD_PHASE_NON_LEG_R0S2_C 0x4B04
|
#define GD_PHASE_NON_LEG_R0S2_C_M 0xFF
|
#define GD_PHASE_NON_LEG_R0S3_C 0x4B04
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#define GD_PHASE_NON_LEG_R0S3_C_M 0xFF00
|
#define GD_PHASE_NON_LEG_R1S2_C 0x4B04
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#define GD_PHASE_NON_LEG_R1S2_C_M 0xFF0000
|
#define GD_PHASE_NON_LEG_R1S3_C 0x4B04
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#define GD_PHASE_NON_LEG_R1S3_C_M 0xFF000000
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#define MANUAL_GD_PHASE_LEGACY_EN_C 0x4B08
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#define MANUAL_GD_PHASE_LEGACY_EN_C_M 0x1
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#define PATH0_R_TSSI_CURVE_P0_C 0x5600
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#define PATH0_R_TSSI_CURVE_P0_C_M 0x3F
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#define PATH0_R_TSSI_CURVE_P1_C 0x5600
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#define PATH0_R_TSSI_CURVE_P1_C_M 0x3F00
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#define PATH0_R_TSSI_CURVE_P2_C 0x5600
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#define PATH0_R_TSSI_CURVE_P2_C_M 0x3F0000
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#define PATH0_R_TSSI_CURVE_P3_C 0x5600
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#define PATH0_R_TSSI_CURVE_P3_C_M 0x3F000000
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#define PATH0_R_TSSI_CURVE_P4_C 0x5604
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#define PATH0_R_TSSI_CURVE_P4_C_M 0x3F
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#define PATH0_R_TSSI_CURVE_P5_C 0x5604
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#define PATH0_R_TSSI_CURVE_P5_C_M 0x3F00
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#define PATH0_R_TSSI_CURVE_P6_C 0x5604
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#define PATH0_R_TSSI_CURVE_P6_C_M 0x3F0000
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#define PATH0_R_TSSI_CURVE_EN_C 0x5604
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#define PATH0_R_TSSI_CURVE_EN_C_M 0x80000000
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C 0x5608
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C_M 0x1FF
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C 0x5608
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C_M 0x3FE00
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C 0x5608
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C_M 0x7FC0000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C 0x560C
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C_M 0x1FF
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C 0x560C
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C_M 0x3FE00
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C 0x560C
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C_M 0x7FC0000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C 0x5610
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C_M 0x1FF
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C 0x5610
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C_M 0x3FE00
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C 0x5610
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C_M 0x7FC0000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C 0x5614
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C_M 0x1FF
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C 0x5614
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C_M 0x3FE00
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C 0x5614
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C_M 0x7FC0000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C 0x5618
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C_M 0x1FF
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C 0x5618
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C_M 0x3FE00
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C 0x5618
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C_M 0x7FC0000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C 0x561C
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#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C_M 0x1FF
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C 0x561C
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C_M 0xFF0000
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C 0x561C
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C_M 0xFF000000
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C 0x5620
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C_M 0xFF
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C 0x5620
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C_M 0xFF00
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C 0x5620
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C_M 0xFF0000
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C 0x5620
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C_M 0xFF000000
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C 0x5624
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C_M 0xFF
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C 0x5624
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C_M 0xFF00
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C 0x5624
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C_M 0xFF0000
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C 0x5624
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C_M 0xFF000000
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C 0x5628
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C_M 0xFF
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C 0x5628
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C_M 0xFF00
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C 0x5628
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C_M 0xFF0000
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C 0x5628
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C_M 0xFF000000
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C 0x562C
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C_M 0xFF
|
#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C 0x562C
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#define PATH0_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C_M 0xFF00
|
#define PATH0_R_TSSI_J_OFDM_G0_C 0x5630
|
#define PATH0_R_TSSI_J_OFDM_G0_C_M 0x3FF
|
#define PATH0_R_TSSI_J_OFDM_G1_C 0x5630
|
#define PATH0_R_TSSI_J_OFDM_G1_C_M 0xFFC00
|
#define PATH0_R_TSSI_J_OFDM_G2_C 0x5630
|
#define PATH0_R_TSSI_J_OFDM_G2_C_M 0x3FF00000
|
#define PATH0_R_TSSI_J_OFDM_G3_C 0x5634
|
#define PATH0_R_TSSI_J_OFDM_G3_C_M 0x3FF
|
#define PATH0_R_TSSI_J_OFDM_G4_C 0x5634
|
#define PATH0_R_TSSI_J_OFDM_G4_C_M 0xFFC00
|
#define PATH0_R_TSSI_J_OFDM_G5_C 0x5634
|
#define PATH0_R_TSSI_J_OFDM_G5_C_M 0x3FF00000
|
#define PATH0_R_TSSI_J_OFDM_G6_C 0x5638
|
#define PATH0_R_TSSI_J_OFDM_G6_C_M 0x3FF
|
#define PATH0_R_TSSI_J_OFDM_G7_C 0x5638
|
#define PATH0_R_TSSI_J_OFDM_G7_C_M 0xFFC00
|
#define PATH0_R_TSSI_J_CCK_G0_C 0x563C
|
#define PATH0_R_TSSI_J_CCK_G0_C_M 0x3FF
|
#define PATH0_R_TSSI_J_CCK_G1_C 0x563C
|
#define PATH0_R_TSSI_J_CCK_G1_C_M 0xFFC00
|
#define PATH0_R_TSSI_J_CCK_G2_C 0x563C
|
#define PATH0_R_TSSI_J_CCK_G2_C_M 0x3FF00000
|
#define PATH0_R_TSSI_J_CCK_G3_C 0x5640
|
#define PATH0_R_TSSI_J_CCK_G3_C_M 0x3FF
|
#define PATH0_R_TSSI_J_CCK_G4_C 0x5640
|
#define PATH0_R_TSSI_J_CCK_G4_C_M 0xFFC00
|
#define PATH0_R_TSSI_J_CCK_G5_C 0x5640
|
#define PATH0_R_TSSI_J_CCK_G5_C_M 0x3FF00000
|
#define PATH0_R_TSSI_J_CCK_G6_C 0x5644
|
#define PATH0_R_TSSI_J_CCK_G6_C_M 0x3FF
|
#define PATH0_R_TSSI_J_CCK_G7_C 0x5644
|
#define PATH0_R_TSSI_J_CCK_G7_C_M 0xFFC00
|
#define PATH0_R_TXRFC_RFMODE_FORCE_VAL_C 0x5648
|
#define PATH0_R_TXRFC_RFMODE_FORCE_VAL_C_M 0xF
|
#define PATH0_R_TXRFC_RFMODE_FORCE_ON_C 0x5648
|
#define PATH0_R_TXRFC_RFMODE_FORCE_ON_C_M 0x10
|
#define PATH0_R_TXRFC_TSSI_OFST_FORCE_VAL_C 0x5648
|
#define PATH0_R_TXRFC_TSSI_OFST_FORCE_VAL_C_M 0x3E0
|
#define PATH0_R_TXRFC_TSSI_OFST_FORCE_ON_C 0x5648
|
#define PATH0_R_TXRFC_TSSI_OFST_FORCE_ON_C_M 0x400
|
#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_VAL_C 0x5648
|
#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_VAL_C_M 0x800
|
#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_ON_C 0x5648
|
#define PATH0_R_TXRFC_TX_CCK_IND_FORCE_ON_C_M 0x1000
|
#define PATH0_R_TXRFC_TXAGC_RF_FORCE_VAL_C 0x5648
|
#define PATH0_R_TXRFC_TXAGC_RF_FORCE_VAL_C_M 0x7E000
|
#define PATH0_R_TXRFC_TXAGC_RF_FORCE_ON_C 0x5648
|
#define PATH0_R_TXRFC_TXAGC_RF_FORCE_ON_C_M 0x80000
|
#define PATH0_R_TXRFC_GAIN_TX_FORCE_VAL_C 0x564C
|
#define PATH0_R_TXRFC_GAIN_TX_FORCE_VAL_C_M 0x1F
|
#define PATH0_R_TXRFC_GAIN_TX_FORCE_ON_C 0x564C
|
#define PATH0_R_TXRFC_GAIN_TX_FORCE_ON_C_M 0x20
|
#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C 0x564C
|
#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C_M 0xC0
|
#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C 0x564C
|
#define PATH0_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C_M 0x100
|
#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C 0x564C
|
#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C_M 0x600
|
#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C 0x564C
|
#define PATH0_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C_M 0x800
|
#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C 0x564C
|
#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C_M 0xE000
|
#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C 0x564C
|
#define PATH0_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C_M 0x10000
|
#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_VAL_C 0x564C
|
#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_VAL_C_M 0xE0000
|
#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_ON_C 0x564C
|
#define PATH0_R_TXRFC_TSSI_CURVE_FORCE_ON_C_M 0x100000
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C 0x5650
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C_M 0x1F
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_C 0x5650
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_C_M 0x3E0
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C 0x5650
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C_M 0x7C00
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C 0x5650
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C_M 0xF8000
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C 0x5650
|
#define PATH0_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C_M 0x1F00000
|
#define PATH0_R_TSSI_DCK_BY_CURVE_EN_C 0x5650
|
#define PATH0_R_TSSI_DCK_BY_CURVE_EN_C_M 0x80000000
|
#define PATH0_R_TSSI_DCK_BY_CURVE_0_C 0x5654
|
#define PATH0_R_TSSI_DCK_BY_CURVE_0_C_M 0xFFF
|
#define PATH0_R_TSSI_DCK_BY_CURVE_1_C 0x5654
|
#define PATH0_R_TSSI_DCK_BY_CURVE_1_C_M 0xFFF000
|
#define PATH0_R_TSSI_DCK_BY_CURVE_2_C 0x5658
|
#define PATH0_R_TSSI_DCK_BY_CURVE_2_C_M 0xFFF
|
#define PATH0_R_TSSI_DCK_BY_CURVE_3_C 0x5658
|
#define PATH0_R_TSSI_DCK_BY_CURVE_3_C_M 0xFFF000
|
#define PATH0_R_TSSI_DCK_BY_CURVE_4_C 0x565C
|
#define PATH0_R_TSSI_DCK_BY_CURVE_4_C_M 0xFFF
|
#define PATH0_R_TSSI_DCK_BY_CURVE_5_C 0x565C
|
#define PATH0_R_TSSI_DCK_BY_CURVE_5_C_M 0xFFF000
|
#define PATH0_R_TSSI_DCK_BY_CURVE_6_C 0x5660
|
#define PATH0_R_TSSI_DCK_BY_CURVE_6_C_M 0xFFF
|
#define PATH0_R_TSSI_DCK_BY_CURVE_7_C 0x5660
|
#define PATH0_R_TSSI_DCK_BY_CURVE_7_C_M 0xFFF000
|
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C 0x5664
|
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C_M 0x7
|
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C 0x5664
|
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C_M 0x38
|
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C 0x5664
|
#define PATH0_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C_M 0x1C0
|
#define PATH0_R_TSSI_DCK_MOVING_AVG_LEN_C 0x5664
|
#define PATH0_R_TSSI_DCK_MOVING_AVG_LEN_C_M 0x7000
|
#define PATH0_R_TSSI_DCK_MOVING_AVG_CLR_C 0x5664
|
#define PATH0_R_TSSI_DCK_MOVING_AVG_CLR_C_M 0x8000
|
#define PATH0_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C 0x5664
|
#define PATH0_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C_M 0xF0000
|
#define PATH0_R_TSSI_DCK_MOVING_AVG_INI_DIS_C 0x5664
|
#define PATH0_R_TSSI_DCK_MOVING_AVG_INI_DIS_C_M 0x100000
|
#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C 0x5668
|
#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C_M 0x1
|
#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C 0x5668
|
#define PATH0_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C_M 0x2
|
#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C 0x5668
|
#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C_M 0x4
|
#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_ON_C 0x5668
|
#define PATH0_R_TXRFC_EN_PA_GAPK_FORCE_ON_C_M 0x8
|
#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C 0x5668
|
#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C_M 0x7F0
|
#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C 0x5668
|
#define PATH0_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C_M 0x800
|
#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C 0x5668
|
#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C_M 0x3F000
|
#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C 0x5668
|
#define PATH0_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C_M 0x40000
|
#define PATH0_R_TSSI_TIMEOUT_TIME_C 0x566C
|
#define PATH0_R_TSSI_TIMEOUT_TIME_C_M 0xFFF
|
#define PATH0_R_TSSI_TIMEOUT_UNIT_C 0x566C
|
#define PATH0_R_TSSI_TIMEOUT_UNIT_C_M 0x3000
|
#define PATH0_R_DIS_TXAGC_RFC_SRC_FIX_C 0x5684
|
#define PATH0_R_DIS_TXAGC_RFC_SRC_FIX_C_M 0x40000000
|
#define PATH0_R_TXAGC_MAX_C 0x5800
|
#define PATH0_R_TXAGC_MAX_C_M 0xFF
|
#define PATH0_R_TXAGC_MIN_C 0x5800
|
#define PATH0_R_TXAGC_MIN_C_M 0xFF00
|
#define PATH0_R_TXAGC_RF_MAX_C 0x5800
|
#define PATH0_R_TXAGC_RF_MAX_C_M 0x3F0000
|
#define PATH0_R_TXAGC_RF_MIN_C 0x5800
|
#define PATH0_R_TXAGC_RF_MIN_C_M 0xFC00000
|
#define PATH0_R_DPD_OFST_EN_C 0x5800
|
#define PATH0_R_DPD_OFST_EN_C_M 0x10000000
|
#define PATH0_R_TXAGCSWING_EN_C 0x5800
|
#define PATH0_R_TXAGCSWING_EN_C_M 0x20000000
|
#define PATH0_R_DIS_CCK_SWING_TSSI_OFST_C 0x5800
|
#define PATH0_R_DIS_CCK_SWING_TSSI_OFST_C_M 0x40000000
|
#define PATH0_R_DIS_CCK_SWING_TXAGC_C 0x5800
|
#define PATH0_R_DIS_CCK_SWING_TXAGC_C_M 0x80000000
|
#define PATH0_R_TXAGC_OFDM_REF_DBM_C 0x5804
|
#define PATH0_R_TXAGC_OFDM_REF_DBM_C_M 0x1FF
|
#define PATH0_R_TXAGC_OFDM_REF_CW_C 0x5804
|
#define PATH0_R_TXAGC_OFDM_REF_CW_C_M 0x3FE00
|
#define PATH0_R_TSSI_MAP_OFST_OFDM_C 0x5804
|
#define PATH0_R_TSSI_MAP_OFST_OFDM_C_M 0x7FC0000
|
#define PATH0_R_DPD_OFST_C 0x5804
|
#define PATH0_R_DPD_OFST_C_M 0xF8000000
|
#define PATH0_R_TXAGC_CCK_REF_DBM_C 0x5808
|
#define PATH0_R_TXAGC_CCK_REF_DBM_C_M 0x1FF
|
#define PATH0_R_TXAGC_CCK_REF_CW_C 0x5808
|
#define PATH0_R_TXAGC_CCK_REF_CW_C_M 0x3FE00
|
#define PATH0_R_TSSI_MAP_OFST_CCK_C 0x5808
|
#define PATH0_R_TSSI_MAP_OFST_CCK_C_M 0x7FC0000
|
#define PATH0_R_TSSI_MAP_SLOPE_OFDM_C 0x580C
|
#define PATH0_R_TSSI_MAP_SLOPE_OFDM_C_M 0x7F
|
#define PATH0_R_TSSI_MAP_SLOPE_CCK_C 0x580C
|
#define PATH0_R_TSSI_MAP_SLOPE_CCK_C_M 0x7F00
|
#define PATH0_R_TXPW_FORCE_RDY_C 0x580C
|
#define PATH0_R_TXPW_FORCE_RDY_C_M 0x8000
|
#define PATH0_R_TSSI_ADC_DC_OFST_RE_C 0x580C
|
#define PATH0_R_TSSI_ADC_DC_OFST_RE_C_M 0xFFF0000
|
#define PATH0_R_TSSI_PARAM_OFDM_20M_ONLY_C 0x580C
|
#define PATH0_R_TSSI_PARAM_OFDM_20M_ONLY_C_M 0x10000000
|
#define PATH0_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C 0x580C
|
#define PATH0_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C_M 0x20000000
|
#define PATH0_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C 0x580C
|
#define PATH0_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x40000000
|
#define PATH0_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C 0x580C
|
#define PATH0_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x80000000
|
#define PATH0_R_TXAGC_PSEUDO_CW_C 0x5810
|
#define PATH0_R_TXAGC_PSEUDO_CW_C_M 0x1FF
|
#define PATH0_R_TXAGC_PSEUDO_CW_EN_C 0x5810
|
#define PATH0_R_TXAGC_PSEUDO_CW_EN_C_M 0x200
|
#define PATH0_R_TMETER_T0_C 0x5810
|
#define PATH0_R_TMETER_T0_C_M 0xFC00
|
#define PATH0_R_DIS_TSSI_F_C 0x5810
|
#define PATH0_R_DIS_TSSI_F_C_M 0x10000
|
#define PATH0_R_TMETER_TBL_RA_C 0x5810
|
#define PATH0_R_TMETER_TBL_RA_C_M 0x7E0000
|
#define PATH0_R_TMETER_TBL_RD_C 0x5810
|
#define PATH0_R_TMETER_TBL_RD_C_M 0x800000
|
#define PATH0_R_TSSI_THERMAL_PW_TRK_EN_C 0x5810
|
#define PATH0_R_TSSI_THERMAL_PW_TRK_EN_C_M 0x1000000
|
#define PATH0_R_TMETER_TBL_FORCE_WEN_C 0x5810
|
#define PATH0_R_TMETER_TBL_FORCE_WEN_C_M 0x2000000
|
#define PATH0_R_TMETER_TBL_FORCE_REN_C 0x5810
|
#define PATH0_R_TMETER_TBL_FORCE_REN_C_M 0x4000000
|
#define PATH0_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C 0x5810
|
#define PATH0_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C_M 0x8000000
|
#define PATH0_R_TSSI_DONT_USE_UPD_ADC_C 0x5810
|
#define PATH0_R_TSSI_DONT_USE_UPD_ADC_C_M 0x10000000
|
#define PATH0_R_TSSI_BYPASS_TSSI_FORCE_OFF_C 0x5810
|
#define PATH0_R_TSSI_BYPASS_TSSI_FORCE_OFF_C_M 0x20000000
|
#define PATH0_R_TSSI_DBG_PORT_EN_C 0x5810
|
#define PATH0_R_TSSI_DBG_PORT_EN_C_M 0x40000000
|
#define PATH0_R_TSSI_DONT_BND_ALOGK_TO_POS_C 0x5810
|
#define PATH0_R_TSSI_DONT_BND_ALOGK_TO_POS_C_M 0x80000000
|
#define PATH0_R_TSSI_RF_GAP_TBL_RA_C 0x5814
|
#define PATH0_R_TSSI_RF_GAP_TBL_RA_C_M 0x3F
|
#define PATH0_R_TSSI_RF_GAP_EN_C 0x5814
|
#define PATH0_R_TSSI_RF_GAP_EN_C_M 0x40
|
#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_WEN_C 0x5814
|
#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_WEN_C_M 0x80
|
#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_REN_C 0x5814
|
#define PATH0_R_TSSI_RF_GAP_TBL_FORCE_REN_C_M 0x100
|
#define PATH0_R_TSSI_RF_GAP_TBL_RD_C 0x5814
|
#define PATH0_R_TSSI_RF_GAP_TBL_RD_C_M 0x200
|
#define PATH0_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C 0x5814
|
#define PATH0_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C_M 0x400
|
#define PATH0_R_TSSI_BYPASS_TSSI_C_C 0x5814
|
#define PATH0_R_TSSI_BYPASS_TSSI_C_C_M 0x800
|
#define PATH0_R_TSSI_DCK_AUTO_BYPASS_UPD_C 0x5814
|
#define PATH0_R_TSSI_DCK_AUTO_BYPASS_UPD_C_M 0x1000
|
#define PATH0_R_TSSI_DCK_AUTO_EN_C 0x5814
|
#define PATH0_R_TSSI_DCK_AUTO_EN_C_M 0x2000
|
#define PATH0_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C 0x5814
|
#define PATH0_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C_M 0x4000
|
#define PATH0_R_TSSI_DCK_AUTO_AVG_POINT_C 0x5814
|
#define PATH0_R_TSSI_DCK_AUTO_AVG_POINT_C_M 0x38000
|
#define PATH0_R_TSSI_DCK_AUTO_START_DLY_C 0x5814
|
#define PATH0_R_TSSI_DCK_AUTO_START_DLY_C_M 0x3C0000
|
#define PATH0_R_TSSI_ADC_AMPLIFY_C 0x5814
|
#define PATH0_R_TSSI_ADC_AMPLIFY_C_M 0xC00000
|
#define PATH0_R_TSSI_PW_TRK_USE_025DB_C 0x5814
|
#define PATH0_R_TSSI_PW_TRK_USE_025DB_C_M 0x1000000
|
#define PATH0_R_TSSI_DCK_SEL_C 0x5814
|
#define PATH0_R_TSSI_DCK_SEL_C_M 0x18000000
|
#define PATH0_R_TSSI_TXADC_PW_SV_EN_C 0x5814
|
#define PATH0_R_TSSI_TXADC_PW_SV_EN_C_M 0x20000000
|
#define PATH0_R_TSSI_RF_GAP_DE_CMB_OPT_C 0x5814
|
#define PATH0_R_TSSI_RF_GAP_DE_CMB_OPT_C_M 0x40000000
|
#define PATH0_R_TSSI_RF_GAP_DE_OFST_EN_C 0x5814
|
#define PATH0_R_TSSI_RF_GAP_DE_OFST_EN_C_M 0x80000000
|
#define PATH0_R_TXAGC_OFST_C 0x5818
|
#define PATH0_R_TXAGC_OFST_C_M 0xFF
|
#define PATH0_R_HE_ER_STF_PW_OFST_C 0x5818
|
#define PATH0_R_HE_ER_STF_PW_OFST_C_M 0x1FF00
|
#define PATH0_R_HE_STF_PW_OFST_C 0x5818
|
#define PATH0_R_HE_STF_PW_OFST_C_M 0x3FE0000
|
#define PATH0_R_TSSI_OSCILLATION_CNT_CLR_C 0x5818
|
#define PATH0_R_TSSI_OSCILLATION_CNT_CLR_C_M 0x4000000
|
#define PATH0_R_TSSI_OFST_BY_RFC_C 0x5818
|
#define PATH0_R_TSSI_OFST_BY_RFC_C_M 0x8000000
|
#define PATH0_R_TSSI_PW_TRK_AUTO_EN_C 0x5818
|
#define PATH0_R_TSSI_PW_TRK_AUTO_EN_C_M 0x10000000
|
#define PATH0_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C 0x5818
|
#define PATH0_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C_M 0x20000000
|
#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_EN_C 0x5818
|
#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_EN_C_M 0x40000000
|
#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C 0x5818
|
#define PATH0_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C_M 0x80000000
|
#define PATH0_R_TSSI_ADC_AVG_POINT_CCK_C 0x581C
|
#define PATH0_R_TSSI_ADC_AVG_POINT_CCK_C_M 0x3FF
|
#define PATH0_R_TSSI_ADC_AVG_POINT_OFDM_C 0x581C
|
#define PATH0_R_TSSI_ADC_AVG_POINT_OFDM_C_M 0xFFC00
|
#define PATH0_R_TSSI_SLOPE_CAL_EN_C 0x581C
|
#define PATH0_R_TSSI_SLOPE_CAL_EN_C_M 0x100000
|
#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C 0x581C
|
#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C_M 0x1E00000
|
#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C 0x581C
|
#define PATH0_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C_M 0x1E000000
|
#define PATH0_R_TSSI_ADC_NON_SQUARE_EN_C 0x581C
|
#define PATH0_R_TSSI_ADC_NON_SQUARE_EN_C_M 0x20000000
|
#define PATH0_R_TSSI_PSEUDO_TRK_MOD_EN_C 0x581C
|
#define PATH0_R_TSSI_PSEUDO_TRK_MOD_EN_C_M 0x80000000
|
#define PATH0_R_TSSI_SLOPE_A_C 0x5820
|
#define PATH0_R_TSSI_SLOPE_A_C_M 0xFFF
|
#define PATH0_R_TSSI_PKT_AVG_NUM_C 0x5820
|
#define PATH0_R_TSSI_PKT_AVG_NUM_C_M 0xF000
|
#define PATH0_R_TSSI_PW_TRK_SWING_LIM_C 0x5820
|
#define PATH0_R_TSSI_PW_TRK_SWING_LIM_C_M 0x1F0000
|
#define PATH0_R_TSSI_PW_TRK_SW_OFST_C 0x5820
|
#define PATH0_R_TSSI_PW_TRK_SW_OFST_C_M 0x1FE00000
|
#define PATH0_R_TSSI_ISEPA_C 0x5820
|
#define PATH0_R_TSSI_ISEPA_C_M 0x40000000
|
#define PATH0_R_TSSI_EN_C 0x5820
|
#define PATH0_R_TSSI_EN_C_M 0x80000000
|
#define PATH0_R_TSSI_A_OFDM_5M_C 0x5824
|
#define PATH0_R_TSSI_A_OFDM_5M_C_M 0x3FFFF
|
#define PATH0_R_TSSI_B_OFDM_5M_C 0x5824
|
#define PATH0_R_TSSI_B_OFDM_5M_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_K_OFDM_5M_C 0x5828
|
#define PATH0_R_TSSI_K_OFDM_5M_C_M 0xFFF
|
#define PATH0_R_TSSI_DE_OFDM_5M_C 0x5828
|
#define PATH0_R_TSSI_DE_OFDM_5M_C_M 0x3FF000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C 0x5828
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C_M 0x7FC00000
|
#define PATH0_R_TSSI_A_OFDM_10M_C 0x582C
|
#define PATH0_R_TSSI_A_OFDM_10M_C_M 0x3FFFF
|
#define PATH0_R_TSSI_B_OFDM_10M_C 0x582C
|
#define PATH0_R_TSSI_B_OFDM_10M_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_K_OFDM_10M_C 0x5830
|
#define PATH0_R_TSSI_K_OFDM_10M_C_M 0xFFF
|
#define PATH0_R_TSSI_DE_OFDM_10M_C 0x5830
|
#define PATH0_R_TSSI_DE_OFDM_10M_C_M 0x3FF000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C 0x5830
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C_M 0x7FC00000
|
#define PATH0_R_TSSI_A_OFDM_20M_C 0x5834
|
#define PATH0_R_TSSI_A_OFDM_20M_C_M 0x3FFFF
|
#define PATH0_R_TSSI_B_OFDM_20M_C 0x5834
|
#define PATH0_R_TSSI_B_OFDM_20M_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_K_OFDM_20M_C 0x5838
|
#define PATH0_R_TSSI_K_OFDM_20M_C_M 0xFFF
|
#define PATH0_R_TSSI_DE_OFDM_20M_C 0x5838
|
#define PATH0_R_TSSI_DE_OFDM_20M_C_M 0x3FF000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C 0x5838
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C_M 0x7FC00000
|
#define PATH0_R_TSSI_A_OFDM_40M_C 0x583C
|
#define PATH0_R_TSSI_A_OFDM_40M_C_M 0x3FFFF
|
#define PATH0_R_TSSI_B_OFDM_40M_C 0x583C
|
#define PATH0_R_TSSI_B_OFDM_40M_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_K_OFDM_40M_C 0x5840
|
#define PATH0_R_TSSI_K_OFDM_40M_C_M 0xFFF
|
#define PATH0_R_TSSI_DE_OFDM_40M_C 0x5840
|
#define PATH0_R_TSSI_DE_OFDM_40M_C_M 0x3FF000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C 0x5840
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C_M 0x7FC00000
|
#define PATH0_R_TSSI_A_OFDM_80M_C 0x5844
|
#define PATH0_R_TSSI_A_OFDM_80M_C_M 0x3FFFF
|
#define PATH0_R_TSSI_B_OFDM_80M_C 0x5844
|
#define PATH0_R_TSSI_B_OFDM_80M_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_K_OFDM_80M_C 0x5848
|
#define PATH0_R_TSSI_K_OFDM_80M_C_M 0xFFF
|
#define PATH0_R_TSSI_DE_OFDM_80M_C 0x5848
|
#define PATH0_R_TSSI_DE_OFDM_80M_C_M 0x3FF000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C 0x5848
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C_M 0x7FC00000
|
#define PATH0_R_TSSI_A_OFDM_80_80M_C 0x584C
|
#define PATH0_R_TSSI_A_OFDM_80_80M_C_M 0x3FFFF
|
#define PATH0_R_TSSI_B_OFDM_80_80M_C 0x584C
|
#define PATH0_R_TSSI_B_OFDM_80_80M_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_K_OFDM_80_80M_C 0x5850
|
#define PATH0_R_TSSI_K_OFDM_80_80M_C_M 0xFFF
|
#define PATH0_R_TSSI_DE_OFDM_80_80M_C 0x5850
|
#define PATH0_R_TSSI_DE_OFDM_80_80M_C_M 0x3FF000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C 0x5850
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C_M 0x7FC00000
|
#define PATH0_R_TSSI_A_CCK_LONG_C 0x5854
|
#define PATH0_R_TSSI_A_CCK_LONG_C_M 0x3FFFF
|
#define PATH0_R_TSSI_B_CCK_LONG_C 0x5854
|
#define PATH0_R_TSSI_B_CCK_LONG_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_K_CCK_LONG_C 0x5858
|
#define PATH0_R_TSSI_K_CCK_LONG_C_M 0xFFF
|
#define PATH0_R_TSSI_DE_CCK_LONG_C 0x5858
|
#define PATH0_R_TSSI_DE_CCK_LONG_C_M 0x3FF000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C 0x5858
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C_M 0x7FC00000
|
#define PATH0_R_TSSI_A_CCK_SHORT_C 0x585C
|
#define PATH0_R_TSSI_A_CCK_SHORT_C_M 0x3FFFF
|
#define PATH0_R_TSSI_B_CCK_SHORT_C 0x585C
|
#define PATH0_R_TSSI_B_CCK_SHORT_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_K_CCK_SHORT_C 0x5860
|
#define PATH0_R_TSSI_K_CCK_SHORT_C_M 0xFFF
|
#define PATH0_R_TSSI_DE_CCK_SHORT_C 0x5860
|
#define PATH0_R_TSSI_DE_CCK_SHORT_C_M 0x3FF000
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C 0x5860
|
#define PATH0_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C_M 0x7FC00000
|
#define PATH0_RSWING_NO_LIM_C 0x5860
|
#define PATH0_RSWING_NO_LIM_C_M 0x80000000
|
#define PATH0_R_TSSI_DELTA_CODE_MAX_C 0x5864
|
#define PATH0_R_TSSI_DELTA_CODE_MAX_C_M 0x3FF
|
#define PATH0_R_TSSI_DELTA_CODE_MIN_C 0x5864
|
#define PATH0_R_TSSI_DELTA_CODE_MIN_C_M 0xFFC00
|
#define PATH0_R_RFC_TMETER_T1_FORCE_VAL_C 0x5864
|
#define PATH0_R_RFC_TMETER_T1_FORCE_VAL_C_M 0x3F00000
|
#define PATH0_R_RFC_TMETER_T1_FORCE_ON_C 0x5864
|
#define PATH0_R_RFC_TMETER_T1_FORCE_ON_C_M 0x4000000
|
#define PATH0_R_GOTHROUGH_TX_IQKDPK_C 0x5864
|
#define PATH0_R_GOTHROUGH_TX_IQKDPK_C_M 0x8000000
|
#define PATH0_R_GOTHROUGH_RX_IQKDPK_C 0x5864
|
#define PATH0_R_GOTHROUGH_RX_IQKDPK_C_M 0x10000000
|
#define PATH0_R_IQK_IO_RFC_EN_C 0x5864
|
#define PATH0_R_IQK_IO_RFC_EN_C_M 0x20000000
|
#define PATH0_R_TX_IMFIR2_FORCE_RDY_C 0x5864
|
#define PATH0_R_TX_IMFIR2_FORCE_RDY_C_M 0x40000000
|
#define PATH0_R_CLK_GATING_TD_PATH_FORCE_ON_C 0x5864
|
#define PATH0_R_CLK_GATING_TD_PATH_FORCE_ON_C_M 0x80000000
|
#define PATH0_R_ANT_TRAIN_EN_C 0x5868
|
#define PATH0_R_ANT_TRAIN_EN_C_M 0x1
|
#define PATH0_R_TX_ANT_SEL_C 0x5868
|
#define PATH0_R_TX_ANT_SEL_C_M 0x2
|
#define PATH0_R_RFE_BUF_EN_C 0x5868
|
#define PATH0_R_RFE_BUF_EN_C_M 0x4
|
#define PATH0_R_LNAON_AGC_C 0x5868
|
#define PATH0_R_LNAON_AGC_C_M 0x8
|
#define PATH0_R_TRSW_BIT_BT_C 0x5868
|
#define PATH0_R_TRSW_BIT_BT_C_M 0x10
|
#define PATH0_R_TRSW_S_C 0x5868
|
#define PATH0_R_TRSW_S_C_M 0x20
|
#define PATH0_R_TRSW_O_C 0x5868
|
#define PATH0_R_TRSW_O_C_M 0x40
|
#define PATH0_R_TRSWB_O_C 0x5868
|
#define PATH0_R_TRSWB_O_C_M 0x80
|
#define PATH0_R_BT_FORCE_ANTIDX_C 0x5868
|
#define PATH0_R_BT_FORCE_ANTIDX_C_M 0xF00
|
#define PATH0_R_BT_FORCE_ANTIDX_EN_C 0x5868
|
#define PATH0_R_BT_FORCE_ANTIDX_EN_C_M 0x1000
|
#define PATH0_R_ANT_MODULE_RFE_OPT_C 0x5868
|
#define PATH0_R_ANT_MODULE_RFE_OPT_C_M 0xC000
|
#define PATH0_R_RFSW_TR_C 0x5868
|
#define PATH0_R_RFSW_TR_C_M 0xFFFF0000
|
#define PATH0_R_ANTSEL_C 0x586C
|
#define PATH0_R_ANTSEL_C_M 0xFFFFFFFF
|
#define PATH0_R_RFSW_ANT_31_0__C 0x5870
|
#define PATH0_R_RFSW_ANT_31_0__C_M 0xFFFFFFFF
|
#define PATH0_R_RFSW_ANT_63_32__C 0x5874
|
#define PATH0_R_RFSW_ANT_63_32__C_M 0xFFFFFFFF
|
#define PATH0_R_RFSW_ANT_95_64__C 0x5878
|
#define PATH0_R_RFSW_ANT_95_64__C_M 0xFFFFFFFF
|
#define PATH0_R_RFSW_ANT_127_96__C 0x587C
|
#define PATH0_R_RFSW_ANT_127_96__C_M 0xFFFFFFFF
|
#define PATH0_R_RFE_SEL_31_0__C 0x5880
|
#define PATH0_R_RFE_SEL_31_0__C_M 0xFFFFFFFF
|
#define PATH0_R_RFE_SEL_63_32__C 0x5884
|
#define PATH0_R_RFE_SEL_63_32__C_M 0xFFFFFFFF
|
#define PATH0_R_RFE_SEL_95_64__C 0x5888
|
#define PATH0_R_RFE_SEL_95_64__C_M 0xFFFFFFFF
|
#define PATH0_R_RFE_SEL_127_96__C 0x588C
|
#define PATH0_R_RFE_SEL_127_96__C_M 0xFFFFFFFF
|
#define PATH0_R_RFE_INV_C 0x5890
|
#define PATH0_R_RFE_INV_C_M 0xFFFFFFFF
|
#define PATH0_R_RFE_OPT_C 0x5894
|
#define PATH0_R_RFE_OPT_C_M 0xFFFFFFF
|
#define PATH0_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C 0x5894
|
#define PATH0_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C_M 0x10000000
|
#define PATH0_R_PATH_NOTRSW_BT_C 0x5894
|
#define PATH0_R_PATH_NOTRSW_BT_C_M 0x20000000
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C 0x5898
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C_M 0xFF
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C 0x5898
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C_M 0xFF00
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C 0x5898
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C_M 0xFF0000
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C 0x5898
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C_M 0xFF000000
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C 0x589C
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C_M 0xFF
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C 0x589C
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C_M 0xFF00
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C 0x589C
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C_M 0xFF0000
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C 0x589C
|
#define PATH0_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C_M 0xFF000000
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56_C 0x58A0
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56_C_M 0xFF
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56_2_C 0x58A0
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56_2_C_M 0xFF00
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56_4_C 0x58A0
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56_4_C_M 0xFF0000
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56_8_C 0x58A0
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56_8_C_M 0xFF000000
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56X2_C 0x58A4
|
#define PATH0_R_HE_LSTF_PW_OFST_52_56X2_C_M 0xFF
|
#define PATH0_R_TSSI_GAP_S0_C 0x58A4
|
#define PATH0_R_TSSI_GAP_S0_C_M 0x1FF00
|
#define PATH0_R_TSSI_GAP_S1_C 0x58A4
|
#define PATH0_R_TSSI_GAP_S1_C_M 0x3FE0000
|
#define PATH0_R_TSSI_GAP_S2_C 0x58A8
|
#define PATH0_R_TSSI_GAP_S2_C_M 0x1FF
|
#define PATH0_R_TSSI_GAP_S3_C 0x58A8
|
#define PATH0_R_TSSI_GAP_S3_C_M 0x3FE00
|
#define PATH0_R_TSSI_GAP_S4_C 0x58A8
|
#define PATH0_R_TSSI_GAP_S4_C_M 0x7FC0000
|
#define PATH0_R_TSSI_GAP_S5_C 0x58AC
|
#define PATH0_R_TSSI_GAP_S5_C_M 0x1FF
|
#define PATH0_R_TSSI_GAP_S6_C 0x58AC
|
#define PATH0_R_TSSI_GAP_S6_C_M 0x3FE00
|
#define PATH0_R_TSSI_GAP_S7_C 0x58AC
|
#define PATH0_R_TSSI_GAP_S7_C_M 0x7FC0000
|
#define PATH0_R_IQK_DPK_PATH_RST_C 0x58AC
|
#define PATH0_R_IQK_DPK_PATH_RST_C_M 0x8000000
|
#define PATH0_R_RX_CFIR_TAP_DEC_AT_HT_C 0x58AC
|
#define PATH0_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x10000000
|
#define PATH0_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x58AC
|
#define PATH0_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x20000000
|
#define PATH0_R_RX_CFIR_TAP_DEC_AT_HE_C 0x58AC
|
#define PATH0_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x40000000
|
#define PATH0_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x58AC
|
#define PATH0_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x80000000
|
#define PATH0_R_DAC_GAIN_COMP_TBL_RA_C 0x58B0
|
#define PATH0_R_DAC_GAIN_COMP_TBL_RA_C_M 0x7F
|
#define PATH0_R_DAC_GAIN_COMP_TBL_RD_C 0x58B0
|
#define PATH0_R_DAC_GAIN_COMP_TBL_RD_C_M 0x80
|
#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C 0x58B0
|
#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C_M 0x100
|
#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_REN_C 0x58B0
|
#define PATH0_R_DAC_GAIN_COMP_TBL_FORCE_REN_C_M 0x200
|
#define PATH0_R_DAC_GAIN_COMP_EN_C 0x58B0
|
#define PATH0_R_DAC_GAIN_COMP_EN_C_M 0x400
|
#define PATH0_R_TSSI_CW_COMP_EN_C 0x58B0
|
#define PATH0_R_TSSI_CW_COMP_EN_C_M 0x800
|
#define PATH0_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C 0x58B0
|
#define PATH0_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C_M 0x8000
|
#define PATH0_R_TSSI_OSCILLATION_HALT_TRK_TH_C 0x58B0
|
#define PATH0_R_TSSI_OSCILLATION_HALT_TRK_TH_C_M 0xFFFF0000
|
#define PATH0_R_TSSI_DBG_SEL_C 0x58B4
|
#define PATH0_R_TSSI_DBG_SEL_C_M 0x1F
|
#define PATH0_R_GAIN_TX_IPA_FORCE_ON_C 0x58B4
|
#define PATH0_R_GAIN_TX_IPA_FORCE_ON_C_M 0x20
|
#define PATH0_R_GAIN_TX_IPA_FORCE_VAL_C 0x58B4
|
#define PATH0_R_GAIN_TX_IPA_FORCE_VAL_C_M 0x1C0
|
#define PATH0_R_TXPW_TBL_IOQ_DIS_C 0x58B4
|
#define PATH0_R_TXPW_TBL_IOQ_DIS_C_M 0x200
|
#define PATH0_R_RFTXEN_SAMPLING_SHIFT_C 0x58B4
|
#define PATH0_R_RFTXEN_SAMPLING_SHIFT_C_M 0xF000
|
#define PATH0_R_TMETER_T0_CW_C 0x58B4
|
#define PATH0_R_TMETER_T0_CW_C_M 0xFF0000
|
#define PATH0_R_TSSI_F_WAIT_UPD_OFDM_C 0x58B4
|
#define PATH0_R_TSSI_F_WAIT_UPD_OFDM_C_M 0x7F000000
|
#define PATH0_R_TSSI_F_WAIT_UPD_CCK_SHORT_C 0x58B8
|
#define PATH0_R_TSSI_F_WAIT_UPD_CCK_SHORT_C_M 0x7F
|
#define PATH0_R_TSSI_F_WAIT_UPD_CCK_LONG_C 0x58B8
|
#define PATH0_R_TSSI_F_WAIT_UPD_CCK_LONG_C_M 0x7F00
|
#define PATH0_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C 0x58B8
|
#define PATH0_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C_M 0x7F0000
|
#define PATH0_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C 0x58B8
|
#define PATH0_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C_M 0x7F000000
|
#define PATH0_R_TXAGC_OFST_MAX_C 0x58BC
|
#define PATH0_R_TXAGC_OFST_MAX_C_M 0xFF
|
#define PATH0_R_TXAGC_OFST_MIN_C 0x58BC
|
#define PATH0_R_TXAGC_OFST_MIN_C_M 0xFF00
|
#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_C_M 0x10000
|
#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C_M 0x20000
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_C_M 0x40000
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C_M 0x80000
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_C_M 0x100000
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C_M 0x200000
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C_M 0x400000
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C_M 0x800000
|
#define PATH0_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C_M 0x1000000
|
#define PATH0_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C_M 0x2000000
|
#define PATH0_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C 0x58BC
|
#define PATH0_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C_M 0x4000000
|
#define PATH0_R_GAIN_TX_GAPK_FORCE_VAL_C 0x58C0
|
#define PATH0_R_GAIN_TX_GAPK_FORCE_VAL_C_M 0xF
|
#define PATH0_R_GAIN_TX_GAPK_FORCE_ON_C 0x58C0
|
#define PATH0_R_GAIN_TX_GAPK_FORCE_ON_C_M 0x10
|
#define PATH0_R_GAIN_TX_PAD_FORCE_VAL_C 0x58C0
|
#define PATH0_R_GAIN_TX_PAD_FORCE_VAL_C_M 0x3E0
|
#define PATH0_R_GAIN_TX_PAD_FORCE_ON_C 0x58C0
|
#define PATH0_R_GAIN_TX_PAD_FORCE_ON_C_M 0x400
|
#define PATH0_R_GAIN_TX_FORCE_VAL_C 0x58C0
|
#define PATH0_R_GAIN_TX_FORCE_VAL_C_M 0xF800
|
#define PATH0_R_GAIN_TX_FORCE_ON_C 0x58C0
|
#define PATH0_R_GAIN_TX_FORCE_ON_C_M 0x10000
|
#define PATH0_R_TSSISWING_LIM_PEAK_OFDM_C 0x58C0
|
#define PATH0_R_TSSISWING_LIM_PEAK_OFDM_C_M 0xE0000
|
#define PATH0_R_TSSISWING_LIM_PEAK_CCK_C 0x58C0
|
#define PATH0_R_TSSISWING_LIM_PEAK_CCK_C_M 0x700000
|
#define PATH0_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C 0x58C0
|
#define PATH0_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C_M 0x800000
|
#define PATH0_R_TSSI_TRACK_AT_SMALL_SWING_C 0x58C0
|
#define PATH0_R_TSSI_TRACK_AT_SMALL_SWING_C_M 0x1000000
|
#define PATH0_R_BYPASS_TSSI_CCK_EN_C 0x58C0
|
#define PATH0_R_BYPASS_TSSI_CCK_EN_C_M 0x2000000
|
#define PATH0_R_BYPASS_TSSI_LEGACY_EN_C 0x58C0
|
#define PATH0_R_BYPASS_TSSI_LEGACY_EN_C_M 0x4000000
|
#define PATH0_R_BYPASS_TSSI_HT_EN_C 0x58C0
|
#define PATH0_R_BYPASS_TSSI_HT_EN_C_M 0x8000000
|
#define PATH0_R_BYPASS_TSSI_VHT_EN_C 0x58C0
|
#define PATH0_R_BYPASS_TSSI_VHT_EN_C_M 0x10000000
|
#define PATH0_R_BYPASS_TSSI_HE_EN_C 0x58C0
|
#define PATH0_R_BYPASS_TSSI_HE_EN_C_M 0x20000000
|
#define PATH0_R_BYPASS_TSSI_HE_ER_SU_EN_C 0x58C0
|
#define PATH0_R_BYPASS_TSSI_HE_ER_SU_EN_C_M 0x40000000
|
#define PATH0_R_BYPASS_TSSI_HE_TB_EN_C 0x58C0
|
#define PATH0_R_BYPASS_TSSI_HE_TB_EN_C_M 0x80000000
|
#define PATH0_R_RF_GAP_CAL_BND0_C 0x58C4
|
#define PATH0_R_RF_GAP_CAL_BND0_C_M 0x3F
|
#define PATH0_R_RF_GAP_CAL_BND1_C 0x58C4
|
#define PATH0_R_RF_GAP_CAL_BND1_C_M 0xFC0
|
#define PATH0_R_RF_GAP_CAL_BND2_C 0x58C4
|
#define PATH0_R_RF_GAP_CAL_BND2_C_M 0x3F000
|
#define PATH0_R_TSSI_ADC_OFST_BND01_C 0x58C4
|
#define PATH0_R_TSSI_ADC_OFST_BND01_C_M 0x3FFC0000
|
#define PATH0_R_TSSI_RF_GAP_BY_RANGE_EN_C 0x58C4
|
#define PATH0_R_TSSI_RF_GAP_BY_RANGE_EN_C_M 0x40000000
|
#define PATH0_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C 0x58C4
|
#define PATH0_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C_M 0x80000000
|
#define PATH0_R_TSSI_ADC_OFST_BND12_C 0x58C8
|
#define PATH0_R_TSSI_ADC_OFST_BND12_C_M 0xFFF
|
#define PATH0_R_TSSI_ADC_OFST_BND22_C 0x58C8
|
#define PATH0_R_TSSI_ADC_OFST_BND22_C_M 0xFFF000
|
#define PATH0_R_ADC_FIFO_PATH_EN_FORCE_ON_C 0x58C8
|
#define PATH0_R_ADC_FIFO_PATH_EN_FORCE_ON_C_M 0x1000000
|
#define PATH0_R_TXINFO_CH_WITH_DATA_DECODE_C 0x58C8
|
#define PATH0_R_TXINFO_CH_WITH_DATA_DECODE_C_M 0x6000000
|
#define PATH0_R_BYPASS_TSSI_VHT_MU_EN_C 0x58C8
|
#define PATH0_R_BYPASS_TSSI_VHT_MU_EN_C_M 0x10000000
|
#define PATH0_R_BYPASS_TSSI_HE_MU_EN_C 0x58C8
|
#define PATH0_R_BYPASS_TSSI_HE_MU_EN_C_M 0x20000000
|
#define PATH0_R_BYPASS_TSSI_HE_RU_EN_C 0x58C8
|
#define PATH0_R_BYPASS_TSSI_HE_RU_EN_C_M 0x40000000
|
#define PATH0_R_BYPASS_TSSI_TXBF_EN_C 0x58C8
|
#define PATH0_R_BYPASS_TSSI_TXBF_EN_C_M 0x80000000
|
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL0_C 0x58CC
|
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL0_C_M 0x7
|
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL1_C 0x58CC
|
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL1_C_M 0x38
|
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL2_C 0x58CC
|
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL2_C_M 0x1C0
|
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL3_C 0x58CC
|
#define PATH0_R_TSSI_SLOPE_CAL_PA_SEL3_C_M 0xE00
|
#define PATH0_R_TSSI_SLOPE_CAL_SEL_IPA_C 0x58CC
|
#define PATH0_R_TSSI_SLOPE_CAL_SEL_IPA_C_M 0x1000
|
#define PATH0_R_TX_GAIN_CCK_MORE_ADJ_C 0x58CC
|
#define PATH0_R_TX_GAIN_CCK_MORE_ADJ_C_M 0xFF000000
|
#define PATH0_R_TX_GAIN_SCALE_FORCE_VAL_C 0x58D0
|
#define PATH0_R_TX_GAIN_SCALE_FORCE_VAL_C_M 0xFFF
|
#define PATH0_R_TX_GAIN_SCALE_FORCE_ON_C 0x58D0
|
#define PATH0_R_TX_GAIN_SCALE_FORCE_ON_C_M 0x1000
|
#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_C 0x58D0
|
#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_C_M 0x1E000
|
#define PATH0_R_TX_LSTF_PW_EST_LEN_C 0x58D0
|
#define PATH0_R_TX_LSTF_PW_EST_LEN_C_M 0x3FE0000
|
#define PATH0_R_TX_LSTF_PW_EST_SEL_EVEN_C 0x58D0
|
#define PATH0_R_TX_LSTF_PW_EST_SEL_EVEN_C_M 0x4000000
|
#define PATH0_R_TSSI_C_MAP_UNFIX_C 0x58D0
|
#define PATH0_R_TSSI_C_MAP_UNFIX_C_M 0x80000000
|
#define PATH0_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C 0x58D4
|
#define PATH0_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C_M 0xFF
|
#define PATH0_R_TSSI_BYPASS_TXPW_MAX_C 0x58D4
|
#define PATH0_R_TSSI_BYPASS_TXPW_MAX_C_M 0x3FE00
|
#define PATH0_R_TSSI_BYPASS_TXPW_MIN_C 0x58D4
|
#define PATH0_R_TSSI_BYPASS_TXPW_MIN_C_M 0x7FC0000
|
#define PATH0_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C 0x58D4
|
#define PATH0_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C_M 0x8000000
|
#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C 0x58D4
|
#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C_M 0x10000000
|
#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_POST_C 0x58D4
|
#define PATH0_R_TX_GAIN_SPLIT_FOR_DPD_POST_C_M 0x20000000
|
#define PATH0_R_TXPW_SPLIT_FOR_DPD_C 0x58D4
|
#define PATH0_R_TXPW_SPLIT_FOR_DPD_C_M 0x40000000
|
#define PATH0_R_TXAGC_TP_MASK_EN_C 0x58D4
|
#define PATH0_R_TXAGC_TP_MASK_EN_C_M 0x80000000
|
#define PATH0_R_TSSI_BYPASS_BY_C_MAX_C 0x58D8
|
#define PATH0_R_TSSI_BYPASS_BY_C_MAX_C_M 0x1FF
|
#define PATH0_R_TSSI_BYPASS_BY_C_MIN_C 0x58D8
|
#define PATH0_R_TSSI_BYPASS_BY_C_MIN_C_M 0x3FE00
|
#define PATH0_R_TSSI_BYPASS_BY_C_SEL_C 0x58D8
|
#define PATH0_R_TSSI_BYPASS_BY_C_SEL_C_M 0xC0000
|
#define PATH0_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C 0x58D8
|
#define PATH0_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C_M 0xFFF00000
|
#define PATH0_R_TXAGC_OFST_FIX_ERR_MAX_C 0x58DC
|
#define PATH0_R_TXAGC_OFST_FIX_ERR_MAX_C_M 0xFF
|
#define PATH0_R_TXAGC_OFST_FIX_ERR_MIN_C 0x58DC
|
#define PATH0_R_TXAGC_OFST_FIX_ERR_MIN_C_M 0xFF00
|
#define PATH0_R_TXAGC_OFST_FIX_C 0x58DC
|
#define PATH0_R_TXAGC_OFST_FIX_C_M 0x10000
|
#define PATH0_R_TSSI_C_FORCE_VAL_C 0x58DC
|
#define PATH0_R_TSSI_C_FORCE_VAL_C_M 0x1FF00000
|
#define PATH0_R_TSSI_C_FORCE_ON_C 0x58DC
|
#define PATH0_R_TSSI_C_FORCE_ON_C_M 0x20000000
|
#define PATH0_R_TXPW_RSTB_MAN_ON_C 0x58DC
|
#define PATH0_R_TXPW_RSTB_MAN_ON_C_M 0x40000000
|
#define PATH0_R_TXPW_RSTB_MAN_C 0x58DC
|
#define PATH0_R_TXPW_RSTB_MAN_C_M 0x80000000
|
#define PATH0_R_TXAGC_OFDM_REF_CW_OFST_C 0x58E0
|
#define PATH0_R_TXAGC_OFDM_REF_CW_OFST_C_M 0x3FF
|
#define PATH0_R_TXAGC_CCK_REF_CW_OFST_C 0x58E0
|
#define PATH0_R_TXAGC_CCK_REF_CW_OFST_C_M 0x3FF000
|
#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C 0x58E0
|
#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C_M 0x7F000000
|
#define PATH0_R_TXPW_RDY_NO_DLY_C 0x58E0
|
#define PATH0_R_TXPW_RDY_NO_DLY_C_M 0x80000000
|
#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C 0x58E4
|
#define PATH0_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C_M 0x7F
|
#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C 0x58E4
|
#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C_M 0x80
|
#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C 0x58E4
|
#define PATH0_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C_M 0x700
|
#define PATH0_R_TXAGC_OFST_MOVING_AVG_LEN_C 0x58E4
|
#define PATH0_R_TXAGC_OFST_MOVING_AVG_LEN_C_M 0x3800
|
#define PATH0_R_TXAGC_OFST_MOVING_AVG_CLR_C 0x58E4
|
#define PATH0_R_TXAGC_OFST_MOVING_AVG_CLR_C_M 0x4000
|
#define PATH0_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C 0x58E4
|
#define PATH0_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C_M 0x8000
|
#define PATH0_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C 0x58E4
|
#define PATH0_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C_M 0xF0000
|
#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C 0x58E4
|
#define PATH0_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C_M 0x7F00000
|
#define PATH0_R_TXPW_RSTB_SUB_SEL_C 0x58E4
|
#define PATH0_R_TXPW_RSTB_SUB_SEL_C_M 0x8000000
|
#define PATH0_R_TXPW_RSTB_SUB_C 0x58E4
|
#define PATH0_R_TXPW_RSTB_SUB_C_M 0x10000000
|
#define PATH0_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C 0x58E4
|
#define PATH0_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C_M 0x20000000
|
#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MAX_C 0x58F0
|
#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MAX_C_M 0x1FF
|
#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MIN_C 0x58F0
|
#define PATH0_R_TSSI_BYPASS_FINAL_CODE_MIN_C_M 0x3FE00
|
#define PATH0_R_GOTHROUGH_TX_GAIN_POST_DPD_C 0x58F0
|
#define PATH0_R_GOTHROUGH_TX_GAIN_POST_DPD_C_M 0x40000
|
#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C 0x58F0
|
#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C_M 0x80000
|
#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C 0x58F0
|
#define PATH0_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C_M 0xFFF00000
|
#define PATH0_R_RF_GAP_CAL_OFST_BND00_10BITS_C 0x58F4
|
#define PATH0_R_RF_GAP_CAL_OFST_BND00_10BITS_C_M 0x3FF
|
#define PATH0_R_RF_GAP_CAL_OFST_BND01_10BITS_C 0x58F4
|
#define PATH0_R_RF_GAP_CAL_OFST_BND01_10BITS_C_M 0xFFC00
|
#define PATH0_R_RF_GAP_CAL_OFST_BND12_10BITS_C 0x58F4
|
#define PATH0_R_RF_GAP_CAL_OFST_BND12_10BITS_C_M 0x3FF00000
|
#define PATH0_R_RF_GAP_CAL_OFST_BND22_10BITS_C 0x58F8
|
#define PATH0_R_RF_GAP_CAL_OFST_BND22_10BITS_C_M 0x3FF
|
#define PATH0_R_LOG_VAL_OFST_CCK_C 0x58F8
|
#define PATH0_R_LOG_VAL_OFST_CCK_C_M 0x3FFFFC00
|
#define PATH0_R_TSSI_ADC_PATH_Q_C 0x58F8
|
#define PATH0_R_TSSI_ADC_PATH_Q_C_M 0x40000000
|
#define PATH0_R_DAC_COMP_POST_DPD_EN_C 0x58F8
|
#define PATH0_R_DAC_COMP_POST_DPD_EN_C_M 0x80000000
|
#define PATH0_R_LOG_VAL_OFST_OFDM_C 0x58FC
|
#define PATH0_R_LOG_VAL_OFST_OFDM_C_M 0xFFFFF
|
#define PATH0_R_UPD_TXAGC_OFST_LATENCY_C 0x58FC
|
#define PATH0_R_UPD_TXAGC_OFST_LATENCY_C_M 0x700000
|
#define PATH0_R_TSSI_UPD_TMETER_EN_C 0x58FC
|
#define PATH0_R_TSSI_UPD_TMETER_EN_C_M 0x800000
|
#define PATH0_R_TXRFC_BW_TXFORCE_VAL_C 0x58FC
|
#define PATH0_R_TXRFC_BW_TXFORCE_VAL_C_M 0x3000000
|
#define PATH0_R_TXRFC_BW_TXFORCE_ON_C 0x58FC
|
#define PATH0_R_TXRFC_BW_TXFORCE_ON_C_M 0x4000000
|
#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_ON_C 0x58FC
|
#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_ON_C_M 0x8000000
|
#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_VAL_C 0x58FC
|
#define PATH0_R_TXRFC_DAC_0P5DB_FORCE_VAL_C_M 0x10000000
|
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C 0x5A00
|
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C 0x5A00
|
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C 0x5A04
|
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C 0x5A04
|
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C 0x5A08
|
#define PATH0_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C 0x5A08
|
#define PATH0_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C 0x5A0C
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C 0x5A0C
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C 0x5A10
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C 0x5A10
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C 0x5A14
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C 0x5A14
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C 0x5A18
|
#define PATH0_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C 0x5A18
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C 0x5A1C
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C 0x5A1C
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C 0x5A20
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C 0x5A20
|
#define PATH0_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_TXSC0_C 0x5A24
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_TXSC0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C 0x5A24
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C 0x5A28
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C 0x5A28
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C 0x5A2C
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C 0x5A2C
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C 0x5A30
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C 0x5A30
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C 0x5A34
|
#define PATH0_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C 0x5A34
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C 0x5A38
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C 0x5A38
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C 0x5A3C
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C 0x5A3C
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C 0x5A40
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C 0x5A40
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C 0x5A44
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C 0x5A44
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C 0x5A48
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C 0x5A48
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C 0x5A4C
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C 0x5A4C
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C 0x5A50
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C 0x5A50
|
#define PATH0_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C 0x5A54
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C 0x5A54
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C 0x5A58
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C 0x5A58
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C 0x5A5C
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C 0x5A5C
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C 0x5A60
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C 0x5A60
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C 0x5A64
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C 0x5A64
|
#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C 0x5A68
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C 0x5A68
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C 0x5A6C
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C 0x5A6C
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C 0x5A70
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#define PATH0_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C 0x5A70
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C 0x5A74
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C 0x5A74
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C 0x5A78
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C 0x5A78
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C 0x5A7C
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C 0x5A7C
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C 0x5A80
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C 0x5A80
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C 0x5A84
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C 0x5A84
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C 0x5A88
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C 0x5A88
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C 0x5A8C
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C 0x5A8C
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C 0x5A90
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C 0x5A90
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C 0x5A94
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C 0x5A94
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C 0x5A98
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C 0x5A98
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C 0x5A9C
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C 0x5A9C
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C 0x5AA0
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C 0x5AA0
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C 0x5AA4
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C 0x5AA4
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C 0x5AA8
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C 0x5AA8
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C_M 0xFFFF0000
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C 0x5AAC
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C 0x5AAC
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C 0x5AB0
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C 0x5AB0
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C 0x5AB4
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C_M 0xFFFF
|
#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C 0x5AB4
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C 0x5AB8
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C 0x5AB8
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C 0x5ABC
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C 0x5ABC
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C_M 0xFFFF0000
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C 0x5AC0
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#define PATH0_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C_M 0xFFFF
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#define PATH0_R_DAC_GAIN_COMP_UNEXPECTED_C 0x5AC0
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#define PATH0_R_DAC_GAIN_COMP_UNEXPECTED_C_M 0xFFFF0000
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS0_C 0x5C00
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS0_C_M 0xFF
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS1_C 0x5C00
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS1_C_M 0xFF00
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS2_C 0x5C00
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS2_C_M 0xFF0000
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS3_C 0x5C00
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS3_C_M 0xFF000000
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS4_C 0x5C04
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS4_C_M 0xFF
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS5_C 0x5C04
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS5_C_M 0xFF00
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS6_C 0x5C04
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS6_C_M 0xFF0000
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS7_C 0x5C04
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS7_C_M 0xFF000000
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS8_C 0x5C08
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS8_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS9_C 0x5C08
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS9_C_M 0xFF00
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS10_C 0x5C08
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS10_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS11_C 0x5C08
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS11_C_M 0xFF000000
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS12_C 0x5C0C
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS12_C_M 0xFF
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS13_C 0x5C0C
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS13_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS14_C 0x5C0C
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#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS14_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS15_C 0x5C0C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS15_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS16_C 0x5C10
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS16_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS17_C 0x5C10
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS17_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS18_C 0x5C10
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS18_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS19_C 0x5C10
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS19_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS20_C 0x5C14
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS20_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS21_C 0x5C14
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS21_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS22_C 0x5C14
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS22_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS23_C 0x5C14
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS23_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS24_C 0x5C18
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS24_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS25_C 0x5C18
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS25_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS26_C 0x5C18
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS26_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS27_C 0x5C18
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS27_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS28_C 0x5C1C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS28_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS29_C 0x5C1C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS29_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS30_C 0x5C1C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS30_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS31_C 0x5C1C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_POS31_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG32_C 0x5C20
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG32_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG31_C 0x5C20
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG31_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG30_C 0x5C20
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG30_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG29_C 0x5C20
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG29_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG28_C 0x5C24
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG28_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG27_C 0x5C24
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG27_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG26_C 0x5C24
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG26_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG25_C 0x5C24
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG25_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG24_C 0x5C28
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG24_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG23_C 0x5C28
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG23_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG22_C 0x5C28
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG22_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG21_C 0x5C28
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG21_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG20_C 0x5C2C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG20_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG19_C 0x5C2C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG19_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG18_C 0x5C2C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG18_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG17_C 0x5C2C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG17_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG16_C 0x5C30
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG16_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG15_C 0x5C30
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG15_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG14_C 0x5C30
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG14_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG13_C 0x5C30
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG13_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG12_C 0x5C34
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG12_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG11_C 0x5C34
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG11_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG10_C 0x5C34
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG10_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG9_C 0x5C34
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG9_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG8_C 0x5C38
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG8_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG7_C 0x5C38
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG7_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG6_C 0x5C38
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG6_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG5_C 0x5C38
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG5_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG4_C 0x5C3C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG4_C_M 0xFF
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG3_C 0x5C3C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG3_C_M 0xFF00
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG2_C 0x5C3C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG2_C_M 0xFF0000
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG1_C 0x5C3C
|
#define PATH0_R_TSSI_OFST_TMETER_T0_T1_NEG1_C_M 0xFF000000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_0_C 0x5C40
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_0_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_1_C 0x5C40
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_1_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_2_C 0x5C44
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_2_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_3_C 0x5C44
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_3_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_4_C 0x5C48
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_4_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_5_C 0x5C48
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_5_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_6_C 0x5C4C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_6_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_7_C 0x5C4C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_7_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_8_C 0x5C50
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_8_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_9_C 0x5C50
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_9_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_10_C 0x5C54
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_10_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_11_C 0x5C54
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_11_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_12_C 0x5C58
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_12_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_13_C 0x5C58
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_13_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_14_C 0x5C5C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_14_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_15_C 0x5C5C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_15_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_16_C 0x5C60
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_16_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_17_C 0x5C60
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_17_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_18_C 0x5C64
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_18_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_19_C 0x5C64
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_19_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_20_C 0x5C68
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_20_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_21_C 0x5C68
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_21_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_22_C 0x5C6C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_22_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_23_C 0x5C6C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_23_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_24_C 0x5C70
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_24_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_25_C 0x5C70
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_25_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_26_C 0x5C74
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_26_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_27_C 0x5C74
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_27_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_28_C 0x5C78
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_28_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_29_C 0x5C78
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_29_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_30_C 0x5C7C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_30_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_31_C 0x5C7C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_31_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_32_C 0x5C80
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_32_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_33_C 0x5C80
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_33_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_34_C 0x5C84
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_34_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_35_C 0x5C84
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_35_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_36_C 0x5C88
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_36_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_37_C 0x5C88
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_37_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_38_C 0x5C8C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_38_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_39_C 0x5C8C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_39_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_40_C 0x5C90
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_40_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_41_C 0x5C90
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_41_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_42_C 0x5C94
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_42_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_43_C 0x5C94
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_43_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_44_C 0x5C98
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_44_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_45_C 0x5C98
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_45_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_46_C 0x5C9C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_46_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_47_C 0x5C9C
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_47_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_48_C 0x5CA0
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_48_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_49_C 0x5CA0
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_49_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_50_C 0x5CA4
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_50_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_51_C 0x5CA4
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_51_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_52_C 0x5CA8
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_52_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_53_C 0x5CA8
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_53_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_54_C 0x5CAC
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_54_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_55_C 0x5CAC
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_55_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_56_C 0x5CB0
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_56_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_57_C 0x5CB0
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_57_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_58_C 0x5CB4
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_58_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_59_C 0x5CB4
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_59_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_60_C 0x5CB8
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_60_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_61_C 0x5CB8
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_61_C_M 0x3FF0000
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_62_C 0x5CBC
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_62_C_M 0x3FF
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_63_C 0x5CBC
|
#define PATH0_R_TSSI_OFST_RF_GAIN_IDX_63_C_M 0x3FF0000
|
#define PATH1_R_TSSI_CURVE_P0_C 0x7600
|
#define PATH1_R_TSSI_CURVE_P0_C_M 0x3F
|
#define PATH1_R_TSSI_CURVE_P1_C 0x7600
|
#define PATH1_R_TSSI_CURVE_P1_C_M 0x3F00
|
#define PATH1_R_TSSI_CURVE_P2_C 0x7600
|
#define PATH1_R_TSSI_CURVE_P2_C_M 0x3F0000
|
#define PATH1_R_TSSI_CURVE_P3_C 0x7600
|
#define PATH1_R_TSSI_CURVE_P3_C_M 0x3F000000
|
#define PATH1_R_TSSI_CURVE_P4_C 0x7604
|
#define PATH1_R_TSSI_CURVE_P4_C_M 0x3F
|
#define PATH1_R_TSSI_CURVE_P5_C 0x7604
|
#define PATH1_R_TSSI_CURVE_P5_C_M 0x3F00
|
#define PATH1_R_TSSI_CURVE_P6_C 0x7604
|
#define PATH1_R_TSSI_CURVE_P6_C_M 0x3F0000
|
#define PATH1_R_TSSI_CURVE_EN_C 0x7604
|
#define PATH1_R_TSSI_CURVE_EN_C_M 0x80000000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C 0x7608
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G0_C_M 0x1FF
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C 0x7608
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G1_C_M 0x3FE00
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C 0x7608
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G2_C_M 0x7FC0000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C 0x760C
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G3_C_M 0x1FF
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C 0x760C
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G4_C_M 0x3FE00
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C 0x760C
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G5_C_M 0x7FC0000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C 0x7610
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G6_C_M 0x1FF
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C 0x7610
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_G7_C_M 0x3FE00
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C 0x7610
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G0_C_M 0x7FC0000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C 0x7614
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G1_C_M 0x1FF
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C 0x7614
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G2_C_M 0x3FE00
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C 0x7614
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G3_C_M 0x7FC0000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C 0x7618
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G4_C_M 0x1FF
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C 0x7618
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G5_C_M 0x3FE00
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C 0x7618
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G6_C_M 0x7FC0000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C 0x761C
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_G7_C_M 0x1FF
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C 0x761C
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G0_C_M 0xFF0000
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C 0x761C
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G1_C_M 0xFF000000
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C 0x7620
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G2_C_M 0xFF
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C 0x7620
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G3_C_M 0xFF00
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C 0x7620
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G4_C_M 0xFF0000
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C 0x7620
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G5_C_M 0xFF000000
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C 0x7624
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G6_C_M 0xFF
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C 0x7624
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_OFDM_G7_C_M 0xFF00
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C 0x7624
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G0_C_M 0xFF0000
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C 0x7624
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G1_C_M 0xFF000000
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C 0x7628
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#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G2_C_M 0xFF
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C 0x7628
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#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G3_C_M 0xFF00
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C 0x7628
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#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G4_C_M 0xFF0000
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C 0x7628
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#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G5_C_M 0xFF000000
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C 0x762C
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#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G6_C_M 0xFF
|
#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C 0x762C
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#define PATH1_R_TSSI_SLOPE_CAL_GAIN_DIFF_CCK_G7_C_M 0xFF00
|
#define PATH1_R_TSSI_J_OFDM_G0_C 0x7630
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#define PATH1_R_TSSI_J_OFDM_G0_C_M 0x3FF
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#define PATH1_R_TSSI_J_OFDM_G1_C 0x7630
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#define PATH1_R_TSSI_J_OFDM_G1_C_M 0xFFC00
|
#define PATH1_R_TSSI_J_OFDM_G2_C 0x7630
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#define PATH1_R_TSSI_J_OFDM_G2_C_M 0x3FF00000
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#define PATH1_R_TSSI_J_OFDM_G3_C 0x7634
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#define PATH1_R_TSSI_J_OFDM_G3_C_M 0x3FF
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#define PATH1_R_TSSI_J_OFDM_G4_C 0x7634
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#define PATH1_R_TSSI_J_OFDM_G4_C_M 0xFFC00
|
#define PATH1_R_TSSI_J_OFDM_G5_C 0x7634
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#define PATH1_R_TSSI_J_OFDM_G5_C_M 0x3FF00000
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#define PATH1_R_TSSI_J_OFDM_G6_C 0x7638
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#define PATH1_R_TSSI_J_OFDM_G6_C_M 0x3FF
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#define PATH1_R_TSSI_J_OFDM_G7_C 0x7638
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#define PATH1_R_TSSI_J_OFDM_G7_C_M 0xFFC00
|
#define PATH1_R_TSSI_J_CCK_G0_C 0x763C
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#define PATH1_R_TSSI_J_CCK_G0_C_M 0x3FF
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#define PATH1_R_TSSI_J_CCK_G1_C 0x763C
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#define PATH1_R_TSSI_J_CCK_G1_C_M 0xFFC00
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#define PATH1_R_TSSI_J_CCK_G2_C 0x763C
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#define PATH1_R_TSSI_J_CCK_G2_C_M 0x3FF00000
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#define PATH1_R_TSSI_J_CCK_G3_C 0x7640
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#define PATH1_R_TSSI_J_CCK_G3_C_M 0x3FF
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#define PATH1_R_TSSI_J_CCK_G4_C 0x7640
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#define PATH1_R_TSSI_J_CCK_G4_C_M 0xFFC00
|
#define PATH1_R_TSSI_J_CCK_G5_C 0x7640
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#define PATH1_R_TSSI_J_CCK_G5_C_M 0x3FF00000
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#define PATH1_R_TSSI_J_CCK_G6_C 0x7644
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#define PATH1_R_TSSI_J_CCK_G6_C_M 0x3FF
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#define PATH1_R_TSSI_J_CCK_G7_C 0x7644
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#define PATH1_R_TSSI_J_CCK_G7_C_M 0xFFC00
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#define PATH1_R_TXRFC_RFMODE_FORCE_VAL_C 0x7648
|
#define PATH1_R_TXRFC_RFMODE_FORCE_VAL_C_M 0xF
|
#define PATH1_R_TXRFC_RFMODE_FORCE_ON_C 0x7648
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#define PATH1_R_TXRFC_RFMODE_FORCE_ON_C_M 0x10
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#define PATH1_R_TXRFC_TSSI_OFST_FORCE_VAL_C 0x7648
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#define PATH1_R_TXRFC_TSSI_OFST_FORCE_VAL_C_M 0x3E0
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#define PATH1_R_TXRFC_TSSI_OFST_FORCE_ON_C 0x7648
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#define PATH1_R_TXRFC_TSSI_OFST_FORCE_ON_C_M 0x400
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#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_VAL_C 0x7648
|
#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_VAL_C_M 0x800
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#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_ON_C 0x7648
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#define PATH1_R_TXRFC_TX_CCK_IND_FORCE_ON_C_M 0x1000
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#define PATH1_R_TXRFC_TXAGC_RF_FORCE_VAL_C 0x7648
|
#define PATH1_R_TXRFC_TXAGC_RF_FORCE_VAL_C_M 0x7E000
|
#define PATH1_R_TXRFC_TXAGC_RF_FORCE_ON_C 0x7648
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#define PATH1_R_TXRFC_TXAGC_RF_FORCE_ON_C_M 0x80000
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#define PATH1_R_TXRFC_GAIN_TX_FORCE_VAL_C 0x764C
|
#define PATH1_R_TXRFC_GAIN_TX_FORCE_VAL_C_M 0x1F
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#define PATH1_R_TXRFC_GAIN_TX_FORCE_ON_C 0x764C
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#define PATH1_R_TXRFC_GAIN_TX_FORCE_ON_C_M 0x20
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#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C 0x764C
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#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_VAL_C_M 0xC0
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#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C 0x764C
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#define PATH1_R_TXRFC_TX_IQK_SEL_RF_FORCE_ON_C_M 0x100
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#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C 0x764C
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#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_VAL_C_M 0x600
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#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C 0x764C
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#define PATH1_R_TXRFC_TX_PW_GAIN_RANGE_FORCE_ON_C_M 0x800
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#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C 0x764C
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#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_VAL_C_M 0xE000
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#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C 0x764C
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#define PATH1_R_TXRFC_TX_TRACK_GAIN_RANGE_FORCE_ON_C_M 0x10000
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#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_VAL_C 0x764C
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#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_VAL_C_M 0xE0000
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#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_ON_C 0x764C
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#define PATH1_R_TXRFC_TSSI_CURVE_FORCE_ON_C_M 0x100000
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#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C 0x7650
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#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_X2_C_M 0x1F
|
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_C 0x7650
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#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_C_M 0x3E0
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#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C 0x7650
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#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_2_C_M 0x7C00
|
#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C 0x7650
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#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_4_C_M 0xF8000
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#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C 0x7650
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#define PATH1_R_TSSI_CURVE_OFST_AT_HE_52_56_8_C_M 0x1F00000
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#define PATH1_R_TSSI_DCK_BY_CURVE_EN_C 0x7650
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#define PATH1_R_TSSI_DCK_BY_CURVE_EN_C_M 0x80000000
|
#define PATH1_R_TSSI_DCK_BY_CURVE_0_C 0x7654
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#define PATH1_R_TSSI_DCK_BY_CURVE_0_C_M 0xFFF
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#define PATH1_R_TSSI_DCK_BY_CURVE_1_C 0x7654
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#define PATH1_R_TSSI_DCK_BY_CURVE_1_C_M 0xFFF000
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#define PATH1_R_TSSI_DCK_BY_CURVE_2_C 0x7658
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#define PATH1_R_TSSI_DCK_BY_CURVE_2_C_M 0xFFF
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#define PATH1_R_TSSI_DCK_BY_CURVE_3_C 0x7658
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#define PATH1_R_TSSI_DCK_BY_CURVE_3_C_M 0xFFF000
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#define PATH1_R_TSSI_DCK_BY_CURVE_4_C 0x765C
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#define PATH1_R_TSSI_DCK_BY_CURVE_4_C_M 0xFFF
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#define PATH1_R_TSSI_DCK_BY_CURVE_5_C 0x765C
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#define PATH1_R_TSSI_DCK_BY_CURVE_5_C_M 0xFFF000
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#define PATH1_R_TSSI_DCK_BY_CURVE_6_C 0x7660
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#define PATH1_R_TSSI_DCK_BY_CURVE_6_C_M 0xFFF
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#define PATH1_R_TSSI_DCK_BY_CURVE_7_C 0x7660
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#define PATH1_R_TSSI_DCK_BY_CURVE_7_C_M 0xFFF000
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#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C 0x7664
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#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_0_C_M 0x7
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#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C 0x7664
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#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_1_C_M 0x38
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#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C 0x7664
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#define PATH1_R_TSSI_DCK_AT_TSSI_CURVE_EQ_2_C_M 0x1C0
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#define PATH1_R_TSSI_DCK_MOVING_AVG_LEN_C 0x7664
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#define PATH1_R_TSSI_DCK_MOVING_AVG_LEN_C_M 0x7000
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#define PATH1_R_TSSI_DCK_MOVING_AVG_CLR_C 0x7664
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#define PATH1_R_TSSI_DCK_MOVING_AVG_CLR_C_M 0x8000
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#define PATH1_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C 0x7664
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#define PATH1_R_TSSI_DCK_MOVING_AVG_RPT_SEL_C_M 0xF0000
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#define PATH1_R_TSSI_DCK_MOVING_AVG_INI_DIS_C 0x7664
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#define PATH1_R_TSSI_DCK_MOVING_AVG_INI_DIS_C_M 0x100000
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#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C 0x7668
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#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_VAL_C_M 0x1
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#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C 0x7668
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#define PATH1_R_TXRFC_EN_PAD_GAPK_FORCE_ON_C_M 0x2
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#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C 0x7668
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#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_VAL_C_M 0x4
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#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_ON_C 0x7668
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#define PATH1_R_TXRFC_EN_PA_GAPK_FORCE_ON_C_M 0x8
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#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C 0x7668
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#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_VAL_C_M 0x7F0
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#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C 0x7668
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#define PATH1_R_TXRFC_PAD_GAPK_IDX_FORCE_ON_C_M 0x800
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#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C 0x7668
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#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_VAL_C_M 0x3F000
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#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C 0x7668
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#define PATH1_R_TXRFC_PA_GAPK_IDX_FORCE_ON_C_M 0x40000
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#define PATH1_R_TSSI_TIMEOUT_TIME_C 0x766C
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#define PATH1_R_TSSI_TIMEOUT_TIME_C_M 0xFFF
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#define PATH1_R_TSSI_TIMEOUT_UNIT_C 0x766C
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#define PATH1_R_TSSI_TIMEOUT_UNIT_C_M 0x3000
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#define PATH1_R_DIS_TXAGC_RFC_SRC_FIX_C 0x7684
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#define PATH1_R_DIS_TXAGC_RFC_SRC_FIX_C_M 0x40000000
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#define PATH1_R_TXAGC_MAX_C 0x7800
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#define PATH1_R_TXAGC_MAX_C_M 0xFF
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#define PATH1_R_TXAGC_MIN_C 0x7800
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#define PATH1_R_TXAGC_MIN_C_M 0xFF00
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#define PATH1_R_TXAGC_RF_MAX_C 0x7800
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#define PATH1_R_TXAGC_RF_MAX_C_M 0x3F0000
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#define PATH1_R_TXAGC_RF_MIN_C 0x7800
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#define PATH1_R_TXAGC_RF_MIN_C_M 0xFC00000
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#define PATH1_R_DPD_OFST_EN_C 0x7800
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#define PATH1_R_DPD_OFST_EN_C_M 0x10000000
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#define PATH1_R_TXAGCSWING_EN_C 0x7800
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#define PATH1_R_TXAGCSWING_EN_C_M 0x20000000
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#define PATH1_R_DIS_CCK_SWING_TSSI_OFST_C 0x7800
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#define PATH1_R_DIS_CCK_SWING_TSSI_OFST_C_M 0x40000000
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#define PATH1_R_DIS_CCK_SWING_TXAGC_C 0x7800
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#define PATH1_R_DIS_CCK_SWING_TXAGC_C_M 0x80000000
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#define PATH1_R_TXAGC_OFDM_REF_DBM_C 0x7804
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#define PATH1_R_TXAGC_OFDM_REF_DBM_C_M 0x1FF
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#define PATH1_R_TXAGC_OFDM_REF_CW_C 0x7804
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#define PATH1_R_TXAGC_OFDM_REF_CW_C_M 0x3FE00
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#define PATH1_R_TSSI_MAP_OFST_OFDM_C 0x7804
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#define PATH1_R_TSSI_MAP_OFST_OFDM_C_M 0x7FC0000
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#define PATH1_R_DPD_OFST_C 0x7804
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#define PATH1_R_DPD_OFST_C_M 0xF8000000
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#define PATH1_R_TXAGC_CCK_REF_DBM_C 0x7808
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#define PATH1_R_TXAGC_CCK_REF_DBM_C_M 0x1FF
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#define PATH1_R_TXAGC_CCK_REF_CW_C 0x7808
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#define PATH1_R_TXAGC_CCK_REF_CW_C_M 0x3FE00
|
#define PATH1_R_TSSI_MAP_OFST_CCK_C 0x7808
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#define PATH1_R_TSSI_MAP_OFST_CCK_C_M 0x7FC0000
|
#define PATH1_R_TSSI_MAP_SLOPE_OFDM_C 0x780C
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#define PATH1_R_TSSI_MAP_SLOPE_OFDM_C_M 0x7F
|
#define PATH1_R_TSSI_MAP_SLOPE_CCK_C 0x780C
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#define PATH1_R_TSSI_MAP_SLOPE_CCK_C_M 0x7F00
|
#define PATH1_R_TXPW_FORCE_RDY_C 0x780C
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#define PATH1_R_TXPW_FORCE_RDY_C_M 0x8000
|
#define PATH1_R_TSSI_ADC_DC_OFST_RE_C 0x780C
|
#define PATH1_R_TSSI_ADC_DC_OFST_RE_C_M 0xFFF0000
|
#define PATH1_R_TSSI_PARAM_OFDM_20M_ONLY_C 0x780C
|
#define PATH1_R_TSSI_PARAM_OFDM_20M_ONLY_C_M 0x10000000
|
#define PATH1_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C 0x780C
|
#define PATH1_R_TSSI_SLOPE_CAL_PARAM_OFDM_20M_ONLY_C_M 0x20000000
|
#define PATH1_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C 0x780C
|
#define PATH1_R_TSSI_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x40000000
|
#define PATH1_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C 0x780C
|
#define PATH1_R_TSSI_SLOPE_CAL_PARAM_CCK_LONG_PPDU_ONLY_C_M 0x80000000
|
#define PATH1_R_TXAGC_PSEUDO_CW_C 0x7810
|
#define PATH1_R_TXAGC_PSEUDO_CW_C_M 0x1FF
|
#define PATH1_R_TXAGC_PSEUDO_CW_EN_C 0x7810
|
#define PATH1_R_TXAGC_PSEUDO_CW_EN_C_M 0x200
|
#define PATH1_R_TMETER_T0_C 0x7810
|
#define PATH1_R_TMETER_T0_C_M 0xFC00
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#define PATH1_R_DIS_TSSI_F_C 0x7810
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#define PATH1_R_DIS_TSSI_F_C_M 0x10000
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#define PATH1_R_TMETER_TBL_RA_C 0x7810
|
#define PATH1_R_TMETER_TBL_RA_C_M 0x7E0000
|
#define PATH1_R_TMETER_TBL_RD_C 0x7810
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#define PATH1_R_TMETER_TBL_RD_C_M 0x800000
|
#define PATH1_R_TSSI_THERMAL_PW_TRK_EN_C 0x7810
|
#define PATH1_R_TSSI_THERMAL_PW_TRK_EN_C_M 0x1000000
|
#define PATH1_R_TMETER_TBL_FORCE_WEN_C 0x7810
|
#define PATH1_R_TMETER_TBL_FORCE_WEN_C_M 0x2000000
|
#define PATH1_R_TMETER_TBL_FORCE_REN_C 0x7810
|
#define PATH1_R_TMETER_TBL_FORCE_REN_C_M 0x4000000
|
#define PATH1_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C 0x7810
|
#define PATH1_R_TSSI_DONT_RST_AT_BEGIN_OF_PKT_C_M 0x8000000
|
#define PATH1_R_TSSI_DONT_USE_UPD_ADC_C 0x7810
|
#define PATH1_R_TSSI_DONT_USE_UPD_ADC_C_M 0x10000000
|
#define PATH1_R_TSSI_BYPASS_TSSI_FORCE_OFF_C 0x7810
|
#define PATH1_R_TSSI_BYPASS_TSSI_FORCE_OFF_C_M 0x20000000
|
#define PATH1_R_TSSI_DBG_PORT_EN_C 0x7810
|
#define PATH1_R_TSSI_DBG_PORT_EN_C_M 0x40000000
|
#define PATH1_R_TSSI_DONT_BND_ALOGK_TO_POS_C 0x7810
|
#define PATH1_R_TSSI_DONT_BND_ALOGK_TO_POS_C_M 0x80000000
|
#define PATH1_R_TSSI_RF_GAP_TBL_RA_C 0x7814
|
#define PATH1_R_TSSI_RF_GAP_TBL_RA_C_M 0x3F
|
#define PATH1_R_TSSI_RF_GAP_EN_C 0x7814
|
#define PATH1_R_TSSI_RF_GAP_EN_C_M 0x40
|
#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_WEN_C 0x7814
|
#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_WEN_C_M 0x80
|
#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_REN_C 0x7814
|
#define PATH1_R_TSSI_RF_GAP_TBL_FORCE_REN_C_M 0x100
|
#define PATH1_R_TSSI_RF_GAP_TBL_RD_C 0x7814
|
#define PATH1_R_TSSI_RF_GAP_TBL_RD_C_M 0x200
|
#define PATH1_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C 0x7814
|
#define PATH1_R_TSSI_ADC_PREAMBLE_GATING_FORCE_ON_C_M 0x400
|
#define PATH1_R_TSSI_BYPASS_TSSI_C_C 0x7814
|
#define PATH1_R_TSSI_BYPASS_TSSI_C_C_M 0x800
|
#define PATH1_R_TSSI_DCK_AUTO_BYPASS_UPD_C 0x7814
|
#define PATH1_R_TSSI_DCK_AUTO_BYPASS_UPD_C_M 0x1000
|
#define PATH1_R_TSSI_DCK_AUTO_EN_C 0x7814
|
#define PATH1_R_TSSI_DCK_AUTO_EN_C_M 0x2000
|
#define PATH1_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C 0x7814
|
#define PATH1_R_TSSI_DCK_AUTO_START_AT_PHYTXON_C_M 0x4000
|
#define PATH1_R_TSSI_DCK_AUTO_AVG_POINT_C 0x7814
|
#define PATH1_R_TSSI_DCK_AUTO_AVG_POINT_C_M 0x38000
|
#define PATH1_R_TSSI_DCK_AUTO_START_DLY_C 0x7814
|
#define PATH1_R_TSSI_DCK_AUTO_START_DLY_C_M 0x3C0000
|
#define PATH1_R_TSSI_ADC_AMPLIFY_C 0x7814
|
#define PATH1_R_TSSI_ADC_AMPLIFY_C_M 0xC00000
|
#define PATH1_R_TSSI_PW_TRK_USE_025DB_C 0x7814
|
#define PATH1_R_TSSI_PW_TRK_USE_025DB_C_M 0x1000000
|
#define PATH1_R_TSSI_DCK_SEL_C 0x7814
|
#define PATH1_R_TSSI_DCK_SEL_C_M 0x18000000
|
#define PATH1_R_TSSI_TXADC_PW_SV_EN_C 0x7814
|
#define PATH1_R_TSSI_TXADC_PW_SV_EN_C_M 0x20000000
|
#define PATH1_R_TSSI_RF_GAP_DE_CMB_OPT_C 0x7814
|
#define PATH1_R_TSSI_RF_GAP_DE_CMB_OPT_C_M 0x40000000
|
#define PATH1_R_TSSI_RF_GAP_DE_OFST_EN_C 0x7814
|
#define PATH1_R_TSSI_RF_GAP_DE_OFST_EN_C_M 0x80000000
|
#define PATH1_R_TXAGC_OFST_C 0x7818
|
#define PATH1_R_TXAGC_OFST_C_M 0xFF
|
#define PATH1_R_HE_ER_STF_PW_OFST_C 0x7818
|
#define PATH1_R_HE_ER_STF_PW_OFST_C_M 0x1FF00
|
#define PATH1_R_HE_STF_PW_OFST_C 0x7818
|
#define PATH1_R_HE_STF_PW_OFST_C_M 0x3FE0000
|
#define PATH1_R_TSSI_OSCILLATION_CNT_CLR_C 0x7818
|
#define PATH1_R_TSSI_OSCILLATION_CNT_CLR_C_M 0x4000000
|
#define PATH1_R_TSSI_OFST_BY_RFC_C 0x7818
|
#define PATH1_R_TSSI_OFST_BY_RFC_C_M 0x8000000
|
#define PATH1_R_TSSI_PW_TRK_AUTO_EN_C 0x7818
|
#define PATH1_R_TSSI_PW_TRK_AUTO_EN_C_M 0x10000000
|
#define PATH1_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C 0x7818
|
#define PATH1_R_TSSI_PW_TRK_DONT_ACC_PRE_PW_C_M 0x20000000
|
#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_EN_C 0x7818
|
#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_EN_C_M 0x40000000
|
#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C 0x7818
|
#define PATH1_R_TSSI_PW_TRK_MANUAL_UPD_TRIG_C_M 0x80000000
|
#define PATH1_R_TSSI_ADC_AVG_POINT_CCK_C 0x781C
|
#define PATH1_R_TSSI_ADC_AVG_POINT_CCK_C_M 0x3FF
|
#define PATH1_R_TSSI_ADC_AVG_POINT_OFDM_C 0x781C
|
#define PATH1_R_TSSI_ADC_AVG_POINT_OFDM_C_M 0xFFC00
|
#define PATH1_R_TSSI_SLOPE_CAL_EN_C 0x781C
|
#define PATH1_R_TSSI_SLOPE_CAL_EN_C_M 0x100000
|
#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C 0x781C
|
#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_OFDM_C_M 0x1E00000
|
#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C 0x781C
|
#define PATH1_R_TSSI_ADC_SAMPLING_SHIFT_CCK_C_M 0x1E000000
|
#define PATH1_R_TSSI_ADC_NON_SQUARE_EN_C 0x781C
|
#define PATH1_R_TSSI_ADC_NON_SQUARE_EN_C_M 0x20000000
|
#define PATH1_R_TSSI_PSEUDO_TRK_MOD_EN_C 0x781C
|
#define PATH1_R_TSSI_PSEUDO_TRK_MOD_EN_C_M 0x80000000
|
#define PATH1_R_TSSI_SLOPE_A_C 0x7820
|
#define PATH1_R_TSSI_SLOPE_A_C_M 0xFFF
|
#define PATH1_R_TSSI_PKT_AVG_NUM_C 0x7820
|
#define PATH1_R_TSSI_PKT_AVG_NUM_C_M 0xF000
|
#define PATH1_R_TSSI_PW_TRK_SWING_LIM_C 0x7820
|
#define PATH1_R_TSSI_PW_TRK_SWING_LIM_C_M 0x1F0000
|
#define PATH1_R_TSSI_PW_TRK_SW_OFST_C 0x7820
|
#define PATH1_R_TSSI_PW_TRK_SW_OFST_C_M 0x1FE00000
|
#define PATH1_R_TSSI_ISEPA_C 0x7820
|
#define PATH1_R_TSSI_ISEPA_C_M 0x40000000
|
#define PATH1_R_TSSI_EN_C 0x7820
|
#define PATH1_R_TSSI_EN_C_M 0x80000000
|
#define PATH1_R_TSSI_A_OFDM_5M_C 0x7824
|
#define PATH1_R_TSSI_A_OFDM_5M_C_M 0x3FFFF
|
#define PATH1_R_TSSI_B_OFDM_5M_C 0x7824
|
#define PATH1_R_TSSI_B_OFDM_5M_C_M 0x3FFC0000
|
#define PATH1_R_TSSI_K_OFDM_5M_C 0x7828
|
#define PATH1_R_TSSI_K_OFDM_5M_C_M 0xFFF
|
#define PATH1_R_TSSI_DE_OFDM_5M_C 0x7828
|
#define PATH1_R_TSSI_DE_OFDM_5M_C_M 0x3FF000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C 0x7828
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_5M_C_M 0x7FC00000
|
#define PATH1_R_TSSI_A_OFDM_10M_C 0x782C
|
#define PATH1_R_TSSI_A_OFDM_10M_C_M 0x3FFFF
|
#define PATH1_R_TSSI_B_OFDM_10M_C 0x782C
|
#define PATH1_R_TSSI_B_OFDM_10M_C_M 0x3FFC0000
|
#define PATH1_R_TSSI_K_OFDM_10M_C 0x7830
|
#define PATH1_R_TSSI_K_OFDM_10M_C_M 0xFFF
|
#define PATH1_R_TSSI_DE_OFDM_10M_C 0x7830
|
#define PATH1_R_TSSI_DE_OFDM_10M_C_M 0x3FF000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C 0x7830
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_10M_C_M 0x7FC00000
|
#define PATH1_R_TSSI_A_OFDM_20M_C 0x7834
|
#define PATH1_R_TSSI_A_OFDM_20M_C_M 0x3FFFF
|
#define PATH1_R_TSSI_B_OFDM_20M_C 0x7834
|
#define PATH1_R_TSSI_B_OFDM_20M_C_M 0x3FFC0000
|
#define PATH1_R_TSSI_K_OFDM_20M_C 0x7838
|
#define PATH1_R_TSSI_K_OFDM_20M_C_M 0xFFF
|
#define PATH1_R_TSSI_DE_OFDM_20M_C 0x7838
|
#define PATH1_R_TSSI_DE_OFDM_20M_C_M 0x3FF000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C 0x7838
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_20M_C_M 0x7FC00000
|
#define PATH1_R_TSSI_A_OFDM_40M_C 0x783C
|
#define PATH1_R_TSSI_A_OFDM_40M_C_M 0x3FFFF
|
#define PATH1_R_TSSI_B_OFDM_40M_C 0x783C
|
#define PATH1_R_TSSI_B_OFDM_40M_C_M 0x3FFC0000
|
#define PATH1_R_TSSI_K_OFDM_40M_C 0x7840
|
#define PATH1_R_TSSI_K_OFDM_40M_C_M 0xFFF
|
#define PATH1_R_TSSI_DE_OFDM_40M_C 0x7840
|
#define PATH1_R_TSSI_DE_OFDM_40M_C_M 0x3FF000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C 0x7840
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_40M_C_M 0x7FC00000
|
#define PATH1_R_TSSI_A_OFDM_80M_C 0x7844
|
#define PATH1_R_TSSI_A_OFDM_80M_C_M 0x3FFFF
|
#define PATH1_R_TSSI_B_OFDM_80M_C 0x7844
|
#define PATH1_R_TSSI_B_OFDM_80M_C_M 0x3FFC0000
|
#define PATH1_R_TSSI_K_OFDM_80M_C 0x7848
|
#define PATH1_R_TSSI_K_OFDM_80M_C_M 0xFFF
|
#define PATH1_R_TSSI_DE_OFDM_80M_C 0x7848
|
#define PATH1_R_TSSI_DE_OFDM_80M_C_M 0x3FF000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C 0x7848
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80M_C_M 0x7FC00000
|
#define PATH1_R_TSSI_A_OFDM_80_80M_C 0x784C
|
#define PATH1_R_TSSI_A_OFDM_80_80M_C_M 0x3FFFF
|
#define PATH1_R_TSSI_B_OFDM_80_80M_C 0x784C
|
#define PATH1_R_TSSI_B_OFDM_80_80M_C_M 0x3FFC0000
|
#define PATH1_R_TSSI_K_OFDM_80_80M_C 0x7850
|
#define PATH1_R_TSSI_K_OFDM_80_80M_C_M 0xFFF
|
#define PATH1_R_TSSI_DE_OFDM_80_80M_C 0x7850
|
#define PATH1_R_TSSI_DE_OFDM_80_80M_C_M 0x3FF000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C 0x7850
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_OFDM_80_80M_C_M 0x7FC00000
|
#define PATH1_R_TSSI_A_CCK_LONG_C 0x7854
|
#define PATH1_R_TSSI_A_CCK_LONG_C_M 0x3FFFF
|
#define PATH1_R_TSSI_B_CCK_LONG_C 0x7854
|
#define PATH1_R_TSSI_B_CCK_LONG_C_M 0x3FFC0000
|
#define PATH1_R_TSSI_K_CCK_LONG_C 0x7858
|
#define PATH1_R_TSSI_K_CCK_LONG_C_M 0xFFF
|
#define PATH1_R_TSSI_DE_CCK_LONG_C 0x7858
|
#define PATH1_R_TSSI_DE_CCK_LONG_C_M 0x3FF000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C 0x7858
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_LONG_C_M 0x7FC00000
|
#define PATH1_R_TSSI_A_CCK_SHORT_C 0x785C
|
#define PATH1_R_TSSI_A_CCK_SHORT_C_M 0x3FFFF
|
#define PATH1_R_TSSI_B_CCK_SHORT_C 0x785C
|
#define PATH1_R_TSSI_B_CCK_SHORT_C_M 0x3FFC0000
|
#define PATH1_R_TSSI_K_CCK_SHORT_C 0x7860
|
#define PATH1_R_TSSI_K_CCK_SHORT_C_M 0xFFF
|
#define PATH1_R_TSSI_DE_CCK_SHORT_C 0x7860
|
#define PATH1_R_TSSI_DE_CCK_SHORT_C_M 0x3FF000
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C 0x7860
|
#define PATH1_R_TSSI_SLOPE_CAL_CW_DIFF_CCK_SHORT_C_M 0x7FC00000
|
#define PATH1_RSWING_NO_LIM_C 0x7860
|
#define PATH1_RSWING_NO_LIM_C_M 0x80000000
|
#define PATH1_R_TSSI_DELTA_CODE_MAX_C 0x7864
|
#define PATH1_R_TSSI_DELTA_CODE_MAX_C_M 0x3FF
|
#define PATH1_R_TSSI_DELTA_CODE_MIN_C 0x7864
|
#define PATH1_R_TSSI_DELTA_CODE_MIN_C_M 0xFFC00
|
#define PATH1_R_RFC_TMETER_T1_FORCE_VAL_C 0x7864
|
#define PATH1_R_RFC_TMETER_T1_FORCE_VAL_C_M 0x3F00000
|
#define PATH1_R_RFC_TMETER_T1_FORCE_ON_C 0x7864
|
#define PATH1_R_RFC_TMETER_T1_FORCE_ON_C_M 0x4000000
|
#define PATH1_R_GOTHROUGH_TX_IQKDPK_C 0x7864
|
#define PATH1_R_GOTHROUGH_TX_IQKDPK_C_M 0x8000000
|
#define PATH1_R_GOTHROUGH_RX_IQKDPK_C 0x7864
|
#define PATH1_R_GOTHROUGH_RX_IQKDPK_C_M 0x10000000
|
#define PATH1_R_IQK_IO_RFC_EN_C 0x7864
|
#define PATH1_R_IQK_IO_RFC_EN_C_M 0x20000000
|
#define PATH1_R_TX_IMFIR2_FORCE_RDY_C 0x7864
|
#define PATH1_R_TX_IMFIR2_FORCE_RDY_C_M 0x40000000
|
#define PATH1_R_CLK_GATING_TD_PATH_FORCE_ON_C 0x7864
|
#define PATH1_R_CLK_GATING_TD_PATH_FORCE_ON_C_M 0x80000000
|
#define PATH1_R_ANT_TRAIN_EN_C 0x7868
|
#define PATH1_R_ANT_TRAIN_EN_C_M 0x1
|
#define PATH1_R_TX_ANT_SEL_C 0x7868
|
#define PATH1_R_TX_ANT_SEL_C_M 0x2
|
#define PATH1_R_RFE_BUF_EN_C 0x7868
|
#define PATH1_R_RFE_BUF_EN_C_M 0x4
|
#define PATH1_R_LNAON_AGC_C 0x7868
|
#define PATH1_R_LNAON_AGC_C_M 0x8
|
#define PATH1_R_TRSW_BIT_BT_C 0x7868
|
#define PATH1_R_TRSW_BIT_BT_C_M 0x10
|
#define PATH1_R_TRSW_S_C 0x7868
|
#define PATH1_R_TRSW_S_C_M 0x20
|
#define PATH1_R_TRSW_O_C 0x7868
|
#define PATH1_R_TRSW_O_C_M 0x40
|
#define PATH1_R_TRSWB_O_C 0x7868
|
#define PATH1_R_TRSWB_O_C_M 0x80
|
#define PATH1_R_BT_FORCE_ANTIDX_C 0x7868
|
#define PATH1_R_BT_FORCE_ANTIDX_C_M 0xF00
|
#define PATH1_R_BT_FORCE_ANTIDX_EN_C 0x7868
|
#define PATH1_R_BT_FORCE_ANTIDX_EN_C_M 0x1000
|
#define PATH1_R_ANT_MODULE_RFE_OPT_C 0x7868
|
#define PATH1_R_ANT_MODULE_RFE_OPT_C_M 0xC000
|
#define PATH1_R_RFSW_TR_C 0x7868
|
#define PATH1_R_RFSW_TR_C_M 0xFFFF0000
|
#define PATH1_R_ANTSEL_C 0x786C
|
#define PATH1_R_ANTSEL_C_M 0xFFFFFFFF
|
#define PATH1_R_RFSW_ANT_31_0__C 0x7870
|
#define PATH1_R_RFSW_ANT_31_0__C_M 0xFFFFFFFF
|
#define PATH1_R_RFSW_ANT_63_32__C 0x7874
|
#define PATH1_R_RFSW_ANT_63_32__C_M 0xFFFFFFFF
|
#define PATH1_R_RFSW_ANT_95_64__C 0x7878
|
#define PATH1_R_RFSW_ANT_95_64__C_M 0xFFFFFFFF
|
#define PATH1_R_RFSW_ANT_127_96__C 0x787C
|
#define PATH1_R_RFSW_ANT_127_96__C_M 0xFFFFFFFF
|
#define PATH1_R_RFE_SEL_31_0__C 0x7880
|
#define PATH1_R_RFE_SEL_31_0__C_M 0xFFFFFFFF
|
#define PATH1_R_RFE_SEL_63_32__C 0x7884
|
#define PATH1_R_RFE_SEL_63_32__C_M 0xFFFFFFFF
|
#define PATH1_R_RFE_SEL_95_64__C 0x7888
|
#define PATH1_R_RFE_SEL_95_64__C_M 0xFFFFFFFF
|
#define PATH1_R_RFE_SEL_127_96__C 0x788C
|
#define PATH1_R_RFE_SEL_127_96__C_M 0xFFFFFFFF
|
#define PATH1_R_RFE_INV_C 0x7890
|
#define PATH1_R_RFE_INV_C_M 0xFFFFFFFF
|
#define PATH1_R_RFE_OPT_C 0x7894
|
#define PATH1_R_RFE_OPT_C_M 0xFFFFFFF
|
#define PATH1_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C 0x7894
|
#define PATH1_R_PATH_HW_ANTSW_DIS_BY_GNT_BT_C_M 0x10000000
|
#define PATH1_R_PATH_NOTRSW_BT_C 0x7894
|
#define PATH1_R_PATH_NOTRSW_BT_C_M 0x20000000
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C 0x7898
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_5M_C_M 0xFF
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C 0x7898
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_10M_C_M 0xFF00
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C 0x7898
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_20M_C_M 0xFF0000
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C 0x7898
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_40M_C_M 0xFF000000
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C 0x789C
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80M_C_M 0xFF
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C 0x789C
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_OFDM_80_80M_C_M 0xFF00
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C 0x789C
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_LONG_C_M 0xFF0000
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C 0x789C
|
#define PATH1_R_TSSI_SLOPE_GAIN_IDX_DIFF_CCK_SHORT_C_M 0xFF000000
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56_C 0x78A0
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56_C_M 0xFF
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56_2_C 0x78A0
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56_2_C_M 0xFF00
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56_4_C 0x78A0
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56_4_C_M 0xFF0000
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56_8_C 0x78A0
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56_8_C_M 0xFF000000
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56X2_C 0x78A4
|
#define PATH1_R_HE_LSTF_PW_OFST_52_56X2_C_M 0xFF
|
#define PATH1_R_TSSI_GAP_S0_C 0x78A4
|
#define PATH1_R_TSSI_GAP_S0_C_M 0x1FF00
|
#define PATH1_R_TSSI_GAP_S1_C 0x78A4
|
#define PATH1_R_TSSI_GAP_S1_C_M 0x3FE0000
|
#define PATH1_R_TSSI_GAP_S2_C 0x78A8
|
#define PATH1_R_TSSI_GAP_S2_C_M 0x1FF
|
#define PATH1_R_TSSI_GAP_S3_C 0x78A8
|
#define PATH1_R_TSSI_GAP_S3_C_M 0x3FE00
|
#define PATH1_R_TSSI_GAP_S4_C 0x78A8
|
#define PATH1_R_TSSI_GAP_S4_C_M 0x7FC0000
|
#define PATH1_R_TSSI_GAP_S5_C 0x78AC
|
#define PATH1_R_TSSI_GAP_S5_C_M 0x1FF
|
#define PATH1_R_TSSI_GAP_S6_C 0x78AC
|
#define PATH1_R_TSSI_GAP_S6_C_M 0x3FE00
|
#define PATH1_R_TSSI_GAP_S7_C 0x78AC
|
#define PATH1_R_TSSI_GAP_S7_C_M 0x7FC0000
|
#define PATH1_R_IQK_DPK_PATH_RST_C 0x78AC
|
#define PATH1_R_IQK_DPK_PATH_RST_C_M 0x8000000
|
#define PATH1_R_RX_CFIR_TAP_DEC_AT_HT_C 0x78AC
|
#define PATH1_R_RX_CFIR_TAP_DEC_AT_HT_C_M 0x10000000
|
#define PATH1_R_RX_CFIR_TAP_DEC_AT_VHT_C 0x78AC
|
#define PATH1_R_RX_CFIR_TAP_DEC_AT_VHT_C_M 0x20000000
|
#define PATH1_R_RX_CFIR_TAP_DEC_AT_HE_C 0x78AC
|
#define PATH1_R_RX_CFIR_TAP_DEC_AT_HE_C_M 0x40000000
|
#define PATH1_R_RX_CFIR_TAP_DEC_AT_CCK_C 0x78AC
|
#define PATH1_R_RX_CFIR_TAP_DEC_AT_CCK_C_M 0x80000000
|
#define PATH1_R_DAC_GAIN_COMP_TBL_RA_C 0x78B0
|
#define PATH1_R_DAC_GAIN_COMP_TBL_RA_C_M 0x7F
|
#define PATH1_R_DAC_GAIN_COMP_TBL_RD_C 0x78B0
|
#define PATH1_R_DAC_GAIN_COMP_TBL_RD_C_M 0x80
|
#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C 0x78B0
|
#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_WEN_C_M 0x100
|
#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_REN_C 0x78B0
|
#define PATH1_R_DAC_GAIN_COMP_TBL_FORCE_REN_C_M 0x200
|
#define PATH1_R_DAC_GAIN_COMP_EN_C 0x78B0
|
#define PATH1_R_DAC_GAIN_COMP_EN_C_M 0x400
|
#define PATH1_R_TSSI_CW_COMP_EN_C 0x78B0
|
#define PATH1_R_TSSI_CW_COMP_EN_C_M 0x800
|
#define PATH1_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C 0x78B0
|
#define PATH1_R_TSSI_OSCILLATION_CNT_AUTO_CLR_DIS_C_M 0x8000
|
#define PATH1_R_TSSI_OSCILLATION_HALT_TRK_TH_C 0x78B0
|
#define PATH1_R_TSSI_OSCILLATION_HALT_TRK_TH_C_M 0xFFFF0000
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#define PATH1_R_TSSI_DBG_SEL_C 0x78B4
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#define PATH1_R_TSSI_DBG_SEL_C_M 0x1F
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#define PATH1_R_GAIN_TX_IPA_FORCE_ON_C 0x78B4
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#define PATH1_R_GAIN_TX_IPA_FORCE_ON_C_M 0x20
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#define PATH1_R_GAIN_TX_IPA_FORCE_VAL_C 0x78B4
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#define PATH1_R_GAIN_TX_IPA_FORCE_VAL_C_M 0x1C0
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#define PATH1_R_TXPW_TBL_IOQ_DIS_C 0x78B4
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#define PATH1_R_TXPW_TBL_IOQ_DIS_C_M 0x200
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#define PATH1_R_RFTXEN_SAMPLING_SHIFT_C 0x78B4
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#define PATH1_R_RFTXEN_SAMPLING_SHIFT_C_M 0xF000
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#define PATH1_R_TMETER_T0_CW_C 0x78B4
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#define PATH1_R_TMETER_T0_CW_C_M 0xFF0000
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#define PATH1_R_TSSI_F_WAIT_UPD_OFDM_C 0x78B4
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#define PATH1_R_TSSI_F_WAIT_UPD_OFDM_C_M 0x7F000000
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#define PATH1_R_TSSI_F_WAIT_UPD_CCK_SHORT_C 0x78B8
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#define PATH1_R_TSSI_F_WAIT_UPD_CCK_SHORT_C_M 0x7F
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#define PATH1_R_TSSI_F_WAIT_UPD_CCK_LONG_C 0x78B8
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#define PATH1_R_TSSI_F_WAIT_UPD_CCK_LONG_C_M 0x7F00
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#define PATH1_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C 0x78B8
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#define PATH1_R_TSSI_CCK_LONG_ADC_SAMPLING_SHIFT_C_M 0x7F0000
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#define PATH1_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C 0x78B8
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#define PATH1_R_TSSI_CCK_SHORT_ADC_SAMPLING_SHIFT_C_M 0x7F000000
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#define PATH1_R_TXAGC_OFST_MAX_C 0x78BC
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#define PATH1_R_TXAGC_OFST_MAX_C_M 0xFF
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#define PATH1_R_TXAGC_OFST_MIN_C 0x78BC
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#define PATH1_R_TXAGC_OFST_MIN_C_M 0xFF00
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#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_C_M 0x10000
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#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_LTE_RX_EQ_VAL_C_M 0x20000
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#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_C_M 0x40000
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#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_GNT_WL_EQ_VAL_C_M 0x80000
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#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_C_M 0x100000
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#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_EQ_VAL_C_M 0x200000
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#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_C_M 0x400000
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#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_GNT_BT_TX_EQ_VAL_C_M 0x800000
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#define PATH1_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_FTM_A2A_AFELBK_EQ1_C_M 0x1000000
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#define PATH1_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_FTM_LBK_EQ1_C_M 0x2000000
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#define PATH1_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C 0x78BC
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#define PATH1_R_TSSI_BYPASS_AT_FTM_RFLBK_EQ1_C_M 0x4000000
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#define PATH1_R_GAIN_TX_GAPK_FORCE_VAL_C 0x78C0
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#define PATH1_R_GAIN_TX_GAPK_FORCE_VAL_C_M 0xF
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#define PATH1_R_GAIN_TX_GAPK_FORCE_ON_C 0x78C0
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#define PATH1_R_GAIN_TX_GAPK_FORCE_ON_C_M 0x10
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#define PATH1_R_GAIN_TX_PAD_FORCE_VAL_C 0x78C0
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#define PATH1_R_GAIN_TX_PAD_FORCE_VAL_C_M 0x3E0
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#define PATH1_R_GAIN_TX_PAD_FORCE_ON_C 0x78C0
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#define PATH1_R_GAIN_TX_PAD_FORCE_ON_C_M 0x400
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#define PATH1_R_GAIN_TX_FORCE_VAL_C 0x78C0
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#define PATH1_R_GAIN_TX_FORCE_VAL_C_M 0xF800
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#define PATH1_R_GAIN_TX_FORCE_ON_C 0x78C0
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#define PATH1_R_GAIN_TX_FORCE_ON_C_M 0x10000
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#define PATH1_R_TSSISWING_LIM_PEAK_OFDM_C 0x78C0
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#define PATH1_R_TSSISWING_LIM_PEAK_OFDM_C_M 0xE0000
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#define PATH1_R_TSSISWING_LIM_PEAK_CCK_C 0x78C0
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#define PATH1_R_TSSISWING_LIM_PEAK_CCK_C_M 0x700000
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#define PATH1_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C 0x78C0
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#define PATH1_R_CLR_TXAGC_OFST_IF_VAL_CHANGE_EN_C_M 0x800000
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#define PATH1_R_TSSI_TRACK_AT_SMALL_SWING_C 0x78C0
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#define PATH1_R_TSSI_TRACK_AT_SMALL_SWING_C_M 0x1000000
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#define PATH1_R_BYPASS_TSSI_CCK_EN_C 0x78C0
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#define PATH1_R_BYPASS_TSSI_CCK_EN_C_M 0x2000000
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#define PATH1_R_BYPASS_TSSI_LEGACY_EN_C 0x78C0
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#define PATH1_R_BYPASS_TSSI_LEGACY_EN_C_M 0x4000000
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#define PATH1_R_BYPASS_TSSI_HT_EN_C 0x78C0
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#define PATH1_R_BYPASS_TSSI_HT_EN_C_M 0x8000000
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#define PATH1_R_BYPASS_TSSI_VHT_EN_C 0x78C0
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#define PATH1_R_BYPASS_TSSI_VHT_EN_C_M 0x10000000
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#define PATH1_R_BYPASS_TSSI_HE_EN_C 0x78C0
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#define PATH1_R_BYPASS_TSSI_HE_EN_C_M 0x20000000
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#define PATH1_R_BYPASS_TSSI_HE_ER_SU_EN_C 0x78C0
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#define PATH1_R_BYPASS_TSSI_HE_ER_SU_EN_C_M 0x40000000
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#define PATH1_R_BYPASS_TSSI_HE_TB_EN_C 0x78C0
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#define PATH1_R_BYPASS_TSSI_HE_TB_EN_C_M 0x80000000
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#define PATH1_R_RF_GAP_CAL_BND0_C 0x78C4
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#define PATH1_R_RF_GAP_CAL_BND0_C_M 0x3F
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#define PATH1_R_RF_GAP_CAL_BND1_C 0x78C4
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#define PATH1_R_RF_GAP_CAL_BND1_C_M 0xFC0
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#define PATH1_R_RF_GAP_CAL_BND2_C 0x78C4
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#define PATH1_R_RF_GAP_CAL_BND2_C_M 0x3F000
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#define PATH1_R_TSSI_ADC_OFST_BND01_C 0x78C4
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#define PATH1_R_TSSI_ADC_OFST_BND01_C_M 0x3FFC0000
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#define PATH1_R_TSSI_RF_GAP_BY_RANGE_EN_C 0x78C4
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#define PATH1_R_TSSI_RF_GAP_BY_RANGE_EN_C_M 0x40000000
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#define PATH1_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C 0x78C4
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#define PATH1_R_TSSI_RF_GAP_BY_RANGE_DCK_EN_C_M 0x80000000
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#define PATH1_R_TSSI_ADC_OFST_BND12_C 0x78C8
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#define PATH1_R_TSSI_ADC_OFST_BND12_C_M 0xFFF
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#define PATH1_R_TSSI_ADC_OFST_BND22_C 0x78C8
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#define PATH1_R_TSSI_ADC_OFST_BND22_C_M 0xFFF000
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#define PATH1_R_ADC_FIFO_PATH_EN_FORCE_ON_C 0x78C8
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#define PATH1_R_ADC_FIFO_PATH_EN_FORCE_ON_C_M 0x1000000
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#define PATH1_R_TXINFO_CH_WITH_DATA_DECODE_C 0x78C8
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#define PATH1_R_TXINFO_CH_WITH_DATA_DECODE_C_M 0x6000000
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#define PATH1_R_BYPASS_TSSI_VHT_MU_EN_C 0x78C8
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#define PATH1_R_BYPASS_TSSI_VHT_MU_EN_C_M 0x10000000
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#define PATH1_R_BYPASS_TSSI_HE_MU_EN_C 0x78C8
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#define PATH1_R_BYPASS_TSSI_HE_MU_EN_C_M 0x20000000
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#define PATH1_R_BYPASS_TSSI_HE_RU_EN_C 0x78C8
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#define PATH1_R_BYPASS_TSSI_HE_RU_EN_C_M 0x40000000
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#define PATH1_R_BYPASS_TSSI_TXBF_EN_C 0x78C8
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#define PATH1_R_BYPASS_TSSI_TXBF_EN_C_M 0x80000000
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#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL0_C 0x78CC
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#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL0_C_M 0x7
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#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL1_C 0x78CC
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#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL1_C_M 0x38
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#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL2_C 0x78CC
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#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL2_C_M 0x1C0
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#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL3_C 0x78CC
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#define PATH1_R_TSSI_SLOPE_CAL_PA_SEL3_C_M 0xE00
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#define PATH1_R_TSSI_SLOPE_CAL_SEL_IPA_C 0x78CC
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#define PATH1_R_TSSI_SLOPE_CAL_SEL_IPA_C_M 0x1000
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#define PATH1_R_TX_GAIN_CCK_MORE_ADJ_C 0x78CC
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#define PATH1_R_TX_GAIN_CCK_MORE_ADJ_C_M 0xFF000000
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#define PATH1_R_TX_GAIN_SCALE_FORCE_VAL_C 0x78D0
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#define PATH1_R_TX_GAIN_SCALE_FORCE_VAL_C_M 0xFFF
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#define PATH1_R_TX_GAIN_SCALE_FORCE_ON_C 0x78D0
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#define PATH1_R_TX_GAIN_SCALE_FORCE_ON_C_M 0x1000
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#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_C 0x78D0
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#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_C_M 0x1E000
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#define PATH1_R_TX_LSTF_PW_EST_LEN_C 0x78D0
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#define PATH1_R_TX_LSTF_PW_EST_LEN_C_M 0x3FE0000
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#define PATH1_R_TX_LSTF_PW_EST_SEL_EVEN_C 0x78D0
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#define PATH1_R_TX_LSTF_PW_EST_SEL_EVEN_C_M 0x4000000
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#define PATH1_R_TSSI_C_MAP_UNFIX_C 0x78D0
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#define PATH1_R_TSSI_C_MAP_UNFIX_C_M 0x80000000
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#define PATH1_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C 0x78D4
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#define PATH1_R_BYPASS_TSSI_HE_TB_CH_WITH_DATA_C_M 0xFF
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#define PATH1_R_TSSI_BYPASS_TXPW_MAX_C 0x78D4
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#define PATH1_R_TSSI_BYPASS_TXPW_MAX_C_M 0x3FE00
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#define PATH1_R_TSSI_BYPASS_TXPW_MIN_C 0x78D4
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#define PATH1_R_TSSI_BYPASS_TXPW_MIN_C_M 0x7FC0000
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#define PATH1_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C 0x78D4
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#define PATH1_R_DELTA_TSSI_TOP_GCK_FORCE_ON_C_M 0x8000000
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#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C 0x78D4
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#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_PRE_C_M 0x10000000
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#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_POST_C 0x78D4
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#define PATH1_R_TX_GAIN_SPLIT_FOR_DPD_POST_C_M 0x20000000
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#define PATH1_R_TXPW_SPLIT_FOR_DPD_C 0x78D4
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#define PATH1_R_TXPW_SPLIT_FOR_DPD_C_M 0x40000000
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#define PATH1_R_TXAGC_TP_MASK_EN_C 0x78D4
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#define PATH1_R_TXAGC_TP_MASK_EN_C_M 0x80000000
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#define PATH1_R_TSSI_BYPASS_BY_C_MAX_C 0x78D8
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#define PATH1_R_TSSI_BYPASS_BY_C_MAX_C_M 0x1FF
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#define PATH1_R_TSSI_BYPASS_BY_C_MIN_C 0x78D8
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#define PATH1_R_TSSI_BYPASS_BY_C_MIN_C_M 0x3FE00
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#define PATH1_R_TSSI_BYPASS_BY_C_SEL_C 0x78D8
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#define PATH1_R_TSSI_BYPASS_BY_C_SEL_C_M 0xC0000
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#define PATH1_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C 0x78D8
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#define PATH1_R_TSSI_BYPASS_AVG_R_SMALLER_THAN_TH_C_M 0xFFF00000
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#define PATH1_R_TXAGC_OFST_FIX_ERR_MAX_C 0x78DC
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#define PATH1_R_TXAGC_OFST_FIX_ERR_MAX_C_M 0xFF
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#define PATH1_R_TXAGC_OFST_FIX_ERR_MIN_C 0x78DC
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#define PATH1_R_TXAGC_OFST_FIX_ERR_MIN_C_M 0xFF00
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#define PATH1_R_TXAGC_OFST_FIX_C 0x78DC
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#define PATH1_R_TXAGC_OFST_FIX_C_M 0x10000
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#define PATH1_R_TSSI_C_FORCE_VAL_C 0x78DC
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#define PATH1_R_TSSI_C_FORCE_VAL_C_M 0x1FF00000
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#define PATH1_R_TSSI_C_FORCE_ON_C 0x78DC
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#define PATH1_R_TSSI_C_FORCE_ON_C_M 0x20000000
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#define PATH1_R_TXPW_RSTB_MAN_ON_C 0x78DC
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#define PATH1_R_TXPW_RSTB_MAN_ON_C_M 0x40000000
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#define PATH1_R_TXPW_RSTB_MAN_C 0x78DC
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#define PATH1_R_TXPW_RSTB_MAN_C_M 0x80000000
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#define PATH1_R_TXAGC_OFDM_REF_CW_OFST_C 0x78E0
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#define PATH1_R_TXAGC_OFDM_REF_CW_OFST_C_M 0x3FF
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#define PATH1_R_TXAGC_CCK_REF_CW_OFST_C 0x78E0
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#define PATH1_R_TXAGC_CCK_REF_CW_OFST_C_M 0x3FF000
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#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C 0x78E0
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#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_C_M 0x7F000000
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#define PATH1_R_TXPW_RDY_NO_DLY_C 0x78E0
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#define PATH1_R_TXPW_RDY_NO_DLY_C_M 0x80000000
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#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C 0x78E4
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#define PATH1_R_TSSI_OFDM_ADC_SAMPLING_SHIFT_HE_TB_C_M 0x7F
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#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C 0x78E4
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#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_ON_C_M 0x80
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#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C 0x78E4
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#define PATH1_R_FORCE_RFC_PREAMLE_PW_TYPE_VAL_C_M 0x700
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#define PATH1_R_TXAGC_OFST_MOVING_AVG_LEN_C 0x78E4
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#define PATH1_R_TXAGC_OFST_MOVING_AVG_LEN_C_M 0x3800
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#define PATH1_R_TXAGC_OFST_MOVING_AVG_CLR_C 0x78E4
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#define PATH1_R_TXAGC_OFST_MOVING_AVG_CLR_C_M 0x4000
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#define PATH1_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C 0x78E4
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#define PATH1_R_TXAGC_OFST_MOVING_AVG_INI_DIS_C_M 0x8000
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#define PATH1_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C 0x78E4
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#define PATH1_R_TXAGC_OFST_MOVING_AVG_RPT_SEL_C_M 0xF0000
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#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C 0x78E4
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#define PATH1_R_TX_LSTF_PW_EST_STARTING_SHIFT_MORE_C_M 0x7F00000
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#define PATH1_R_TXPW_RSTB_SUB_SEL_C 0x78E4
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#define PATH1_R_TXPW_RSTB_SUB_SEL_C_M 0x8000000
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#define PATH1_R_TXPW_RSTB_SUB_C 0x78E4
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#define PATH1_R_TXPW_RSTB_SUB_C_M 0x10000000
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#define PATH1_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C 0x78E4
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#define PATH1_R_BYPASS_TSSI_RST_DAC_FIFO_SEL_EN_C_M 0x20000000
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#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MAX_C 0x78F0
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#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MAX_C_M 0x1FF
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#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MIN_C 0x78F0
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#define PATH1_R_TSSI_BYPASS_FINAL_CODE_MIN_C_M 0x3FE00
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#define PATH1_R_GOTHROUGH_TX_GAIN_POST_DPD_C 0x78F0
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#define PATH1_R_GOTHROUGH_TX_GAIN_POST_DPD_C_M 0x40000
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#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C 0x78F0
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#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_ON_C_M 0x80000
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#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C 0x78F0
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#define PATH1_R_TX_GAIN_SCALE_POST_DPD_FORCE_VAL_C_M 0xFFF00000
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#define PATH1_R_RF_GAP_CAL_OFST_BND00_10BITS_C 0x78F4
|
#define PATH1_R_RF_GAP_CAL_OFST_BND00_10BITS_C_M 0x3FF
|
#define PATH1_R_RF_GAP_CAL_OFST_BND01_10BITS_C 0x78F4
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#define PATH1_R_RF_GAP_CAL_OFST_BND01_10BITS_C_M 0xFFC00
|
#define PATH1_R_RF_GAP_CAL_OFST_BND12_10BITS_C 0x78F4
|
#define PATH1_R_RF_GAP_CAL_OFST_BND12_10BITS_C_M 0x3FF00000
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#define PATH1_R_RF_GAP_CAL_OFST_BND22_10BITS_C 0x78F8
|
#define PATH1_R_RF_GAP_CAL_OFST_BND22_10BITS_C_M 0x3FF
|
#define PATH1_R_LOG_VAL_OFST_CCK_C 0x78F8
|
#define PATH1_R_LOG_VAL_OFST_CCK_C_M 0x3FFFFC00
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#define PATH1_R_TSSI_ADC_PATH_Q_C 0x78F8
|
#define PATH1_R_TSSI_ADC_PATH_Q_C_M 0x40000000
|
#define PATH1_R_DAC_COMP_POST_DPD_EN_C 0x78F8
|
#define PATH1_R_DAC_COMP_POST_DPD_EN_C_M 0x80000000
|
#define PATH1_R_LOG_VAL_OFST_OFDM_C 0x78FC
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#define PATH1_R_LOG_VAL_OFST_OFDM_C_M 0xFFFFF
|
#define PATH1_R_UPD_TXAGC_OFST_LATENCY_C 0x78FC
|
#define PATH1_R_UPD_TXAGC_OFST_LATENCY_C_M 0x700000
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#define PATH1_R_TSSI_UPD_TMETER_EN_C 0x78FC
|
#define PATH1_R_TSSI_UPD_TMETER_EN_C_M 0x800000
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#define PATH1_R_TXRFC_BW_TXFORCE_VAL_C 0x78FC
|
#define PATH1_R_TXRFC_BW_TXFORCE_VAL_C_M 0x3000000
|
#define PATH1_R_TXRFC_BW_TXFORCE_ON_C 0x78FC
|
#define PATH1_R_TXRFC_BW_TXFORCE_ON_C_M 0x4000000
|
#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_ON_C 0x78FC
|
#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_ON_C_M 0x8000000
|
#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_VAL_C 0x78FC
|
#define PATH1_R_TXRFC_DAC_0P5DB_FORCE_VAL_C_M 0x10000000
|
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C 0x7A00
|
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_20_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C 0x7A00
|
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_20_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C 0x7A04
|
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC0_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C 0x7A04
|
#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC0_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C 0x7A08
|
#define PATH1_R_DAC_GAIN_COMP_CCK_SHORT_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C 0x7A08
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#define PATH1_R_DAC_GAIN_COMP_CCK_LONG_PPDU_TYPE_40_TXSC1_2_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C 0x7A0C
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_20_TXSC0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C 0x7A0C
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_40_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C 0x7A10
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_40_TXSC1_2_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C 0x7A10
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C 0x7A14
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC1_2_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C 0x7A14
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_80_TXSC3_4_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C 0x7A18
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#define PATH1_R_DAC_GAIN_COMP_LEGACY_DUP_80_TXSC9_10_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C 0x7A18
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_20_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C 0x7A1C
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C 0x7A1C
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_40_TXSC1_2_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C 0x7A20
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC3_4_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C 0x7A20
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#define PATH1_R_DAC_GAIN_COMP_HT_VHT_80_TXSC9_10_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_TXSC0_C 0x7A24
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_TXSC0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C 0x7A24
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C 0x7A28
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC1_2_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C 0x7A28
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC3_4_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C 0x7A2C
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC5_6_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C 0x7A2C
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC7_8_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C 0x7A30
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC9_10_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C 0x7A30
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC11_12_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C 0x7A34
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#define PATH1_R_DAC_GAIN_COMP_VHT_80_80_TXSC13_14_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C 0x7A34
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_20_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C 0x7A38
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C 0x7A38
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_40_TXSC1_2_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C 0x7A3C
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC1_2_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C 0x7A3C
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC3_4_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C 0x7A40
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC9_10_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C 0x7A40
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C 0x7A44
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C 0x7A44
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC1_2_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C 0x7A48
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC3_4_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C 0x7A48
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC5_6_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C 0x7A4C
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC7_8_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C 0x7A4C
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC9_10_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C 0x7A50
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC11_12_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C 0x7A50
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#define PATH1_R_DAC_GAIN_COMP_HE_SU_80_80_TXSC13_14_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C 0x7A54
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_20_TXSC0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C 0x7A54
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C 0x7A58
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_40_TXSC1_2_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C 0x7A58
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC1_2_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C 0x7A5C
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC3_4_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C 0x7A5C
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC9_10_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C 0x7A60
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_TXSC0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C 0x7A60
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C 0x7A64
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC1_2_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C 0x7A64
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC3_4_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C 0x7A68
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC5_6_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C 0x7A68
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC7_8_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C 0x7A6C
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC9_10_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C 0x7A6C
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC11_12_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C 0x7A70
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#define PATH1_R_DAC_GAIN_COMP_HE_ER_SU_80_80_TXSC13_14_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C 0x7A70
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_20_DBW20_TXSC0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C 0x7A74
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_C0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C 0x7A74
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW40_TXSC0_TCD_80_40_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C 0x7A78
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_40_DBW20_TXSC1_2_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C 0x7A78
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC1_2_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C 0x7A7C
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW20_TXSC3_4_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C 0x7A7C
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C 0x7A80
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C 0x7A80
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C 0x7A84
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_F0_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C 0x7A84
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_80_10_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C 0x7A88
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_40_20_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C 0x7A88
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_60_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C 0x7A8C
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_DBW80_TXSC0_TCD_C0_30_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C 0x7A8C
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC1_2_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C 0x7A90
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC3_4_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C 0x7A90
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC5_6_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C 0x7A94
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW20_TXSC7_8_C_M 0xFFFF
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C 0x7A94
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_C0_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C 0x7A98
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_80_40_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C 0x7A98
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC9_10_TCD_40_80_C_M 0xFFFF0000
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C 0x7A9C
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#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_C0_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C 0x7A9C
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_80_40_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C 0x7AA0
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW40_TXSC11_12_TCD_40_80_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C 0x7AA0
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_80_10_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C 0x7AA4
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_10_80_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C 0x7AA4
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_40_20_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C 0x7AA8
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_20_40_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C 0x7AA8
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_60_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C 0x7AAC
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_C0_30_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C 0x7AAC
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_TXSC13_14_TCD_30_C0_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C 0x7AB0
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_80_01_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C 0x7AB0
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_60_06_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C 0x7AB4
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_40_02_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C 0x7AB4
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_20_04_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C 0x7AB8
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_10_08_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C 0x7AB8
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_C0_03_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C 0x7ABC
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_30_0C_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C 0x7ABC
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_F0_0F_C_M 0xFFFF0000
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C 0x7AC0
|
#define PATH1_R_DAC_GAIN_COMP_HE_TB_80_80_DBW80_80_TXSC0_TCD_FF_C_M 0xFFFF
|
#define PATH1_R_DAC_GAIN_COMP_UNEXPECTED_C 0x7AC0
|
#define PATH1_R_DAC_GAIN_COMP_UNEXPECTED_C_M 0xFFFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS0_C 0x7C00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS0_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS1_C 0x7C00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS1_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS2_C 0x7C00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS2_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS3_C 0x7C00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS3_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS4_C 0x7C04
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS4_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS5_C 0x7C04
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS5_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS6_C 0x7C04
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS6_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS7_C 0x7C04
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS7_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS8_C 0x7C08
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS8_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS9_C 0x7C08
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS9_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS10_C 0x7C08
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS10_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS11_C 0x7C08
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS11_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS12_C 0x7C0C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS12_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS13_C 0x7C0C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS13_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS14_C 0x7C0C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS14_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS15_C 0x7C0C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS15_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS16_C 0x7C10
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS16_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS17_C 0x7C10
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS17_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS18_C 0x7C10
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS18_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS19_C 0x7C10
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS19_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS20_C 0x7C14
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS20_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS21_C 0x7C14
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS21_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS22_C 0x7C14
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS22_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS23_C 0x7C14
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS23_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS24_C 0x7C18
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS24_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS25_C 0x7C18
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS25_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS26_C 0x7C18
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS26_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS27_C 0x7C18
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS27_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS28_C 0x7C1C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS28_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS29_C 0x7C1C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS29_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS30_C 0x7C1C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS30_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS31_C 0x7C1C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_POS31_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG32_C 0x7C20
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG32_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG31_C 0x7C20
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG31_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG30_C 0x7C20
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG30_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG29_C 0x7C20
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG29_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG28_C 0x7C24
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG28_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG27_C 0x7C24
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG27_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG26_C 0x7C24
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG26_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG25_C 0x7C24
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG25_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG24_C 0x7C28
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG24_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG23_C 0x7C28
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG23_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG22_C 0x7C28
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG22_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG21_C 0x7C28
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG21_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG20_C 0x7C2C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG20_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG19_C 0x7C2C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG19_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG18_C 0x7C2C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG18_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG17_C 0x7C2C
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG17_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG16_C 0x7C30
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG16_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG15_C 0x7C30
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG15_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG14_C 0x7C30
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG14_C_M 0xFF0000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG13_C 0x7C30
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG13_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG12_C 0x7C34
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG12_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG11_C 0x7C34
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG11_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG10_C 0x7C34
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG10_C_M 0xFF0000
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG9_C 0x7C34
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG9_C_M 0xFF000000
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG8_C 0x7C38
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG8_C_M 0xFF
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG7_C 0x7C38
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG7_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG6_C 0x7C38
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG6_C_M 0xFF0000
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG5_C 0x7C38
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG5_C_M 0xFF000000
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG4_C 0x7C3C
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG4_C_M 0xFF
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG3_C 0x7C3C
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG3_C_M 0xFF00
|
#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG2_C 0x7C3C
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG2_C_M 0xFF0000
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG1_C 0x7C3C
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#define PATH1_R_TSSI_OFST_TMETER_T0_T1_NEG1_C_M 0xFF000000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_0_C 0x7C40
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_0_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_1_C 0x7C40
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_1_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_2_C 0x7C44
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_2_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_3_C 0x7C44
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_3_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_4_C 0x7C48
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_4_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_5_C 0x7C48
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_5_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_6_C 0x7C4C
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_6_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_7_C 0x7C4C
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_7_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_8_C 0x7C50
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_8_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_9_C 0x7C50
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_9_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_10_C 0x7C54
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_10_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_11_C 0x7C54
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_11_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_12_C 0x7C58
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_12_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_13_C 0x7C58
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_13_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_14_C 0x7C5C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_14_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_15_C 0x7C5C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_15_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_16_C 0x7C60
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_16_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_17_C 0x7C60
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_17_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_18_C 0x7C64
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_18_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_19_C 0x7C64
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_19_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_20_C 0x7C68
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_20_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_21_C 0x7C68
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_21_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_22_C 0x7C6C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_22_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_23_C 0x7C6C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_23_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_24_C 0x7C70
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_24_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_25_C 0x7C70
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_25_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_26_C 0x7C74
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_26_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_27_C 0x7C74
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_27_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_28_C 0x7C78
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_28_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_29_C 0x7C78
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_29_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_30_C 0x7C7C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_30_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_31_C 0x7C7C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_31_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_32_C 0x7C80
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_32_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_33_C 0x7C80
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_33_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_34_C 0x7C84
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_34_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_35_C 0x7C84
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_35_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_36_C 0x7C88
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_36_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_37_C 0x7C88
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_37_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_38_C 0x7C8C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_38_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_39_C 0x7C8C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_39_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_40_C 0x7C90
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_40_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_41_C 0x7C90
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_41_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_42_C 0x7C94
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_42_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_43_C 0x7C94
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_43_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_44_C 0x7C98
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_44_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_45_C 0x7C98
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_45_C_M 0x3FF0000
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_46_C 0x7C9C
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_46_C_M 0x3FF
|
#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_47_C 0x7C9C
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_47_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_48_C 0x7CA0
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_48_C_M 0x3FF
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_49_C 0x7CA0
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_49_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_50_C 0x7CA4
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_50_C_M 0x3FF
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_51_C 0x7CA4
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_51_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_52_C 0x7CA8
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_52_C_M 0x3FF
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_53_C 0x7CA8
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_53_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_54_C 0x7CAC
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_54_C_M 0x3FF
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_55_C 0x7CAC
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_55_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_56_C 0x7CB0
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_56_C_M 0x3FF
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_57_C 0x7CB0
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_57_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_58_C 0x7CB4
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_58_C_M 0x3FF
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_59_C 0x7CB4
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_59_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_60_C 0x7CB8
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_60_C_M 0x3FF
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_61_C 0x7CB8
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_61_C_M 0x3FF0000
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_62_C 0x7CBC
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_62_C_M 0x3FF
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_63_C 0x7CBC
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#define PATH1_R_TSSI_OFST_RF_GAIN_IDX_63_C_M 0x3FF0000
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#define FPGA_DC_OFST_0_C 0xC000
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#define FPGA_DC_OFST_0_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_1_C 0xC004
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#define FPGA_DC_OFST_1_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_2_C 0xC008
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#define FPGA_DC_OFST_2_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_3_C 0xC00C
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#define FPGA_DC_OFST_3_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_4_C 0xC010
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#define FPGA_DC_OFST_4_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_5_C 0xC014
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#define FPGA_DC_OFST_5_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_6_C 0xC018
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#define FPGA_DC_OFST_6_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_7_C 0xC01C
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#define FPGA_DC_OFST_7_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_8_C 0xC020
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#define FPGA_DC_OFST_8_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_9_C 0xC024
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#define FPGA_DC_OFST_9_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_10_C 0xC028
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#define FPGA_DC_OFST_10_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_11_C 0xC02C
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#define FPGA_DC_OFST_11_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_12_C 0xC030
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#define FPGA_DC_OFST_12_C_M 0xFFFFFFFF
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#define FPGA_DC_OFST_13_C 0xC034
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#define FPGA_DC_OFST_13_C_M 0xFFFFFFFF
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#define INV_TIASHRINK_C 0xC038
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#define INV_TIASHRINK_C_M 0x1
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#endif
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