/** @file */
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/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#ifndef _MAC_AX_TRXCFG_H_
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#define _MAC_AX_TRXCFG_H_
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#include "../type.h"
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#include "hw.h"
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#include "init.h"
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#include "role.h"
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#include "cmac_tx.h"
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#include "rx_filter.h"
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#include "dle.h"
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#include "hci_fc.h"
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#include "mport.h"
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#include "spatial_reuse.h"
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/*--------------------Define -------------------------------------------*/
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#define TRXCFG_WAIT_CNT 2000
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#define TRXCFG_WAIT_US 1
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/* MPDU Processor Control */
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#define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
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#define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
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#define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0
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/* RMAC timeout control */
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#if (MAC_AX_8852C_SUPPORT) && defined(PHL_FEATURE_AP)
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#define TRXCFG_RMAC_CCA_TO 128
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#else
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#define TRXCFG_RMAC_CCA_TO 32
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#endif
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#define TRXCFG_RMAC_DATA_TO 15
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#define S_AX_TXSC_20M_0 0
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#define S_AX_TXSC_20M_4 4
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#define S_AX_TXSC_40M_0 0
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#define S_AX_TXSC_40M_4 4
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#define S_AX_TXSC_80M_0 0
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#define S_AX_TXSC_80M_4 4
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#define RRSR_OFDM_CCK_EN 3
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/* TRXPTCL SIFS TIME*/
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#define WMAC_SPEC_SIFS_OFDM_52A 0x15
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#define WMAC_SPEC_SIFS_OFDM_52B 0x11
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#define WMAC_SPEC_SIFS_OFDM_52C 0x11
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#define WMAC_SPEC_SIFS_OFDM_51B 0x11
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#define WMAC_SPEC_SIFS_OFDM_52BT 0x11
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#define WMAC_SPEC_SIFS_CCK 0xA
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/* RRSR disable 5.5M CCK*/
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#define WMAC_CCK_EN_1M 0x1
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#define WMAC_RRSR_RATE_LEGACY_EN 0x1
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/* SRAM fifo address */
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#define CMAC_TBL_BASE_ADDR 0x18840000
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#define CMAC1_START_ADDR 0xE000
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#define CMAC1_END_ADDR 0xFFFF
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#if MAC_AX_ASIC_TEMP
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#define R_AX_LTECOEX_CTRL 0x38
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#define R_AX_LTECOEX_CTRL_2 0x3C
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#endif
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#define S_AX_CTS2S_TH_1K 4
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#define S_AX_CTS2S_TH_SEC_256B 1
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#define S_AX_PTCL_TO_2MS 0x3F
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#define LBK_PLCP_DLY_DEF 0x28
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#define LBK_PLCP_DLY_FPGA 0x46
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#define PLD_RLS_MAX_PG 127
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#define RX_MAX_LEN_UNIT 512
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/* if spec max len is not align to rx max len unit, add 1 unit */
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#define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
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#define SCH_PREBKF_24US 0x18
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#define SCH_PREBKF_16US 0x10
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#define BCN_IFS_25US 0x19
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#define SIFS_MACTXEN_T1_V0 0x47
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#define SIFS_MACTXEN_T1_V1 0x40
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#define SIFS_MACTXEN_T1_V2 0x3E
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#define SDIO_DRV_INFO_SIZE 2
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#define DMA_MOD_PCIE_1B 0x0
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#define DMA_MOD_PCIE_4B 0x1
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#define DMA_MOD_USB 0x2
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#define DMA_MOD_SDIO 0x3
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#define NAV_12MS 0x5D // (12ms, unit: 128us)
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#define NAV_25MS 0xC4 // (25ms, unit: 128us)
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#define FWD_TO_HOST 0
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#define FWD_TO_WLCPU 1
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#define FWD_TO_DATACPU 2
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#define AMPDU_MAX_LEN_VHT_262K 0x3FF80
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#define SS2F_PATH_WLCPU 0x0A
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#define NAV_UPPER_DEFAULT 0
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#define TCR_UDF_THSD 0x6
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#define TXDFIFO_HIGH_MCS_THRE 0x7
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#define TXDFIFO_LOW_MCS_THRE 0x7
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#define B_AX_TX_TO 0x2
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#define DRVINFO_PATCH_SIZE 0x5
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/* response reference rate */
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#define REF2RXRATEANDCCTBL 0
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#define REF2RXRATEONLY 1
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/*The number of STA in UL SS2FRPT*/
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#define MAX_ULSS2F_SU_STA_NUM 0x3
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#define MAX_ULSS2F_TWT_STA_NUM 0x3
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#define MAX_ULSS2F_RU_STA_NUM 0x3
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/*The number of STA in DL SS2FRPT*/
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#define MAX_DLSS2F_SU_STA_NUM 0xF
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#define MAX_DLSS2F_MU_STA_NUM 0xF
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#define MAX_DLSS2F_RU_STA_NUM 0xF
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/*The bsr len threshold of UL SS2FRPT*/
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#define UL_NORMAL_SS2FWRPT_BSR_THRES 0x50
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#define UL_LATCY_SS2FWRPT_BSR_THRES 0x1
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/*--------------------Define MACRO--------------------------------------*/
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#define RX_FULL_MODE (B_AX_RU0_PTR_FULL_MODE | B_AX_RU1_PTR_FULL_MODE | \
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B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | \
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B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE)
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/*--------------------Define Enum---------------------------------------*/
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/*--------------------Define Struct-------------------------------------*/
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/**
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* @addtogroup Basic_TRX
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* @{
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* @addtogroup TX_Config
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* @{
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*/
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/**
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* @brief mac_enable_imr
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*
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* @param *adapter
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* @param band
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* @param sel
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 mac_enable_imr(struct mac_ax_adapter *adapter, u8 band,
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enum mac_ax_hwmod_sel sel);
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u32 ser_imr_config(struct mac_ax_adapter *adapter, u8 band,
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enum mac_ax_hwmod_sel sel);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup Basic_TRX
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* @{
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* @addtogroup TX_Config
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* @{
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*/
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/**
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* @brief check_mac_en
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*
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* @param *adapter
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* @param band
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* @param sel
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 check_mac_en(struct mac_ax_adapter *adapter, u8 band,
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enum mac_ax_hwmod_sel sel);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup Basic_TRX
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* @{
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* @addtogroup TX_Config
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* @{
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*/
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/**
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* @brief mac_check_access
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*
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* @param *adapter
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* @param offset
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 mac_check_access(struct mac_ax_adapter *adapter, u32 offset);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup Basic_TRX
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* @{
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* @addtogroup TX_Config
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* @{
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*/
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/**
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* @brief cmac_init
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*
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* @param *adapter
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* @param *info
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* @param band
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 cmac_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info,
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enum mac_ax_band band);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup Basic_TRX
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* @{
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* @addtogroup TX_Config
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* @{
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*/
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/**
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* @brief mac_trx_init
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*
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* @param *adapter
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* @param *info
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 mac_trx_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup Basic_TRX
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* @{
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* @addtogroup TX_Config
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* @{
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*/
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/**
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* @brief mac_tx_mode_sel
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*
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* @param *adapter
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* @param *mode_sel
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 mac_tx_mode_sel(struct mac_ax_adapter *adapter,
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struct mac_ax_mac_tx_mode_sel *mode_sel);
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/**
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* @}
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* @}
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*/
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/**
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* @addtogroup Basic_TRX
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* @{
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* @addtogroup TX_Config
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* @{
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*/
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/**
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* @brief mac_two_nav_cfg
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*
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* @param *adapter
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* @param *info
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* @return Please Place Description here.
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* @retval u32
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*/
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u32 mac_two_nav_cfg(struct mac_ax_adapter *adapter,
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struct mac_ax_2nav_info *info);
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/**
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* @}
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* @}
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*
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*//**
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* @brief mac_sifs_chk_edcca_en
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*
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* @param *adapter
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* @param *band
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* @param *en
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* @return check cca in sifs enable/disable
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* @retval u32
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*/
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u32 mac_sifs_chk_cca_en(struct mac_ax_adapter *adapter, u8 band, u8 en);
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/**
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* @}
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* @}
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*/
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/**
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* @}
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* @}
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*
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*//**
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* @brief _patch_rsp_ack
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*
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* @param *adapter
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* @param *band
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* @param *en
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* @return check cca in sifs enable/disable
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* @retval u32
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*/
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u32 _patch_rsp_ack(struct mac_ax_adapter *adapter,
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struct mac_ax_resp_chk_cca *cfg);
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/**
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* @}
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* @}
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*/
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/**
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* @brief chk_patch_ss2f_path
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*
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* @param *adapter
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* @return Please Place Description here.
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* @retval bool
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*/
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bool chk_patch_ss2f_path(struct mac_ax_adapter *adapter);
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/**
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* @brief mac_feat_init
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*
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* @param *adapter
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* @return Please Place Description here.
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* @retval bool
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*/
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u32 mac_feat_init(struct mac_ax_adapter *adapter, struct mac_ax_trx_info *info);
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#endif
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