/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#include "rrsr_8852b.h"
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#if MAC_AX_8852B_SUPPORT
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u32 mac_get_rrsr_cfg_8852b(struct mac_ax_adapter *adapter,
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struct mac_ax_rrsr_cfg *cfg)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u32 val32, rrsr_ctl_0, rrsr_ctl_1;
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val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL);
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if (val32 != MACSUCCESS) {
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PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band);
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return val32;
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}
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rrsr_ctl_0 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ?
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R_AX_TRXPTCL_RRSR_CTL_0_C1 : R_AX_TRXPTCL_RRSR_CTL_0);
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cfg->rrsr_rate_en = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_RATE_EN);
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cfg->doppler_en = ((rrsr_ctl_0 & B_AX_WMAC_RESP_DOPPLEB_AX_EN) != 0);
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cfg->dcm_en = ((rrsr_ctl_0 & B_AX_WMAC_RESP_DCM_EN) != 0);
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cfg->cck_cfg = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RRSB_AX_CCK);
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cfg->rsc = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_RSC);
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cfg->ref_rate_sel = ((rrsr_ctl_0 & B_AX_WMAC_RESP_REF_RATE_SEL) != 0);
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cfg->ref_rate = GET_FIELD(rrsr_ctl_0, B_AX_WMAC_RESP_REF_RATE);
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cfg->ftm_rrsr_rate_en = GET_FIELD(rrsr_ctl_0, B_AX_FTM_RRSR_RATE_EN);
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rrsr_ctl_1 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ?
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R_AX_TRXPTCL_RRSR_CTL_1_C1 : R_AX_TRXPTCL_RRSR_CTL_1);
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cfg->ofdm_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_OFDM);
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cfg->ht_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_HT);
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cfg->vht_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_VHT);
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cfg->he_cfg = GET_FIELD(rrsr_ctl_1, B_AX_WMAC_RRSR_HE);
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return MACSUCCESS;
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}
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u32 mac_set_rrsr_cfg_8852b(struct mac_ax_adapter *adapter,
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struct mac_ax_rrsr_cfg *cfg)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u32 val32, rrsr_ctl_0, rrsr_ctl_1;
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val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL);
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if (val32 != MACSUCCESS) {
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PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band);
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return val32;
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}
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rrsr_ctl_0 = SET_WORD(cfg->rrsr_rate_en, B_AX_WMAC_RESP_RATE_EN) |
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(cfg->doppler_en ? B_AX_WMAC_RESP_DOPPLEB_AX_EN : 0) |
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(cfg->dcm_en ? B_AX_WMAC_RESP_DCM_EN : 0) |
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SET_WORD(cfg->cck_cfg, B_AX_WMAC_RRSB_AX_CCK) |
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SET_WORD(cfg->rsc, B_AX_WMAC_RESP_RSC) |
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(cfg->ref_rate_sel ? B_AX_WMAC_RESP_REF_RATE_SEL : 0) |
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SET_WORD(cfg->ftm_rrsr_rate_en, B_AX_FTM_RRSR_RATE_EN) |
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SET_WORD(cfg->ref_rate, B_AX_WMAC_RESP_REF_RATE);
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rrsr_ctl_1 = SET_WORD(cfg->ofdm_cfg, B_AX_WMAC_RRSR_OFDM) |
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SET_WORD(cfg->ht_cfg, B_AX_WMAC_RRSR_HT) |
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SET_WORD(cfg->vht_cfg, B_AX_WMAC_RRSR_VHT) |
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SET_WORD(cfg->he_cfg, B_AX_WMAC_RRSR_HE);
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// add fw offload later
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if (cfg->band == MAC_AX_BAND_0) {
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MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_0, rrsr_ctl_0);
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MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_1, rrsr_ctl_1);
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} else {
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MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_0_C1, rrsr_ctl_0);
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MAC_REG_W32(R_AX_TRXPTCL_RRSR_CTL_1_C1, rrsr_ctl_1);
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}
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return MACSUCCESS;
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}
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u32 mac_get_cts_rrsr_cfg_8852b(struct mac_ax_adapter *adapter,
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struct mac_ax_cts_rrsr_cfg *cfg)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u32 val32;
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val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL);
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if (val32 != MACSUCCESS) {
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PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band);
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return val32;
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}
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val32 = MAC_REG_R32((cfg->band == MAC_AX_BAND_1) ?
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R_AX_TRXPTCL_CTS_RRSR_C1 : R_AX_TRXPTCL_CTS_RRSR);
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cfg->cts_rrsr_rsc = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_RSC);
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cfg->cts_rrsr_opt = ((val32 & B_AX_WMAC_CTS_RESP_OPT) != 0);
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cfg->cts_rrsr_cck_cfg = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_CCK);
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cfg->cts_rrsr_ofdm_cfg = GET_FIELD(val32, B_AX_WMAC_CTS_RRSR_OFDM);
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return MACSUCCESS;
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}
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u32 mac_set_cts_rrsr_cfg_8852b(struct mac_ax_adapter *adapter,
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struct mac_ax_cts_rrsr_cfg *cfg)
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{
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struct mac_ax_intf_ops *ops = adapter_to_intf_ops(adapter);
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u32 val32;
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val32 = check_mac_en(adapter, cfg->band, MAC_AX_CMAC_SEL);
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if (val32 != MACSUCCESS) {
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PLTFM_MSG_ERR("[ERR]%s CMAC%d not enable\n", __func__, cfg->band);
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return val32;
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}
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val32 = SET_WORD(cfg->cts_rrsr_rsc, B_AX_WMAC_CTS_RRSR_RSC) |
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(cfg->cts_rrsr_opt ? B_AX_WMAC_CTS_RESP_OPT : 0) |
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SET_WORD(cfg->cts_rrsr_cck_cfg, B_AX_WMAC_CTS_RRSR_CCK) |
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SET_WORD(cfg->cts_rrsr_ofdm_cfg, B_AX_WMAC_CTS_RRSR_OFDM);
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// add fw offload later
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if (cfg->band == MAC_AX_BAND_0)
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MAC_REG_W32(R_AX_TRXPTCL_CTS_RRSR, val32);
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else
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MAC_REG_W32(R_AX_TRXPTCL_CTS_RRSR_C1, val32);
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return MACSUCCESS;
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}
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#endif /* #if MAC_AX_8852B_SUPPORT */
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