/******************************************************************************
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*
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* Copyright(c) 2019 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HAL_STRUCT_H_
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#define _HAL_STRUCT_H_
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struct hal_info_t;
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#define hal_get_trx_ops(_halinfo) (_halinfo->trx_ops)
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/**
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* struct hal_trx_ops - hw ic specific operations
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*
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* @init: the function for initializing IC specific data and hw configuration
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* @deinit: the function for deinitializing IC specific data and hw configuration
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* @query_tx_res: the function for querying hw tx resource
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* @query_rx_res: the function for querying hw rx resource
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* @map_hw_tx_chnl: the function for getting mapping hw tx channel
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* @qsel_to_tid: the function for converting hw qsel to tid value
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* @query_txch_num: the function for querying total hw tx dma channels number
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* @query_rxch_num: the function for querying total hw rx dma channels number
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* @update_wd: the function for updating wd page for xmit packet
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* @update_txbd: the function for updating tx bd for xmit packet
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* @tx_start: the function to trigger hw to start tx
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* @get_fwcmd_queue_idx: the function to get fwcmd queue idx
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* @check_rxrdy: the function check if hw rx buffer is ready to access
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* @handle_rxbd_info: the function handling hw rxbd information
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* @handle_rx_buffer: the function handling hw rx buffer
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* @update_rxbd: the function for updating rx bd for recv packet
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* @notify_rxdone: the function to notify hw rx done
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* @handle_wp_rpt: the function parsing wp report content
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* @query_txch_hwband: which hwband that txch belong to
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* @query_txch_map: fill txch map by band_idx
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*/
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struct hal_trx_ops {
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u8 (*map_hw_tx_chnl)(struct hal_info_t *hal, u16 macid, enum rtw_phl_ring_cat cat, u8 band);
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u8 (*query_txch_num)(void);
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u8 (*query_rxch_num)(void);
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u32 (*hal_get_wd_len)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req);
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#ifdef CONFIG_PCI_HCI
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enum rtw_hal_status (*init)(struct hal_info_t *hal, u8 *txbd_buf, u8 *rxbd_buf);
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void (*deinit)(struct hal_info_t *hal);
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u16 (*query_tx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch,
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u16 *host_idx, u16 *hw_idx);
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u16 (*query_rx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch,
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u16 *host_idx, u16 *hw_idx);
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u16 (*get_rxbd_num)(struct rtw_hal_com_t *hal_com, u8 dma_ch);
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u16 (*get_rxbuf_num)(struct rtw_hal_com_t *hal_com, u8 dma_ch);
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u16 (*get_rxbuf_size)(struct rtw_hal_com_t *hal_com, u8 dma_ch);
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void (*cfg_dma_io)(struct hal_info_t *hal, u8 en);
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void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch);
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void (*cfg_txhci)(struct hal_info_t *hal, u8 en);
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void (*cfg_rxhci)(struct hal_info_t *hal, u8 en);
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void (*clr_rwptr)(struct hal_info_t *hal);
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void (*rst_bdram)(struct hal_info_t *hal);
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void (*cfg_rsvd_ctrl)(struct hal_info_t *hal);
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u8 (*qsel_to_tid)(struct hal_info_t *hal, u8 qsel_id, u8 tid_indic);
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u8 (*query_txch_hwband)(u8 dma_ch);
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void (*query_txch_map)(enum phl_band_idx band, void *ch_map);
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enum rtw_hal_status
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(*update_wd)(struct hal_info_t *hal, struct rtw_phl_pkt_req *req);
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enum rtw_hal_status
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(*update_txbd)(struct hal_info_t *hal,
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struct tx_base_desc *txbd_ring,
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struct rtw_wd_page *wd_page,
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u8 ch_idx, u16 wd_num);
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enum rtw_hal_status
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(*tx_start)(struct hal_info_t *hal,
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struct tx_base_desc *txbd, u8 dma_ch);
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u8 (*get_fwcmd_queue_idx)(void);
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u8 (*check_rxrdy)(struct rtw_phl_com_t *phl_com,
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struct rtw_rx_buf *rx_buf, u8 dma_ch);
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enum rtw_hal_status
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(*handle_rx_buffer)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal,
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u8 *buf, u32 buf_size,
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struct rtw_phl_rx_pkt *rxpkt);
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u8 (*handle_rxbd_info)(struct hal_info_t *hal, u8 *rxbuf, u16 *buf_size);
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enum rtw_hal_status
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(*update_rxbd)(struct hal_info_t *hal,
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struct rx_base_desc *rxbd,
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struct rtw_rx_buf *rx_buf, u8 ch_idx);
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enum rtw_hal_status
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(*notify_rxdone)(struct hal_info_t *hal,
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struct rx_base_desc *rxbd, u8 ch, u16 rxcnt);
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u16 (*handle_wp_rpt)(struct hal_info_t *hal, u8 *rp, u16 len,
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u8 *sw_retry, u8 *dma_ch, u16 *wp_seq, u8 *mac_id,
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u8 *ac_queue, u8 *txsts);
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#endif /*CONFIG_PCI_HCI*/
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#ifdef CONFIG_USB_HCI
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enum rtw_hal_status (*init)(struct hal_info_t *hal);
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void (*deinit)(struct hal_info_t *hal);
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enum rtw_hal_status
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(*hal_fill_wd)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req,
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u8 *wd_buf, u32 *wd_len);
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u8 (*get_bulkout_id)(struct hal_info_t *hal, u8 ch_dma, u8 mode);
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enum rtw_hal_status
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(*handle_rx_buffer)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal,
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u8 *buf, u32 buf_size,
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struct rtw_phl_rx_pkt *rxpkt);
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enum rtw_hal_status
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(*query_hal_info)(struct hal_info_t *hal, u8 info_id, void *value);
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enum rtw_hal_status
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(*usb_tx_agg_cfg)(struct hal_info_t *hal, u8* wd_buf, u8 agg_num);
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enum rtw_hal_status
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(*usb_rx_agg_cfg)(struct hal_info_t *hal, u8 mode, u8 agg_mode,
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u8 drv_define, u8 timeout, u8 size, u8 pkt_num);
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u8 (*get_fwcmd_queue_idx)(void);
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u8 (*get_max_bulkout_wd_num)(struct hal_info_t *hal);
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void (*cfg_dma_io)(struct hal_info_t *hal, u8 en);
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void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch);
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void (*cfg_txhci)(struct hal_info_t *hal, u8 en);
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void (*cfg_rxhci)(struct hal_info_t *hal, u8 en);
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void (*clr_rwptr)(struct hal_info_t *hal);
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void (*rst_bdram)(struct hal_info_t *hal);
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void (*cfg_rsvd_ctrl)(struct hal_info_t *hal);
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u16 (*handle_wp_rpt)(struct hal_info_t *hal, u8 *rp, u16 len,
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u8 *mac_id, u8 *ac_queue, u8 *txsts);
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#endif /*CONFIG_USB_HCI*/
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#ifdef CONFIG_SDIO_HCI
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enum rtw_hal_status (*init)(struct hal_info_t *hal);
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void (*deinit)(struct hal_info_t *hal);
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u16 (*query_tx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch,
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u16 *host_idx, u16 *hw_idx);
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u16 (*query_rx_res)(struct rtw_hal_com_t *hal_com, u8 dma_ch,
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u16 *host_idx, u16 *hw_idx);
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u16 (*get_rxbd_num)(struct rtw_hal_com_t *hal_com, u8 dma_ch);
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u16 (*get_rxbuf_num)(struct rtw_hal_com_t *hal_com, u8 dma_ch);
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u16 (*get_rxbuf_size)(struct rtw_hal_com_t *hal_com, u8 dma_ch);
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enum rtw_hal_status
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(*hal_fill_wd)(struct hal_info_t *hal, struct rtw_xmit_req *tx_req,
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u8 *wd_buf, u32 *wd_len);
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u8 (*get_fwcmd_queue_idx)(void);
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void (*cfg_dma_io)(struct hal_info_t *hal, u8 en);
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void (*cfg_txdma)(struct hal_info_t *hal, u8 en, u8 dma_ch);
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void (*cfg_txhci)(struct hal_info_t *hal, u8 en);
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void (*cfg_rxhci)(struct hal_info_t *hal, u8 en);
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void (*clr_rwptr)(struct hal_info_t *hal);
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void (*rst_bdram)(struct hal_info_t *hal);
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void (*cfg_rsvd_ctrl)(struct hal_info_t *hal);
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enum rtw_hal_status(*handle_rx_buffer)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal,
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u8 *buf, u32 buf_size,
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struct rtw_phl_rx_pkt *rxpkt);
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#endif
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};
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#define hal_get_ops(_halinfo) (&_halinfo->hal_ops)
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#define hal_get_regu_ops(_halops_) (&((_halops_)->regu_ops))
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struct hal_regu_ops {
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u8 (*hal_query_group_cntry_num)(
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struct rtw_regu_policy *policy, u8 group_id);
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u8 (*hal_get_cntry_idx)(char *cntry);
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u8 (*hal_get_cntry_tbl_size)(void);
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u8 (*hal_get_chnlplan_ver)(void);
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u8 (*hal_get_country_ver)(void);
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u8 (*hal_get_domain_regulation)(u8 domain, u8 band);
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u8 (*hal_get_domain_idx)(u8 domain, bool is_6g);
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u8 (*hal_get_cat6g_by_country)(char *country);
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void (*hal_get_6g_regulatory_info)(u8 domain, u8 *dm_code,
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u8 *regulation, u8 *ch_idx);
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void (*hal_qry_cntry_chnlplan)(
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struct rtw_regulation_country_chplan *chplan, char *country);
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void (*hal_get_chplan_update_info)(
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u8 group, u8 did, void *info, enum band_type band);
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void (*hal_fill_group_cntry_list)(
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struct rtw_regu_policy *policy, char *list,
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u32 group_size, u8 group_id);
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void (*hal_get_chdef_6g)(
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u8 ch_idx, struct chdef_6ghz *chdef);
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};
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struct hal_ops_t {
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/*** initialize section ***/
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void (*read_chip_version)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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void (*init_hal_spec)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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void (*init_default_value)(struct hal_info_t *hal);
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void (*init_int_default_value)(struct hal_info_t *hal, enum rtw_hal_int_set_opt opt);
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u32 (*hal_hci_configure)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal,
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struct rtw_ic_info *ic_info);
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enum rtw_hal_status (*hal_get_efuse)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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#ifdef CONFIG_PCI_HCI
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enum rtw_hal_status (*hal_set_pcicfg)(struct hal_info_t *hal);
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#endif /* CONFIG_PCI_HCI */
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enum rtw_hal_status (*hal_init)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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void (*hal_deinit)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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enum rtw_hal_status (*hal_start)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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enum rtw_hal_status (*hal_stop)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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enum rtw_hal_status (*hal_cfg_fw)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal,
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char *ic_name,
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enum rtw_fw_type fw_type);
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enum rf_path (*get_path_from_ant_num)(u8 antnum);
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#ifdef CONFIG_WOWLAN
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enum rtw_hal_status (*hal_wow_init)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta);
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enum rtw_hal_status (*hal_wow_deinit)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta);
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#endif /* CONFIG_WOWLAN */
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/* MP */
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enum rtw_hal_status (*hal_mp_init)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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enum rtw_hal_status (*hal_mp_deinit)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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bool (*hal_mp_path_chk)(struct rtw_phl_com_t *phl_com,
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u8 ant_tx,
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u8 cur_phy);
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/*IO ops*/
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u32 (*read_macreg)(struct hal_info_t *hal,
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u32 offset, u32 bit_mask);
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void (*write_macreg)(struct hal_info_t *hal,
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u32 offset, u32 bit_mask, u32 data);
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u32 (*read_bbreg)(struct hal_info_t *hal,
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u32 offset, u32 bit_mask);
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void (*write_bbreg)(struct hal_info_t *hal,
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u32 offset, u32 bit_mask, u32 data);
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u32 (*read_rfreg)(struct hal_info_t *hal,
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enum rf_path path, u32 offset, u32 bit_mask);
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void (*write_rfreg)(struct hal_info_t *hal,
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enum rf_path path, u32 offset, u32 bit_mask, u32 data);
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#ifdef RTW_WKARD_BUS_WRITE
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enum rtw_hal_status (*write_reg_post_cfg)(struct hal_info_t *hal_info,
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u32 offset, u32 value);
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#endif
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/*** interrupt hdl section ***/
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void (*disable_interrupt_isr)(struct hal_info_t *hal);
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void (*enable_interrupt)(struct hal_info_t *hal);
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void (*disable_interrupt)(struct hal_info_t *hal);
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void (*config_interrupt)(struct hal_info_t *hal, enum rtw_phl_config_int int_mode);
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bool (*recognize_interrupt)(struct hal_info_t *hal);
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bool (*recognize_halt_c2h_interrupt)(struct hal_info_t *hal);
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void (*clear_interrupt)(struct hal_info_t *hal);
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u32 (*interrupt_handler)(struct hal_info_t *hal);
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void (*restore_interrupt)(struct hal_info_t *hal);
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void (*restore_rx_interrupt)(struct hal_info_t *hal);
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#ifdef PHL_RXSC_ISR
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enum rtw_hal_status (*check_rpq_isr)(u8 dma_ch, u32 rx_int_array);
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#endif
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/* regu */
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struct hal_regu_ops regu_ops;
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#ifdef RTW_PHL_BCN
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enum rtw_hal_status (*cfg_bcn)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry);
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enum rtw_hal_status (*upt_bcn)(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal, struct rtw_bcn_entry *bcn_entry);
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#endif
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#ifdef CONFIG_PCI_HCI
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enum rtw_hal_status (*get_pcicfg)(struct hal_info_t *hal,
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struct rtw_pcie_cfgspc_param *cfg);
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#endif
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#ifdef CONFIG_RTW_MULTI_DEV_MULTI_BAND
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enum rtw_hal_status (*cfg_share_xstal)(struct hal_info_t *hal,
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struct rtw_phl_com_t *phl_com,
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bool is_share);
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#endif /* CONFIG_RTW_MULTI_DEV_MULTI_BAND */
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enum rtw_hal_status (*cfg_ppdu_sts)(struct hal_info_t *hal,
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struct hal_ppdu_sts_cfg *cfg);
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};
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struct hal_info_t {
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struct rtw_phl_com_t *phl_com;
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struct rtw_hal_com_t *hal_com;
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_os_atomic hal_mac_mem;
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struct hal_trx_ops *trx_ops;
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struct hal_ops_t hal_ops;
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#ifdef CONFIG_PCI_HCI
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void *txch_map;
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#endif
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void *rpr_cfg;
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void *mac; /*halmac*/
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void *bb;
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void *rf;
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void *btc;
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void *efuse;
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u8 monitor_mode[MAX_BAND_NUM]; /* default: 0 */
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};
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struct c2h_evt_msg {
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union {
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struct rtw_tx_pkt_rpt tx_rpt;
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#ifdef CONFIG_PHL_TWT
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struct rtw_phl_twt_wait_anno_rpt twt_anno_rpt;
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#endif
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struct rtw_bcn_early_rpt bcn_erly_rpt;
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} u;
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};
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struct hal_c2h_hdl {
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u8 cat;
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u8 cls_min;
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u8 cls_max;
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u32 (*c2h_hdl)(void *hal, struct rtw_c2h_info *c2h, struct c2h_evt_msg *c2h_msg);
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void (*c2h_buf_wb)(void *hal, struct rtw_c2h_info *c2h, u32 evt_id, struct c2h_evt_msg *c2h_msg);
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};
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#ifdef CONFIG_PHL_CHANNEL_INFO
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enum chinfo_ch_mode {
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CH_INFO_LEGACY_CH = 0,
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CH_INFO_MIMO_CH = 1,
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CH_INFO_MAX,
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};
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struct chinfo_bbcr_cfg {
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bool ch_i_phy0_en;
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bool ch_i_phy1_en;
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bool ch_i_data_src;
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bool ch_i_cmprs;
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u8 ch_i_grp_num_non_he;
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u8 ch_i_grp_num_he;
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u8 ch_i_blk_start_idx;
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u8 ch_i_blk_end_idx;
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u32 ch_i_ele_bitmap;
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enum chinfo_ch_mode ch_i_type;
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u8 ch_i_seg_len;
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};
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/*sync from struct bb_ch_rpt_hdr_info */
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struct ch_rpt_hdr_info {
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u16 total_len_l; /*header(16byte) + Raw data length(Unit: byte)*/
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#if (PLATFOM_IS_LITTLE_ENDIAN)
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u8 total_len_m:1;
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u8 total_seg_num:7;
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#else
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u8 total_seg_num:7;
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u8 total_len_m:1;
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#endif
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u8 avg_noise_pow;
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#if (PLATFOM_IS_LITTLE_ENDIAN)
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u8 is_pkt_end:1;
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u8 set_valid:1;
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u8 n_rx:3;
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u8 n_sts:3;
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#else
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u8 n_sts:3;
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u8 n_rx:3;
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u8 set_valid:1;
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u8 is_pkt_end:1;
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#endif
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u8 segment_size; /*unit (8Byte)*/
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u8 sts0_evm;
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u8 seq_num;
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};
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/*sync from struct bb_phy_info_rpt */
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struct phy_info_rpt {
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u8 rssi[2];
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u16 rsvd_0;
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u8 rssi_avg;
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#if (PLATFOM_IS_LITTLE_ENDIAN)
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u8 rxsc:4;
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u8 sts1_evm_l:4;
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u8 sts1_evm_m:4;
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u8 rsvd_1:4;
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#else
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u8 rsvd_1:4;
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u8 sts1_evm_m:4;
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u8 sts1_evm_l:4;
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u8 rxsc:4;
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#endif
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u8 rsvd_2;
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};
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struct ch_info_drv_rpt {
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u32 raw_data_len;
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u8 seg_idx_curr;
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bool get_ch_rpt_success;
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};
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#endif /* CONFIG_PHL_CHANNEL_INFO */
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#endif /*_HAL_STRUCT_H_*/
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