/******************************************************************************
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*
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* Copyright(c) 2019 - 2021 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HAL_DEF_H_
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#define _HAL_DEF_H_
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#define halcom_to_drvpriv(_hcom) (_hcom->drv_priv)
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#define hal_get_chip_id(_halcom) (_halcom->chip_id)
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#define MAX_WD_LEN (48)
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#define MAX_WD_BODY_LEN (24)
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#define MAX_BAENTRY 16
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#define HAL_MAX_PATH HALBB_MAX_PATH
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enum hal_path {
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PATH_NON = 0,
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PATH_A = 0x00000001,
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PATH_B = 0x00000002,
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PATH_C = 0x00000004,
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PATH_D = 0x00000008,
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PATH_AB = (PATH_A | PATH_B),
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PATH_AC = (PATH_A | PATH_C),
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PATH_AD = (PATH_A | PATH_D),
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PATH_BC = (PATH_B | PATH_C),
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PATH_BD = (PATH_B | PATH_D),
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PATH_CD = (PATH_C | PATH_D),
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PATH_ABC = (PATH_A | PATH_B | PATH_C),
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PATH_ABD = (PATH_A | PATH_B | PATH_D),
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PATH_ACD = (PATH_A | PATH_C | PATH_D),
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PATH_BCD = (PATH_B | PATH_C | PATH_D),
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PATH_ABCD = (PATH_A | PATH_B | PATH_C | PATH_D),
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PATH_AUTO = 0xff /*for auto path selection*/
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};
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enum HAL_CMD_ID {
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HAL_HELP,
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MAC_DD_DBG,
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MAC_DUMP_SEC_CAM_TBL
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};
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struct hal_cmd_info {
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char name[16];
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u8 id;
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};
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static const struct hal_cmd_info hal_cmd_i[] = {
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{"-h", HAL_HELP},
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{"dd_dbg", MAC_DD_DBG},/*@do not move this element to other position*/
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{"sec_cam_tbl", MAC_DUMP_SEC_CAM_TBL}
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};
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enum rtw_hal_ser_rsn {
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HAL_SER_RSN_NONE = 0,
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HAL_SER_RSN_WOW,
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HAL_SER_RSN_RFK
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};
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enum rtw_hal_status {
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RTW_HAL_STATUS_SUCCESS, /* 0 */
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RTW_HAL_STATUS_FAILURE, /* 1 */
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RTW_HAL_STATUS_RESOURCE, /* 2 */
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RTW_HAL_STATUS_IO_INIT_FAILURE, /* 3 */
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RTW_HAL_STATUS_MAC_INIT_FAILURE, /* 4 */
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RTW_HAL_STATUS_BB_INIT_FAILURE, /* 5 */
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RTW_HAL_STATUS_RF_INIT_FAILURE, /* 6 */
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RTW_HAL_STATUS_BTC_INIT_FAILURE, /* 7 */
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RTW_HAL_STATUS_HAL_INIT_FAILURE, /* 8 */
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RTW_HAL_STATUS_EFUSE_UNINIT, /* 9 */
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RTW_HAL_STATUS_EFUSE_IVALID_OFFSET, /* 10 */
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RTW_HAL_STATUS_EFUSE_PG_FAIL, /* 11 */
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RTW_HAL_STATUS_MAC_API_FAILURE, /* 12 */
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RTW_HAL_STATUS_BB_CH_INFO_LAST_SEG, /*13*/
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RTW_HAL_STATUS_UNKNOWN_RFE_TYPE, /* 14 */
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RTW_HAL_STATUS_TIMEOUT, /* 15 */
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RTW_HAL_STATUS_NOT_SUPPORT, /* 16 */
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};
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#define FW_FILE_NIC_POSTFIX ""
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#define FW_FILE_NIC_CE_POSTFIX "_ce"
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#define FW_FILE_WOWLAN_POSTFIX "_wowlan"
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#define FW_FILE_SPIC_POSTFIX "_spic"
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#define FW_FILE_AP_POSTFIX "_ap"
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enum _rtw_hal_query_info {
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RTW_HAL_RXDESC_SIZE,
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};
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enum rtw_h2c_pkt_type {
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H2CB_TYPE_CMD = 0,
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H2CB_TYPE_DATA = 1,
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H2CB_TYPE_LONG_DATA = 2,
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H2CB_TYPE_MAX = 0x3
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};
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enum tx_pause_rson {
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PAUSE_RSON_NOR_SCAN, /*normal scan*/
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PAUSE_RSON_UNSPEC_BY_MACID, /*P2P_SCAN*/
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PAUSE_RSON_RFK,
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PAUSE_RSON_PSD,
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PAUSE_RSON_DFS,
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PAUSE_RSON_DFS_CSA, /* allow beacon only */
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PAUSE_RSON_DFS_CSA_MG, /* allow beacon and mgnt frame */
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PAUSE_RSON_DFS_CAC,
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PAUSE_RSON_DBCC,
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PAUSE_RSON_RESET,
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PAUSE_RSON_MAX
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};
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enum rtw_hal_config_int {
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RTW_HAL_EN_DEFAULT_INT,
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RTW_HAL_DIS_DEFAULT_INT,
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RTW_HAL_STOP_RX_INT,
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RTW_HAL_RESUME_RX_INT,
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RTW_HAL_SER_HANDSHAKE_MODE,
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RTW_HAL_EN_HCI_INT,
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RTW_HAL_DIS_HCI_INT,
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RTW_HAL_CONFIG_INT_MAX
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};
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enum hal_mp_efuse_type {
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HAL_MP_EFUSE_WIFI = 0,
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HAL_MP_EFUSE_BT,
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HAL_MP_EFUSE_NONE,
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};
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struct rtw_g6_h2c_hdr {
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u8 h2c_class; //0x0~0x7: Phydm; 0x8~0xF: RF; 0x10~0x17: BTC
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u8 h2c_func;
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u8 seq_valid:1;
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u8 seq:3;
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u8 seq_stop:1;
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enum rtw_h2c_pkt_type type; //0:cmd ; 1:cmd+data ; 2:cmd+long data
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u16 content_len:12;
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u16 rec_ack:1; //Ack when receive H2C
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u16 done_ack:1; //Ack when FW execute H2C cmd done
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u16 rsvd2:2;
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};
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/**
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* @c2h_cat: target category of this c2h / c2h ack
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* @c2h_class: target class of this c2h / c2h ack
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* @c2h_func: target function of this c2h / c2h ack
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* @type_rec_ack: set 1 as a receive ack to this c2h
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* @type_done_ack: set 1 as a done ack to this c2h
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* @h2c_return: status code of done ack responding to h2c
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*
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*/
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struct rtw_c2h_info {
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u8 c2h_cat;
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u8 c2h_class;
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u8 c2h_func;
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u8 type_rec_ack:1;
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u8 type_done_ack:1;
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u8 rsvd:6;
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u8 h2c_return;/*H2C return value, 0 = success*/
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u8 h2c_seq;
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u16 content_len;
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u8 *content;
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};
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#define RTW_BTC_OVERWRITE_BUF_LEN 10
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struct hal_bt_msg {
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_os_lock lock;
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u16 len;
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u16 cnt; /* update cnt */
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u8 latest[RTW_BTC_OVERWRITE_BUF_LEN];
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u8 working[RTW_BTC_OVERWRITE_BUF_LEN];
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};
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struct btc_fw_msg {
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_os_lock lock;
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u32 fev_cnt; /* fw event cnt, need to be protected by lock */
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struct hal_bt_msg btinfo;
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struct hal_bt_msg scbd;
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/* common fwinfo queue */
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struct phl_queue idleq;
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struct phl_queue waitq;
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};
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struct btc_ctrl_t {
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u8 lps;
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u8 tx_time;
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u8 tx_retry;
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u8 disable_rx_stbc;
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};
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/*except version*/
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struct ver_ctrl_t {
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u64 mac_ver;
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u64 bb_ver;
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u64 rf_ver;
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u64 btc_ver;
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u64 fw_ver;
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};
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struct hal_mu_score_tbl_ctrl {
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u32 mu_sc_thr:2;
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u32 mu_opt:1;
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u32 rsvd:29;
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};
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#define HAL_MAX_MU_SCORE_SIZE 8 /* Unit: Byte */
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struct hal_mu_score_tbl_score {
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u8 valid;
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u16 macid;
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u8 score[HAL_MAX_MU_SCORE_SIZE]; /*by case: [1:0], [3:2], ..... */
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};
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#define HAL_MAX_MU_STA_NUM 6
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struct hal_mu_score_tbl {
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struct hal_mu_score_tbl_ctrl mu_ctrl;
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_os_lock lock;
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u8 num_mu_sta; /*By IC, shall alway <= than HAL_MAX_MU_STA_NUM , 0 = tbl invalid */
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u8 sz_mu_score; /*By IC, shall alway <= than HAL_MAX_MU_SCORE_SIZE , 0 = score invalid */
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struct hal_mu_score_tbl_score mu_score[HAL_MAX_MU_STA_NUM]; /* mu_score[num_mu_sta] */
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};
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#define HAL_MAX_VHT_BFRP_NUM 3
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#define HAL_MAX_HE_BFRP_NUM 2
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#define HLA_MAX_BFRP_NUM ((HAL_MAX_VHT_BFRP_NUM > HAL_MAX_HE_BFRP_NUM) ?\
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HAL_MAX_VHT_BFRP_NUM : HAL_MAX_HE_BFRP_NUM)
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#define HAL_MAX_VHT_SND_STA_NUM HAL_MAX_VHT_BFRP_NUM + 1
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#define HAL_MAX_HE_BFRP_STA_NUM 4
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#define HAL_MAX_HE_SND_STA_NUM HAL_MAX_HE_BFRP_NUM * HAL_MAX_HE_BFRP_STA_NUM
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struct hal_frame_hdr {
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u16 frame_ctl;
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u16 duration;
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u8 addr1[MAC_ALEN];
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u8 addr2[MAC_ALEN];
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};
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struct hal_npda_dialog_token {
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u8 rsvd:1;
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u8 he:1;
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u8 token:6;
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};
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#define HAL_NPDA_AC_SU 0
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#define HAL_NPDA_AC_MU 1
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#define HAL_NDPA_AX_FB_SU_NG_4 0
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#define HAL_NDPA_AX_FB_SU_NG_16 2
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#define HAL_NDPA_AX_FB_MU_NG_4 1
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#define HAL_NDPA_AX_FB_MU_NG_16 3
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#define HAL_NDPA_AX_FB_CQI 3
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#define HAL_NPDA_AX_CB_SU42_MU75 0
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#define HAL_NPDA_AX_CB_SU64_MU97 1
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struct hal_he_snd_f2p {
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u16 csi_len_bfrp:12;
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u16 tb_t_pe_bfrp:2;
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u16 tri_pad_bfrp:2;
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u16 ul_cqi_rpt_tri_bfrp:1;
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u16 rf_gain_idx_bfrp:10;
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u16 fix_gain_en_bfrp:1;
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u16 rsvd:4;
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};
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struct hal_vht_ndpa_sta_info {
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u32 aid12:12;
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u32 feedback_type:1;
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u32 nc:3;
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u32 rsvd:16;
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};
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struct hal_he_ndpa_sta_info {
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u32 aid:11;
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u32 bw:14;
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u32 fb_ng:2;
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u32 disambiguation:1;
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u32 cb:1;
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u32 nc:3;
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};
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struct hal_ndpa_para {
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struct hal_frame_hdr common;
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struct hal_npda_dialog_token snd_dialog;
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u32 ndpa_sta_info[HAL_MAX_HE_SND_STA_NUM];
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};
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struct hal_he_trg_frm_cmn {
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u32 tgr_info: 4;
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u32 ul_len: 12;
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u32 more_tf: 1;
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u32 cs_rqd: 1;
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u32 ul_bw: 2;
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u32 gi_ltf: 2;
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u32 mimo_ltfmode: 1;
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u32 num_heltf: 3;
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u32 ul_pktext: 3;
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u32 ul_stbc: 1;
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u32 ldpc_extra_sym: 1;
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u32 dplr: 1;
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u32 ap_tx_pwr: 6;
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u32 ul_sr: 16;
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u32 ul_siga2_rsvd: 9;
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u32 rsvd: 1;
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};
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struct hal_he_trg_fm_user {
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u16 aid12;
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u8 ru_pos;
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u8 ul_fec_code;
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u8 ul_mcs;
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u8 ul_dcm;
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u8 ss_alloc;
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u8 ul_tgt_rssi;
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};
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struct hal_bfrp_he {
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struct hal_he_trg_frm_cmn common;
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struct hal_he_trg_fm_user user[HAL_MAX_HE_BFRP_STA_NUM];
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u8 fbseg_rexmit_bmp[HAL_MAX_HE_BFRP_STA_NUM];/*BFRP only*/
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struct hal_he_snd_f2p f2p_info;
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};
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struct hal_bfrp_vht {
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u8 rexmit_bmp;
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};
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struct hal_bfrp_para {
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struct hal_frame_hdr hdr[HLA_MAX_BFRP_NUM];
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struct hal_bfrp_he he_para[HAL_MAX_HE_BFRP_NUM];
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struct hal_bfrp_vht vht_para[HAL_MAX_VHT_BFRP_NUM];
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};
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struct hal_snd_wd_para {
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u16 txpktsize;
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u16 ndpa_duration;
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u16 datarate:9;
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u16 macid:7;
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u8 force_txop:1;
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u8 data_bw:2;
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u8 gi_ltf:3;
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u8 data_er:1;
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u8 data_dcm:1;
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u8 data_stbc:1;
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u8 data_ldpc:1;
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u8 data_bw_er:1;
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u8 multiport_id:1;
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u8 mbssid:4;
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u8 signaling_ta_pkt_sc:4;
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u8 sw_define:4;
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u8 txpwr_ofset_type:3;
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u8 lifetime_sel:3;
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u8 stf_mode:1;
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u8 disdatafb:1;
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u8 data_txcnt_lmt_sel:1;
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u8 data_txcnt_lmt:6;
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u8 sifs_tx:1;
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u8 snd_pkt_sel:3;
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u8 ndpa:2;
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u8 rsvd:3;
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};
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#define HAL_FEXG_TYPE_AC_SU 31
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#define HAL_FEXG_TYPE_AC_MU_1 32
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#define HAL_FEXG_TYPE_AC_MU_2 33
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#define HAL_FEXG_TYPE_AC_MU_3 34
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#define HAL_FEXG_TYPE_AX_SU 35
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#define HAL_FEXG_TYPE_AX_MU_1 36
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#define HAL_FEXG_TYPE_AX_MU_2 37
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struct hal_ax_fwcmd_snd {
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u8 frame_ex_type;
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u8 bfrp0_sta_nr;
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u8 bfrp1_sta_nr;
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u16 macid[8];
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struct hal_ndpa_para ndpa;
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struct hal_bfrp_para bfrp;
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/**
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* HE: NDPA NDP HE_Trigger_BFRP (CSI) BFRP (CSI)
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* VHT: NDPA NDP (CSI) VHT_BFRP (CSI) BFRP (CSI) BFRP (CSI)
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**/
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struct hal_snd_wd_para wd[HLA_MAX_BFRP_NUM + 2];
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};
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struct rtw_hal_com_t;
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struct hal_io_ops {
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u8(*_read8)(struct rtw_hal_com_t *hal, u32 addr);
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u16(*_read16)(struct rtw_hal_com_t *hal, u32 addr);
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u32(*_read32)(struct rtw_hal_com_t *hal, u32 addr);
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void (*_read_mem)(struct rtw_hal_com_t *hal, u32 addr, u32 cnt, u8 *pmem);
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int (*_write8)(struct rtw_hal_com_t *hal, u32 addr, u8 val);
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int (*_write16)(struct rtw_hal_com_t *hal, u32 addr, u16 val);
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int (*_write32)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
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int (*_write_mem)(struct rtw_hal_com_t *hal, u32 addr, u32 length, u8 *pdata);
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#ifdef RTW_WKARD_BUS_WRITE
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int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
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#endif
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#ifdef CONFIG_SDIO_HCI
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u8(*_sd_f0_read8)(struct rtw_hal_com_t *hal, u32 addr);
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#ifdef CONFIG_SDIO_INDIRECT_ACCESS
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u8(*_sd_iread8)(struct rtw_hal_com_t *hal, u32 addr);
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u16(*_sd_iread16)(struct rtw_hal_com_t *hal, u32 addr);
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u32(*_sd_iread32)(struct rtw_hal_com_t *hal, u32 addr);
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int (*_sd_iwrite8)(struct rtw_hal_com_t *hal, u32 addr, u8 val);
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int (*_sd_iwrite16)(struct rtw_hal_com_t *hal, u32 addr, u16 val);
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int (*_sd_iwrite32)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
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#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
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#endif
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};
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struct hal_io_priv {
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#ifdef CONFIG_SDIO_INDIRECT_ACCESS
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_os_mutex sd_indirect_access_mutex;
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#endif
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struct hal_io_ops io_ops;
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};
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enum pcfg_type {
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PCFG_FUNC_SW,
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PCFG_TBTT_AGG,
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PCFG_TBTT_SHIFT,
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PCFG_HIQ_WIN,
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PCFG_HIQ_DTIM,
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PCFG_HIQ_MAX,
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PCFG_BCN_INTERVAL, /* Beacon Interval */
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PCFG_BSS_CLR,
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PCFG_BCN_EN,
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PCFG_MBSSID_EN, /* M-BSSID ID enable */
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PCFG_BCN_DRP_ALL
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};
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/*
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* refers to _usb.h
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* #define USB11 0x1
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* #define USB2 0x2
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* #define USB3 0x3
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* */
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enum usb_type {
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USB_1_1 = 1,
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USB_2_0,
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USB_3_0,
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};
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#ifdef RTW_PHL_BCN
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struct bcn_entry_pool {
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u8 bcn_num;
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_os_list bcn_list;
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_os_lock bcn_lock;
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};
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#endif
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enum rtw_hal_int_set_opt {
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INT_SET_OPT_HAL_INIT,
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INT_SET_OPT_SER_START,
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INT_SET_OPT_SER_DONE,
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INT_SET_OPT_PS_START,
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INT_SET_OPT_PS_STOP
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};
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struct hal_intr_mask_cfg {
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u8 halt_c2h_en;
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u8 wdt_en;
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};
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struct hal_halt_c2h_int {
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/* halt c2h */
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u32 intr;
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u32 val_mask;
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u32 val_default;
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};
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struct hal_watchdog_timer_int {
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/* watchdog timer */
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u32 intr;
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u32 val_mask;
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u32 val_default;
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};
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struct hal_int_array {
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struct hal_halt_c2h_int halt_c2h_int;
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struct hal_watchdog_timer_int watchdog_timer_int;
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};
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/* c2h event id for hal/phl layer */
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enum rtw_hal_c2h_ev {
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HAL_C2H_EV_DO_NOTHING = 0,
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HAL_C2H_EV_BB_MUGRP_DOWN = 1,/* BB Process C2H mu-score-tbl done */
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HAL_C2H_EV_BTC_INFO = 2, /* BTC event */
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HAL_C2H_EV_BTC_SCBD = 3, /* BTC event */
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HAL_C2H_EV_MAC_TSF32_TOG = 4, /* MAC event */
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HAL_C2H_EV_MAX
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};
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/* ppdu status : per user info */
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struct hal_ppdu_sts_usr {
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/* MAC */
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u8 vld:1;
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u8 has_data:1;
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u8 has_ctrl:1;
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u8 has_mgnt:1;
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u8 has_bcn:1;
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u16 macid;
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};
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enum hal_rxcnt_sel {
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HAL_RXCNT_OFDM_OK = 0,
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HAL_RXCNT_OFDM_FAIL = 1,
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HAL_RXCNT_OFDM_FAM = 2,
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HAL_RXCNT_CCK_OK = 3,
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HAL_RXCNT_CCK_FAIL = 4,
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HAL_RXCNT_CCK_FAM = 5,
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HAL_RXCNT_HT_OK = 6,
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HAL_RXCNT_HT_FAIL = 7,
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HAL_RXCNT_HT_PPDU = 8,
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HAL_RXCNT_HT_FAM = 9,
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HAL_RXCNT_VHTSU_OK = 0xA,
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HAL_RXCNT_VHTSU_FAIL = 0xB,
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HAL_RXCNT_VHTSU_PPDU = 0xC,
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HAL_RXCNT_VHTSU_FAM = 0xD,
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HAL_RXCNT_VHTMU_OK = 0xE,
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HAL_RXCNT_VHTMU_FAIL = 0xF,
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HAL_RXCNT_VHTMU_PPDU = 0x10,
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HAL_RXCNT_VHTMU_FAM = 0x11,
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HAL_RXCNT_HESU_OK = 0x12,
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HAL_RXCNT_HESU_FAIL = 0x13,
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HAL_RXCNT_HESU_PPDU = 0x14,
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HAL_RXCNT_HESU_FAM = 0x15,
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HAL_RXCNT_HEMU_OK = 0x16,
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HAL_RXCNT_HEMU_FAIL = 0x17,
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HAL_RXCNT_HEMU_PPDU = 0x18,
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HAL_RXCNT_HEMU_FAM = 0x19,
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HAL_RXCNT_HETB_OK = 0x1A,
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HAL_RXCNT_HETB_FAIL = 0x1B,
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HAL_RXCNT_HETB_PPDU = 0x1C,
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HAL_RXCNT_HETB_FAM = 0x1D,
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HAL_RXCNT_INVD = 0x1E,
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HAL_RXCNT_RECCA = 0x1F,
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HAL_RXCNT_FULLDRP = 0x20,
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HAL_RXCNT_FULLDRP_PKT = 0x21,
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HAL_RXCNT_RXDMA = 0x22,
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HAL_RXCNT_USER0 = 0x23,
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HAL_RXCNT_USER1 = 0x24,
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HAL_RXCNT_USER2 = 0x25,
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HAL_RXCNT_USER3 = 0x26,
|
HAL_RXCNT_CONT_FCS = 0x27,
|
HAL_RXCNT_PKTFLTR_DRP = 0x28,
|
HAL_RXCNT_CSIPKT_DMA_OK = 0x29,
|
HAL_RXCNT_CSIPKT_DMA_DROP = 0x2A,
|
HAL_RXCNT_MAX
|
};
|
|
enum hal_rate_mode {
|
HAL_LEGACY_MODE = 0,
|
HAL_HT_MODE = 1,
|
HAL_VHT_MODE = 2,
|
HAL_HE_MODE = 3
|
};
|
|
enum hal_rate_bw {
|
HAL_RATE_BW_20 = 0,
|
HAL_RATE_BW_40 = 1,
|
HAL_RATE_BW_80 = 2,
|
HAL_RATE_BW_160 = 3,
|
};
|
|
struct hal_ppdu_rx_cnt {
|
u16 ppdu_cnt[HAL_RXCNT_MAX];
|
};
|
|
/* ppdu sts mac bmp_append_info */
|
#define HAL_PPDU_MAC_INFO BIT(1)
|
#define HAL_PPDU_PLCP BIT(3)
|
#define HAL_PPDU_RX_CNT BIT(2)
|
/* ppdu sts mac bmp_filter */
|
#define HAL_PPDU_HAS_A1M BIT(4)
|
#define HAL_PPDU_HAS_CRC_OK BIT(5)
|
#define HAL_PPDU_HAS_DMA_OK BIT(6)
|
|
/* ppdu status (mac info + phy info) */
|
struct hal_ppdu_sts {
|
#define RTW_HAL_PPDU_STS_MAX_USR 4
|
/* MAC */
|
/* NOTE: (rx_cnt, plcp, phy_st)_ptr are only available before phl_recycle_rx_buf() */
|
u8 *rx_cnt_ptr;
|
u8 *plcp_ptr;
|
u8 *phy_st_ptr; /* for bb phy status */
|
u8 plcp_size;
|
u32 phy_st_size;/* for bb phy status */
|
u32 rx_cnt_size;
|
u8 usr_num;
|
struct hal_ppdu_sts_usr usr[RTW_HAL_PPDU_STS_MAX_USR];
|
struct hal_ppdu_rx_cnt rx_cnt;
|
};
|
|
#define HAL_RSSI_MAVG_NUM 16
|
#define STA_UPDATE_MA_RSSI_FAST(_RSSI, _VAL) _RSSI = ((_RSSI * \
|
(HAL_RSSI_MAVG_NUM - 1)) + _VAL) \
|
/ HAL_RSSI_MAVG_NUM
|
|
struct rtw_cfo_info {
|
s32 cfo_tail;
|
s32 pre_cfo_avg;
|
s32 cfo_avg;
|
u16 cfo_cnt;
|
u32 tp;
|
};
|
|
|
struct rtw_rssi_info {
|
u8 rssi; /* u(8,1), hal-bb provide, read only : 0~110 (dBm = rssi -110) */
|
u16 rssi_ma; /* u(16,5), hal-bb provide, read only : u16 U(12,4)*/
|
u16 rssi_ma_path[4];
|
u16 pkt_cnt_data;
|
u8 rssi_bcn; /* u(8,1), beacon RSSI, hal-bb provide, read only : 0~110 (dBm = rssi -110) */
|
u16 rssi_bcn_ma; /* u(16,5), beacon RSSI, hal-bb provide, read only*/
|
u16 rssi_bcn_ma_path[4];
|
u16 pkt_cnt_bcn;
|
u8 ma_factor:4;
|
u8 ma_factor_bcn:4;
|
u8 rssi_ofdm; /* u(8,1), hal-bb provide, read only : packet, for debug */
|
u8 rssi_cck; /* u(8,1), hal-bb provide, read only : packet, for debug */
|
u8 assoc_rssi; /* phl_rx provide, read only */
|
/* phl_rx provide, read only : Moving Average RSSI information for the STA */
|
u8 ma_rssi; /* moving average : 0 ~ PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */
|
u8 ma_rssi_mgnt; /* moving average rssi for beacon/probe : 0 ~ PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */
|
u16 snr_ma; /* u(16,4), hal-bb provide, read only, SNR= snr_ma dBm*/
|
u16 snr_ma_path[4];
|
};
|
|
struct rtw_rate_info {
|
enum rtw_gi_ltf gi_ltf; /* 3bit GILTF */
|
enum hal_rate_mode mode; /* 2bit 0:legacy, 1:HT, 2:VHT, 3:HE*/
|
enum hal_rate_bw bw; /*2bit 0:5M/10M/20M, 1:40M, 2:80M, 3:160M or 80+80*/
|
u8 mcs_ss_idx; /*HE: 3bit SS + 4bit MCS; non-HE: 5bit MCS/rate idx */
|
u8 mcs_idx;
|
u8 ss; /* 0: 1ss, 1:2ss, ... */
|
bool is_actrl; /* 0: don't append a-ctrl field; 1: append a-ctrl field */
|
bool en_stbc; /* 0: enable stbc; 1: disable stbc */
|
};
|
|
/* from cmn_sta_info */
|
struct rtw_ra_sta_info {
|
/*u8 rate_id; remove !!! use wmode in phl, [PHYDM] ratr_idx*/
|
/*u8 rssi_level; [PHYDM]*/
|
/*u8 is_first_connect:1; change connect flow, [PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/
|
/*u8 is_support_sgi:1; mov to phl [driver]*/
|
/*u8 is_vht_enable:2; mov to phl [driver]*/
|
/*u8 disable_ra:1; mov to hal [driver]*/
|
/*u8 disable_pt:1; remove for no PT, [driver] remove is_disable_power_training*/
|
/*u8 txrx_state:2; ///////////////need to check if needed, [PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/
|
/*u8 is_noisy:1; ///////////////need to check if needed, [PHYDM]*/
|
u16 curr_tx_rate; /*use struct bb_rate_info, [PHYDM] FW->Driver*/
|
enum channel_width ra_bw_mode; /*remove to phl, [Driver] max bandwidth, for RA only*/
|
enum channel_width curr_tx_bw; /*bb_rate_info, [PHYDM] FW->Driver*/
|
/* u8 drv_ractrl; */
|
|
/* Ctrl */
|
bool dis_ra; /*move from rtw_hal_stainfo_t*/
|
bool ra_registered;/*move from rtw_hal_stainfo_t*/
|
u64 ra_mask;/*move from rtw_hal_stainfo_t*/ /*drv decide by specific req*/
|
u64 cur_ra_mask;/*move from rtw_hal_stainfo_t*/
|
/*halbb create, mod by driver and decide by rssi or other*/
|
u8 cal_giltf; /* 3bit gi_ltf ctrl by driver*/
|
bool fix_giltf_en; /*giltf from cal_giltf or halbb*/
|
bool fixed_rt_en;
|
struct rtw_rate_info fixed_rt_i;
|
u8 rainfo_cfg1; /* prepare for other control*/
|
u8 rainfo_cfg2; /* prepare for other control*/
|
|
/* Report */
|
struct rtw_rate_info rpt_rt_i;
|
u8 curr_retry_ratio; /*[HALBB] FW->Driver*/
|
|
bool ra_csi_rate_en;
|
bool fixed_csi_rate_en;
|
u8 band_num;
|
struct rtw_rate_info csi_rate;
|
|
u8 avg_agg;
|
u32 tx_ok_cnt[4];
|
u32 tx_retry_cnt[4];
|
u32 tx_total_cnt;
|
/*u64 ramask;*/
|
};
|
|
struct rtw_mura_info {
|
/* Ctrl */
|
bool fixed_rt_en;
|
struct rtw_rate_info fixed_rt_i;
|
/* Report */
|
struct rtw_rate_info rpt_rt_i;
|
u8 curr_retry_ratio; /*[PHYDM] FW->Driver*/
|
};
|
|
/* from cmn_sta_info */
|
struct rtw_dtp_info {
|
u8 dyn_tx_power; /*Dynamic Tx power offset*/
|
u8 last_tx_power;
|
u8 sta_tx_high_power_lvl:4;
|
u8 sta_last_dtp_lvl:4;
|
};
|
|
struct rtw_hal_muba_info {
|
u32 fix_ba:1;
|
u32 ru_psd:9;
|
u32 tf_rate:9;
|
u32 rf_gain_fix:1;
|
u32 rf_gain_idx:10;
|
u32 tb_ppdu_bw:2;
|
u8 dcm:1;
|
u8 ss:3;
|
u8 mcs:4;
|
u8 gi_ltf:3;
|
u8 doppler:1;
|
u8 stbc:1;
|
u8 sta_coding:1;
|
u8 tb_t_pe_nom:2;
|
u8 pr20_bw_en:1;
|
u8 ma_type: 1;
|
u8 rsvd1: 6;
|
};
|
|
enum rtw_hal_protection_type {
|
HAL_PROT_NO_PROETCT = 0,
|
HAL_PROT_PRIUSER_HW_RTS = 1,
|
HAL_PROT_RTS = 2,
|
HAL_PROT_CTS2SELF = 3,
|
HAL_PROT_MU_RTS = 4,
|
HAL_PROT_HW_DEFAULT_ = 5
|
};
|
|
enum rtw_hal_ack_resp_type {
|
HAL_ACK_N_MINUS_1USER_BA = 0,
|
HAL_ACK_N_USER_BA = 1,
|
HAL_ACK_MU_BAR = 2,
|
HAL_ACK_HTP_ACK = 3,
|
HAL_ACK_HW_DEFAULT = 4
|
};
|
|
struct rtw_wp_rpt_stats {
|
u32 busy_cnt;
|
u32 tx_ok_cnt;
|
u32 tx_fail_cnt;
|
u32 rty_fail_cnt;
|
u32 lifetime_drop_cnt;
|
u32 macid_drop_cnt;
|
u32 sw_drop_cnt;
|
u32 recycle_fail_cnt;
|
u32 delay_tx_ok_cnt;
|
u32 delay_rty_fail_cnt;
|
u32 delay_lifetime_drop_cnt;
|
u32 delay_macid_drop_cnt;
|
};
|
|
struct rtw_trx_stat {
|
u32 rx_ok_cnt;
|
u32 rx_err_cnt;
|
u16 rx_rate_plurality;
|
/* add lock for tx statistics */
|
_os_lock tx_sts_lock;
|
/* Below info is for release report*/
|
u32 tx_fail_cnt;
|
u32 tx_ok_cnt;
|
#if defined(CONFIG_PHL_RELEASE_RPT_ENABLE) || defined(CONFIG_PCI_HCI)
|
struct rtw_wp_rpt_stats *wp_rpt_stats;
|
#endif
|
#ifdef CONFIG_PCI_HCI
|
u32 ltr_tx_dly_count;
|
u32 ltr_last_tx_dly_time;
|
u32 rx_rdu_cnt;
|
#endif
|
#ifdef CONFIG_VW_REFINE
|
u16 pretx_fail; /* pretx fail count */
|
u16 phltx_cnt; /* phl_tx run count */
|
|
u32 vw_cnt_snd; /* total send count for veriwave data */
|
u32 vw_cnt_rev; /* total recv count for veriwave data */
|
u32 vw_cnt_err; /* total err count for veriwave data */
|
#endif
|
u16 rx_rate;
|
u8 rx_bw;
|
u8 rx_gi_ltf;
|
};
|
|
struct bacam_ctrl_t {
|
u8 used_map[MAX_BAENTRY];
|
u8 tid[MAX_BAENTRY];
|
u16 mac_id[MAX_BAENTRY];
|
u8 count;
|
};
|
|
struct rtw_hal_stainfo_t {
|
/* from cmn_sta_info */
|
u16 dm_ctrl;
|
/* struct su_ra_info */
|
struct rtw_rssi_info rssi_stat;
|
struct rtw_cfo_info cfo_stat;
|
|
/* Beamform Related */
|
u8 bf_cap;/* sta's beamform capability : ht/vht/he + bfee/bfer */
|
void *bf_entry;
|
u16 bf_csi_buf;
|
u16 bf_csi_buf_swap;/*used in mu swap mode*/
|
/* BFee capability */
|
u8 max_nc;
|
u8 nr;
|
u8 ng16;/* 0:non-support ; BIT0:support SU ; BIT1:support MU */
|
u8 cb_sz;/* 0:non-support ; BIT0:support (4,2) SU ; BIT1:support (7,5) MU */
|
u8 support_cqi_fb;
|
/*mu group*/
|
u8 mugrp_bmp;
|
u32 mu_score;
|
/*FW Frame Exchange : when STA is primary STA, prefer protect type and ack resp type in MU*/
|
enum rtw_hal_protection_type prot_type;
|
enum rtw_hal_ack_resp_type resp_type;
|
|
/* from cmn_sta_info */
|
struct rtw_ra_sta_info ra_info;
|
/* from cmn_sta_info */
|
struct rtw_dtp_info dtp_stat;
|
struct rtw_trx_stat trx_stat;
|
void *bb_sta;
|
};
|
|
|
|
struct bus_hw_cap_t {
|
#ifdef CONFIG_PCI_HCI
|
enum rtw_pcie_bus_func_cap_t l0s_ctrl;
|
enum rtw_pcie_bus_func_cap_t l1_ctrl;
|
enum rtw_pcie_bus_func_cap_t l1ss_ctrl;
|
enum rtw_pcie_bus_func_cap_t wake_ctrl;
|
enum rtw_pcie_bus_func_cap_t crq_ctrl;
|
u8 clkdly_ctrl;
|
u8 l0sdly_ctrl;
|
u8 l1dly_ctrl;
|
u8 ltr_sw_ctrl; /* whether ltr can be controlled by sw */
|
u8 ltr_hw_ctrl;
|
u16 max_txbd_num;
|
u16 max_rxbd_num;
|
u16 max_rpbd_num;
|
u32 max_rxbuf_size;
|
u32 max_rpbuf_size;
|
u8 max_phyaddr_num;
|
u8 max_wd_page_size;
|
u8 txbd_len;
|
u8 rxbd_len;
|
u8 wdb_size;
|
u8 wdi_size;
|
u8 addr_info_size;
|
u8 seq_info_size;
|
#elif defined (CONFIG_USB_HCI)
|
u32 tx_buf_size;
|
u32 tx_buf_num;
|
u32 tx_mgnt_buf_size;
|
u32 tx_mgnt_buf_num;
|
u32 tx_h2c_buf_num;
|
u32 rx_buf_size;
|
u32 rx_buf_align_size;
|
u32 rx_buf_num;
|
u32 in_token_num;
|
#elif defined (CONFIG_SDIO_HCI)
|
u32 tx_buf_size;
|
u32 tx_buf_num;
|
u32 tx_mgnt_buf_size;
|
u32 tx_mgnt_buf_num;
|
u32 rx_buf_size;
|
u32 rx_buf_num;
|
#else
|
u8 temp_for_struct_empty; /* for undefined interface */
|
#endif
|
};
|
|
/* phy capability of phy */
|
struct phy_hw_cap_t {
|
#ifdef RTW_WKARD_BTC_RFETYPE
|
u8 rfe_type;
|
#endif
|
u8 tx_num;
|
u8 rx_num;
|
u8 tx_path_num;
|
u8 rx_path_num;
|
u16 hw_rts_time_th;
|
u16 hw_rts_len_th;
|
u32 txagg_num;
|
};
|
|
|
/*PHYx + Sx*/
|
enum phl_phy_idx {
|
HW_PHY_0,
|
HW_PHY_1,
|
HW_PHY_MAX
|
};
|
|
enum phl_pwr_table {
|
PWR_BY_RATE = BIT0,
|
PWR_LIMIT = BIT1,
|
PWR_LIMIT_RU = BIT2
|
};
|
|
enum phl_rf_mode {
|
RF_MODE_NORMAL = 0,
|
RF_MODE_SHUTDOWN = 1,
|
RF_MODE_STANDBY = 2,
|
RF_MODE_RX = 3,
|
RF_MODE_TX = 4,
|
RF_MODE_MAX
|
};
|
|
enum phl_pwr_ctrl {
|
ALL_TIME_CTRL = 0,
|
GNT_TIME_CTRL,
|
PWR_CTRL_MAX
|
};
|
|
/*--------------------------[Structure]-------------------------------------*/
|
#if 0
|
enum rtw_tpu_op_mode {
|
TPU_NORMAL_MODE = 0,
|
TPU_DBG_MODE = 1
|
};
|
|
struct rtw_tpu_pwr_by_rate_info { /*TX Power Unit (TPU)*/
|
s8 pwr_by_rate_lgcy[TPU_SIZE_PWR_TAB_lGCY];
|
s8 pwr_by_rate[HAL_MAX_PATH][TPU_SIZE_PWR_TAB];
|
};
|
|
struct rtw_tpu_pwr_imt_info { /*TX Power Unit (TPU)*/
|
s8 pwr_lmt_cck_20m[HAL_MAX_PATH][TPU_SIZE_BF];
|
s8 pwr_lmt_cck_40m[HAL_MAX_PATH][TPU_SIZE_BF];
|
s8 pwr_lmt_lgcy_20m[HAL_MAX_PATH][TPU_SIZE_BF]; /*ofdm*/
|
s8 pwr_lmt_20m[HAL_MAX_PATH][TPU_SIZE_BW20_SC][TPU_SIZE_BF];
|
s8 pwr_lmt_40m[HAL_MAX_PATH][TPU_SIZE_BW40_SC][TPU_SIZE_BF];
|
s8 pwr_lmt_80m[HAL_MAX_PATH][TPU_SIZE_BW80_SC][TPU_SIZE_BF];
|
s8 pwr_lmt_160m[HAL_MAX_PATH][TPU_SIZE_BF];
|
s8 pwr_lmt_40m_0p5[HAL_MAX_PATH][TPU_SIZE_BF];
|
s8 pwr_lmt_40m_2p5[HAL_MAX_PATH][TPU_SIZE_BF];
|
};
|
|
struct rtw_tpu_info { /*TX Power Unit (TPU)*/
|
enum rtw_tpu_op_mode op_mode; /*In debug mode, only debug tool control TPU APIs*/
|
bool normal_mode_lock_en;
|
s8 ofst_int; /*SW: S(8,3) -16 ~ +15.875 (dB)*/
|
u8 ofst_fraction; /*[0:3] * 0.125(dBm)*/
|
enum hal_path ref_pow_path; /*Select the path with larger pow as the re_ path*/
|
u8 path_pow_ofst_decrease; /* Select the path with lower pow and subtract pow_path_ofst_decrease from path_ref*/
|
u8 base_cw_0db; /*[63~39~15]: [+24~0~-24 dBm]*/
|
u16 tssi_16dBm_cw;
|
/*[Ref Pwr]*/
|
s16 ref_pow_ofdm; /*-> HW: s(9,2)*/
|
s16 ref_pow_cck; /*-> HW: s(9,2)*/
|
u16 ref_pow_ofdm_cw; /*BBCR 0x58E0[9:0]*/
|
u16 ref_pow_cck_cw; /*BBCR 0x58E0[21:12]*/
|
/*[Pwr Ofsset]*/ /*-> HW: s(7,1)*/
|
s8 pwr_ofst_mode[TPU_SIZE_MODE]; /*0~4: HE, VHT, HT, Legacy, CCK, */
|
s8 pwr_ofst_bw[TPU_SIZE_BW]; /*0~4: 80_80, 160, 80, 40, 20*/
|
/*[Pwr By rate]*/ /*-> HW: s(7,1)*/
|
struct rtw_tpu_pwr_by_rate_info rtw_tpu_pwr_by_rate_i;
|
/*[Pwr Limit]*/ /*-> HW: s(7,1)*/
|
struct rtw_tpu_pwr_imt_info rtw_tpu_pwr_imt_i;
|
/*[Pwr Limit RUA]*/ /*-> HW: s(7,1)*/
|
s8 pwr_lmt_ru[HAL_MAX_PATH][TPU_SIZE_RUA][TPU_SIZE_BW20_SC];
|
u16 pwr_lmt_ru_mem_size;
|
bool pwr_lmt_en;
|
bool ext_pwr_lmt_en;
|
struct rtw_phl_ext_pwr_lmt_info ext_pwr_lmt_i;
|
u8 tx_ptrn_shap_idx;
|
u8 tx_ptrn_shap_idx_cck;
|
u16 pwr_constraint_mb;
|
};
|
#endif
|
struct rtw_hal_stat_info {
|
u32 cnt_fail_all;
|
u32 cnt_cck_fail;
|
u32 cnt_ofdm_fail;
|
u32 cnt_cca_all;
|
u32 cnt_ofdm_cca;
|
u32 cnt_cck_cca;
|
u32 cnt_crc32_error_all;
|
u32 cnt_he_crc32_error;
|
u32 cnt_vht_crc32_error;
|
u32 cnt_ht_crc32_error ;
|
u32 cnt_ofdm_crc32_error;
|
u32 cnt_cck_crc32_error;
|
u32 cnt_crc32_ok_all;
|
u32 cnt_he_crc32_ok;
|
u32 cnt_vht_crc32_ok;
|
u32 cnt_ht_crc32_ok;
|
u32 cnt_ofdm_crc32_ok;
|
u32 cnt_cck_crc32_ok;
|
u32 igi_fa_rssi;
|
};
|
|
struct rtw_hw_band {
|
struct rtw_chan_def cur_chandef;
|
u8 ppdu_sts_appen_info;
|
u8 ppdu_sts_filter;
|
struct rtw_tpu_info rtw_tpu_i; /*TX Power Unit (TPU)*/
|
union bb_tpu_all_info bb_tpu_all_i; /*TX Power Unit (TPU)*/
|
u16 tx_pause[PAUSE_RSON_MAX]; /* ref: enum rtw_sch_txen_cfg */
|
struct rtw_hal_stat_info stat_info;
|
u8 assoc_sta_cnt; /*number of associated nodes (sta or ap)*/
|
enum rtw_rx_fltr_opt_mode rx_fltr_opt_mode;
|
};
|
|
struct rtw_intr_t {
|
bool en;
|
u32 mask_dflt;
|
u32 mask;
|
u32 val;
|
};
|
|
struct rtw_hal_com_t {
|
enum rtw_chip_id chip_id;
|
enum rtw_cv cv;
|
enum rtw_cv acv;
|
enum rtw_fv fv;
|
|
struct ver_ctrl_t mac_vc;
|
struct ver_ctrl_t bb_vc;
|
struct ver_ctrl_t rf_vc;
|
struct ver_ctrl_t btc_vc;
|
struct ver_ctrl_t fw_vc;
|
|
struct protocol_cap_t proto_hw_cap[MAX_BAND_NUM]; /* wifi protocol capability from EFUSE/halmac/halbb/halrf/... */
|
struct phy_hw_cap_t phy_hw_cap[MAX_BAND_NUM]; /* phy capability from EFUSE/halmac/halbb/halrf/... */
|
struct dev_cap_t dev_hw_cap;
|
|
struct bus_hw_cap_t bus_hw_cap; /* Bus HW capability */
|
struct bus_cap_t bus_cap; /* Final bus capability */
|
struct hal_io_priv iopriv;
|
#ifdef DBG_HAL_MAC_MEM_MOINTOR
|
_os_atomic hal_mac_mem;
|
#endif
|
#ifdef DBG_HAL_MEM_MOINTOR
|
_os_atomic hal_mem;
|
#endif
|
bool is_hal_init;
|
struct rtw_hw_band band[MAX_BAND_NUM];/*band0/band1 for DBCC*/
|
|
bool dbcc_en;
|
u8 assoc_sta_cnt; /*number of associated nodes (sta or ap)*/
|
|
#ifdef RTW_WKARD_SINGLE_PATH_RSSI
|
enum rf_path cur_rx_rfpath;
|
#endif
|
#ifdef CONFIG_PCI_HCI /*TODO move to hal_info_t*/
|
/*interrupt*/
|
u32 int_array[4];
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u32 int_mask[4];
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u32 int_mask_default[4];
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struct rtw_intr_t _intr_ind[4];
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struct rtw_intr_t _intr[4];
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bool in_ps_intr_cfg;
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#ifdef PHL_RXSC_ISR
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u32 rx_int_array;
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#endif
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#endif /* CONFIG_PCI_HCI */
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#ifdef CONFIG_SDIO_HCI /*TODO move to hal_info_t*/
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u32 block_sz;
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/*interrupt*/
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/*
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* Change type of int_mask from u32 to unsigned long for bit operation
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* API, ex: _os_test_and_clear_bit() and _os_test_and_set_bit() .
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*/
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unsigned long int_mask;
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u32 int_mask_default;
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#endif /* CONFIG_SDIO_HCI */
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struct hal_int_array intr;
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#ifdef RTW_PHL_BCN
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struct bcn_entry_pool bcn_pool;
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#endif
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struct rtw_trx_stat trx_stat;
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void *hal_priv;/*pointer to hal_info*/
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void *drv_priv; /*drv priv*/
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void *csi_obj;
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void *bf_obj;
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void *snd_obj;
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struct hal_mu_score_tbl bb_mu_score_tbl;
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bool csi_para_ctrl_sel;
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struct btc_ctrl_t btc_ctrl;
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struct btc_fw_msg btc_msg;
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#ifdef RTW_WKARD_CCX_RPT_LIMIT_CTRL
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u8 spe_pkt_cnt_lmt;
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#endif
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u32 uuid;
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u8 scanofld_en;
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struct bacam_ctrl_t ba_ctl;
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};
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#define FL_CFG_OP_SET 0
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#define FL_CFG_OP_CLR 1
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#define FL_CFG_OP_INFO 2
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#define FL_CFG_TYPE_LEVEL 0
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#define FL_CFG_TYPE_OUTPUT 1
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#define FL_CFG_TYPE_COMP 2
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#define FL_CFG_TYPE_COMP_EXT 3
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#define FL_LV_OFF 0
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#define FL_LV_CRT 1
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#define FL_LV_SER 2
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#define FL_LV_WARN 3
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#define FL_LV_LOUD 4
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#define FL_LV_TR 5
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#define FL_OP_UART BIT0
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#define FL_OP_C2H BIT1
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#define FL_OP_SNI BIT2
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struct rtw_hal_fw_log_cfg {
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u32 level;
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u32 output;
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u32 comp;
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u32 comp_ext;
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};
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enum pkt_ofld_op_type {
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PKT_OFLD_ADD = 0,
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PKT_OFLD_DEL = 1,
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PKT_OFLD_READ = 2,
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PKT_OFLD_MAX
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};
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struct pkt_ofld_info {
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struct list_head req_q;
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u32 req_cnt;
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u8 id;
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};
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struct pkt_ofld_entry {
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struct list_head list;
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u16 macid;
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struct pkt_ofld_info pkt_info[PKT_OFLD_TYPE_MAX];
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};
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enum rtw_c2h_cat {
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C2H_CAT_TEST = 0,
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C2H_CAT_MAC = 1,
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C2H_CAT_OUTSRC = 2,
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C2H_CAT_MAX = 3
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};
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enum rtw_c2h_clas {
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C2H_CLS_PHYDM_MIN = 0,
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C2H_CLS_PHYDM_MAX = 7,
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C2H_CLS_RF_MIN = 8,
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C2H_CLS_RF_MAX = 0xf,
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C2H_CLS_BTC_MIN = 0x10,
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C2H_CLS_BTC_MAX = 0x17,
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C2H_CLS_MAX = 0x18
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};
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#define C2H_CLS_MAC_MIN 0x00
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#define C2H_CLS_MAC_MAX 0xFF
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enum rtw_hal_ps_pwr_req_src {
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HAL_BB_PWR_REQ = 0,
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HAL_RF_PWR_REQ = 1,
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HAL_MAC_PWR_REQ = 2,
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HAL_BTC_PWR_REQ = 3
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};
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struct rtw_hal_lps_info {
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u8 en;
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u16 macid;
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enum rtw_lps_listen_bcn_mode listen_bcn_mode;
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u8 awake_interval;
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enum rtw_lps_smart_ps_mode smart_ps_mode;
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u8 bcnnohit_en;
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u8 dyntxant_en;
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u8 maxtxant;
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u8 lpstxant;
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};
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struct rtw_hal_ips_info {
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u8 en;
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u16 macid;
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};
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enum ps_pwr_state {
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PS_PWR_STATE_ACTIVE = 0,
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PS_PWR_STATE_BAND0_RFON = 1,
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PS_PWR_STATE_BAND1_RFON = 2,
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PS_PWR_STATE_BAND0_RFOFF = 3,
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PS_PWR_STATE_BAND1_RFOFF = 4,
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PS_PWR_STATE_CLK_GATED = 5,
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PS_PWR_STATE_PWR_GATED = 6,
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PS_PWR_STATE_MAX,
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};
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#ifdef CONFIG_PHL_DFS
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struct hal_mac_dfs_rpt_cfg {
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bool rpt_en;
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u8 rpt_num_th;
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bool rpt_en_to;
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u8 rpt_to;
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};
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|
struct hal_dfs_rpt {
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u8 *dfs_ptr;
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u16 dfs_num;
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u8 phy_idx; /*phy0,phy1*/
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};
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#endif
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#ifdef CONFIG_WOWLAN
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struct rtw_hal_wow_cfg {
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struct rtw_keep_alive_info *keep_alive_cfg;
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struct rtw_disc_det_info *disc_det_cfg;
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struct rtw_nlo_info *nlo_cfg;
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struct rtw_arp_ofld_info *arp_ofld_cfg;
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struct rtw_ndp_ofld_info *ndp_ofld_cfg;
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struct rtw_gtk_ofld_info *gtk_ofld_cfg;
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struct rtw_realwow_info *realwow_cfg;
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struct rtw_wow_wake_info *wow_wake_cfg;
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struct rtw_pattern_match_info *pattern_match_info;
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struct rtw_wow_gpio_info *wow_gpio;
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struct rtw_periodic_wake_info *periodic_wake_cfg;
|
};
|
#endif /* CONFIG_WOWLAN */
|
|
|
enum hal_tsf_sync_act {
|
HAL_TSF_SYNC_NOW_ONCE = 0,
|
HAL_TSF_EN_SYNC_AUTO = 1,
|
HAL_TSF_DIS_SYNC_AUTO = 2,
|
};
|
|
struct watchdog_nhm_report {
|
u8 ccx_rpt_stamp;
|
u8 ccx_rpt_result;
|
s8 nhm_pwr_dbm;
|
u8 nhm_ratio;
|
};
|
|
#define GT3_TIMEOUT_MASK 0x0FFFFFFF
|
struct hal_mac_dbg_dump_cfg {
|
u32 ss_dbg_0;
|
u32 ss_dbg_1;
|
u8 ss_dbg;
|
u8 dle_dbg;
|
u8 dmac_dbg;
|
u8 cmac_dbg;
|
u8 mac_dbg_port;
|
u8 plersvd_dbg;
|
u8 tx_flow_dbg;
|
};
|
|
/**
|
* @enum rtw_hal_lps_flg_state
|
* @brief rtw_hal_lps_flg_state
|
*
|
* @var rtw_hal_lps_flg_state::RTW_HAL_LPS_FLG_STATE_ACTIVE
|
* Active mode or lps rf off
|
* @var rtw_hal_lps_flg_state::RTW_HAL_LPS_FLG_STATE_LPS
|
* Enter lps cg or lps pg
|
*
|
*/
|
enum rtw_hal_lps_flg_state {
|
RTW_HAL_LPS_FLG_STATE_ACTIVE = 0,
|
RTW_HAL_LPS_FLG_STATE_LPS = 1,
|
RTW_HAL_LPS_FLG_STATE_MAX,
|
};
|
|
struct hal_ppdu_sts_cfg {
|
u8 band_idx;
|
bool ppdu_stat_en;
|
u8 appen_info;
|
u8 filter;
|
bool towcpu;
|
bool todcpu;
|
};
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#endif /*_HAL_DEF_H_*/
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