/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HAL_API_TMP_H_
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#define _HAL_API_TMP_H_
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/**** may be get from hal_com **********************************/
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#define H2C_MSR_ROLE_RSVD 0
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#define H2C_MSR_ROLE_STA 1
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#define H2C_MSR_ROLE_AP 2
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#define H2C_MSR_ROLE_GC 3
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#define H2C_MSR_ROLE_GO 4
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#define H2C_MSR_ROLE_TDLS 5
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#define H2C_MSR_ROLE_ADHOC 6
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#define H2C_MSR_ROLE_MESH 7
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#define H2C_MSR_ROLE_MAX 8
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/*************************************************************************************/
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typedef enum _HW_VARIABLES {
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HW_VAR_NET_TYPE,
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HW_VAR_SET_OPMODE,
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HW_VAR_MAC_ADDR,
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HW_VAR_BSSID,
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HW_VAR_BASIC_RATE,
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HW_VAR_TXPAUSE,
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HW_VAR_BCN_FUNC,
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HW_VAR_CORRECT_TSF,
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HW_VAR_RCR,
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HW_VAR_MLME_DISCONNECT,
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HW_VAR_MLME_SITESURVEY,
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HW_VAR_MLME_JOIN,
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HW_VAR_ON_RCR_AM,
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HW_VAR_OFF_RCR_AM,
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HW_VAR_BEACON_INTERVAL,
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HW_VAR_SLOT_TIME,
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HW_VAR_RESP_SIFS,
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HW_VAR_ACK_PREAMBLE,
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HW_VAR_SEC_CFG,
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HW_VAR_SEC_DK_CFG,
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HW_VAR_BCN_VALID,
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HW_VAR_FREECNT,
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HW_VAR_STOP_BCN,
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HW_VAR_RESUME_BCN,
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/* PHYDM odm->SupportAbility */
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HW_VAR_CAM_EMPTY_ENTRY,
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HW_VAR_CAM_INVALID_ALL,
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HW_VAR_AC_PARAM_VO,
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HW_VAR_AC_PARAM_VI,
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HW_VAR_AC_PARAM_BE,
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HW_VAR_AC_PARAM_BK,
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HW_VAR_ACM_CTRL,
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HW_VAR_AMPDU_MIN_SPACE,
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#ifdef CONFIG_80211N_HT
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HW_VAR_AMPDU_FACTOR,
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#endif /* CONFIG_80211N_HT */
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HW_VAR_RXDMA_AGG_PG_TH,
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HW_VAR_SET_RPWM,
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HW_VAR_CPWM,
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HW_VAR_H2C_FW_PWRMODE,
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HW_VAR_H2C_INACTIVE_IPS,
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HW_VAR_H2C_FW_JOINBSSRPT,
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HW_VAR_TRIGGER_GPIO_0,
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HW_VAR_BT_SET_COEXIST,
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HW_VAR_BT_ISSUE_DELBA,
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HW_VAR_FIFO_CLEARN_UP,
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HW_VAR_RESTORE_HW_SEQ,
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HW_VAR_CHECK_TXBUF,
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HW_VAR_PCIE_STOP_TX_DMA,
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HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
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/* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
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/* Unit in microsecond. 0 means disable this function. */
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#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
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HW_VAR_WOWLAN,
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HW_VAR_WAKEUP_REASON,
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#endif
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HW_VAR_RPWM_TOG,
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#ifdef CONFIG_GPIO_WAKEUP
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HW_VAR_WOW_OUTPUT_GPIO,
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HW_VAR_WOW_INPUT_GPIO,
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HW_SET_GPIO_WL_CTRL,
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#endif
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HW_VAR_SYS_CLKR,
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HW_VAR_NAV_UPPER,
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HW_VAR_CHK_HI_QUEUE_EMPTY,
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HW_VAR_CHK_MGQ_CPU_EMPTY,
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HW_VAR_DL_BCN_SEL,
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HW_VAR_AMPDU_MAX_TIME,
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HW_VAR_WIRELESS_MODE,
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HW_VAR_USB_MODE,
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HW_VAR_PORT_SWITCH,
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HW_VAR_PORT_CFG,
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HW_VAR_SOUNDING_ENTER,
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HW_VAR_SOUNDING_LEAVE,
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HW_VAR_SOUNDING_RATE,
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HW_VAR_SOUNDING_STATUS,
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HW_VAR_SOUNDING_FW_NDPA,
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HW_VAR_SOUNDING_CLK,
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HW_VAR_SOUNDING_SET_GID_TABLE,
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HW_VAR_SOUNDING_CSI_REPORT,
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HW_VAR_DL_RSVD_PAGE,
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HW_VAR_DUMP_MAC_QUEUE_INFO,
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HW_VAR_ASIX_IOT,
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HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO,
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HW_VAR_CH_SW_IQK_INFO_BACKUP,
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HW_VAR_CH_SW_IQK_INFO_RESTORE,
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HW_VAR_DBI,
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HW_VAR_MDIO,
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HW_VAR_L1OFF_CAPABILITY,
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HW_VAR_L1OFF_NIC_SUPPORT,
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#ifdef CONFIG_TDLS
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#ifdef CONFIG_TDLS_CH_SW
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HW_VAR_TDLS_BCN_EARLY_C2H_RPT,
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#endif
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#endif
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HW_VAR_DUMP_MAC_TXFIFO,
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HW_VAR_PWR_CMD,
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HW_VAR_SET_SOML_PARAM,
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HW_VAR_ENABLE_RX_BAR,
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HW_VAR_TSF_AUTO_SYNC,
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HW_VAR_LPS_STATE_CHK,
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#ifdef CONFIG_RTS_FULL_BW
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HW_VAR_SET_RTS_BW,
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#endif
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#if defined(CONFIG_PCI_HCI)
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HW_VAR_ENSWBCN,
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#endif
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HW_VAR_ACKTO,
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HW_VAR_ACKTO_CCK,
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} HW_VARIABLES;
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static inline u8 rtw_hal_set_hwreg(_adapter *padapter, u8 var, u8 *val)
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{
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return 0;
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}
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static inline void rtw_hal_get_hwreg(_adapter *padapter, u8 var, u8 *val)
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{}
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typedef enum _HAL_DEF_VARIABLE {
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HAL_DEF_IS_SUPPORT_ANT_DIV,
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HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
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HAL_DEF_BEAMFORMER_CAP,
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HAL_DEF_BEAMFORMEE_CAP,
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HW_VAR_MAX_RX_AMPDU_FACTOR,
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HW_DEF_RA_INFO_DUMP,
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HAL_DEF_DBG_DUMP_TXPKT,
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HAL_DEF_TX_PAGE_SIZE,
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HW_VAR_BEST_AMPDU_DENSITY,
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} HAL_DEF_VARIABLE;
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static inline u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE def_var, void *val)
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{
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return 0;
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}
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u8 rtw_hal_get_def_var(struct _ADAPTER *a, struct _ADAPTER_LINK *alink,
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enum _HAL_DEF_VARIABLE def_var, void *val);
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static inline void rtw_hal_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key)
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{}
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static inline void rtw_hal_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
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{}
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static inline void rtw_hal_sec_clr_cam_ent(_adapter *adapter, u8 id)
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{}
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static inline bool rtw_hal_sec_read_cam_is_gk(_adapter *adapter, u8 id)
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{
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return _TRUE;
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}
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static inline void rtw_hal_linked_info_dump(_adapter *padapter, u8 benable)
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{}
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static inline bool rtw_hal_get_phy_edcca_flag(_adapter *adapter)
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{
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return _TRUE;
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}
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static inline u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port)
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{
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return 1;
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}
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static inline void rtw_hal_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num)
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{}
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/*u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num);*/
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static inline u8 rtw_hal_get_htndp_tx_rate(_adapter *adapter, u8 bfer_str_num)
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{
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return 0;
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}
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/*u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);*/
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static inline u8 rtw_hal_get_vht_ndp_tx_rate(_adapter *adapter, u8 bfer_str_num)
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{
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return 0;
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}
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static inline u8 rtw_hal_get_sounding_info(_adapter *adapter,u16 *throughput,
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u8 total_bfee_num, u16 *tx_rate)
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{
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return 0;
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}
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static inline void rtw_hal_dump_target_tx_power(void *sel, _adapter *adapter)
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{}
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static inline void rtw_hal_dump_trx_mode(void *sel, _adapter *adapter)
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{}
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#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED)
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#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
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#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0
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#endif
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#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
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void rtw_sw_led_blink_uc_trx_only(LED_DATA *led);
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void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl);
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#endif
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void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl);
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void rtw_led_tx_control(_adapter *adapter, const u8 *da);
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void rtw_led_rx_control(_adapter *adapter, const u8 *da);
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void rtw_led_set_iface_en(_adapter *adapter, u8 en);
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void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask);
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void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask);
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void rtw_led_set_ctl_en_mask_primary(_adapter *adapter);
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void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter);
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#else
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#define rtw_led_control(adapter, ctl) do {} while (0)
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#define rtw_led_tx_control(adapter, da) do {} while (0)
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#define rtw_led_rx_control(adapter, da) do {} while (0)
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#define rtw_led_set_iface_en(adapter, en) do {} while (0)
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#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0)
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#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0)
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#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0)
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#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0)
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#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */
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#ifdef CONFIG_PCI_HCI
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static inline u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
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{ return 0;}
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static inline u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
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{ return 0;}
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static inline u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
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{ return 0;}
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static inline void rtw_hal_unmap_beacon_icf(_adapter *padapter)
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{
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//hal->hal_ops.unmap_beacon_icf(padapter);
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}
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#endif
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#if defined(CONFIG_PCI_HCI)
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static inline u8 rtw_hal_check_nic_enough_desc_all(_adapter *padapter)
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{ return _SUCCESS;}
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#endif
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static inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
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{ return 0;}
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static inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
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{ return 0;}
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static inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
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{ return 0;}
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static inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
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{ return 0;}
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static void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len)
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{
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//adapter->dvobj->hal_func.hal_mac_c2h_handler(adapter, buf, len);
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}
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static inline s32 rtw_hal_fill_h2c_cmd(_adapter *padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
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{
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/*
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_adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
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if (GET_PHL_COM(pri_adapter)->fw_ready == _TRUE)
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return hal->hal_ops.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
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else if (padapter->registrypriv.mp_mode == 0)
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RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
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, FUNC_ADPT_ARG(padapter), ElementID);
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*/
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return 0;
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}
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static inline u8 rtw_hal_get_port(_adapter *adapter)
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{ return 0;}
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static inline void rtw_hal_read_edca(_adapter *adapter, u16 *vo_params, u16 *vi_params,
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u16 *be_params, u16 *bk_params)
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{
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//hal->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params);
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}
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/************************ xmit *******************/
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static inline void rtw_hal_bcn_param_setting(_adapter *padapter)
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{
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//hal->hal_ops.set_beacon_param_handler(padapter);
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}
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static inline void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
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{}
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/****************** GEORGIA_TODO_REDEFINE_IO ************************/
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static inline u32 rtw_hal_get_ltsf(_adapter *adapter)/*get tst low 4 bytes */
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{
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return 0;
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}
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static inline u32 rtw_hal_get_dma_statu(_adapter *adapter)
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{
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return 0;
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}
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#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
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static inline u8 rtw_hal_sdio_leave_suspend(_adapter *adapter)
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{
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return 0;
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}
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#endif
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static inline void rtw_hal_get_version(char *str, u32 len)
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{
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//get hal version
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//rtw_halmac_get_version(str, 30);
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// get fw version
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// get phy (bb/rf) version
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// get btc version
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}
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#endif /*_HAL_API_TMP_H_*/
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