// SPDX-License-Identifier: GPL-2.0
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/*
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* UCSI driver for Cypress CCGx Type-C controller
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*
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* Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
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* Author: Ajay Gupta <ajayg@nvidia.com>
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*
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* Some code borrowed from drivers/usb/typec/ucsi/ucsi_acpi.c
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*/
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/usb/typec_dp.h>
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#include <asm/unaligned.h>
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#include "ucsi.h"
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enum enum_fw_mode {
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BOOT, /* bootloader */
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FW1, /* FW partition-1 (contains secondary fw) */
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FW2, /* FW partition-2 (contains primary fw) */
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FW_INVALID,
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};
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#define CCGX_RAB_DEVICE_MODE 0x0000
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#define CCGX_RAB_INTR_REG 0x0006
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#define DEV_INT BIT(0)
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#define PORT0_INT BIT(1)
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#define PORT1_INT BIT(2)
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#define UCSI_READ_INT BIT(7)
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#define CCGX_RAB_JUMP_TO_BOOT 0x0007
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#define TO_BOOT 'J'
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#define TO_ALT_FW 'A'
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#define CCGX_RAB_RESET_REQ 0x0008
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#define RESET_SIG 'R'
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#define CMD_RESET_I2C 0x0
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#define CMD_RESET_DEV 0x1
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#define CCGX_RAB_ENTER_FLASHING 0x000A
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#define FLASH_ENTER_SIG 'P'
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#define CCGX_RAB_VALIDATE_FW 0x000B
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#define CCGX_RAB_FLASH_ROW_RW 0x000C
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#define FLASH_SIG 'F'
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#define FLASH_RD_CMD 0x0
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#define FLASH_WR_CMD 0x1
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#define FLASH_FWCT1_WR_CMD 0x2
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#define FLASH_FWCT2_WR_CMD 0x3
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#define FLASH_FWCT_SIG_WR_CMD 0x4
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#define CCGX_RAB_READ_ALL_VER 0x0010
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#define CCGX_RAB_READ_FW2_VER 0x0020
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#define CCGX_RAB_UCSI_CONTROL 0x0039
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#define CCGX_RAB_UCSI_CONTROL_START BIT(0)
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#define CCGX_RAB_UCSI_CONTROL_STOP BIT(1)
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#define CCGX_RAB_UCSI_DATA_BLOCK(offset) (0xf000 | ((offset) & 0xff))
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#define REG_FLASH_RW_MEM 0x0200
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#define DEV_REG_IDX CCGX_RAB_DEVICE_MODE
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#define CCGX_RAB_PDPORT_ENABLE 0x002C
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#define PDPORT_1 BIT(0)
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#define PDPORT_2 BIT(1)
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#define CCGX_RAB_RESPONSE 0x007E
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#define ASYNC_EVENT BIT(7)
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/* CCGx events & async msg codes */
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#define RESET_COMPLETE 0x80
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#define EVENT_INDEX RESET_COMPLETE
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#define PORT_CONNECT_DET 0x84
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#define PORT_DISCONNECT_DET 0x85
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#define ROLE_SWAP_COMPELETE 0x87
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/* ccg firmware */
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#define CYACD_LINE_SIZE 527
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#define CCG4_ROW_SIZE 256
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#define FW1_METADATA_ROW 0x1FF
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#define FW2_METADATA_ROW 0x1FE
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#define FW_CFG_TABLE_SIG_SIZE 256
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static int secondary_fw_min_ver = 41;
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enum enum_flash_mode {
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SECONDARY_BL, /* update secondary using bootloader */
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PRIMARY, /* update primary using secondary */
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SECONDARY, /* update secondary using primary */
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FLASH_NOT_NEEDED, /* update not required */
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FLASH_INVALID,
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};
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static const char * const ccg_fw_names[] = {
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"ccg_boot.cyacd",
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"ccg_primary.cyacd",
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"ccg_secondary.cyacd"
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};
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struct ccg_dev_info {
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#define CCG_DEVINFO_FWMODE_SHIFT (0)
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#define CCG_DEVINFO_FWMODE_MASK (0x3 << CCG_DEVINFO_FWMODE_SHIFT)
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#define CCG_DEVINFO_PDPORTS_SHIFT (2)
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#define CCG_DEVINFO_PDPORTS_MASK (0x3 << CCG_DEVINFO_PDPORTS_SHIFT)
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u8 mode;
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u8 bl_mode;
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__le16 silicon_id;
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__le16 bl_last_row;
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} __packed;
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struct version_format {
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__le16 build;
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u8 patch;
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u8 ver;
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#define CCG_VERSION_PATCH(x) ((x) << 16)
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#define CCG_VERSION(x) ((x) << 24)
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#define CCG_VERSION_MIN_SHIFT (0)
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#define CCG_VERSION_MIN_MASK (0xf << CCG_VERSION_MIN_SHIFT)
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#define CCG_VERSION_MAJ_SHIFT (4)
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#define CCG_VERSION_MAJ_MASK (0xf << CCG_VERSION_MAJ_SHIFT)
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} __packed;
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/*
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* Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
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* of missing interrupt when a device is connected for runtime resume
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*/
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#define CCG_FW_BUILD_NVIDIA (('n' << 8) | 'v')
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#define CCG_OLD_FW_VERSION (CCG_VERSION(0x31) | CCG_VERSION_PATCH(10))
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/* Altmode offset for NVIDIA Function Test Board (FTB) */
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#define NVIDIA_FTB_DP_OFFSET (2)
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#define NVIDIA_FTB_DBG_OFFSET (3)
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struct version_info {
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struct version_format base;
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struct version_format app;
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};
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struct fw_config_table {
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u32 identity;
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u16 table_size;
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u8 fwct_version;
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u8 is_key_change;
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u8 guid[16];
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struct version_format base;
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struct version_format app;
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u8 primary_fw_digest[32];
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u32 key_exp_length;
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u8 key_modulus[256];
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u8 key_exp[4];
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};
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/* CCGx response codes */
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enum ccg_resp_code {
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CMD_NO_RESP = 0x00,
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CMD_SUCCESS = 0x02,
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FLASH_DATA_AVAILABLE = 0x03,
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CMD_INVALID = 0x05,
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FLASH_UPDATE_FAIL = 0x07,
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INVALID_FW = 0x08,
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INVALID_ARG = 0x09,
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CMD_NOT_SUPPORT = 0x0A,
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TRANSACTION_FAIL = 0x0C,
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PD_CMD_FAIL = 0x0D,
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UNDEF_ERROR = 0x0F,
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INVALID_RESP = 0x10,
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};
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#define CCG_EVENT_MAX (EVENT_INDEX + 43)
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struct ccg_cmd {
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u16 reg;
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u32 data;
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int len;
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u32 delay; /* ms delay for cmd timeout */
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};
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struct ccg_resp {
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u8 code;
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u8 length;
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};
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struct ucsi_ccg_altmode {
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u16 svid;
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u32 mid;
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u8 linked_idx;
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u8 active_idx;
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#define UCSI_MULTI_DP_INDEX (0xff)
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bool checked;
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} __packed;
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struct ucsi_ccg {
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struct device *dev;
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struct ucsi *ucsi;
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struct i2c_client *client;
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struct ccg_dev_info info;
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/* version info for boot, primary and secondary */
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struct version_info version[FW2 + 1];
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u32 fw_version;
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/* CCG HPI communication flags */
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unsigned long flags;
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#define RESET_PENDING 0
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#define DEV_CMD_PENDING 1
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struct ccg_resp dev_resp;
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u8 cmd_resp;
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int port_num;
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int irq;
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struct work_struct work;
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struct mutex lock; /* to sync between user and driver thread */
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/* fw build with vendor information */
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u16 fw_build;
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struct work_struct pm_work;
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struct completion complete;
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u64 last_cmd_sent;
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bool has_multiple_dp;
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struct ucsi_ccg_altmode orig[UCSI_MAX_ALTMODES];
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struct ucsi_ccg_altmode updated[UCSI_MAX_ALTMODES];
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};
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static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
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{
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struct i2c_client *client = uc->client;
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const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
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unsigned char buf[2];
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struct i2c_msg msgs[] = {
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{
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.addr = client->addr,
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.flags = 0x0,
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.len = sizeof(buf),
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.buf = buf,
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},
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{
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.addr = client->addr,
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.flags = I2C_M_RD,
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.buf = data,
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},
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};
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u32 rlen, rem_len = len, max_read_len = len;
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int status;
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/* check any max_read_len limitation on i2c adapter */
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if (quirks && quirks->max_read_len)
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max_read_len = quirks->max_read_len;
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pm_runtime_get_sync(uc->dev);
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while (rem_len > 0) {
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msgs[1].buf = &data[len - rem_len];
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rlen = min_t(u16, rem_len, max_read_len);
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msgs[1].len = rlen;
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put_unaligned_le16(rab, buf);
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status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
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if (status < 0) {
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dev_err(uc->dev, "i2c_transfer failed %d\n", status);
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pm_runtime_put_sync(uc->dev);
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return status;
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}
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rab += rlen;
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rem_len -= rlen;
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}
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pm_runtime_put_sync(uc->dev);
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return 0;
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}
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static int ccg_write(struct ucsi_ccg *uc, u16 rab, const u8 *data, u32 len)
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{
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struct i2c_client *client = uc->client;
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unsigned char *buf;
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struct i2c_msg msgs[] = {
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{
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.addr = client->addr,
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.flags = 0x0,
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}
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};
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int status;
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buf = kzalloc(len + sizeof(rab), GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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put_unaligned_le16(rab, buf);
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memcpy(buf + sizeof(rab), data, len);
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msgs[0].len = len + sizeof(rab);
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msgs[0].buf = buf;
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pm_runtime_get_sync(uc->dev);
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status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
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if (status < 0) {
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dev_err(uc->dev, "i2c_transfer failed %d\n", status);
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pm_runtime_put_sync(uc->dev);
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kfree(buf);
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return status;
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}
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pm_runtime_put_sync(uc->dev);
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kfree(buf);
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return 0;
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}
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static int ucsi_ccg_init(struct ucsi_ccg *uc)
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{
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unsigned int count = 10;
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u8 data;
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int status;
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data = CCGX_RAB_UCSI_CONTROL_STOP;
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status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
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if (status < 0)
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return status;
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data = CCGX_RAB_UCSI_CONTROL_START;
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status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
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if (status < 0)
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return status;
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/*
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* Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control
|
* register write will push response which must be cleared.
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*/
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do {
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status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
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if (status < 0)
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return status;
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if (!(data & DEV_INT))
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return 0;
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status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
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if (status < 0)
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return status;
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usleep_range(10000, 11000);
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} while (--count);
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return -ETIMEDOUT;
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}
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static void ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg *uc, u8 *data)
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{
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u8 cam, new_cam;
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cam = data[0];
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new_cam = uc->orig[cam].linked_idx;
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uc->updated[new_cam].active_idx = cam;
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data[0] = new_cam;
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}
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static bool ucsi_ccg_update_altmodes(struct ucsi *ucsi,
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struct ucsi_altmode *orig,
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struct ucsi_altmode *updated)
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{
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struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
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struct ucsi_ccg_altmode *alt, *new_alt;
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int i, j, k = 0;
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bool found = false;
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alt = uc->orig;
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new_alt = uc->updated;
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memset(uc->updated, 0, sizeof(uc->updated));
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/*
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* Copy original connector altmodes to new structure.
|
* We need this before second loop since second loop
|
* checks for duplicate altmodes.
|
*/
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for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
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alt[i].svid = orig[i].svid;
|
alt[i].mid = orig[i].mid;
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if (!alt[i].svid)
|
break;
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}
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for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
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if (!alt[i].svid)
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break;
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/* already checked and considered */
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if (alt[i].checked)
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continue;
|
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if (!DP_CONF_GET_PIN_ASSIGN(alt[i].mid)) {
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/* Found Non DP altmode */
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new_alt[k].svid = alt[i].svid;
|
new_alt[k].mid |= alt[i].mid;
|
new_alt[k].linked_idx = i;
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alt[i].linked_idx = k;
|
updated[k].svid = new_alt[k].svid;
|
updated[k].mid = new_alt[k].mid;
|
k++;
|
continue;
|
}
|
|
for (j = i + 1; j < UCSI_MAX_ALTMODES; j++) {
|
if (alt[i].svid != alt[j].svid ||
|
!DP_CONF_GET_PIN_ASSIGN(alt[j].mid)) {
|
continue;
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} else {
|
/* Found duplicate DP mode */
|
new_alt[k].svid = alt[i].svid;
|
new_alt[k].mid |= alt[i].mid | alt[j].mid;
|
new_alt[k].linked_idx = UCSI_MULTI_DP_INDEX;
|
alt[i].linked_idx = k;
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alt[j].linked_idx = k;
|
alt[j].checked = true;
|
found = true;
|
}
|
}
|
if (found) {
|
uc->has_multiple_dp = true;
|
} else {
|
/* Didn't find any duplicate DP altmode */
|
new_alt[k].svid = alt[i].svid;
|
new_alt[k].mid |= alt[i].mid;
|
new_alt[k].linked_idx = i;
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alt[i].linked_idx = k;
|
}
|
updated[k].svid = new_alt[k].svid;
|
updated[k].mid = new_alt[k].mid;
|
k++;
|
}
|
return found;
|
}
|
|
static void ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg *uc,
|
struct ucsi_connector *con,
|
u64 *cmd)
|
{
|
struct ucsi_ccg_altmode *new_port, *port;
|
struct typec_altmode *alt = NULL;
|
u8 new_cam, cam, pin;
|
bool enter_new_mode;
|
int i, j, k = 0xff;
|
|
port = uc->orig;
|
new_cam = UCSI_SET_NEW_CAM_GET_AM(*cmd);
|
new_port = &uc->updated[new_cam];
|
cam = new_port->linked_idx;
|
enter_new_mode = UCSI_SET_NEW_CAM_ENTER(*cmd);
|
|
/*
|
* If CAM is UCSI_MULTI_DP_INDEX then this is DP altmode
|
* with multiple DP mode. Find out CAM for best pin assignment
|
* among all DP mode. Priorite pin E->D->C after making sure
|
* the partner supports that pin.
|
*/
|
if (cam == UCSI_MULTI_DP_INDEX) {
|
if (enter_new_mode) {
|
for (i = 0; con->partner_altmode[i]; i++) {
|
alt = con->partner_altmode[i];
|
if (alt->svid == new_port->svid)
|
break;
|
}
|
/*
|
* alt will always be non NULL since this is
|
* UCSI_SET_NEW_CAM command and so there will be
|
* at least one con->partner_altmode[i] with svid
|
* matching with new_port->svid.
|
*/
|
for (j = 0; port[j].svid; j++) {
|
pin = DP_CONF_GET_PIN_ASSIGN(port[j].mid);
|
if (alt && port[j].svid == alt->svid &&
|
(pin & DP_CONF_GET_PIN_ASSIGN(alt->vdo))) {
|
/* prioritize pin E->D->C */
|
if (k == 0xff || (k != 0xff && pin >
|
DP_CONF_GET_PIN_ASSIGN(port[k].mid))
|
) {
|
k = j;
|
}
|
}
|
}
|
cam = k;
|
new_port->active_idx = cam;
|
} else {
|
cam = new_port->active_idx;
|
}
|
}
|
*cmd &= ~UCSI_SET_NEW_CAM_AM_MASK;
|
*cmd |= UCSI_SET_NEW_CAM_SET_AM(cam);
|
}
|
|
/*
|
* Change the order of vdo values of NVIDIA test device FTB
|
* (Function Test Board) which reports altmode list with vdo=0x3
|
* first and then vdo=0x. Current logic to assign mode value is
|
* based on order in altmode list and it causes a mismatch of CON
|
* and SOP altmodes since NVIDIA GPU connector has order of vdo=0x1
|
* first and then vdo=0x3
|
*/
|
static void ucsi_ccg_nvidia_altmode(struct ucsi_ccg *uc,
|
struct ucsi_altmode *alt)
|
{
|
switch (UCSI_ALTMODE_OFFSET(uc->last_cmd_sent)) {
|
case NVIDIA_FTB_DP_OFFSET:
|
if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DBG_VDO)
|
alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DP_VDO |
|
DP_CAP_DP_SIGNALING | DP_CAP_USB |
|
DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_E));
|
break;
|
case NVIDIA_FTB_DBG_OFFSET:
|
if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DP_VDO)
|
alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DBG_VDO;
|
break;
|
default:
|
break;
|
}
|
}
|
|
static int ucsi_ccg_read(struct ucsi *ucsi, unsigned int offset,
|
void *val, size_t val_len)
|
{
|
struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
|
u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(offset);
|
struct ucsi_altmode *alt;
|
int ret;
|
|
ret = ccg_read(uc, reg, val, val_len);
|
if (ret)
|
return ret;
|
|
if (offset != UCSI_MESSAGE_IN)
|
return ret;
|
|
switch (UCSI_COMMAND(uc->last_cmd_sent)) {
|
case UCSI_GET_CURRENT_CAM:
|
if (uc->has_multiple_dp)
|
ucsi_ccg_update_get_current_cam_cmd(uc, (u8 *)val);
|
break;
|
case UCSI_GET_ALTERNATE_MODES:
|
if (UCSI_ALTMODE_RECIPIENT(uc->last_cmd_sent) ==
|
UCSI_RECIPIENT_SOP) {
|
alt = val;
|
if (alt[0].svid == USB_TYPEC_NVIDIA_VLINK_SID)
|
ucsi_ccg_nvidia_altmode(uc, alt);
|
}
|
break;
|
default:
|
break;
|
}
|
uc->last_cmd_sent = 0;
|
|
return ret;
|
}
|
|
static int ucsi_ccg_async_write(struct ucsi *ucsi, unsigned int offset,
|
const void *val, size_t val_len)
|
{
|
u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(offset);
|
|
return ccg_write(ucsi_get_drvdata(ucsi), reg, val, val_len);
|
}
|
|
static int ucsi_ccg_sync_write(struct ucsi *ucsi, unsigned int offset,
|
const void *val, size_t val_len)
|
{
|
struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
|
struct ucsi_connector *con;
|
int con_index;
|
int ret;
|
|
mutex_lock(&uc->lock);
|
pm_runtime_get_sync(uc->dev);
|
set_bit(DEV_CMD_PENDING, &uc->flags);
|
|
if (offset == UCSI_CONTROL && val_len == sizeof(uc->last_cmd_sent)) {
|
uc->last_cmd_sent = *(u64 *)val;
|
|
if (UCSI_COMMAND(uc->last_cmd_sent) == UCSI_SET_NEW_CAM &&
|
uc->has_multiple_dp) {
|
con_index = (uc->last_cmd_sent >> 16) &
|
UCSI_CMD_CONNECTOR_MASK;
|
con = &uc->ucsi->connector[con_index - 1];
|
ucsi_ccg_update_set_new_cam_cmd(uc, con, (u64 *)val);
|
}
|
}
|
|
ret = ucsi_ccg_async_write(ucsi, offset, val, val_len);
|
if (ret)
|
goto err_clear_bit;
|
|
if (!wait_for_completion_timeout(&uc->complete, msecs_to_jiffies(5000)))
|
ret = -ETIMEDOUT;
|
|
err_clear_bit:
|
clear_bit(DEV_CMD_PENDING, &uc->flags);
|
pm_runtime_put_sync(uc->dev);
|
mutex_unlock(&uc->lock);
|
|
return ret;
|
}
|
|
static const struct ucsi_operations ucsi_ccg_ops = {
|
.read = ucsi_ccg_read,
|
.sync_write = ucsi_ccg_sync_write,
|
.async_write = ucsi_ccg_async_write,
|
.update_altmodes = ucsi_ccg_update_altmodes
|
};
|
|
static irqreturn_t ccg_irq_handler(int irq, void *data)
|
{
|
u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CCI);
|
struct ucsi_ccg *uc = data;
|
u8 intr_reg;
|
u32 cci;
|
int ret;
|
|
ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
|
if (ret)
|
return ret;
|
|
ret = ccg_read(uc, reg, (void *)&cci, sizeof(cci));
|
if (ret)
|
goto err_clear_irq;
|
|
if (UCSI_CCI_CONNECTOR(cci))
|
ucsi_connector_change(uc->ucsi, UCSI_CCI_CONNECTOR(cci));
|
|
if (test_bit(DEV_CMD_PENDING, &uc->flags) &&
|
cci & (UCSI_CCI_ACK_COMPLETE | UCSI_CCI_COMMAND_COMPLETE))
|
complete(&uc->complete);
|
|
err_clear_irq:
|
ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
|
|
return IRQ_HANDLED;
|
}
|
|
static void ccg_pm_workaround_work(struct work_struct *pm_work)
|
{
|
ccg_irq_handler(0, container_of(pm_work, struct ucsi_ccg, pm_work));
|
}
|
|
static int get_fw_info(struct ucsi_ccg *uc)
|
{
|
int err;
|
|
err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)(&uc->version),
|
sizeof(uc->version));
|
if (err < 0)
|
return err;
|
|
uc->fw_version = CCG_VERSION(uc->version[FW2].app.ver) |
|
CCG_VERSION_PATCH(uc->version[FW2].app.patch);
|
|
err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
|
sizeof(uc->info));
|
if (err < 0)
|
return err;
|
|
return 0;
|
}
|
|
static inline bool invalid_async_evt(int code)
|
{
|
return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX);
|
}
|
|
static void ccg_process_response(struct ucsi_ccg *uc)
|
{
|
struct device *dev = uc->dev;
|
|
if (uc->dev_resp.code & ASYNC_EVENT) {
|
if (uc->dev_resp.code == RESET_COMPLETE) {
|
if (test_bit(RESET_PENDING, &uc->flags))
|
uc->cmd_resp = uc->dev_resp.code;
|
get_fw_info(uc);
|
}
|
if (invalid_async_evt(uc->dev_resp.code))
|
dev_err(dev, "invalid async evt %d\n",
|
uc->dev_resp.code);
|
} else {
|
if (test_bit(DEV_CMD_PENDING, &uc->flags)) {
|
uc->cmd_resp = uc->dev_resp.code;
|
clear_bit(DEV_CMD_PENDING, &uc->flags);
|
} else {
|
dev_err(dev, "dev resp 0x%04x but no cmd pending\n",
|
uc->dev_resp.code);
|
}
|
}
|
}
|
|
static int ccg_read_response(struct ucsi_ccg *uc)
|
{
|
unsigned long target = jiffies + msecs_to_jiffies(1000);
|
struct device *dev = uc->dev;
|
u8 intval;
|
int status;
|
|
/* wait for interrupt status to get updated */
|
do {
|
status = ccg_read(uc, CCGX_RAB_INTR_REG, &intval,
|
sizeof(intval));
|
if (status < 0)
|
return status;
|
|
if (intval & DEV_INT)
|
break;
|
usleep_range(500, 600);
|
} while (time_is_after_jiffies(target));
|
|
if (time_is_before_jiffies(target)) {
|
dev_err(dev, "response timeout error\n");
|
return -ETIME;
|
}
|
|
status = ccg_read(uc, CCGX_RAB_RESPONSE, (u8 *)&uc->dev_resp,
|
sizeof(uc->dev_resp));
|
if (status < 0)
|
return status;
|
|
status = ccg_write(uc, CCGX_RAB_INTR_REG, &intval, sizeof(intval));
|
if (status < 0)
|
return status;
|
|
return 0;
|
}
|
|
/* Caller must hold uc->lock */
|
static int ccg_send_command(struct ucsi_ccg *uc, struct ccg_cmd *cmd)
|
{
|
struct device *dev = uc->dev;
|
int ret;
|
|
switch (cmd->reg & 0xF000) {
|
case DEV_REG_IDX:
|
set_bit(DEV_CMD_PENDING, &uc->flags);
|
break;
|
default:
|
dev_err(dev, "invalid cmd register\n");
|
break;
|
}
|
|
ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len);
|
if (ret < 0)
|
return ret;
|
|
msleep(cmd->delay);
|
|
ret = ccg_read_response(uc);
|
if (ret < 0) {
|
dev_err(dev, "response read error\n");
|
switch (cmd->reg & 0xF000) {
|
case DEV_REG_IDX:
|
clear_bit(DEV_CMD_PENDING, &uc->flags);
|
break;
|
default:
|
dev_err(dev, "invalid cmd register\n");
|
break;
|
}
|
return -EIO;
|
}
|
ccg_process_response(uc);
|
|
return uc->cmd_resp;
|
}
|
|
static int ccg_cmd_enter_flashing(struct ucsi_ccg *uc)
|
{
|
struct ccg_cmd cmd;
|
int ret;
|
|
cmd.reg = CCGX_RAB_ENTER_FLASHING;
|
cmd.data = FLASH_ENTER_SIG;
|
cmd.len = 1;
|
cmd.delay = 50;
|
|
mutex_lock(&uc->lock);
|
|
ret = ccg_send_command(uc, &cmd);
|
|
mutex_unlock(&uc->lock);
|
|
if (ret != CMD_SUCCESS) {
|
dev_err(uc->dev, "enter flashing failed ret=%d\n", ret);
|
return ret;
|
}
|
|
return 0;
|
}
|
|
static int ccg_cmd_reset(struct ucsi_ccg *uc)
|
{
|
struct ccg_cmd cmd;
|
u8 *p;
|
int ret;
|
|
p = (u8 *)&cmd.data;
|
cmd.reg = CCGX_RAB_RESET_REQ;
|
p[0] = RESET_SIG;
|
p[1] = CMD_RESET_DEV;
|
cmd.len = 2;
|
cmd.delay = 5000;
|
|
mutex_lock(&uc->lock);
|
|
set_bit(RESET_PENDING, &uc->flags);
|
|
ret = ccg_send_command(uc, &cmd);
|
if (ret != RESET_COMPLETE)
|
goto err_clear_flag;
|
|
ret = 0;
|
|
err_clear_flag:
|
clear_bit(RESET_PENDING, &uc->flags);
|
|
mutex_unlock(&uc->lock);
|
|
return ret;
|
}
|
|
static int ccg_cmd_port_control(struct ucsi_ccg *uc, bool enable)
|
{
|
struct ccg_cmd cmd;
|
int ret;
|
|
cmd.reg = CCGX_RAB_PDPORT_ENABLE;
|
if (enable)
|
cmd.data = (uc->port_num == 1) ?
|
PDPORT_1 : (PDPORT_1 | PDPORT_2);
|
else
|
cmd.data = 0x0;
|
cmd.len = 1;
|
cmd.delay = 10;
|
|
mutex_lock(&uc->lock);
|
|
ret = ccg_send_command(uc, &cmd);
|
|
mutex_unlock(&uc->lock);
|
|
if (ret != CMD_SUCCESS) {
|
dev_err(uc->dev, "port control failed ret=%d\n", ret);
|
return ret;
|
}
|
return 0;
|
}
|
|
static int ccg_cmd_jump_boot_mode(struct ucsi_ccg *uc, int bl_mode)
|
{
|
struct ccg_cmd cmd;
|
int ret;
|
|
cmd.reg = CCGX_RAB_JUMP_TO_BOOT;
|
|
if (bl_mode)
|
cmd.data = TO_BOOT;
|
else
|
cmd.data = TO_ALT_FW;
|
|
cmd.len = 1;
|
cmd.delay = 100;
|
|
mutex_lock(&uc->lock);
|
|
set_bit(RESET_PENDING, &uc->flags);
|
|
ret = ccg_send_command(uc, &cmd);
|
if (ret != RESET_COMPLETE)
|
goto err_clear_flag;
|
|
ret = 0;
|
|
err_clear_flag:
|
clear_bit(RESET_PENDING, &uc->flags);
|
|
mutex_unlock(&uc->lock);
|
|
return ret;
|
}
|
|
static int
|
ccg_cmd_write_flash_row(struct ucsi_ccg *uc, u16 row,
|
const void *data, u8 fcmd)
|
{
|
struct i2c_client *client = uc->client;
|
struct ccg_cmd cmd;
|
u8 buf[CCG4_ROW_SIZE + 2];
|
u8 *p;
|
int ret;
|
|
/* Copy the data into the flash read/write memory. */
|
put_unaligned_le16(REG_FLASH_RW_MEM, buf);
|
|
memcpy(buf + 2, data, CCG4_ROW_SIZE);
|
|
mutex_lock(&uc->lock);
|
|
ret = i2c_master_send(client, buf, CCG4_ROW_SIZE + 2);
|
if (ret != CCG4_ROW_SIZE + 2) {
|
dev_err(uc->dev, "REG_FLASH_RW_MEM write fail %d\n", ret);
|
mutex_unlock(&uc->lock);
|
return ret < 0 ? ret : -EIO;
|
}
|
|
/* Use the FLASH_ROW_READ_WRITE register to trigger */
|
/* writing of data to the desired flash row */
|
p = (u8 *)&cmd.data;
|
cmd.reg = CCGX_RAB_FLASH_ROW_RW;
|
p[0] = FLASH_SIG;
|
p[1] = fcmd;
|
put_unaligned_le16(row, &p[2]);
|
cmd.len = 4;
|
cmd.delay = 50;
|
if (fcmd == FLASH_FWCT_SIG_WR_CMD)
|
cmd.delay += 400;
|
if (row == 510)
|
cmd.delay += 220;
|
ret = ccg_send_command(uc, &cmd);
|
|
mutex_unlock(&uc->lock);
|
|
if (ret != CMD_SUCCESS) {
|
dev_err(uc->dev, "write flash row failed ret=%d\n", ret);
|
return ret;
|
}
|
|
return 0;
|
}
|
|
static int ccg_cmd_validate_fw(struct ucsi_ccg *uc, unsigned int fwid)
|
{
|
struct ccg_cmd cmd;
|
int ret;
|
|
cmd.reg = CCGX_RAB_VALIDATE_FW;
|
cmd.data = fwid;
|
cmd.len = 1;
|
cmd.delay = 500;
|
|
mutex_lock(&uc->lock);
|
|
ret = ccg_send_command(uc, &cmd);
|
|
mutex_unlock(&uc->lock);
|
|
if (ret != CMD_SUCCESS)
|
return ret;
|
|
return 0;
|
}
|
|
static bool ccg_check_vendor_version(struct ucsi_ccg *uc,
|
struct version_format *app,
|
struct fw_config_table *fw_cfg)
|
{
|
struct device *dev = uc->dev;
|
|
/* Check if the fw build is for supported vendors */
|
if (le16_to_cpu(app->build) != uc->fw_build) {
|
dev_info(dev, "current fw is not from supported vendor\n");
|
return false;
|
}
|
|
/* Check if the new fw build is for supported vendors */
|
if (le16_to_cpu(fw_cfg->app.build) != uc->fw_build) {
|
dev_info(dev, "new fw is not from supported vendor\n");
|
return false;
|
}
|
return true;
|
}
|
|
static bool ccg_check_fw_version(struct ucsi_ccg *uc, const char *fw_name,
|
struct version_format *app)
|
{
|
const struct firmware *fw = NULL;
|
struct device *dev = uc->dev;
|
struct fw_config_table fw_cfg;
|
u32 cur_version, new_version;
|
bool is_later = false;
|
|
if (request_firmware(&fw, fw_name, dev) != 0) {
|
dev_err(dev, "error: Failed to open cyacd file %s\n", fw_name);
|
return false;
|
}
|
|
/*
|
* check if signed fw
|
* last part of fw image is fw cfg table and signature
|
*/
|
if (fw->size < sizeof(fw_cfg) + FW_CFG_TABLE_SIG_SIZE)
|
goto out_release_firmware;
|
|
memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
|
sizeof(fw_cfg) - FW_CFG_TABLE_SIG_SIZE, sizeof(fw_cfg));
|
|
if (fw_cfg.identity != ('F' | 'W' << 8 | 'C' << 16 | 'T' << 24)) {
|
dev_info(dev, "not a signed image\n");
|
goto out_release_firmware;
|
}
|
|
/* compare input version with FWCT version */
|
cur_version = le16_to_cpu(app->build) | CCG_VERSION_PATCH(app->patch) |
|
CCG_VERSION(app->ver);
|
|
new_version = le16_to_cpu(fw_cfg.app.build) |
|
CCG_VERSION_PATCH(fw_cfg.app.patch) |
|
CCG_VERSION(fw_cfg.app.ver);
|
|
if (!ccg_check_vendor_version(uc, app, &fw_cfg))
|
goto out_release_firmware;
|
|
if (new_version > cur_version)
|
is_later = true;
|
|
out_release_firmware:
|
release_firmware(fw);
|
return is_later;
|
}
|
|
static int ccg_fw_update_needed(struct ucsi_ccg *uc,
|
enum enum_flash_mode *mode)
|
{
|
struct device *dev = uc->dev;
|
int err;
|
struct version_info version[3];
|
|
err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
|
sizeof(uc->info));
|
if (err) {
|
dev_err(dev, "read device mode failed\n");
|
return err;
|
}
|
|
err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)version,
|
sizeof(version));
|
if (err) {
|
dev_err(dev, "read device mode failed\n");
|
return err;
|
}
|
|
if (memcmp(&version[FW1], "\0\0\0\0\0\0\0\0",
|
sizeof(struct version_info)) == 0) {
|
dev_info(dev, "secondary fw is not flashed\n");
|
*mode = SECONDARY_BL;
|
} else if (le16_to_cpu(version[FW1].base.build) <
|
secondary_fw_min_ver) {
|
dev_info(dev, "secondary fw version is too low (< %d)\n",
|
secondary_fw_min_ver);
|
*mode = SECONDARY;
|
} else if (memcmp(&version[FW2], "\0\0\0\0\0\0\0\0",
|
sizeof(struct version_info)) == 0) {
|
dev_info(dev, "primary fw is not flashed\n");
|
*mode = PRIMARY;
|
} else if (ccg_check_fw_version(uc, ccg_fw_names[PRIMARY],
|
&version[FW2].app)) {
|
dev_info(dev, "found primary fw with later version\n");
|
*mode = PRIMARY;
|
} else {
|
dev_info(dev, "secondary and primary fw are the latest\n");
|
*mode = FLASH_NOT_NEEDED;
|
}
|
return 0;
|
}
|
|
static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)
|
{
|
struct device *dev = uc->dev;
|
const struct firmware *fw = NULL;
|
const char *p, *s;
|
const char *eof;
|
int err, row, len, line_sz, line_cnt = 0;
|
unsigned long start_time = jiffies;
|
struct fw_config_table fw_cfg;
|
u8 fw_cfg_sig[FW_CFG_TABLE_SIG_SIZE];
|
u8 *wr_buf;
|
|
err = request_firmware(&fw, ccg_fw_names[mode], dev);
|
if (err) {
|
dev_err(dev, "request %s failed err=%d\n",
|
ccg_fw_names[mode], err);
|
return err;
|
}
|
|
if (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >>
|
CCG_DEVINFO_FWMODE_SHIFT) == FW2) {
|
err = ccg_cmd_port_control(uc, false);
|
if (err < 0)
|
goto release_fw;
|
err = ccg_cmd_jump_boot_mode(uc, 0);
|
if (err < 0)
|
goto release_fw;
|
}
|
|
eof = fw->data + fw->size;
|
|
/*
|
* check if signed fw
|
* last part of fw image is fw cfg table and signature
|
*/
|
if (fw->size < sizeof(fw_cfg) + sizeof(fw_cfg_sig))
|
goto not_signed_fw;
|
|
memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
|
sizeof(fw_cfg) - sizeof(fw_cfg_sig), sizeof(fw_cfg));
|
|
if (fw_cfg.identity != ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) {
|
dev_info(dev, "not a signed image\n");
|
goto not_signed_fw;
|
}
|
eof = fw->data + fw->size - sizeof(fw_cfg) - sizeof(fw_cfg_sig);
|
|
memcpy((uint8_t *)&fw_cfg_sig,
|
fw->data + fw->size - sizeof(fw_cfg_sig), sizeof(fw_cfg_sig));
|
|
/* flash fw config table and signature first */
|
err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg,
|
FLASH_FWCT1_WR_CMD);
|
if (err)
|
goto release_fw;
|
|
err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE,
|
FLASH_FWCT2_WR_CMD);
|
if (err)
|
goto release_fw;
|
|
err = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig,
|
FLASH_FWCT_SIG_WR_CMD);
|
if (err)
|
goto release_fw;
|
|
not_signed_fw:
|
wr_buf = kzalloc(CCG4_ROW_SIZE + 4, GFP_KERNEL);
|
if (!wr_buf) {
|
err = -ENOMEM;
|
goto release_fw;
|
}
|
|
err = ccg_cmd_enter_flashing(uc);
|
if (err)
|
goto release_mem;
|
|
/*****************************************************************
|
* CCG firmware image (.cyacd) file line format
|
*
|
* :00rrrrllll[dd....]cc/r/n
|
*
|
* :00 header
|
* rrrr is row number to flash (4 char)
|
* llll is data len to flash (4 char)
|
* dd is a data field represents one byte of data (512 char)
|
* cc is checksum (2 char)
|
* \r\n newline
|
*
|
* Total length: 3 + 4 + 4 + 512 + 2 + 2 = 527
|
*
|
*****************************************************************/
|
|
p = strnchr(fw->data, fw->size, ':');
|
while (p < eof) {
|
s = strnchr(p + 1, eof - p - 1, ':');
|
|
if (!s)
|
s = eof;
|
|
line_sz = s - p;
|
|
if (line_sz != CYACD_LINE_SIZE) {
|
dev_err(dev, "Bad FW format line_sz=%d\n", line_sz);
|
err = -EINVAL;
|
goto release_mem;
|
}
|
|
if (hex2bin(wr_buf, p + 3, CCG4_ROW_SIZE + 4)) {
|
err = -EINVAL;
|
goto release_mem;
|
}
|
|
row = get_unaligned_be16(wr_buf);
|
len = get_unaligned_be16(&wr_buf[2]);
|
|
if (len != CCG4_ROW_SIZE) {
|
err = -EINVAL;
|
goto release_mem;
|
}
|
|
err = ccg_cmd_write_flash_row(uc, row, wr_buf + 4,
|
FLASH_WR_CMD);
|
if (err)
|
goto release_mem;
|
|
line_cnt++;
|
p = s;
|
}
|
|
dev_info(dev, "total %d row flashed. time: %dms\n",
|
line_cnt, jiffies_to_msecs(jiffies - start_time));
|
|
err = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 : FW1);
|
if (err)
|
dev_err(dev, "%s validation failed err=%d\n",
|
(mode == PRIMARY) ? "FW2" : "FW1", err);
|
else
|
dev_info(dev, "%s validated\n",
|
(mode == PRIMARY) ? "FW2" : "FW1");
|
|
err = ccg_cmd_port_control(uc, false);
|
if (err < 0)
|
goto release_mem;
|
|
err = ccg_cmd_reset(uc);
|
if (err < 0)
|
goto release_mem;
|
|
err = ccg_cmd_port_control(uc, true);
|
if (err < 0)
|
goto release_mem;
|
|
release_mem:
|
kfree(wr_buf);
|
|
release_fw:
|
release_firmware(fw);
|
return err;
|
}
|
|
/*******************************************************************************
|
* CCG4 has two copies of the firmware in addition to the bootloader.
|
* If the device is running FW1, FW2 can be updated with the new version.
|
* Dual firmware mode allows the CCG device to stay in a PD contract and support
|
* USB PD and Type-C functionality while a firmware update is in progress.
|
******************************************************************************/
|
static int ccg_fw_update(struct ucsi_ccg *uc, enum enum_flash_mode flash_mode)
|
{
|
int err = 0;
|
|
while (flash_mode != FLASH_NOT_NEEDED) {
|
err = do_flash(uc, flash_mode);
|
if (err < 0)
|
return err;
|
err = ccg_fw_update_needed(uc, &flash_mode);
|
if (err < 0)
|
return err;
|
}
|
dev_info(uc->dev, "CCG FW update successful\n");
|
|
return err;
|
}
|
|
static int ccg_restart(struct ucsi_ccg *uc)
|
{
|
struct device *dev = uc->dev;
|
int status;
|
|
status = ucsi_ccg_init(uc);
|
if (status < 0) {
|
dev_err(dev, "ucsi_ccg_start fail, err=%d\n", status);
|
return status;
|
}
|
|
status = request_threaded_irq(uc->irq, NULL, ccg_irq_handler,
|
IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
|
dev_name(dev), uc);
|
if (status < 0) {
|
dev_err(dev, "request_threaded_irq failed - %d\n", status);
|
return status;
|
}
|
|
status = ucsi_register(uc->ucsi);
|
if (status) {
|
dev_err(uc->dev, "failed to register the interface\n");
|
return status;
|
}
|
|
pm_runtime_enable(uc->dev);
|
return 0;
|
}
|
|
static void ccg_update_firmware(struct work_struct *work)
|
{
|
struct ucsi_ccg *uc = container_of(work, struct ucsi_ccg, work);
|
enum enum_flash_mode flash_mode;
|
int status;
|
|
status = ccg_fw_update_needed(uc, &flash_mode);
|
if (status < 0)
|
return;
|
|
if (flash_mode != FLASH_NOT_NEEDED) {
|
ucsi_unregister(uc->ucsi);
|
pm_runtime_disable(uc->dev);
|
free_irq(uc->irq, uc);
|
|
ccg_fw_update(uc, flash_mode);
|
ccg_restart(uc);
|
}
|
}
|
|
static ssize_t do_flash_store(struct device *dev,
|
struct device_attribute *attr,
|
const char *buf, size_t n)
|
{
|
struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev));
|
bool flash;
|
|
if (kstrtobool(buf, &flash))
|
return -EINVAL;
|
|
if (!flash)
|
return n;
|
|
if (uc->fw_build == 0x0) {
|
dev_err(dev, "fail to flash FW due to missing FW build info\n");
|
return -EINVAL;
|
}
|
|
schedule_work(&uc->work);
|
return n;
|
}
|
|
static DEVICE_ATTR_WO(do_flash);
|
|
static struct attribute *ucsi_ccg_attrs[] = {
|
&dev_attr_do_flash.attr,
|
NULL,
|
};
|
ATTRIBUTE_GROUPS(ucsi_ccg);
|
|
static int ucsi_ccg_probe(struct i2c_client *client,
|
const struct i2c_device_id *id)
|
{
|
struct device *dev = &client->dev;
|
struct ucsi_ccg *uc;
|
int status;
|
|
uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL);
|
if (!uc)
|
return -ENOMEM;
|
|
uc->dev = dev;
|
uc->client = client;
|
mutex_init(&uc->lock);
|
init_completion(&uc->complete);
|
INIT_WORK(&uc->work, ccg_update_firmware);
|
INIT_WORK(&uc->pm_work, ccg_pm_workaround_work);
|
|
/* Only fail FW flashing when FW build information is not provided */
|
status = device_property_read_u16(dev, "ccgx,firmware-build",
|
&uc->fw_build);
|
if (status)
|
dev_err(uc->dev, "failed to get FW build information\n");
|
|
/* reset ccg device and initialize ucsi */
|
status = ucsi_ccg_init(uc);
|
if (status < 0) {
|
dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status);
|
return status;
|
}
|
|
status = get_fw_info(uc);
|
if (status < 0) {
|
dev_err(uc->dev, "get_fw_info failed - %d\n", status);
|
return status;
|
}
|
|
uc->port_num = 1;
|
|
if (uc->info.mode & CCG_DEVINFO_PDPORTS_MASK)
|
uc->port_num++;
|
|
uc->ucsi = ucsi_create(dev, &ucsi_ccg_ops);
|
if (IS_ERR(uc->ucsi))
|
return PTR_ERR(uc->ucsi);
|
|
ucsi_set_drvdata(uc->ucsi, uc);
|
|
status = request_threaded_irq(client->irq, NULL, ccg_irq_handler,
|
IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
|
dev_name(dev), uc);
|
if (status < 0) {
|
dev_err(uc->dev, "request_threaded_irq failed - %d\n", status);
|
goto out_ucsi_destroy;
|
}
|
|
uc->irq = client->irq;
|
|
status = ucsi_register(uc->ucsi);
|
if (status)
|
goto out_free_irq;
|
|
i2c_set_clientdata(client, uc);
|
|
pm_runtime_set_active(uc->dev);
|
pm_runtime_enable(uc->dev);
|
pm_runtime_use_autosuspend(uc->dev);
|
pm_runtime_set_autosuspend_delay(uc->dev, 5000);
|
pm_runtime_idle(uc->dev);
|
|
return 0;
|
|
out_free_irq:
|
free_irq(uc->irq, uc);
|
out_ucsi_destroy:
|
ucsi_destroy(uc->ucsi);
|
|
return status;
|
}
|
|
static int ucsi_ccg_remove(struct i2c_client *client)
|
{
|
struct ucsi_ccg *uc = i2c_get_clientdata(client);
|
|
cancel_work_sync(&uc->pm_work);
|
cancel_work_sync(&uc->work);
|
pm_runtime_disable(uc->dev);
|
ucsi_unregister(uc->ucsi);
|
ucsi_destroy(uc->ucsi);
|
free_irq(uc->irq, uc);
|
|
return 0;
|
}
|
|
static const struct i2c_device_id ucsi_ccg_device_id[] = {
|
{"ccgx-ucsi", 0},
|
{}
|
};
|
MODULE_DEVICE_TABLE(i2c, ucsi_ccg_device_id);
|
|
static int ucsi_ccg_resume(struct device *dev)
|
{
|
struct i2c_client *client = to_i2c_client(dev);
|
struct ucsi_ccg *uc = i2c_get_clientdata(client);
|
|
return ucsi_resume(uc->ucsi);
|
}
|
|
static int ucsi_ccg_runtime_suspend(struct device *dev)
|
{
|
return 0;
|
}
|
|
static int ucsi_ccg_runtime_resume(struct device *dev)
|
{
|
struct i2c_client *client = to_i2c_client(dev);
|
struct ucsi_ccg *uc = i2c_get_clientdata(client);
|
|
/*
|
* Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
|
* of missing interrupt when a device is connected for runtime resume.
|
* Schedule a work to call ISR as a workaround.
|
*/
|
if (uc->fw_build == CCG_FW_BUILD_NVIDIA &&
|
uc->fw_version <= CCG_OLD_FW_VERSION)
|
schedule_work(&uc->pm_work);
|
|
return 0;
|
}
|
|
static const struct dev_pm_ops ucsi_ccg_pm = {
|
.resume = ucsi_ccg_resume,
|
.runtime_suspend = ucsi_ccg_runtime_suspend,
|
.runtime_resume = ucsi_ccg_runtime_resume,
|
};
|
|
static struct i2c_driver ucsi_ccg_driver = {
|
.driver = {
|
.name = "ucsi_ccg",
|
.pm = &ucsi_ccg_pm,
|
.dev_groups = ucsi_ccg_groups,
|
},
|
.probe = ucsi_ccg_probe,
|
.remove = ucsi_ccg_remove,
|
.id_table = ucsi_ccg_device_id,
|
};
|
|
module_i2c_driver(ucsi_ccg_driver);
|
|
MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
|
MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller");
|
MODULE_LICENSE("GPL v2");
|
