/*
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*
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* (C) COPYRIGHT 2011-2016 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained
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* from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#include <linux/io.h>
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#include <mali_kbase.h>
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#include "mali_kbase_cpu_vexpress.h"
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#define HZ_IN_MHZ (1000000)
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#define CORETILE_EXPRESS_A9X4_SCC_START (0x100E2000)
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#define MOTHERBOARD_SYS_CFG_START (0x10000000)
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#define SYS_CFGDATA_OFFSET (0x000000A0)
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#define SYS_CFGCTRL_OFFSET (0x000000A4)
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#define SYS_CFGSTAT_OFFSET (0x000000A8)
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#define SYS_CFGCTRL_START_BIT_VALUE (1 << 31)
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#define READ_REG_BIT_VALUE (0 << 30)
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#define DCC_DEFAULT_BIT_VALUE (0 << 26)
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#define SYS_CFG_OSC_FUNC_BIT_VALUE (1 << 20)
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#define SITE_DEFAULT_BIT_VALUE (1 << 16)
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#define BOARD_STACK_POS_DEFAULT_BIT_VALUE (0 << 12)
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#define DEVICE_DEFAULT_BIT_VALUE (2 << 0)
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#define SYS_CFG_COMPLETE_BIT_VALUE (1 << 0)
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#define SYS_CFG_ERROR_BIT_VALUE (1 << 1)
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#define FEED_REG_BIT_MASK (0x0F)
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#define FCLK_PA_DIVIDE_BIT_SHIFT (0x03)
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#define FCLK_PB_DIVIDE_BIT_SHIFT (0x07)
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#define FCLK_PC_DIVIDE_BIT_SHIFT (0x0B)
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#define AXICLK_PA_DIVIDE_BIT_SHIFT (0x0F)
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#define AXICLK_PB_DIVIDE_BIT_SHIFT (0x13)
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/* the following three values used for reading
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* HBI value of the LogicTile daughterboard */
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#define VE_MOTHERBOARD_PERIPHERALS_SMB_CS7 (0x10000000)
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#define VE_SYS_PROC_ID1_OFFSET (0x00000088)
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#define VE_LOGIC_TILE_HBI_MASK (0x00000FFF)
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#define IS_SINGLE_BIT_SET(val, pos) (val&(1<<pos))
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/**
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* Values used for determining the GPU frequency based on the LogicTile type
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* Used by the function kbase_get_platform_logic_tile_type
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*/
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#define VE_VIRTEX6_GPU_FREQ_MIN 5000
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#define VE_VIRTEX6_GPU_FREQ_MAX 5000
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#define VE_VIRTEX7_GPU_FREQ_MIN 40000
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#define VE_VIRTEX7_GPU_FREQ_MAX 40000
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#define VE_DEFAULT_GPU_FREQ_MIN 5000
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#define VE_DEFAULT_GPU_FREQ_MAX 5000
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#define CPU_CLOCK_SPEED_UNDEFINED (0)
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static u32 cpu_clock_speed = CPU_CLOCK_SPEED_UNDEFINED;
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static DEFINE_RAW_SPINLOCK(syscfg_lock);
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/**
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* kbase_get_vendor_specific_cpu_clock_speed -Retrieves the CPU clock speed
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* @cpu_clock - the value of CPU clock speed in MHz
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*
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* Returns 0 on success, error code otherwise.
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*
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* The implementation is platform specific.
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*/
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int kbase_get_vexpress_cpu_clock_speed(u32 *cpu_clock)
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{
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int err = 0;
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u32 reg_val = 0;
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u32 osc2_value = 0;
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u32 pa_divide = 0;
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u32 pb_divide = 0;
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u32 pc_divide = 0;
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void __iomem *syscfg_reg = NULL;
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void __iomem *scc_reg = NULL;
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if (CPU_CLOCK_SPEED_UNDEFINED != cpu_clock_speed) {
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*cpu_clock = cpu_clock_speed;
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return 0;
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}
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/* Init the value in case something goes wrong */
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*cpu_clock = 0;
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/* Map CPU register into virtual memory */
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syscfg_reg = ioremap(MOTHERBOARD_SYS_CFG_START, 0x1000);
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if (syscfg_reg == NULL) {
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err = -EIO;
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goto syscfg_reg_map_failed;
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}
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scc_reg = ioremap(CORETILE_EXPRESS_A9X4_SCC_START, 0x1000);
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if (scc_reg == NULL) {
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err = -EIO;
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goto scc_reg_map_failed;
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}
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raw_spin_lock(&syscfg_lock);
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/* Read SYS regs - OSC2 */
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reg_val = readl(syscfg_reg + SYS_CFGCTRL_OFFSET);
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/* Check if there is any other undergoing request */
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if (reg_val & SYS_CFGCTRL_START_BIT_VALUE) {
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err = -EBUSY;
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goto ongoing_request;
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}
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/* Reset the CGFGSTAT reg */
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writel(0, (syscfg_reg + SYS_CFGSTAT_OFFSET));
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writel(SYS_CFGCTRL_START_BIT_VALUE | READ_REG_BIT_VALUE |
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DCC_DEFAULT_BIT_VALUE |
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SYS_CFG_OSC_FUNC_BIT_VALUE |
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SITE_DEFAULT_BIT_VALUE |
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BOARD_STACK_POS_DEFAULT_BIT_VALUE |
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DEVICE_DEFAULT_BIT_VALUE,
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(syscfg_reg + SYS_CFGCTRL_OFFSET));
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/* Wait for the transaction to complete */
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while (!(readl(syscfg_reg + SYS_CFGSTAT_OFFSET) &
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SYS_CFG_COMPLETE_BIT_VALUE))
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;
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/* Read SYS_CFGSTAT Register to get the status of submitted
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* transaction */
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reg_val = readl(syscfg_reg + SYS_CFGSTAT_OFFSET);
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if (reg_val & SYS_CFG_ERROR_BIT_VALUE) {
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/* Error while setting register */
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err = -EIO;
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goto set_reg_error;
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}
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osc2_value = readl(syscfg_reg + SYS_CFGDATA_OFFSET);
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/* Read the SCC CFGRW0 register */
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reg_val = readl(scc_reg);
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/*
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* Select the appropriate feed:
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* CFGRW0[0] - CLKOB
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* CFGRW0[1] - CLKOC
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* CFGRW0[2] - FACLK (CLK)B FROM AXICLK PLL)
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*/
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/* Calculate the FCLK */
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if (IS_SINGLE_BIT_SET(reg_val, 0)) {
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/* CFGRW0[0] - CLKOB */
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/* CFGRW0[6:3] */
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pa_divide = ((reg_val & (FEED_REG_BIT_MASK <<
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FCLK_PA_DIVIDE_BIT_SHIFT)) >>
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FCLK_PA_DIVIDE_BIT_SHIFT);
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/* CFGRW0[10:7] */
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pb_divide = ((reg_val & (FEED_REG_BIT_MASK <<
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FCLK_PB_DIVIDE_BIT_SHIFT)) >>
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FCLK_PB_DIVIDE_BIT_SHIFT);
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*cpu_clock = osc2_value * (pa_divide + 1) / (pb_divide + 1);
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} else if (IS_SINGLE_BIT_SET(reg_val, 1)) {
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/* CFGRW0[1] - CLKOC */
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/* CFGRW0[6:3] */
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pa_divide = ((reg_val & (FEED_REG_BIT_MASK <<
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FCLK_PA_DIVIDE_BIT_SHIFT)) >>
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FCLK_PA_DIVIDE_BIT_SHIFT);
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/* CFGRW0[14:11] */
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pc_divide = ((reg_val & (FEED_REG_BIT_MASK <<
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FCLK_PC_DIVIDE_BIT_SHIFT)) >>
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FCLK_PC_DIVIDE_BIT_SHIFT);
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*cpu_clock = osc2_value * (pa_divide + 1) / (pc_divide + 1);
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} else if (IS_SINGLE_BIT_SET(reg_val, 2)) {
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/* CFGRW0[2] - FACLK */
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/* CFGRW0[18:15] */
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pa_divide = ((reg_val & (FEED_REG_BIT_MASK <<
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AXICLK_PA_DIVIDE_BIT_SHIFT)) >>
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AXICLK_PA_DIVIDE_BIT_SHIFT);
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/* CFGRW0[22:19] */
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pb_divide = ((reg_val & (FEED_REG_BIT_MASK <<
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AXICLK_PB_DIVIDE_BIT_SHIFT)) >>
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AXICLK_PB_DIVIDE_BIT_SHIFT);
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*cpu_clock = osc2_value * (pa_divide + 1) / (pb_divide + 1);
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} else {
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err = -EIO;
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}
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set_reg_error:
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ongoing_request:
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raw_spin_unlock(&syscfg_lock);
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*cpu_clock /= HZ_IN_MHZ;
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if (!err)
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cpu_clock_speed = *cpu_clock;
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iounmap(scc_reg);
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scc_reg_map_failed:
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iounmap(syscfg_reg);
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syscfg_reg_map_failed:
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return err;
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}
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/**
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* kbase_get_platform_logic_tile_type - determines which LogicTile type
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* is used by Versatile Express
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*
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* When platform_config build parameter is specified as vexpress, i.e.,
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* platform_config=vexpress, GPU frequency may vary dependent on the
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* particular platform. The GPU frequency depends on the LogicTile type.
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*
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* This function determines which LogicTile type is used by the platform by
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* reading the HBI value of the daughterboard which holds the LogicTile:
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*
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* 0x217 HBI0217 Virtex-6
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* 0x192 HBI0192 Virtex-5
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* 0x247 HBI0247 Virtex-7
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*
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* Return: HBI value of the logic tile daughterboard, zero if not accessible
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*/
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static u32 kbase_get_platform_logic_tile_type(void)
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{
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void __iomem *syscfg_reg = NULL;
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u32 sys_procid1 = 0;
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syscfg_reg = ioremap(VE_MOTHERBOARD_PERIPHERALS_SMB_CS7 + VE_SYS_PROC_ID1_OFFSET, 4);
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if (NULL != syscfg_reg) {
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sys_procid1 = readl(syscfg_reg);
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iounmap(syscfg_reg);
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}
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return sys_procid1 & VE_LOGIC_TILE_HBI_MASK;
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}
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u32 kbase_get_platform_min_freq(void)
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{
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u32 ve_logic_tile = kbase_get_platform_logic_tile_type();
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switch (ve_logic_tile) {
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case 0x217:
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/* Virtex 6, HBI0217 */
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return VE_VIRTEX6_GPU_FREQ_MIN;
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case 0x247:
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/* Virtex 7, HBI0247 */
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return VE_VIRTEX7_GPU_FREQ_MIN;
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default:
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/* all other logic tiles, i.e., Virtex 5 HBI0192
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* or unsuccessful reading from the platform -
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* fall back to some default value */
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return VE_DEFAULT_GPU_FREQ_MIN;
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}
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}
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u32 kbase_get_platform_max_freq(void)
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{
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u32 ve_logic_tile = kbase_get_platform_logic_tile_type();
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switch (ve_logic_tile) {
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case 0x217:
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/* Virtex 6, HBI0217 */
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return VE_VIRTEX6_GPU_FREQ_MAX;
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case 0x247:
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/* Virtex 7, HBI0247 */
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return VE_VIRTEX7_GPU_FREQ_MAX;
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default:
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/* all other logic tiles, i.e., Virtex 5 HBI0192
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* or unsuccessful reading from the platform -
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* fall back to some default value */
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return VE_DEFAULT_GPU_FREQ_MAX;
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}
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}
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