/*
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*
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* (C) COPYRIGHT 2014-2016 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained
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* from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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/*
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* Base kernel property query backend APIs
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*/
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#include <mali_kbase.h>
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#include <backend/gpu/mali_kbase_device_internal.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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#include <mali_kbase_hwaccess_gpuprops.h>
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void kbase_backend_gpuprops_get(struct kbase_device *kbdev,
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struct kbase_gpuprops_regdump *regdump)
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{
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int i;
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/* Fill regdump with the content of the relevant registers */
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regdump->gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID), NULL);
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regdump->l2_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_FEATURES), NULL);
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regdump->suspend_size = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(SUSPEND_SIZE), NULL);
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regdump->tiler_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TILER_FEATURES), NULL);
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regdump->mem_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(MEM_FEATURES), NULL);
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regdump->mmu_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(MMU_FEATURES), NULL);
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regdump->as_present = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(AS_PRESENT), NULL);
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regdump->js_present = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(JS_PRESENT), NULL);
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for (i = 0; i < GPU_MAX_JOB_SLOTS; i++)
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regdump->js_features[i] = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(JS_FEATURES_REG(i)), NULL);
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for (i = 0; i < BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS; i++)
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regdump->texture_features[i] = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TEXTURE_FEATURES_REG(i)), NULL);
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regdump->thread_max_threads = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_MAX_THREADS), NULL);
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regdump->thread_max_workgroup_size = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_MAX_WORKGROUP_SIZE),
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NULL);
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regdump->thread_max_barrier_size = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_MAX_BARRIER_SIZE), NULL);
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regdump->thread_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_FEATURES), NULL);
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regdump->shader_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(SHADER_PRESENT_LO), NULL);
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regdump->shader_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(SHADER_PRESENT_HI), NULL);
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regdump->tiler_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TILER_PRESENT_LO), NULL);
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regdump->tiler_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TILER_PRESENT_HI), NULL);
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regdump->l2_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_PRESENT_LO), NULL);
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regdump->l2_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_PRESENT_HI), NULL);
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regdump->stack_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(STACK_PRESENT_LO), NULL);
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regdump->stack_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(STACK_PRESENT_HI), NULL);
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}
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void kbase_backend_gpuprops_get_features(struct kbase_device *kbdev,
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struct kbase_gpuprops_regdump *regdump)
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{
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if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_COHERENCY_REG)) {
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/* Ensure we can access the GPU registers */
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kbase_pm_register_access_enable(kbdev);
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regdump->coherency_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(COHERENCY_FEATURES), NULL);
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/* We're done accessing the GPU registers for now. */
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kbase_pm_register_access_disable(kbdev);
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} else {
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/* Pre COHERENCY_FEATURES we only supported ACE_LITE */
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regdump->coherency_features =
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COHERENCY_FEATURE_BIT(COHERENCY_NONE) |
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COHERENCY_FEATURE_BIT(COHERENCY_ACE_LITE);
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}
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}
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