/*
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* Copyright (C) 2010-2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/**
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* @file mali_osk_mali.c
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* Implementation of the OS abstraction layer which is specific for the Mali kernel device driver
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*/
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#include "../platform/rk/custom_log.h"
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#include <linux/kernel.h>
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#include <linux/uaccess.h>
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#include <linux/platform_device.h>
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#include <linux/mali/mali_utgard.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "mali_osk_mali.h"
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#include "mali_kernel_common.h" /* MALI_xxx macros */
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#include "mali_osk.h" /* kernel side OS functions */
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#include "mali_kernel_linux.h"
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static mali_bool mali_secure_mode_enabled = MALI_FALSE;
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static mali_bool mali_secure_mode_supported = MALI_FALSE;
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/* Function that init the mali gpu secure mode */
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void (*mali_secure_mode_deinit)(void) = NULL;
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/* Function that reset GPU and enable the mali gpu secure mode */
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int (*mali_gpu_reset_and_secure_mode_enable)(void) = NULL;
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/* Function that reset GPU and disable the mali gpu secure mode */
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int (*mali_gpu_reset_and_secure_mode_disable)(void) = NULL;
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#ifdef CONFIG_MALI_DT
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#define MALI_OSK_INVALID_RESOURCE_ADDRESS 0xFFFFFFFF
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/**
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* Define the max number of resource we could have.
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*/
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#define MALI_OSK_MAX_RESOURCE_NUMBER 27
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/**
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* Define the max number of resource with interrupts, and they are
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* the first 20 elements in array mali_osk_resource_bank.
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*/
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#define MALI_OSK_RESOURCE_WITH_IRQ_NUMBER 20
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/**
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* pp core start and end location in mali_osk_resource_bank array.
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*/
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#define MALI_OSK_RESOURCE_PP_LOCATION_START 2
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#define MALI_OSK_RESOURCE_PP_LOCATION_END 17
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/**
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* L2 cache start and end location in mali_osk_resource_bank array.
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*/
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#define MALI_OSK_RESOURCE_L2_LOCATION_START 20
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#define MALI_OSK_RESOURCE_l2_LOCATION_END 22
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/**
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* DMA unit location.
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*/
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#define MALI_OSK_RESOURCE_DMA_LOCATION 26
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static _mali_osk_resource_t mali_osk_resource_bank[MALI_OSK_MAX_RESOURCE_NUMBER] = {
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/*-------------------------------------------------------*/
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/* rk_ext : to use dts_for_mali_ko_befor_r5p0-01rel0. */
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/* {.description = "Mali_GP", .base = MALI_OFFSET_GP, .irq_name = "IRQGP",}, */
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{.description = "Mali_GP", .base = MALI_OFFSET_GP, .irq_name = "Mali_GP_IRQ",},
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/* {.description = "Mali_GP_MMU", .base = MALI_OFFSET_GP_MMU, .irq_name = "IRQGPMMU",}, */
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{.description = "Mali_GP_MMU", .base = MALI_OFFSET_GP_MMU, .irq_name = "Mali_GP_MMU_IRQ",},
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/* {.description = "Mali_PP0", .base = MALI_OFFSET_PP0, .irq_name = "IRQPP0",}, */
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{.description = "Mali_PP0", .base = MALI_OFFSET_PP0, .irq_name = "Mali_PP0_IRQ",},
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/* {.description = "Mali_PP0_MMU", .base = MALI_OFFSET_PP0_MMU, .irq_name = "IRQPPMMU0",}, */
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{.description = "Mali_PP0_MMU", .base = MALI_OFFSET_PP0_MMU, .irq_name = "Mali_PP0_MMU_IRQ",},
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/* {.description = "Mali_PP1", .base = MALI_OFFSET_PP1, .irq_name = "IRQPP1",}, */
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{.description = "Mali_PP1", .base = MALI_OFFSET_PP1, .irq_name = "Mali_PP1_IRQ",},
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/* {.description = "Mali_PP1_MMU", .base = MALI_OFFSET_PP1_MMU, .irq_name = "IRQPPMMU1",}, */
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{.description = "Mali_PP1_MMU", .base = MALI_OFFSET_PP1_MMU, .irq_name = "Mali_PP1_MMU_IRQ",},
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{.description = "Mali_PP2", .base = MALI_OFFSET_PP2, .irq_name = "Mali_PP2_IRQ",},
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{.description = "Mali_PP2_MMU", .base = MALI_OFFSET_PP2_MMU, .irq_name = "Mali_PP2_MMU_IRQ",},
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{.description = "Mali_PP3", .base = MALI_OFFSET_PP3, .irq_name = "Mali_PP3_IRQ",},
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{.description = "Mali_PP3_MMU", .base = MALI_OFFSET_PP3_MMU, .irq_name = "Mali_PP3_MMU_IRQ",},
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/*-------------------------------------------------------*/
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{.description = "Mali_PP4", .base = MALI_OFFSET_PP4, .irq_name = "IRQPP4",},
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{.description = "Mali_PP4_MMU", .base = MALI_OFFSET_PP4_MMU, .irq_name = "IRQPPMMU4",},
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{.description = "Mali_PP5", .base = MALI_OFFSET_PP5, .irq_name = "IRQPP5",},
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{.description = "Mali_PP5_MMU", .base = MALI_OFFSET_PP5_MMU, .irq_name = "IRQPPMMU5",},
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{.description = "Mali_PP6", .base = MALI_OFFSET_PP6, .irq_name = "IRQPP6",},
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{.description = "Mali_PP6_MMU", .base = MALI_OFFSET_PP6_MMU, .irq_name = "IRQPPMMU6",},
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{.description = "Mali_PP7", .base = MALI_OFFSET_PP7, .irq_name = "IRQPP7",},
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{.description = "Mali_PP7_MMU", .base = MALI_OFFSET_PP7_MMU, .irq_name = "IRQPPMMU",},
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{.description = "Mali_PP_Broadcast", .base = MALI_OFFSET_PP_BCAST, .irq_name = "IRQPP",},
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{.description = "Mali_PMU", .base = MALI_OFFSET_PMU, .irq_name = "IRQPMU",},
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{.description = "Mali_L2", .base = MALI_OFFSET_L2_RESOURCE0,},
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{.description = "Mali_L2", .base = MALI_OFFSET_L2_RESOURCE1,},
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{.description = "Mali_L2", .base = MALI_OFFSET_L2_RESOURCE2,},
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{.description = "Mali_PP_MMU_Broadcast", .base = MALI_OFFSET_PP_BCAST_MMU,},
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{.description = "Mali_Broadcast", .base = MALI_OFFSET_BCAST,},
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{.description = "Mali_DLBU", .base = MALI_OFFSET_DLBU,},
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{.description = "Mali_DMA", .base = MALI_OFFSET_DMA,},
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};
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static int _mali_osk_get_compatible_name(const char **out_string)
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{
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struct device_node *node = mali_platform_device->dev.of_node;
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MALI_DEBUG_ASSERT(NULL != node);
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return of_property_read_string(node, "compatible", out_string);
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}
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_mali_osk_errcode_t _mali_osk_resource_initialize(void)
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{
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mali_bool mali_is_450 = MALI_FALSE, mali_is_470 = MALI_FALSE;
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int i, pp_core_num = 0, l2_core_num = 0;
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struct resource *res;
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const char *compatible_name = NULL;
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if (0 == _mali_osk_get_compatible_name(&compatible_name)) {
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if (0 == strncmp(compatible_name, "arm,mali-450", strlen("arm,mali-450"))) {
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mali_is_450 = MALI_TRUE;
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MALI_DEBUG_PRINT(2, ("mali-450 device tree detected."));
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} else if (0 == strncmp(compatible_name, "arm,mali-470", strlen("arm,mali-470"))) {
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mali_is_470 = MALI_TRUE;
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MALI_DEBUG_PRINT(2, ("mali-470 device tree detected."));
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}
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}
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for (i = 0; i < MALI_OSK_RESOURCE_WITH_IRQ_NUMBER; i++) {
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res = platform_get_resource_byname(mali_platform_device, IORESOURCE_IRQ, mali_osk_resource_bank[i].irq_name);
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if (res) {
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mali_osk_resource_bank[i].irq = res->start;
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} else {
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mali_osk_resource_bank[i].base = MALI_OSK_INVALID_RESOURCE_ADDRESS;
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}
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}
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for (i = MALI_OSK_RESOURCE_PP_LOCATION_START; i <= MALI_OSK_RESOURCE_PP_LOCATION_END; i++) {
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if (MALI_OSK_INVALID_RESOURCE_ADDRESS != mali_osk_resource_bank[i].base) {
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pp_core_num++;
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}
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}
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/* We have to divide by 2, because we caculate twice for only one pp(pp_core and pp_mmu_core). */
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if (0 != pp_core_num % 2) {
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MALI_DEBUG_PRINT(2, ("The value of pp core number isn't normal."));
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return _MALI_OSK_ERR_FAULT;
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}
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pp_core_num /= 2;
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/**
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* we can caculate the number of l2 cache core according the number of pp core number
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* and device type(mali400/mali450/mali470).
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*/
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l2_core_num = 1;
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if (mali_is_450) {
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if (pp_core_num > 4) {
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l2_core_num = 3;
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} else if (pp_core_num <= 4) {
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l2_core_num = 2;
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}
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}
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for (i = MALI_OSK_RESOURCE_l2_LOCATION_END; i > MALI_OSK_RESOURCE_L2_LOCATION_START + l2_core_num - 1; i--) {
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mali_osk_resource_bank[i].base = MALI_OSK_INVALID_RESOURCE_ADDRESS;
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}
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/* If device is not mali-450 type, we have to remove related resource from resource bank. */
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if (!(mali_is_450 || mali_is_470)) {
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for (i = MALI_OSK_RESOURCE_l2_LOCATION_END + 1; i < MALI_OSK_MAX_RESOURCE_NUMBER; i++) {
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mali_osk_resource_bank[i].base = MALI_OSK_INVALID_RESOURCE_ADDRESS;
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}
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}
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if (mali_is_470)
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mali_osk_resource_bank[MALI_OSK_RESOURCE_DMA_LOCATION].base = MALI_OSK_INVALID_RESOURCE_ADDRESS;
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return _MALI_OSK_ERR_OK;
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}
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_mali_osk_errcode_t _mali_osk_resource_find(u32 addr, _mali_osk_resource_t *res)
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{
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int i;
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if (NULL == mali_platform_device) {
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return _MALI_OSK_ERR_ITEM_NOT_FOUND;
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}
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/* Traverse all of resources in resources bank to find the matching one. */
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for (i = 0; i < MALI_OSK_MAX_RESOURCE_NUMBER; i++) {
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if (mali_osk_resource_bank[i].base == addr) {
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if (NULL != res) {
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res->base = addr + _mali_osk_resource_base_address();
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res->description = mali_osk_resource_bank[i].description;
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res->irq = mali_osk_resource_bank[i].irq;
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}
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return _MALI_OSK_ERR_OK;
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}
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}
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return _MALI_OSK_ERR_ITEM_NOT_FOUND;
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}
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uintptr_t _mali_osk_resource_base_address(void)
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{
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struct resource *reg_res = NULL;
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uintptr_t ret = 0;
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reg_res = platform_get_resource(mali_platform_device, IORESOURCE_MEM, 0);
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if (NULL != reg_res) {
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ret = reg_res->start;
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}
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return ret;
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}
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void _mali_osk_device_data_pmu_config_get(u16 *domain_config_array, int array_size)
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{
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struct device_node *node = mali_platform_device->dev.of_node;
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struct property *prop;
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const __be32 *p;
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int length = 0, i = 0;
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u32 u;
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MALI_DEBUG_PRINT(2, ("Get pmu config from device tree configuration.\n"));
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MALI_DEBUG_ASSERT(NULL != node);
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if (!of_get_property(node, "pmu_domain_config", &length)) {
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return;
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}
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if (array_size != length / sizeof(u32)) {
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MALI_PRINT_ERROR(("Wrong pmu domain config in device tree."));
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return;
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}
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of_property_for_each_u32(node, "pmu_domain_config", prop, p, u) {
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domain_config_array[i] = (u16)u;
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i++;
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}
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return;
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}
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u32 _mali_osk_get_pmu_switch_delay(void)
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{
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struct device_node *node = mali_platform_device->dev.of_node;
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u32 switch_delay;
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MALI_DEBUG_ASSERT(NULL != node);
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if (0 == of_property_read_u32(node, "pmu_switch_delay", &switch_delay)) {
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return switch_delay;
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} else {
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MALI_DEBUG_PRINT(2, ("Couldn't find pmu_switch_delay in device tree configuration.\n"));
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}
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return 0;
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}
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#else /* CONFIG_MALI_DT */ /* 若未 定义 CONFIG_MALI_DT. */
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_mali_osk_errcode_t _mali_osk_resource_find(u32 addr, _mali_osk_resource_t *res)
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{
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int i;
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uintptr_t phys_addr;
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if (NULL == mali_platform_device) {
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/* Not connected to a device */
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return _MALI_OSK_ERR_ITEM_NOT_FOUND;
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}
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phys_addr = addr + _mali_osk_resource_base_address();
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for (i = 0; i < mali_platform_device->num_resources; i++) {
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if (IORESOURCE_MEM == resource_type(&(mali_platform_device->resource[i])) &&
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mali_platform_device->resource[i].start == phys_addr) {
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if (NULL != res) {
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res->base = phys_addr;
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res->description = mali_platform_device->resource[i].name;
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/* Any (optional) IRQ resource belonging to this resource will follow */
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if ((i + 1) < mali_platform_device->num_resources &&
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IORESOURCE_IRQ == resource_type(&(mali_platform_device->resource[i + 1]))) {
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res->irq = mali_platform_device->resource[i + 1].start;
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} else {
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res->irq = -1;
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}
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}
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return _MALI_OSK_ERR_OK;
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}
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}
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return _MALI_OSK_ERR_ITEM_NOT_FOUND;
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}
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uintptr_t _mali_osk_resource_base_address(void)
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{
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uintptr_t lowest_addr = (uintptr_t)(0 - 1);
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uintptr_t ret = 0;
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if (NULL != mali_platform_device) {
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int i;
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for (i = 0; i < mali_platform_device->num_resources; i++) {
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if (mali_platform_device->resource[i].flags & IORESOURCE_MEM &&
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mali_platform_device->resource[i].start < lowest_addr) {
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lowest_addr = mali_platform_device->resource[i].start;
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ret = lowest_addr;
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}
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}
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}
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return ret;
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}
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void _mali_osk_device_data_pmu_config_get(u16 *domain_config_array, int array_size)
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{
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_mali_osk_device_data data = { 0, };
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MALI_DEBUG_PRINT(2, ("Get pmu config from platform device data.\n"));
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if (_MALI_OSK_ERR_OK == _mali_osk_device_data_get(&data)) {
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/* Copy the custom customer power domain config */
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_mali_osk_memcpy(domain_config_array, data.pmu_domain_config, sizeof(data.pmu_domain_config));
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}
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return;
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}
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u32 _mali_osk_get_pmu_switch_delay(void)
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{
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_mali_osk_errcode_t err;
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_mali_osk_device_data data = { 0, };
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err = _mali_osk_device_data_get(&data);
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if (_MALI_OSK_ERR_OK == err) {
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return data.pmu_switch_delay;
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}
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return 0;
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}
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#endif /* CONFIG_MALI_DT */
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_mali_osk_errcode_t _mali_osk_device_data_get(_mali_osk_device_data *data)
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{
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MALI_DEBUG_ASSERT_POINTER(data);
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if (NULL != mali_platform_device) {
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struct mali_gpu_device_data *os_data = NULL;
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os_data = (struct mali_gpu_device_data *)mali_platform_device->dev.platform_data;
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if (NULL != os_data) {
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/* Copy data from OS dependant struct to Mali neutral struct (identical!) */
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BUILD_BUG_ON(sizeof(*os_data) != sizeof(*data));
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_mali_osk_memcpy(data, os_data, sizeof(*os_data));
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return _MALI_OSK_ERR_OK;
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}
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}
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return _MALI_OSK_ERR_ITEM_NOT_FOUND;
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}
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u32 _mali_osk_identify_gpu_resource(void)
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{
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if (_MALI_OSK_ERR_OK == _mali_osk_resource_find(MALI_OFFSET_L2_RESOURCE1, NULL))
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/* Mali 450 */
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return 0x450;
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if (_MALI_OSK_ERR_OK == _mali_osk_resource_find(MALI_OFFSET_DLBU, NULL))
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/* Mali 470 */
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return 0x470;
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/* Mali 400 */
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return 0x400;
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}
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mali_bool _mali_osk_shared_interrupts(void)
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{
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u32 irqs[128];
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u32 i, j, irq, num_irqs_found = 0;
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MALI_DEBUG_ASSERT_POINTER(mali_platform_device);
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MALI_DEBUG_ASSERT(128 >= mali_platform_device->num_resources);
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for (i = 0; i < mali_platform_device->num_resources; i++) {
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if (IORESOURCE_IRQ & mali_platform_device->resource[i].flags) {
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irq = mali_platform_device->resource[i].start;
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for (j = 0; j < num_irqs_found; ++j) {
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if (irq == irqs[j]) {
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return MALI_TRUE;
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}
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}
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irqs[num_irqs_found++] = irq;
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}
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}
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return MALI_FALSE;
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}
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_mali_osk_errcode_t _mali_osk_gpu_secure_mode_init(void)
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{
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_mali_osk_device_data data = { 0, };
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if (_MALI_OSK_ERR_OK == _mali_osk_device_data_get(&data)) {
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if ((NULL != data.secure_mode_init) && (NULL != data.secure_mode_deinit)
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&& (NULL != data.gpu_reset_and_secure_mode_enable) && (NULL != data.gpu_reset_and_secure_mode_disable)) {
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int err = data.secure_mode_init();
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if (err) {
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MALI_DEBUG_PRINT(1, ("Failed to init gpu secure mode.\n"));
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return _MALI_OSK_ERR_FAULT;
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}
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mali_secure_mode_deinit = data.secure_mode_deinit;
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mali_gpu_reset_and_secure_mode_enable = data.gpu_reset_and_secure_mode_enable;
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mali_gpu_reset_and_secure_mode_disable = data.gpu_reset_and_secure_mode_disable;
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mali_secure_mode_supported = MALI_TRUE;
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mali_secure_mode_enabled = MALI_FALSE;
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return _MALI_OSK_ERR_OK;
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}
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}
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MALI_DEBUG_PRINT(3, ("GPU secure mode not supported.\n"));
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return _MALI_OSK_ERR_UNSUPPORTED;
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}
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_mali_osk_errcode_t _mali_osk_gpu_secure_mode_deinit(void)
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{
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if (NULL != mali_secure_mode_deinit) {
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mali_secure_mode_deinit();
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mali_secure_mode_enabled = MALI_FALSE;
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mali_secure_mode_supported = MALI_FALSE;
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return _MALI_OSK_ERR_OK;
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}
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MALI_DEBUG_PRINT(3, ("GPU secure mode not supported.\n"));
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return _MALI_OSK_ERR_UNSUPPORTED;
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}
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_mali_osk_errcode_t _mali_osk_gpu_reset_and_secure_mode_enable(void)
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{
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/* the mali executor lock must be held before enter this function. */
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MALI_DEBUG_ASSERT(MALI_FALSE == mali_secure_mode_enabled);
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if (NULL != mali_gpu_reset_and_secure_mode_enable) {
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if (mali_gpu_reset_and_secure_mode_enable()) {
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MALI_DEBUG_PRINT(1, ("Failed to reset GPU or enable gpu secure mode.\n"));
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return _MALI_OSK_ERR_FAULT;
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}
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mali_secure_mode_enabled = MALI_TRUE;
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return _MALI_OSK_ERR_OK;
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}
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MALI_DEBUG_PRINT(1, ("GPU secure mode not supported.\n"));
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return _MALI_OSK_ERR_UNSUPPORTED;
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}
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_mali_osk_errcode_t _mali_osk_gpu_reset_and_secure_mode_disable(void)
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{
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/* the mali executor lock must be held before enter this function. */
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MALI_DEBUG_ASSERT(MALI_TRUE == mali_secure_mode_enabled);
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if (NULL != mali_gpu_reset_and_secure_mode_disable) {
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if (mali_gpu_reset_and_secure_mode_disable()) {
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MALI_DEBUG_PRINT(1, ("Failed to reset GPU or disable gpu secure mode.\n"));
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return _MALI_OSK_ERR_FAULT;
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}
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mali_secure_mode_enabled = MALI_FALSE;
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return _MALI_OSK_ERR_OK;
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}
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MALI_DEBUG_PRINT(1, ("GPU secure mode not supported.\n"));
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return _MALI_OSK_ERR_UNSUPPORTED;
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}
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mali_bool _mali_osk_gpu_secure_mode_is_enabled(void)
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{
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return mali_secure_mode_enabled;
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}
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mali_bool _mali_osk_gpu_secure_mode_is_supported(void)
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{
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return mali_secure_mode_supported;
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}
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