// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2018-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include "hwcnt/mali_kbase_hwcnt_gpu.h"
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#include "hwcnt/mali_kbase_hwcnt_types.h"
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#include <linux/err.h>
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/** enum enable_map_idx - index into a block enable map that spans multiple u64 array elements
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*/
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enum enable_map_idx {
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EM_LO,
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EM_HI,
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EM_COUNT,
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};
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static void kbasep_get_fe_block_type(u64 *dst, enum kbase_hwcnt_set counter_set, bool is_csf)
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{
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switch (counter_set) {
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case KBASE_HWCNT_SET_PRIMARY:
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE;
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break;
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case KBASE_HWCNT_SET_SECONDARY:
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if (is_csf)
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE2;
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else
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE_UNDEFINED;
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break;
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case KBASE_HWCNT_SET_TERTIARY:
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if (is_csf)
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE3;
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else
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE_UNDEFINED;
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break;
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default:
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WARN_ON(true);
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}
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}
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static void kbasep_get_tiler_block_type(u64 *dst, enum kbase_hwcnt_set counter_set)
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{
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switch (counter_set) {
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case KBASE_HWCNT_SET_PRIMARY:
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER;
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break;
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case KBASE_HWCNT_SET_SECONDARY:
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case KBASE_HWCNT_SET_TERTIARY:
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER_UNDEFINED;
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break;
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default:
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WARN_ON(true);
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}
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}
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static void kbasep_get_sc_block_type(u64 *dst, enum kbase_hwcnt_set counter_set, bool is_csf)
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{
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switch (counter_set) {
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case KBASE_HWCNT_SET_PRIMARY:
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC;
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break;
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case KBASE_HWCNT_SET_SECONDARY:
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC2;
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break;
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case KBASE_HWCNT_SET_TERTIARY:
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if (is_csf)
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC3;
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else
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC_UNDEFINED;
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break;
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default:
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WARN_ON(true);
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}
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}
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static void kbasep_get_memsys_block_type(u64 *dst, enum kbase_hwcnt_set counter_set)
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{
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switch (counter_set) {
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case KBASE_HWCNT_SET_PRIMARY:
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS;
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break;
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case KBASE_HWCNT_SET_SECONDARY:
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS2;
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break;
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case KBASE_HWCNT_SET_TERTIARY:
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*dst = KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS_UNDEFINED;
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break;
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default:
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WARN_ON(true);
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}
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}
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/**
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* kbasep_hwcnt_backend_gpu_metadata_create() - Create hardware counter metadata
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* for the GPU.
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* @gpu_info: Non-NULL pointer to hwcnt info for current GPU.
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* @is_csf: true for CSF GPU, otherwise false.
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* @counter_set: The performance counter set to use.
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* @metadata: Non-NULL pointer to where created metadata is stored
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* on success.
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*
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* Return: 0 on success, else error code.
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*/
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static int kbasep_hwcnt_backend_gpu_metadata_create(const struct kbase_hwcnt_gpu_info *gpu_info,
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const bool is_csf,
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enum kbase_hwcnt_set counter_set,
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const struct kbase_hwcnt_metadata **metadata)
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{
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struct kbase_hwcnt_description desc;
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struct kbase_hwcnt_group_description group;
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struct kbase_hwcnt_block_description blks[KBASE_HWCNT_V5_BLOCK_TYPE_COUNT];
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size_t non_sc_block_count;
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size_t sc_block_count;
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WARN_ON(!gpu_info);
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WARN_ON(!metadata);
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/* Calculate number of block instances that aren't shader cores */
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non_sc_block_count = 2 + gpu_info->l2_count;
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/* Calculate number of block instances that are shader cores */
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sc_block_count = fls64(gpu_info->core_mask);
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/*
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* A system can have up to 64 shader cores, but the 64-bit
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* availability mask can't physically represent that many cores as well
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* as the other hardware blocks.
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* Error out if there are more blocks than our implementation can
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* support.
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*/
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if ((sc_block_count + non_sc_block_count) > KBASE_HWCNT_AVAIL_MASK_BITS)
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return -EINVAL;
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/* One Front End block */
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kbasep_get_fe_block_type(&blks[0].type, counter_set, is_csf);
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blks[0].inst_cnt = 1;
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blks[0].hdr_cnt = KBASE_HWCNT_V5_HEADERS_PER_BLOCK;
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blks[0].ctr_cnt = gpu_info->prfcnt_values_per_block - KBASE_HWCNT_V5_HEADERS_PER_BLOCK;
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/* One Tiler block */
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kbasep_get_tiler_block_type(&blks[1].type, counter_set);
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blks[1].inst_cnt = 1;
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blks[1].hdr_cnt = KBASE_HWCNT_V5_HEADERS_PER_BLOCK;
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blks[1].ctr_cnt = gpu_info->prfcnt_values_per_block - KBASE_HWCNT_V5_HEADERS_PER_BLOCK;
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/* l2_count memsys blks */
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kbasep_get_memsys_block_type(&blks[2].type, counter_set);
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blks[2].inst_cnt = gpu_info->l2_count;
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blks[2].hdr_cnt = KBASE_HWCNT_V5_HEADERS_PER_BLOCK;
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blks[2].ctr_cnt = gpu_info->prfcnt_values_per_block - KBASE_HWCNT_V5_HEADERS_PER_BLOCK;
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/*
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* There are as many shader cores in the system as there are bits set in
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* the core mask. However, the dump buffer memory requirements need to
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* take into account the fact that the core mask may be non-contiguous.
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*
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* For example, a system with a core mask of 0b1011 has the same dump
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* buffer memory requirements as a system with 0b1111, but requires more
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* memory than a system with 0b0111. However, core 2 of the system with
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* 0b1011 doesn't physically exist, and the dump buffer memory that
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* accounts for that core will never be written to when we do a counter
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* dump.
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*
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* We find the core mask's last set bit to determine the memory
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* requirements, and embed the core mask into the availability mask so
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* we can determine later which shader cores physically exist.
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*/
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kbasep_get_sc_block_type(&blks[3].type, counter_set, is_csf);
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blks[3].inst_cnt = sc_block_count;
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blks[3].hdr_cnt = KBASE_HWCNT_V5_HEADERS_PER_BLOCK;
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blks[3].ctr_cnt = gpu_info->prfcnt_values_per_block - KBASE_HWCNT_V5_HEADERS_PER_BLOCK;
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WARN_ON(KBASE_HWCNT_V5_BLOCK_TYPE_COUNT != 4);
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group.type = KBASE_HWCNT_GPU_GROUP_TYPE_V5;
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group.blk_cnt = KBASE_HWCNT_V5_BLOCK_TYPE_COUNT;
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group.blks = blks;
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desc.grp_cnt = 1;
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desc.grps = &group;
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desc.clk_cnt = gpu_info->clk_cnt;
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/* The JM, Tiler, and L2s are always available, and are before cores */
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desc.avail_mask = (1ull << non_sc_block_count) - 1;
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/* Embed the core mask directly in the availability mask */
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desc.avail_mask |= (gpu_info->core_mask << non_sc_block_count);
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return kbase_hwcnt_metadata_create(&desc, metadata);
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}
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/**
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* kbasep_hwcnt_backend_jm_dump_bytes() - Get the raw dump buffer size for the
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* GPU.
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* @gpu_info: Non-NULL pointer to hwcnt info for the GPU.
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*
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* Return: Size of buffer the GPU needs to perform a counter dump.
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*/
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static size_t kbasep_hwcnt_backend_jm_dump_bytes(const struct kbase_hwcnt_gpu_info *gpu_info)
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{
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WARN_ON(!gpu_info);
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return (2 + gpu_info->l2_count + fls64(gpu_info->core_mask)) *
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gpu_info->prfcnt_values_per_block * KBASE_HWCNT_VALUE_HW_BYTES;
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}
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int kbase_hwcnt_jm_metadata_create(const struct kbase_hwcnt_gpu_info *gpu_info,
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enum kbase_hwcnt_set counter_set,
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const struct kbase_hwcnt_metadata **out_metadata,
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size_t *out_dump_bytes)
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{
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int errcode;
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const struct kbase_hwcnt_metadata *metadata;
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size_t dump_bytes;
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if (!gpu_info || !out_metadata || !out_dump_bytes)
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return -EINVAL;
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/*
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* For architectures where a max_config interface is available
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* from the arbiter, the v5 dump bytes and the metadata v5 are
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* based on the maximum possible allocation of the HW in the
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* GPU cause it needs to be prepared for the worst case where
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* all the available L2 cache and Shader cores are allocated.
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*/
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dump_bytes = kbasep_hwcnt_backend_jm_dump_bytes(gpu_info);
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errcode = kbasep_hwcnt_backend_gpu_metadata_create(gpu_info, false, counter_set, &metadata);
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if (errcode)
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return errcode;
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/*
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* The physical dump size should be half of dump abstraction size in
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* metadata since physical HW uses 32-bit per value but metadata
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* specifies 64-bit per value.
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*/
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WARN_ON(dump_bytes * 2 != metadata->dump_buf_bytes);
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*out_metadata = metadata;
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*out_dump_bytes = dump_bytes;
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return 0;
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}
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void kbase_hwcnt_jm_metadata_destroy(const struct kbase_hwcnt_metadata *metadata)
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{
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if (!metadata)
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return;
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kbase_hwcnt_metadata_destroy(metadata);
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}
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int kbase_hwcnt_csf_metadata_create(const struct kbase_hwcnt_gpu_info *gpu_info,
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enum kbase_hwcnt_set counter_set,
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const struct kbase_hwcnt_metadata **out_metadata)
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{
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int errcode;
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const struct kbase_hwcnt_metadata *metadata;
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if (!gpu_info || !out_metadata)
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return -EINVAL;
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errcode = kbasep_hwcnt_backend_gpu_metadata_create(gpu_info, true, counter_set, &metadata);
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if (errcode)
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return errcode;
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*out_metadata = metadata;
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return 0;
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}
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void kbase_hwcnt_csf_metadata_destroy(const struct kbase_hwcnt_metadata *metadata)
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{
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if (!metadata)
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return;
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kbase_hwcnt_metadata_destroy(metadata);
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}
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static bool is_block_type_shader(const u64 grp_type, const u64 blk_type, const size_t blk)
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{
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bool is_shader = false;
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/* Warn on unknown group type */
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if (WARN_ON(grp_type != KBASE_HWCNT_GPU_GROUP_TYPE_V5))
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return false;
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if (blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC ||
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blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC2 ||
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blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC3 ||
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blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC_UNDEFINED)
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is_shader = true;
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return is_shader;
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}
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static bool is_block_type_l2_cache(const u64 grp_type, const u64 blk_type)
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{
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bool is_l2_cache = false;
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switch (grp_type) {
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case KBASE_HWCNT_GPU_GROUP_TYPE_V5:
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if (blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS ||
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blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS2 ||
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blk_type == KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS_UNDEFINED)
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is_l2_cache = true;
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break;
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default:
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/* Warn on unknown group type */
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WARN_ON(true);
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}
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return is_l2_cache;
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}
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int kbase_hwcnt_jm_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
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const struct kbase_hwcnt_enable_map *dst_enable_map, u64 pm_core_mask,
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const struct kbase_hwcnt_curr_config *curr_config, bool accumulate)
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{
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const struct kbase_hwcnt_metadata *metadata;
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size_t grp, blk, blk_inst;
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const u64 *dump_src = src;
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size_t src_offset = 0;
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u64 core_mask = pm_core_mask;
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/* Variables to deal with the current configuration */
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int l2_count = 0;
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if (!dst || !src || !dst_enable_map || (dst_enable_map->metadata != dst->metadata))
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return -EINVAL;
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metadata = dst->metadata;
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kbase_hwcnt_metadata_for_each_block(metadata, grp, blk, blk_inst)
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{
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const size_t hdr_cnt = kbase_hwcnt_metadata_block_headers_count(metadata, grp, blk);
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const size_t ctr_cnt =
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kbase_hwcnt_metadata_block_counters_count(metadata, grp, blk);
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const u64 blk_type = kbase_hwcnt_metadata_block_type(metadata, grp, blk);
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const bool is_shader_core = is_block_type_shader(
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kbase_hwcnt_metadata_group_type(metadata, grp), blk_type, blk);
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const bool is_l2_cache = is_block_type_l2_cache(
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kbase_hwcnt_metadata_group_type(metadata, grp), blk_type);
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const bool is_undefined = kbase_hwcnt_is_block_type_undefined(
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kbase_hwcnt_metadata_group_type(metadata, grp), blk_type);
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bool hw_res_available = true;
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/*
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* If l2 blocks is greater than the current allocated number of
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* L2 slices, there is no hw allocated to that block.
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*/
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if (is_l2_cache) {
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l2_count++;
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if (l2_count > curr_config->num_l2_slices)
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hw_res_available = false;
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else
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hw_res_available = true;
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}
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/*
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* For the shader cores, the current shader_mask allocated is
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* always a subgroup of the maximum shader_mask, so after
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* jumping any L2 cache not available the available shader cores
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* will always have a matching set of blk instances available to
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* accumulate them.
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*/
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else
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hw_res_available = true;
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/*
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* Skip block if no values in the destination block are enabled.
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*/
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if (kbase_hwcnt_enable_map_block_enabled(dst_enable_map, grp, blk, blk_inst)) {
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u64 *dst_blk =
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kbase_hwcnt_dump_buffer_block_instance(dst, grp, blk, blk_inst);
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const u64 *src_blk = dump_src + src_offset;
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bool blk_powered;
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if (!is_shader_core) {
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/* Under the current PM system, counters will
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* only be enabled after all non shader core
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* blocks are powered up.
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*/
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blk_powered = true;
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} else {
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/* Check the PM core mask to see if the shader
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* core is powered up.
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*/
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blk_powered = core_mask & 1;
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}
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if (blk_powered && !is_undefined && hw_res_available) {
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/* Only powered and defined blocks have valid data. */
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if (accumulate) {
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kbase_hwcnt_dump_buffer_block_accumulate(dst_blk, src_blk,
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hdr_cnt, ctr_cnt);
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} else {
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kbase_hwcnt_dump_buffer_block_copy(dst_blk, src_blk,
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(hdr_cnt + ctr_cnt));
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}
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} else {
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/* Even though the block might be undefined, the
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* user has enabled counter collection for it.
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* We should not propagate garbage data.
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*/
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if (accumulate) {
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/* No-op to preserve existing values */
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} else {
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/* src is garbage, so zero the dst */
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kbase_hwcnt_dump_buffer_block_zero(dst_blk,
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(hdr_cnt + ctr_cnt));
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}
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}
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}
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/* Just increase the src_offset if the HW is available */
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if (hw_res_available)
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src_offset += (hdr_cnt + ctr_cnt);
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if (is_shader_core)
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core_mask = core_mask >> 1;
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}
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return 0;
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}
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int kbase_hwcnt_csf_dump_get(struct kbase_hwcnt_dump_buffer *dst, u64 *src,
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const struct kbase_hwcnt_enable_map *dst_enable_map, bool accumulate)
|
{
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const struct kbase_hwcnt_metadata *metadata;
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const u64 *dump_src = src;
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size_t src_offset = 0;
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size_t grp, blk, blk_inst;
|
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if (!dst || !src || !dst_enable_map || (dst_enable_map->metadata != dst->metadata))
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return -EINVAL;
|
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metadata = dst->metadata;
|
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kbase_hwcnt_metadata_for_each_block(metadata, grp, blk, blk_inst)
|
{
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const size_t hdr_cnt = kbase_hwcnt_metadata_block_headers_count(metadata, grp, blk);
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const size_t ctr_cnt =
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kbase_hwcnt_metadata_block_counters_count(metadata, grp, blk);
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const uint64_t blk_type = kbase_hwcnt_metadata_block_type(metadata, grp, blk);
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const bool is_undefined = kbase_hwcnt_is_block_type_undefined(
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kbase_hwcnt_metadata_group_type(metadata, grp), blk_type);
|
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/*
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* Skip block if no values in the destination block are enabled.
|
*/
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if (kbase_hwcnt_enable_map_block_enabled(dst_enable_map, grp, blk, blk_inst)) {
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u64 *dst_blk =
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kbase_hwcnt_dump_buffer_block_instance(dst, grp, blk, blk_inst);
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const u64 *src_blk = dump_src + src_offset;
|
|
if (!is_undefined) {
|
if (accumulate) {
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kbase_hwcnt_dump_buffer_block_accumulate(dst_blk, src_blk,
|
hdr_cnt, ctr_cnt);
|
} else {
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kbase_hwcnt_dump_buffer_block_copy(dst_blk, src_blk,
|
(hdr_cnt + ctr_cnt));
|
}
|
} else {
|
/* Even though the block might be undefined, the
|
* user has enabled counter collection for it.
|
* We should not propagate garbage data.
|
*/
|
if (accumulate) {
|
/* No-op to preserve existing values */
|
} else {
|
/* src is garbage, so zero the dst */
|
kbase_hwcnt_dump_buffer_block_zero(dst_blk,
|
(hdr_cnt + ctr_cnt));
|
}
|
}
|
}
|
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src_offset += (hdr_cnt + ctr_cnt);
|
}
|
|
return 0;
|
}
|
|
/**
|
* kbasep_hwcnt_backend_gpu_block_map_from_physical() - Convert from a physical
|
* block enable map to a
|
* block enable map
|
* abstraction.
|
* @phys: Physical 32-bit block enable map
|
* @lo: Non-NULL pointer to where low 64 bits of block enable map abstraction
|
* will be stored.
|
* @hi: Non-NULL pointer to where high 64 bits of block enable map abstraction
|
* will be stored.
|
*/
|
static inline void kbasep_hwcnt_backend_gpu_block_map_from_physical(u32 phys, u64 *lo, u64 *hi)
|
{
|
u64 dwords[2] = { 0, 0 };
|
|
size_t dword_idx;
|
|
for (dword_idx = 0; dword_idx < 2; dword_idx++) {
|
const u16 packed = phys >> (16 * dword_idx);
|
u64 dword = 0;
|
|
size_t hword_bit;
|
|
for (hword_bit = 0; hword_bit < 16; hword_bit++) {
|
const size_t dword_bit = hword_bit * 4;
|
const u64 mask = (packed >> (hword_bit)) & 0x1;
|
|
dword |= mask << (dword_bit + 0);
|
dword |= mask << (dword_bit + 1);
|
dword |= mask << (dword_bit + 2);
|
dword |= mask << (dword_bit + 3);
|
}
|
dwords[dword_idx] = dword;
|
}
|
*lo = dwords[0];
|
*hi = dwords[1];
|
}
|
|
void kbase_hwcnt_gpu_enable_map_to_physical(struct kbase_hwcnt_physical_enable_map *dst,
|
const struct kbase_hwcnt_enable_map *src)
|
{
|
const struct kbase_hwcnt_metadata *metadata;
|
u64 fe_bm[EM_COUNT] = { 0 };
|
u64 shader_bm[EM_COUNT] = { 0 };
|
u64 tiler_bm[EM_COUNT] = { 0 };
|
u64 mmu_l2_bm[EM_COUNT] = { 0 };
|
size_t grp, blk, blk_inst;
|
|
if (WARN_ON(!src) || WARN_ON(!dst))
|
return;
|
|
metadata = src->metadata;
|
|
kbase_hwcnt_metadata_for_each_block(metadata, grp, blk, blk_inst)
|
{
|
const u64 grp_type = kbase_hwcnt_metadata_group_type(metadata, grp);
|
const u64 blk_type = kbase_hwcnt_metadata_block_type(metadata, grp, blk);
|
const u64 *blk_map = kbase_hwcnt_enable_map_block_instance(src, grp, blk, blk_inst);
|
|
if ((enum kbase_hwcnt_gpu_group_type)grp_type == KBASE_HWCNT_GPU_GROUP_TYPE_V5) {
|
const size_t map_stride =
|
kbase_hwcnt_metadata_block_enable_map_stride(metadata, grp, blk);
|
size_t map_idx;
|
|
for (map_idx = 0; map_idx < map_stride; ++map_idx) {
|
if (WARN_ON(map_idx >= EM_COUNT))
|
break;
|
|
switch ((enum kbase_hwcnt_gpu_v5_block_type)blk_type) {
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE_UNDEFINED:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC_UNDEFINED:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER_UNDEFINED:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS_UNDEFINED:
|
/* Nothing to do in this case. */
|
break;
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE2:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE3:
|
fe_bm[map_idx] |= blk_map[map_idx];
|
break;
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER:
|
tiler_bm[map_idx] |= blk_map[map_idx];
|
break;
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC2:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC3:
|
shader_bm[map_idx] |= blk_map[map_idx];
|
break;
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS2:
|
mmu_l2_bm[map_idx] |= blk_map[map_idx];
|
break;
|
default:
|
WARN_ON(true);
|
}
|
}
|
} else {
|
WARN_ON(true);
|
}
|
}
|
|
dst->fe_bm = kbase_hwcnt_backend_gpu_block_map_to_physical(fe_bm[EM_LO], fe_bm[EM_HI]);
|
dst->shader_bm =
|
kbase_hwcnt_backend_gpu_block_map_to_physical(shader_bm[EM_LO], shader_bm[EM_HI]);
|
dst->tiler_bm =
|
kbase_hwcnt_backend_gpu_block_map_to_physical(tiler_bm[EM_LO], tiler_bm[EM_HI]);
|
dst->mmu_l2_bm =
|
kbase_hwcnt_backend_gpu_block_map_to_physical(mmu_l2_bm[EM_LO], mmu_l2_bm[EM_HI]);
|
}
|
|
void kbase_hwcnt_gpu_set_to_physical(enum kbase_hwcnt_physical_set *dst, enum kbase_hwcnt_set src)
|
{
|
switch (src) {
|
case KBASE_HWCNT_SET_PRIMARY:
|
*dst = KBASE_HWCNT_PHYSICAL_SET_PRIMARY;
|
break;
|
case KBASE_HWCNT_SET_SECONDARY:
|
*dst = KBASE_HWCNT_PHYSICAL_SET_SECONDARY;
|
break;
|
case KBASE_HWCNT_SET_TERTIARY:
|
*dst = KBASE_HWCNT_PHYSICAL_SET_TERTIARY;
|
break;
|
default:
|
WARN_ON(true);
|
}
|
}
|
|
void kbase_hwcnt_gpu_enable_map_from_physical(struct kbase_hwcnt_enable_map *dst,
|
const struct kbase_hwcnt_physical_enable_map *src)
|
{
|
const struct kbase_hwcnt_metadata *metadata;
|
|
u64 fe_bm[EM_COUNT] = { 0 };
|
u64 shader_bm[EM_COUNT] = { 0 };
|
u64 tiler_bm[EM_COUNT] = { 0 };
|
u64 mmu_l2_bm[EM_COUNT] = { 0 };
|
size_t grp, blk, blk_inst;
|
|
if (WARN_ON(!src) || WARN_ON(!dst))
|
return;
|
|
metadata = dst->metadata;
|
|
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->fe_bm, &fe_bm[EM_LO], &fe_bm[EM_HI]);
|
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->shader_bm, &shader_bm[EM_LO],
|
&shader_bm[EM_HI]);
|
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->tiler_bm, &tiler_bm[EM_LO],
|
&tiler_bm[EM_HI]);
|
kbasep_hwcnt_backend_gpu_block_map_from_physical(src->mmu_l2_bm, &mmu_l2_bm[EM_LO],
|
&mmu_l2_bm[EM_HI]);
|
|
kbase_hwcnt_metadata_for_each_block(metadata, grp, blk, blk_inst)
|
{
|
const u64 grp_type = kbase_hwcnt_metadata_group_type(metadata, grp);
|
const u64 blk_type = kbase_hwcnt_metadata_block_type(metadata, grp, blk);
|
u64 *blk_map = kbase_hwcnt_enable_map_block_instance(dst, grp, blk, blk_inst);
|
|
if ((enum kbase_hwcnt_gpu_group_type)grp_type == KBASE_HWCNT_GPU_GROUP_TYPE_V5) {
|
const size_t map_stride =
|
kbase_hwcnt_metadata_block_enable_map_stride(metadata, grp, blk);
|
size_t map_idx;
|
|
for (map_idx = 0; map_idx < map_stride; ++map_idx) {
|
if (WARN_ON(map_idx >= EM_COUNT))
|
break;
|
|
switch ((enum kbase_hwcnt_gpu_v5_block_type)blk_type) {
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE_UNDEFINED:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC_UNDEFINED:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER_UNDEFINED:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS_UNDEFINED:
|
/* Nothing to do in this case. */
|
break;
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE2:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_FE3:
|
blk_map[map_idx] = fe_bm[map_idx];
|
break;
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_TILER:
|
blk_map[map_idx] = tiler_bm[map_idx];
|
break;
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC2:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_SC3:
|
blk_map[map_idx] = shader_bm[map_idx];
|
break;
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS:
|
case KBASE_HWCNT_GPU_V5_BLOCK_TYPE_PERF_MEMSYS2:
|
blk_map[map_idx] = mmu_l2_bm[map_idx];
|
break;
|
default:
|
WARN_ON(true);
|
}
|
}
|
} else {
|
WARN_ON(true);
|
}
|
}
|
}
|
|
void kbase_hwcnt_gpu_patch_dump_headers(struct kbase_hwcnt_dump_buffer *buf,
|
const struct kbase_hwcnt_enable_map *enable_map)
|
{
|
const struct kbase_hwcnt_metadata *metadata;
|
size_t grp, blk, blk_inst;
|
|
if (WARN_ON(!buf) || WARN_ON(!enable_map) || WARN_ON(buf->metadata != enable_map->metadata))
|
return;
|
|
metadata = buf->metadata;
|
|
kbase_hwcnt_metadata_for_each_block(metadata, grp, blk, blk_inst)
|
{
|
const u64 grp_type = kbase_hwcnt_metadata_group_type(metadata, grp);
|
u64 *buf_blk = kbase_hwcnt_dump_buffer_block_instance(buf, grp, blk, blk_inst);
|
const u64 *blk_map =
|
kbase_hwcnt_enable_map_block_instance(enable_map, grp, blk, blk_inst);
|
|
if ((enum kbase_hwcnt_gpu_group_type)grp_type == KBASE_HWCNT_GPU_GROUP_TYPE_V5) {
|
const size_t map_stride =
|
kbase_hwcnt_metadata_block_enable_map_stride(metadata, grp, blk);
|
u64 prfcnt_bm[EM_COUNT] = { 0 };
|
u32 prfcnt_en = 0;
|
size_t map_idx;
|
|
for (map_idx = 0; map_idx < map_stride; ++map_idx) {
|
if (WARN_ON(map_idx >= EM_COUNT))
|
break;
|
|
prfcnt_bm[map_idx] = blk_map[map_idx];
|
}
|
|
prfcnt_en = kbase_hwcnt_backend_gpu_block_map_to_physical(prfcnt_bm[EM_LO],
|
prfcnt_bm[EM_HI]);
|
|
buf_blk[KBASE_HWCNT_V5_PRFCNT_EN_HEADER] = prfcnt_en;
|
} else {
|
WARN_ON(true);
|
}
|
}
|
}
|
