// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include <mali_kbase.h>
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#include <mali_kbase_ctx_sched.h>
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#include <hwcnt/mali_kbase_hwcnt_context.h>
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#include <device/mali_kbase_device.h>
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#include <backend/gpu/mali_kbase_irq_internal.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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#include <mali_kbase_regs_history_debugfs.h>
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#include <csf/mali_kbase_csf_trace_buffer.h>
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#include <csf/ipa_control/mali_kbase_csf_ipa_control.h>
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#include <mali_kbase_reset_gpu.h>
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#include <csf/mali_kbase_csf_firmware_log.h>
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enum kbasep_soft_reset_status {
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RESET_SUCCESS = 0,
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SOFT_RESET_FAILED,
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L2_ON_FAILED,
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MCU_REINIT_FAILED
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};
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static inline bool
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kbase_csf_reset_state_is_silent(enum kbase_csf_reset_gpu_state state)
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{
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return (state == KBASE_CSF_RESET_GPU_COMMITTED_SILENT);
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}
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static inline bool
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kbase_csf_reset_state_is_committed(enum kbase_csf_reset_gpu_state state)
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{
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return (state == KBASE_CSF_RESET_GPU_COMMITTED ||
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state == KBASE_CSF_RESET_GPU_COMMITTED_SILENT);
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}
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static inline bool
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kbase_csf_reset_state_is_active(enum kbase_csf_reset_gpu_state state)
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{
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return (state == KBASE_CSF_RESET_GPU_HAPPENING);
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}
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/**
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* DOC: Mechanism for coherent access to the HW with respect to GPU reset
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*
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* Access to the HW from non-atomic context outside of the reset thread must
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* use kbase_reset_gpu_prevent_and_wait() / kbase_reset_gpu_try_prevent().
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*
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* This currently works by taking the &kbase_device's csf.reset.sem, for
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* 'write' access by the GPU reset thread and 'read' access by every other
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* thread. The use of this rw_semaphore means:
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*
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* - there will be mutual exclusion (and thus waiting) between the thread doing
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* reset ('writer') and threads trying to access the GPU for 'normal'
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* operations ('readers')
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*
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* - multiple threads may prevent reset from happening without serializing each
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* other prematurely. Note that at present the wait for reset to finish has
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* to be done higher up in the driver than actual GPU access, at a point
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* where it won't cause lock ordering issues. At such a point, some paths may
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* actually lead to no GPU access, but we would prefer to avoid serializing
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* at that level
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*
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* - lockdep (if enabled in the kernel) will check such uses for deadlock
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*
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* If instead &kbase_device's csf.reset.wait &wait_queue_head_t were used on
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* its own, we'd also need to add a &lockdep_map and appropriate lockdep calls
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* to make use of lockdep checking in all places where the &wait_queue_head_t
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* is waited upon or signaled.
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*
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* Indeed places where we wait on &kbase_device's csf.reset.wait (such as
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* kbase_reset_gpu_wait()) are the only places where we need extra call(s) to
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* lockdep, and they are made on the existing rw_semaphore.
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*
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* For non-atomic access, the &kbase_device's csf.reset.state member should be
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* checked instead, such as by using kbase_reset_gpu_is_active().
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*
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* Ideally the &rw_semaphore should be replaced in future with a single mutex
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* that protects any access to the GPU, via reset or otherwise.
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*/
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int kbase_reset_gpu_prevent_and_wait(struct kbase_device *kbdev)
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{
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down_read(&kbdev->csf.reset.sem);
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if (atomic_read(&kbdev->csf.reset.state) ==
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KBASE_CSF_RESET_GPU_FAILED) {
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up_read(&kbdev->csf.reset.sem);
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return -ENOMEM;
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}
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if (WARN_ON(kbase_reset_gpu_is_active(kbdev))) {
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up_read(&kbdev->csf.reset.sem);
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return -EFAULT;
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}
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return 0;
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}
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KBASE_EXPORT_TEST_API(kbase_reset_gpu_prevent_and_wait);
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int kbase_reset_gpu_try_prevent(struct kbase_device *kbdev)
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{
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if (!down_read_trylock(&kbdev->csf.reset.sem))
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return -EAGAIN;
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if (atomic_read(&kbdev->csf.reset.state) ==
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KBASE_CSF_RESET_GPU_FAILED) {
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up_read(&kbdev->csf.reset.sem);
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return -ENOMEM;
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}
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if (WARN_ON(kbase_reset_gpu_is_active(kbdev))) {
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up_read(&kbdev->csf.reset.sem);
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return -EFAULT;
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}
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return 0;
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}
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void kbase_reset_gpu_allow(struct kbase_device *kbdev)
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{
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up_read(&kbdev->csf.reset.sem);
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}
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KBASE_EXPORT_TEST_API(kbase_reset_gpu_allow);
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void kbase_reset_gpu_assert_prevented(struct kbase_device *kbdev)
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{
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#if KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE
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lockdep_assert_held_read(&kbdev->csf.reset.sem);
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#else
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lockdep_assert_held(&kbdev->csf.reset.sem);
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#endif
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WARN_ON(kbase_reset_gpu_is_active(kbdev));
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}
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void kbase_reset_gpu_assert_failed_or_prevented(struct kbase_device *kbdev)
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{
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if (atomic_read(&kbdev->csf.reset.state) == KBASE_CSF_RESET_GPU_FAILED)
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return;
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#if KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE
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lockdep_assert_held_read(&kbdev->csf.reset.sem);
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#else
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lockdep_assert_held(&kbdev->csf.reset.sem);
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#endif
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WARN_ON(kbase_reset_gpu_is_active(kbdev));
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}
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/* Mark the reset as now happening, and synchronize with other threads that
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* might be trying to access the GPU
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*/
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static void kbase_csf_reset_begin_hw_access_sync(
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struct kbase_device *kbdev,
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enum kbase_csf_reset_gpu_state initial_reset_state)
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{
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unsigned long hwaccess_lock_flags;
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unsigned long scheduler_spin_lock_flags;
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/* Note this is a WARN/atomic_set because it is a software issue for a
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* race to be occurring here
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*/
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WARN_ON(!kbase_csf_reset_state_is_committed(initial_reset_state));
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down_write(&kbdev->csf.reset.sem);
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/* Threads in atomic context accessing the HW will hold one of these
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* locks, so synchronize with them too.
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*/
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spin_lock_irqsave(&kbdev->hwaccess_lock, hwaccess_lock_flags);
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kbase_csf_scheduler_spin_lock(kbdev, &scheduler_spin_lock_flags);
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atomic_set(&kbdev->csf.reset.state, KBASE_RESET_GPU_HAPPENING);
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kbase_csf_scheduler_spin_unlock(kbdev, scheduler_spin_lock_flags);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, hwaccess_lock_flags);
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}
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/* Mark the reset as finished and allow others threads to once more access the
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* GPU
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*/
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static void kbase_csf_reset_end_hw_access(struct kbase_device *kbdev,
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int err_during_reset,
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bool firmware_inited)
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{
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unsigned long hwaccess_lock_flags;
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unsigned long scheduler_spin_lock_flags;
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WARN_ON(!kbase_csf_reset_state_is_active(
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atomic_read(&kbdev->csf.reset.state)));
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/* Once again, we synchronize with atomic context threads accessing the
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* HW, as otherwise any actions they defer could get lost
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*/
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spin_lock_irqsave(&kbdev->hwaccess_lock, hwaccess_lock_flags);
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kbase_csf_scheduler_spin_lock(kbdev, &scheduler_spin_lock_flags);
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if (!err_during_reset) {
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atomic_set(&kbdev->csf.reset.state,
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KBASE_CSF_RESET_GPU_NOT_PENDING);
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} else {
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dev_err(kbdev->dev, "Reset failed to complete");
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atomic_set(&kbdev->csf.reset.state, KBASE_CSF_RESET_GPU_FAILED);
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}
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kbase_csf_scheduler_spin_unlock(kbdev, scheduler_spin_lock_flags);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, hwaccess_lock_flags);
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/* Invoke the scheduling tick after formally finishing the reset,
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* otherwise the tick might start too soon and notice that reset
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* is still in progress.
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*/
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up_write(&kbdev->csf.reset.sem);
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wake_up(&kbdev->csf.reset.wait);
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if (!err_during_reset && likely(firmware_inited))
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kbase_csf_scheduler_enable_tick_timer(kbdev);
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}
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static void kbase_csf_debug_dump_registers(struct kbase_device *kbdev)
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{
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kbase_io_history_dump(kbdev);
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dev_err(kbdev->dev, "Register state:");
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dev_err(kbdev->dev, " GPU_IRQ_RAWSTAT=0x%08x GPU_STATUS=0x%08x MCU_STATUS=0x%08x",
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kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)),
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kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_STATUS)),
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kbase_reg_read(kbdev, GPU_CONTROL_REG(MCU_STATUS)));
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dev_err(kbdev->dev, " JOB_IRQ_RAWSTAT=0x%08x MMU_IRQ_RAWSTAT=0x%08x GPU_FAULTSTATUS=0x%08x",
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kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_RAWSTAT)),
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kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_RAWSTAT)),
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kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS)));
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dev_err(kbdev->dev, " GPU_IRQ_MASK=0x%08x JOB_IRQ_MASK=0x%08x MMU_IRQ_MASK=0x%08x",
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kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)),
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kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK)),
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kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)));
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dev_err(kbdev->dev, " PWR_OVERRIDE0=0x%08x PWR_OVERRIDE1=0x%08x",
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kbase_reg_read(kbdev, GPU_CONTROL_REG(PWR_OVERRIDE0)),
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kbase_reg_read(kbdev, GPU_CONTROL_REG(PWR_OVERRIDE1)));
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dev_err(kbdev->dev, " SHADER_CONFIG=0x%08x L2_MMU_CONFIG=0x%08x TILER_CONFIG=0x%08x",
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kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_CONFIG)),
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kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_MMU_CONFIG)),
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kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_CONFIG)));
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}
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/**
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* kbase_csf_hwcnt_on_reset_error() - Sets HWCNT to appropriate state in the
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* event of an error during GPU reset.
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* @kbdev: Pointer to KBase device
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*/
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static void kbase_csf_hwcnt_on_reset_error(struct kbase_device *kbdev)
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{
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unsigned long flags;
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/* Treat this as an unrecoverable error for HWCNT */
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kbase_hwcnt_backend_csf_on_unrecoverable_error(&kbdev->hwcnt_gpu_iface);
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/* Re-enable counters to ensure matching enable/disable pair.
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* This might reduce the hwcnt disable count to 0, and therefore
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* trigger actual re-enabling of hwcnt.
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* However, as the backend is now in the unrecoverable error state,
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* re-enabling will immediately fail and put the context into the error
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* state, preventing the hardware from being touched (which could have
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* risked a hang).
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*/
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kbase_csf_scheduler_spin_lock(kbdev, &flags);
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kbase_hwcnt_context_enable(kbdev->hwcnt_gpu_ctx);
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kbase_csf_scheduler_spin_unlock(kbdev, flags);
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}
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static enum kbasep_soft_reset_status kbase_csf_reset_gpu_once(struct kbase_device *kbdev,
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bool firmware_inited, bool silent)
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{
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unsigned long flags;
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int err;
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enum kbasep_soft_reset_status ret = RESET_SUCCESS;
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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spin_lock(&kbdev->mmu_mask_change);
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kbase_pm_reset_start_locked(kbdev);
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dev_dbg(kbdev->dev,
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"We're about to flush out the IRQs and their bottom halves\n");
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kbdev->irq_reset_flush = true;
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/* Disable IRQ to avoid IRQ handlers to kick in after releasing the
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* spinlock; this also clears any outstanding interrupts
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*/
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kbase_pm_disable_interrupts_nolock(kbdev);
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spin_unlock(&kbdev->mmu_mask_change);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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dev_dbg(kbdev->dev, "Ensure that any IRQ handlers have finished\n");
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/* Must be done without any locks IRQ handlers will take. */
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kbase_synchronize_irqs(kbdev);
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dev_dbg(kbdev->dev, "Flush out any in-flight work items\n");
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kbase_flush_mmu_wqs(kbdev);
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dev_dbg(kbdev->dev,
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"The flush has completed so reset the active indicator\n");
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kbdev->irq_reset_flush = false;
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if (!silent)
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dev_err(kbdev->dev, "Resetting GPU (allowing up to %d ms)",
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RESET_TIMEOUT);
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/* Output the state of some interesting registers to help in the
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* debugging of GPU resets, and dump the firmware trace buffer
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*/
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if (!silent) {
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kbase_csf_debug_dump_registers(kbdev);
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if (likely(firmware_inited))
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kbase_csf_firmware_log_dump_buffer(kbdev);
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}
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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kbase_ipa_control_handle_gpu_reset_pre(kbdev);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
|
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/* Tell hardware counters a reset is about to occur.
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* If the backend is in an unrecoverable error state (e.g. due to
|
* firmware being unresponsive) this will transition the backend out of
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* it, on the assumption a reset will fix whatever problem there was.
|
*/
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kbase_hwcnt_backend_csf_on_before_reset(&kbdev->hwcnt_gpu_iface);
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mutex_lock(&kbdev->pm.lock);
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/* Reset the GPU */
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err = kbase_pm_init_hw(kbdev, 0);
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mutex_unlock(&kbdev->pm.lock);
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|
if (WARN_ON(err))
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return SOFT_RESET_FAILED;
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mutex_lock(&kbdev->mmu_hw_mutex);
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
|
kbase_ctx_sched_restore_all_as(kbdev);
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kbase_ipa_control_handle_gpu_reset_post(kbdev);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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mutex_unlock(&kbdev->mmu_hw_mutex);
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|
kbase_pm_enable_interrupts(kbdev);
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mutex_lock(&kbdev->pm.lock);
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kbase_pm_reset_complete(kbdev);
|
/* Synchronously wait for the reload of firmware to complete */
|
err = kbase_pm_wait_for_desired_state(kbdev);
|
mutex_unlock(&kbdev->pm.lock);
|
|
if (err) {
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if (!kbase_pm_l2_is_in_desired_state(kbdev))
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ret = L2_ON_FAILED;
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else if (!kbase_pm_mcu_is_in_desired_state(kbdev))
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ret = MCU_REINIT_FAILED;
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}
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|
return ret;
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}
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static int kbase_csf_reset_gpu_now(struct kbase_device *kbdev, bool firmware_inited, bool silent)
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{
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unsigned long flags;
|
enum kbasep_soft_reset_status ret;
|
|
WARN_ON(kbdev->irq_reset_flush);
|
/* The reset must now be happening otherwise other threads will not
|
* have been synchronized with to stop their access to the HW
|
*/
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#if KERNEL_VERSION(5, 3, 0) <= LINUX_VERSION_CODE
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lockdep_assert_held_write(&kbdev->csf.reset.sem);
|
#elif KERNEL_VERSION(4, 10, 0) <= LINUX_VERSION_CODE
|
lockdep_assert_held_exclusive(&kbdev->csf.reset.sem);
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#else
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lockdep_assert_held(&kbdev->csf.reset.sem);
|
#endif
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WARN_ON(!kbase_reset_gpu_is_active(kbdev));
|
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/* Reset the scheduler state before disabling the interrupts as suspend
|
* of active CSG slots would also be done as a part of reset.
|
*/
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if (likely(firmware_inited))
|
kbase_csf_scheduler_reset(kbdev);
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cancel_work_sync(&kbdev->csf.firmware_reload_work);
|
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dev_dbg(kbdev->dev, "Disable GPU hardware counters.\n");
|
/* This call will block until counters are disabled. */
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kbase_hwcnt_context_disable(kbdev->hwcnt_gpu_ctx);
|
|
ret = kbase_csf_reset_gpu_once(kbdev, firmware_inited, silent);
|
if (ret == SOFT_RESET_FAILED) {
|
dev_err(kbdev->dev, "Soft-reset failed");
|
goto err;
|
} else if (ret == L2_ON_FAILED) {
|
dev_err(kbdev->dev, "L2 power up failed after the soft-reset");
|
goto err;
|
} else if (ret == MCU_REINIT_FAILED) {
|
dev_err(kbdev->dev, "MCU re-init failed trying full firmware reload");
|
/* Since MCU reinit failed despite successful soft reset, we can try
|
* the firmware full reload.
|
*/
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kbdev->csf.firmware_full_reload_needed = true;
|
ret = kbase_csf_reset_gpu_once(kbdev, firmware_inited, true);
|
if (ret != RESET_SUCCESS) {
|
dev_err(kbdev->dev,
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"MCU Re-init failed even after trying full firmware reload, ret = [%d]",
|
ret);
|
goto err;
|
}
|
}
|
|
/* Re-enable GPU hardware counters */
|
kbase_csf_scheduler_spin_lock(kbdev, &flags);
|
kbase_hwcnt_context_enable(kbdev->hwcnt_gpu_ctx);
|
kbase_csf_scheduler_spin_unlock(kbdev, flags);
|
if (!silent)
|
dev_err(kbdev->dev, "Reset complete");
|
return 0;
|
err:
|
|
kbase_csf_hwcnt_on_reset_error(kbdev);
|
return -1;
|
}
|
|
static void kbase_csf_reset_gpu_worker(struct work_struct *data)
|
{
|
struct kbase_device *kbdev = container_of(data, struct kbase_device,
|
csf.reset.work);
|
bool gpu_sleep_mode_active = false;
|
bool firmware_inited;
|
unsigned long flags;
|
int err = 0;
|
const enum kbase_csf_reset_gpu_state initial_reset_state =
|
atomic_read(&kbdev->csf.reset.state);
|
const bool silent =
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kbase_csf_reset_state_is_silent(initial_reset_state);
|
|
/* Ensure any threads (e.g. executing the CSF scheduler) have finished
|
* using the HW
|
*/
|
kbase_csf_reset_begin_hw_access_sync(kbdev, initial_reset_state);
|
|
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
|
firmware_inited = kbdev->csf.firmware_inited;
|
#ifdef KBASE_PM_RUNTIME
|
gpu_sleep_mode_active = kbdev->pm.backend.gpu_sleep_mode_active;
|
#endif
|
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
|
|
if (unlikely(gpu_sleep_mode_active)) {
|
#ifdef KBASE_PM_RUNTIME
|
/* As prior to GPU reset all on-slot groups are suspended,
|
* need to wake up the MCU from sleep.
|
* No pm active reference is taken here since GPU is in sleep
|
* state and both runtime & system suspend synchronize with the
|
* GPU reset before they wake up the GPU to suspend on-slot
|
* groups. GPUCORE-29850 would add the proper handling.
|
*/
|
kbase_pm_lock(kbdev);
|
if (kbase_pm_force_mcu_wakeup_after_sleep(kbdev))
|
dev_warn(kbdev->dev, "Wait for MCU wake up failed on GPU reset");
|
kbase_pm_unlock(kbdev);
|
|
err = kbase_csf_reset_gpu_now(kbdev, firmware_inited, silent);
|
#endif
|
} else if (!kbase_pm_context_active_handle_suspend(kbdev,
|
KBASE_PM_SUSPEND_HANDLER_DONT_REACTIVATE)) {
|
err = kbase_csf_reset_gpu_now(kbdev, firmware_inited, silent);
|
kbase_pm_context_idle(kbdev);
|
}
|
|
kbase_disjoint_state_down(kbdev);
|
|
/* Allow other threads to once again use the GPU */
|
kbase_csf_reset_end_hw_access(kbdev, err, firmware_inited);
|
}
|
|
bool kbase_prepare_to_reset_gpu(struct kbase_device *kbdev, unsigned int flags)
|
{
|
if (flags & RESET_FLAGS_HWC_UNRECOVERABLE_ERROR)
|
kbase_hwcnt_backend_csf_on_unrecoverable_error(
|
&kbdev->hwcnt_gpu_iface);
|
|
if (atomic_cmpxchg(&kbdev->csf.reset.state,
|
KBASE_CSF_RESET_GPU_NOT_PENDING,
|
KBASE_CSF_RESET_GPU_PREPARED) !=
|
KBASE_CSF_RESET_GPU_NOT_PENDING)
|
/* Some other thread is already resetting the GPU */
|
return false;
|
|
return true;
|
}
|
KBASE_EXPORT_TEST_API(kbase_prepare_to_reset_gpu);
|
|
bool kbase_prepare_to_reset_gpu_locked(struct kbase_device *kbdev,
|
unsigned int flags)
|
{
|
lockdep_assert_held(&kbdev->hwaccess_lock);
|
|
return kbase_prepare_to_reset_gpu(kbdev, flags);
|
}
|
|
void kbase_reset_gpu(struct kbase_device *kbdev)
|
{
|
/* Note this is a WARN/atomic_set because it is a software issue for
|
* a race to be occurring here
|
*/
|
if (WARN_ON(atomic_read(&kbdev->csf.reset.state) !=
|
KBASE_RESET_GPU_PREPARED))
|
return;
|
|
atomic_set(&kbdev->csf.reset.state, KBASE_CSF_RESET_GPU_COMMITTED);
|
dev_err(kbdev->dev, "Preparing to soft-reset GPU\n");
|
|
kbase_disjoint_state_up(kbdev);
|
|
queue_work(kbdev->csf.reset.workq, &kbdev->csf.reset.work);
|
}
|
KBASE_EXPORT_TEST_API(kbase_reset_gpu);
|
|
void kbase_reset_gpu_locked(struct kbase_device *kbdev)
|
{
|
lockdep_assert_held(&kbdev->hwaccess_lock);
|
|
kbase_reset_gpu(kbdev);
|
}
|
|
int kbase_reset_gpu_silent(struct kbase_device *kbdev)
|
{
|
if (atomic_cmpxchg(&kbdev->csf.reset.state,
|
KBASE_CSF_RESET_GPU_NOT_PENDING,
|
KBASE_CSF_RESET_GPU_COMMITTED_SILENT) !=
|
KBASE_CSF_RESET_GPU_NOT_PENDING) {
|
/* Some other thread is already resetting the GPU */
|
return -EAGAIN;
|
}
|
|
kbase_disjoint_state_up(kbdev);
|
|
queue_work(kbdev->csf.reset.workq, &kbdev->csf.reset.work);
|
|
return 0;
|
}
|
KBASE_EXPORT_TEST_API(kbase_reset_gpu_silent);
|
|
bool kbase_reset_gpu_is_active(struct kbase_device *kbdev)
|
{
|
enum kbase_csf_reset_gpu_state reset_state =
|
atomic_read(&kbdev->csf.reset.state);
|
|
/* For CSF, the reset is considered active only when the reset worker
|
* is actually executing and other threads would have to wait for it to
|
* complete
|
*/
|
return kbase_csf_reset_state_is_active(reset_state);
|
}
|
|
bool kbase_reset_gpu_is_not_pending(struct kbase_device *kbdev)
|
{
|
return atomic_read(&kbdev->csf.reset.state) == KBASE_CSF_RESET_GPU_NOT_PENDING;
|
}
|
|
int kbase_reset_gpu_wait(struct kbase_device *kbdev)
|
{
|
const long wait_timeout =
|
kbase_csf_timeout_in_jiffies(kbase_get_timeout_ms(kbdev, CSF_GPU_RESET_TIMEOUT));
|
long remaining;
|
|
/* Inform lockdep we might be trying to wait on a reset (as
|
* would've been done with down_read() - which has no 'timeout'
|
* variant), then use wait_event_timeout() to implement the timed
|
* wait.
|
*
|
* in CONFIG_PROVE_LOCKING builds, this should catch potential 'time
|
* bound' deadlocks such as:
|
* - incorrect lock order with respect to others locks
|
* - current thread has prevented reset
|
* - current thread is executing the reset worker
|
*/
|
might_lock_read(&kbdev->csf.reset.sem);
|
|
remaining = wait_event_timeout(
|
kbdev->csf.reset.wait,
|
(atomic_read(&kbdev->csf.reset.state) ==
|
KBASE_CSF_RESET_GPU_NOT_PENDING) ||
|
(atomic_read(&kbdev->csf.reset.state) ==
|
KBASE_CSF_RESET_GPU_FAILED),
|
wait_timeout);
|
|
if (!remaining) {
|
dev_warn(kbdev->dev, "Timed out waiting for the GPU reset to complete");
|
|
|
return -ETIMEDOUT;
|
} else if (atomic_read(&kbdev->csf.reset.state) ==
|
KBASE_CSF_RESET_GPU_FAILED) {
|
return -ENOMEM;
|
}
|
|
return 0;
|
}
|
KBASE_EXPORT_TEST_API(kbase_reset_gpu_wait);
|
|
int kbase_reset_gpu_init(struct kbase_device *kbdev)
|
{
|
kbdev->csf.reset.workq = alloc_workqueue("Mali reset workqueue", 0, 1);
|
if (kbdev->csf.reset.workq == NULL)
|
return -ENOMEM;
|
|
INIT_WORK(&kbdev->csf.reset.work, kbase_csf_reset_gpu_worker);
|
|
init_waitqueue_head(&kbdev->csf.reset.wait);
|
init_rwsem(&kbdev->csf.reset.sem);
|
|
return 0;
|
}
|
|
void kbase_reset_gpu_term(struct kbase_device *kbdev)
|
{
|
destroy_workqueue(kbdev->csf.reset.workq);
|
}
|
