// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2010, 2012-2015, 2017-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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/*
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* Model Linux Framework interfaces.
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*/
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#include <mali_kbase.h>
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#include <gpu/mali_kbase_gpu_regmap.h>
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#include "backend/gpu/mali_kbase_model_linux.h"
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#include "device/mali_kbase_device.h"
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#include "mali_kbase_irq_internal.h"
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#include <linux/kthread.h>
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struct model_irq_data {
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struct kbase_device *kbdev;
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struct work_struct work;
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};
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static void serve_job_irq(struct work_struct *work)
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{
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struct model_irq_data *data = container_of(work, struct model_irq_data,
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work);
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struct kbase_device *kbdev = data->kbdev;
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/* Make sure no worker is already serving this IRQ */
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while (atomic_cmpxchg(&kbdev->serving_job_irq, 1, 0) == 1) {
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u32 val;
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while ((val = kbase_reg_read(kbdev,
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JOB_CONTROL_REG(JOB_IRQ_STATUS)))) {
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unsigned long flags;
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/* Handle the IRQ */
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spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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#if MALI_USE_CSF
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kbase_csf_interrupt(kbdev, val);
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#else
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kbase_job_done(kbdev, val);
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#endif
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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}
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}
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kmem_cache_free(kbdev->irq_slab, data);
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}
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static void serve_gpu_irq(struct work_struct *work)
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{
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struct model_irq_data *data = container_of(work, struct model_irq_data,
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work);
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struct kbase_device *kbdev = data->kbdev;
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/* Make sure no worker is already serving this IRQ */
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while (atomic_cmpxchg(&kbdev->serving_gpu_irq, 1, 0) == 1) {
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u32 val;
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while ((val = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(GPU_IRQ_STATUS)))) {
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/* Handle the IRQ */
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kbase_gpu_interrupt(kbdev, val);
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}
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}
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kmem_cache_free(kbdev->irq_slab, data);
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}
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static void serve_mmu_irq(struct work_struct *work)
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{
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struct model_irq_data *data = container_of(work, struct model_irq_data,
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work);
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struct kbase_device *kbdev = data->kbdev;
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/* Make sure no worker is already serving this IRQ */
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if (atomic_cmpxchg(&kbdev->serving_mmu_irq, 1, 0) == 1) {
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u32 val;
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while ((val = kbase_reg_read(kbdev,
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MMU_REG(MMU_IRQ_STATUS)))) {
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/* Handle the IRQ */
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kbase_mmu_interrupt(kbdev, val);
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}
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}
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kmem_cache_free(kbdev->irq_slab, data);
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}
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void gpu_device_raise_irq(void *model, u32 irq)
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{
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struct model_irq_data *data;
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struct kbase_device *kbdev = gpu_device_get_data(model);
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KBASE_DEBUG_ASSERT(kbdev);
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data = kmem_cache_alloc(kbdev->irq_slab, GFP_ATOMIC);
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if (data == NULL)
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return;
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data->kbdev = kbdev;
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switch (irq) {
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case MODEL_LINUX_JOB_IRQ:
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INIT_WORK(&data->work, serve_job_irq);
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atomic_set(&kbdev->serving_job_irq, 1);
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break;
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case MODEL_LINUX_GPU_IRQ:
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INIT_WORK(&data->work, serve_gpu_irq);
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atomic_set(&kbdev->serving_gpu_irq, 1);
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break;
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case MODEL_LINUX_MMU_IRQ:
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INIT_WORK(&data->work, serve_mmu_irq);
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atomic_set(&kbdev->serving_mmu_irq, 1);
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break;
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default:
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dev_warn(kbdev->dev, "Unknown IRQ");
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kmem_cache_free(kbdev->irq_slab, data);
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data = NULL;
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break;
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}
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if (data != NULL)
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queue_work(kbdev->irq_workq, &data->work);
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}
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void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value)
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{
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unsigned long flags;
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spin_lock_irqsave(&kbdev->reg_op_lock, flags);
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midgard_model_write_reg(kbdev->model, offset, value);
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spin_unlock_irqrestore(&kbdev->reg_op_lock, flags);
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}
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KBASE_EXPORT_TEST_API(kbase_reg_write);
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u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&kbdev->reg_op_lock, flags);
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midgard_model_read_reg(kbdev->model, offset, &val);
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spin_unlock_irqrestore(&kbdev->reg_op_lock, flags);
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return val;
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}
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KBASE_EXPORT_TEST_API(kbase_reg_read);
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int kbase_install_interrupts(struct kbase_device *kbdev)
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{
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KBASE_DEBUG_ASSERT(kbdev);
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atomic_set(&kbdev->serving_job_irq, 0);
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atomic_set(&kbdev->serving_gpu_irq, 0);
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atomic_set(&kbdev->serving_mmu_irq, 0);
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kbdev->irq_workq = alloc_ordered_workqueue("dummy irq queue", 0);
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if (kbdev->irq_workq == NULL)
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return -ENOMEM;
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kbdev->irq_slab = kmem_cache_create("dummy_irq_slab",
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sizeof(struct model_irq_data), 0, 0, NULL);
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if (kbdev->irq_slab == NULL) {
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destroy_workqueue(kbdev->irq_workq);
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return -ENOMEM;
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}
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return 0;
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}
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void kbase_release_interrupts(struct kbase_device *kbdev)
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{
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KBASE_DEBUG_ASSERT(kbdev);
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destroy_workqueue(kbdev->irq_workq);
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kmem_cache_destroy(kbdev->irq_slab);
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}
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void kbase_synchronize_irqs(struct kbase_device *kbdev)
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{
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KBASE_DEBUG_ASSERT(kbdev);
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flush_workqueue(kbdev->irq_workq);
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}
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KBASE_EXPORT_TEST_API(kbase_synchronize_irqs);
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int kbase_set_custom_irq_handler(struct kbase_device *kbdev,
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irq_handler_t custom_handler,
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int irq_type)
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{
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return 0;
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}
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KBASE_EXPORT_TEST_API(kbase_set_custom_irq_handler);
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irqreturn_t kbase_gpu_irq_test_handler(int irq, void *data, u32 val)
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{
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if (!val)
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return IRQ_NONE;
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return IRQ_HANDLED;
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}
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KBASE_EXPORT_TEST_API(kbase_gpu_irq_test_handler);
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int kbase_gpu_device_create(struct kbase_device *kbdev)
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{
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kbdev->model = midgard_model_create(kbdev);
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if (kbdev->model == NULL)
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return -ENOMEM;
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spin_lock_init(&kbdev->reg_op_lock);
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return 0;
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}
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/**
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* kbase_gpu_device_destroy - Destroy GPU device
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*
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* @kbdev: kbase device
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*/
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void kbase_gpu_device_destroy(struct kbase_device *kbdev)
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{
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midgard_model_destroy(kbdev->model);
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}
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