// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include <mali_kbase.h>
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#include <mali_kbase_bits.h>
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#include <mali_kbase_config_defaults.h>
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#include <device/mali_kbase_device.h>
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#include "mali_kbase_l2_mmu_config.h"
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/**
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* struct l2_mmu_config_limit_region - L2 MMU limit field
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*
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* @value: The default value to load into the L2_MMU_CONFIG register
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* @mask: The shifted mask of the field in the L2_MMU_CONFIG register
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* @shift: The shift of where the field starts in the L2_MMU_CONFIG register
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* This should be the same value as the smaller of the two mask
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* values
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*/
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struct l2_mmu_config_limit_region {
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u32 value, mask, shift;
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};
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/**
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* struct l2_mmu_config_limit - L2 MMU read and write limit
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*
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* @product_model: The GPU for which this entry applies
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* @read: Values for the read limit field
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* @write: Values for the write limit field
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*/
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struct l2_mmu_config_limit {
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u32 product_model;
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struct l2_mmu_config_limit_region read;
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struct l2_mmu_config_limit_region write;
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};
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/*
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* Zero represents no limit
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*
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* For LBEX TBEX TBAX TTRX and TNAX:
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* The value represents the number of outstanding reads (6 bits) or writes (5 bits)
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*
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* For all other GPUS it is a fraction see: mali_kbase_config_defaults.h
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*/
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static const struct l2_mmu_config_limit limits[] = {
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/* GPU, read, write */
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{GPU_ID2_PRODUCT_LBEX,
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{0, GENMASK(10, 5), 5},
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{0, GENMASK(16, 12), 12} },
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{GPU_ID2_PRODUCT_TBEX,
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{0, GENMASK(10, 5), 5},
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{0, GENMASK(16, 12), 12} },
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{GPU_ID2_PRODUCT_TBAX,
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{0, GENMASK(10, 5), 5},
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{0, GENMASK(16, 12), 12} },
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{GPU_ID2_PRODUCT_TTRX,
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{0, GENMASK(12, 7), 7},
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{0, GENMASK(17, 13), 13} },
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{GPU_ID2_PRODUCT_TNAX,
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{0, GENMASK(12, 7), 7},
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{0, GENMASK(17, 13), 13} },
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{GPU_ID2_PRODUCT_TGOX,
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{KBASE_3BIT_AID_32, GENMASK(14, 12), 12},
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{KBASE_3BIT_AID_32, GENMASK(17, 15), 15} },
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{GPU_ID2_PRODUCT_TNOX,
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{KBASE_3BIT_AID_32, GENMASK(14, 12), 12},
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{KBASE_3BIT_AID_32, GENMASK(17, 15), 15} },
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};
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int kbase_set_mmu_quirks(struct kbase_device *kbdev)
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{
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/* All older GPUs had 2 bits for both fields, this is a default */
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struct l2_mmu_config_limit limit = {
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0, /* Any GPU not in the limits array defined above */
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{KBASE_AID_32, GENMASK(25, 24), 24},
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{KBASE_AID_32, GENMASK(27, 26), 26}
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};
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u32 product_model, gpu_id;
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u32 mmu_config;
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int i;
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gpu_id = kbdev->gpu_props.props.raw_props.gpu_id;
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product_model = gpu_id & GPU_ID2_PRODUCT_MODEL;
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/* Limit the GPU bus bandwidth if the platform needs this. */
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for (i = 0; i < ARRAY_SIZE(limits); i++) {
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if (product_model == limits[i].product_model) {
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limit = limits[i];
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break;
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}
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}
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mmu_config = kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_MMU_CONFIG));
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if (kbase_is_gpu_removed(kbdev))
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return -EIO;
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mmu_config &= ~(limit.read.mask | limit.write.mask);
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/* Can't use FIELD_PREP() macro here as the mask isn't constant */
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mmu_config |= (limit.read.value << limit.read.shift) |
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(limit.write.value << limit.write.shift);
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kbdev->hw_quirks_mmu = mmu_config;
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if (kbdev->system_coherency == COHERENCY_ACE) {
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/* Allow memory configuration disparity to be ignored,
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* we optimize the use of shared memory and thus we
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* expect some disparity in the memory configuration.
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*/
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kbdev->hw_quirks_mmu |= L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY;
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}
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return 0;
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}
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