// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2014-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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/*
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* Base kernel property query backend APIs
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*/
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#include <mali_kbase.h>
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#include <device/mali_kbase_device.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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#include <backend/gpu/mali_kbase_cache_policy_backend.h>
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#include <mali_kbase_hwaccess_gpuprops.h>
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int kbase_backend_gpuprops_get(struct kbase_device *kbdev,
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struct kbase_gpuprops_regdump *regdump)
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{
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int i;
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struct kbase_gpuprops_regdump registers = { 0 };
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/* Fill regdump with the content of the relevant registers */
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registers.gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID));
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registers.l2_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_FEATURES));
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registers.tiler_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TILER_FEATURES));
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registers.mem_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(MEM_FEATURES));
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registers.mmu_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(MMU_FEATURES));
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registers.as_present = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(AS_PRESENT));
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#if !MALI_USE_CSF
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registers.js_present = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(JS_PRESENT));
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#else /* !MALI_USE_CSF */
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registers.js_present = 0;
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#endif /* !MALI_USE_CSF */
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for (i = 0; i < GPU_MAX_JOB_SLOTS; i++)
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#if !MALI_USE_CSF
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registers.js_features[i] = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(JS_FEATURES_REG(i)));
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#else /* !MALI_USE_CSF */
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registers.js_features[i] = 0;
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#endif /* !MALI_USE_CSF */
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for (i = 0; i < BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS; i++)
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registers.texture_features[i] = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TEXTURE_FEATURES_REG(i)));
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registers.thread_max_threads = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_MAX_THREADS));
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registers.thread_max_workgroup_size = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_MAX_WORKGROUP_SIZE));
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registers.thread_max_barrier_size = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_MAX_BARRIER_SIZE));
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registers.thread_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_FEATURES));
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registers.thread_tls_alloc = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(THREAD_TLS_ALLOC));
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registers.shader_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(SHADER_PRESENT_LO));
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registers.shader_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(SHADER_PRESENT_HI));
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registers.tiler_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TILER_PRESENT_LO));
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registers.tiler_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(TILER_PRESENT_HI));
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registers.l2_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_PRESENT_LO));
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registers.l2_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_PRESENT_HI));
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registers.stack_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(STACK_PRESENT_LO));
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registers.stack_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(STACK_PRESENT_HI));
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if (registers.gpu_id >= GPU_ID2_PRODUCT_MAKE(11, 8, 5, 2)) {
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registers.gpu_features_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(GPU_FEATURES_LO));
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registers.gpu_features_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(GPU_FEATURES_HI));
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} else {
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registers.gpu_features_lo = 0;
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registers.gpu_features_hi = 0;
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}
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if (!kbase_is_gpu_removed(kbdev)) {
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*regdump = registers;
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return 0;
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} else
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return -EIO;
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}
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int kbase_backend_gpuprops_get_curr_config(struct kbase_device *kbdev,
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struct kbase_current_config_regdump *curr_config_regdump)
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{
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if (WARN_ON(!kbdev) || WARN_ON(!curr_config_regdump))
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return -EINVAL;
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curr_config_regdump->mem_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(MEM_FEATURES));
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curr_config_regdump->shader_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(SHADER_PRESENT_LO));
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curr_config_regdump->shader_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(SHADER_PRESENT_HI));
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curr_config_regdump->l2_present_lo = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_PRESENT_LO));
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curr_config_regdump->l2_present_hi = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_PRESENT_HI));
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if (kbase_is_gpu_removed(kbdev))
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return -EIO;
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return 0;
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}
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int kbase_backend_gpuprops_get_features(struct kbase_device *kbdev,
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struct kbase_gpuprops_regdump *regdump)
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{
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u32 coherency_features;
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int error = 0;
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/* Ensure we can access the GPU registers */
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kbase_pm_register_access_enable(kbdev);
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coherency_features = kbase_cache_get_coherency_features(kbdev);
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if (kbase_is_gpu_removed(kbdev))
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error = -EIO;
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regdump->coherency_features = coherency_features;
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if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_CORE_FEATURES))
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regdump->core_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(CORE_FEATURES));
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else
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regdump->core_features = 0;
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kbase_pm_register_access_disable(kbdev);
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return error;
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}
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int kbase_backend_gpuprops_get_l2_features(struct kbase_device *kbdev,
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struct kbase_gpuprops_regdump *regdump)
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{
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if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_L2_CONFIG)) {
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u32 l2_features = kbase_reg_read(kbdev,
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GPU_CONTROL_REG(L2_FEATURES));
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u32 l2_config =
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kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_CONFIG));
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u32 asn_hash[ASN_HASH_COUNT] = {
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0,
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};
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int i;
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if (kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_ASN_HASH)) {
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for (i = 0; i < ASN_HASH_COUNT; i++)
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asn_hash[i] = kbase_reg_read(
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kbdev, GPU_CONTROL_REG(ASN_HASH(i)));
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}
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if (kbase_is_gpu_removed(kbdev))
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return -EIO;
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regdump->l2_features = l2_features;
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regdump->l2_config = l2_config;
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for (i = 0; i < ASN_HASH_COUNT; i++)
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regdump->l2_asn_hash[i] = asn_hash[i];
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}
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return 0;
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}
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