// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2014-2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#include <mali_kbase.h>
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#include <tl/mali_kbase_tracepoints.h>
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#include <backend/gpu/mali_kbase_devfreq.h>
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#include <backend/gpu/mali_kbase_pm_internal.h>
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#include <linux/of.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/devfreq.h>
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#if IS_ENABLED(CONFIG_DEVFREQ_THERMAL)
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#include <linux/devfreq_cooling.h>
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#endif
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#include <linux/version.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include "mali_kbase_devfreq.h"
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#include <soc/rockchip/rockchip_ipa.h>
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#include <soc/rockchip/rockchip_opp_select.h>
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#include <soc/rockchip/rockchip_system_monitor.h>
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static struct devfreq_simple_ondemand_data ondemand_data;
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static struct monitor_dev_profile mali_mdevp = {
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.type = MONITOR_TYPE_DEV,
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.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
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.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
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.update_volt = rockchip_monitor_check_rate_volt,
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};
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/**
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* get_voltage() - Get the voltage value corresponding to the nominal frequency
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* used by devfreq.
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* @kbdev: Device pointer
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* @freq: Nominal frequency in Hz passed by devfreq.
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*
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* This function will be called only when the opp table which is compatible with
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* "operating-points-v2-mali", is not present in the devicetree for GPU device.
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*
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* Return: Voltage value in micro volts, 0 in case of error.
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*/
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static unsigned long get_voltage(struct kbase_device *kbdev, unsigned long freq)
|
{
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struct dev_pm_opp *opp;
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unsigned long voltage = 0;
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#if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
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rcu_read_lock();
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#endif
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opp = dev_pm_opp_find_freq_exact(kbdev->dev, freq, true);
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if (IS_ERR_OR_NULL(opp))
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dev_err(kbdev->dev, "Failed to get opp (%d)\n", PTR_ERR_OR_ZERO(opp));
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else {
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voltage = dev_pm_opp_get_voltage(opp);
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#if KERNEL_VERSION(4, 11, 0) <= LINUX_VERSION_CODE
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dev_pm_opp_put(opp);
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#endif
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}
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#if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
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rcu_read_unlock();
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#endif
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/* Return the voltage in micro volts */
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return voltage;
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}
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void kbase_devfreq_opp_translate(struct kbase_device *kbdev, unsigned long freq,
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u64 *core_mask, unsigned long *freqs, unsigned long *volts)
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{
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unsigned int i;
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for (i = 0; i < kbdev->num_opps; i++) {
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if (kbdev->devfreq_table[i].opp_freq == freq) {
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unsigned int j;
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*core_mask = kbdev->devfreq_table[i].core_mask;
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for (j = 0; j < kbdev->nr_clocks; j++) {
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freqs[j] =
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kbdev->devfreq_table[i].real_freqs[j];
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volts[j] =
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kbdev->devfreq_table[i].opp_volts[j];
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}
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break;
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}
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}
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/* If failed to find OPP, return all cores enabled
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* and nominal frequency and the corresponding voltage.
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*/
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if (i == kbdev->num_opps) {
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unsigned long voltage = get_voltage(kbdev, freq);
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*core_mask = kbdev->gpu_props.props.raw_props.shader_present;
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for (i = 0; i < kbdev->nr_clocks; i++) {
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freqs[i] = freq;
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volts[i] = voltage;
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}
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}
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}
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int kbase_devfreq_opp_helper(struct dev_pm_set_opp_data *data)
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{
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struct device *dev = data->dev;
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struct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];
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struct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];
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struct regulator *vdd_reg = data->regulators[0];
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struct dev_pm_opp_supply *old_supply_mem;
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struct dev_pm_opp_supply *new_supply_mem;
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struct regulator *mem_reg;
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struct clk *clk = data->clk;
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struct kbase_device *kbdev = dev_get_drvdata(dev);
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struct rockchip_opp_info *opp_info = &kbdev->opp_info;
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unsigned long old_freq = data->old_opp.rate;
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unsigned long new_freq = data->new_opp.rate;
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unsigned int reg_count = data->regulator_count;
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bool is_set_rm = true;
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bool is_set_clk = true;
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u32 target_rm = UINT_MAX;
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int ret = 0;
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if (reg_count > 1) {
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old_supply_mem = &data->old_opp.supplies[1];
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new_supply_mem = &data->new_opp.supplies[1];
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mem_reg = data->regulators[1];
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}
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if (!pm_runtime_active(dev)) {
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is_set_rm = false;
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if (opp_info->scmi_clk)
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is_set_clk = false;
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}
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ret = clk_bulk_prepare_enable(opp_info->num_clks, opp_info->clks);
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if (ret) {
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dev_err(dev, "failed to enable opp clks\n");
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return ret;
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}
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rockchip_get_read_margin(dev, opp_info, new_supply_vdd->u_volt,
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&target_rm);
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/* Change frequency */
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dev_dbg(dev, "switching OPP: %lu Hz --> %lu Hz\n", old_freq, new_freq);
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/* Scaling up? Scale voltage before frequency */
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if (new_freq >= old_freq) {
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rockchip_set_intermediate_rate(dev, opp_info, clk, old_freq,
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new_freq, true, is_set_clk);
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if (reg_count > 1) {
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ret = regulator_set_voltage(mem_reg,
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new_supply_mem->u_volt,
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INT_MAX);
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if (ret) {
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dev_err(dev, "failed to set volt %lu uV for mem reg\n",
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new_supply_mem->u_volt);
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goto restore_voltage;
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}
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}
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ret = regulator_set_voltage(vdd_reg, new_supply_vdd->u_volt,
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INT_MAX);
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if (ret) {
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dev_err(dev, "failed to set volt %lu uV for vdd reg\n",
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new_supply_vdd->u_volt);
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goto restore_voltage;
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}
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rockchip_set_read_margin(dev, opp_info, target_rm, is_set_rm);
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if (is_set_clk && clk_set_rate(clk, new_freq)) {
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ret = -EINVAL;
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dev_err(dev, "failed to set clk rate\n");
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goto restore_rm;
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}
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/* Scaling down? Scale voltage after frequency */
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} else {
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rockchip_set_intermediate_rate(dev, opp_info, clk, old_freq,
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new_freq, false, is_set_clk);
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rockchip_set_read_margin(dev, opp_info, target_rm, is_set_rm);
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if (is_set_clk && clk_set_rate(clk, new_freq)) {
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ret = -EINVAL;
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dev_err(dev, "failed to set clk rate\n");
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goto restore_rm;
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}
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ret = regulator_set_voltage(vdd_reg, new_supply_vdd->u_volt,
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INT_MAX);
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if (ret) {
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dev_err(dev, "failed to set volt %lu uV for vdd reg\n",
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new_supply_vdd->u_volt);
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goto restore_freq;
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}
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if (reg_count > 1) {
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ret = regulator_set_voltage(mem_reg,
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new_supply_mem->u_volt,
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INT_MAX);
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if (ret) {
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dev_err(dev, "failed to set volt %lu uV for mem reg\n",
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new_supply_mem->u_volt);
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goto restore_voltage;
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}
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}
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}
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clk_bulk_disable_unprepare(opp_info->num_clks, opp_info->clks);
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return 0;
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restore_freq:
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if (is_set_clk && clk_set_rate(clk, old_freq))
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dev_err(dev, "failed to restore old-freq %lu Hz\n", old_freq);
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restore_rm:
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rockchip_get_read_margin(dev, opp_info, old_supply_vdd->u_volt,
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&target_rm);
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rockchip_set_read_margin(dev, opp_info, opp_info->target_rm, is_set_rm);
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restore_voltage:
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if (reg_count > 1 && old_supply_mem->u_volt)
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regulator_set_voltage(mem_reg, old_supply_mem->u_volt, INT_MAX);
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regulator_set_voltage(vdd_reg, old_supply_vdd->u_volt, INT_MAX);
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clk_bulk_disable_unprepare(opp_info->num_clks, opp_info->clks);
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return ret;
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}
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static int
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kbase_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
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{
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struct kbase_device *kbdev = dev_get_drvdata(dev);
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struct dev_pm_opp *opp;
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int ret = 0;
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if (!mali_mdevp.is_checked)
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return -EINVAL;
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opp = devfreq_recommended_opp(dev, freq, flags);
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if (IS_ERR(opp))
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return PTR_ERR(opp);
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dev_pm_opp_put(opp);
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if (*freq == kbdev->current_nominal_freq)
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return 0;
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rockchip_monitor_volt_adjust_lock(kbdev->mdev_info);
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ret = dev_pm_opp_set_rate(dev, *freq);
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if (!ret) {
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kbdev->current_nominal_freq = *freq;
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KBASE_TLSTREAM_AUX_DEVFREQ_TARGET(kbdev, (u64)*freq);
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}
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rockchip_monitor_volt_adjust_unlock(kbdev->mdev_info);
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return ret;
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}
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void kbase_devfreq_force_freq(struct kbase_device *kbdev, unsigned long freq)
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{
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unsigned long target_freq = freq;
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kbase_devfreq_target(kbdev->dev, &target_freq, 0);
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}
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static int
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kbase_devfreq_cur_freq(struct device *dev, unsigned long *freq)
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{
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struct kbase_device *kbdev = dev_get_drvdata(dev);
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*freq = kbdev->current_nominal_freq;
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return 0;
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}
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static int
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kbase_devfreq_status(struct device *dev, struct devfreq_dev_status *stat)
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{
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struct kbase_device *kbdev = dev_get_drvdata(dev);
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struct kbasep_pm_metrics diff;
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kbase_pm_get_dvfs_metrics(kbdev, &kbdev->last_devfreq_metrics, &diff);
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stat->busy_time = diff.time_busy;
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stat->total_time = diff.time_busy + diff.time_idle;
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stat->current_frequency = kbdev->current_nominal_freq;
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stat->private_data = NULL;
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#if MALI_USE_CSF && defined CONFIG_DEVFREQ_THERMAL
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if (!kbdev->dfc_power.dyn_power_coeff)
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kbase_ipa_reset_data(kbdev);
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#endif
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return 0;
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}
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static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev,
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struct devfreq_dev_profile *dp)
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{
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int count;
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int i = 0;
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unsigned long freq;
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struct dev_pm_opp *opp;
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#if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
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rcu_read_lock();
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#endif
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count = dev_pm_opp_get_opp_count(kbdev->dev);
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#if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
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rcu_read_unlock();
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#endif
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if (count < 0)
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return count;
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dp->freq_table = kmalloc_array(count, sizeof(dp->freq_table[0]),
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GFP_KERNEL);
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if (!dp->freq_table)
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return -ENOMEM;
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#if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
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rcu_read_lock();
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#endif
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for (i = 0, freq = ULONG_MAX; i < count; i++, freq--) {
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opp = dev_pm_opp_find_freq_floor(kbdev->dev, &freq);
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if (IS_ERR(opp))
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break;
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#if KERNEL_VERSION(4, 11, 0) <= LINUX_VERSION_CODE
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dev_pm_opp_put(opp);
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#endif /* KERNEL_VERSION(4, 11, 0) <= LINUX_VERSION_CODE */
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dp->freq_table[i] = freq;
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}
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#if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
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rcu_read_unlock();
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#endif
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if (count != i)
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dev_warn(kbdev->dev, "Unable to enumerate all OPPs (%d!=%d\n",
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count, i);
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dp->max_state = i;
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|
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/* Have the lowest clock as suspend clock.
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* It may be overridden by 'opp-mali-errata-1485982'.
|
*/
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if (kbdev->pm.backend.gpu_clock_slow_down_wa) {
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freq = 0;
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opp = dev_pm_opp_find_freq_ceil(kbdev->dev, &freq);
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if (IS_ERR(opp)) {
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dev_err(kbdev->dev, "failed to find slowest clock");
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return 0;
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}
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dev_pm_opp_put(opp);
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dev_info(kbdev->dev, "suspend clock %lu from slowest", freq);
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kbdev->pm.backend.gpu_clock_suspend_freq = freq;
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}
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return 0;
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}
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static void kbase_devfreq_term_freq_table(struct kbase_device *kbdev)
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{
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struct devfreq_dev_profile *dp = &kbdev->devfreq_profile;
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kfree(dp->freq_table);
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dp->freq_table = NULL;
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}
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static void kbase_devfreq_term_core_mask_table(struct kbase_device *kbdev)
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{
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kfree(kbdev->devfreq_table);
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kbdev->devfreq_table = NULL;
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}
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static void kbase_devfreq_exit(struct device *dev)
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{
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struct kbase_device *kbdev = dev_get_drvdata(dev);
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if (kbdev)
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kbase_devfreq_term_freq_table(kbdev);
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}
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static void kbasep_devfreq_read_suspend_clock(struct kbase_device *kbdev,
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struct device_node *node)
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{
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u64 freq = 0;
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int err = 0;
|
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/* Check if this node is the opp entry having 'opp-mali-errata-1485982'
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* to get the suspend clock, otherwise skip it.
|
*/
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if (!of_property_read_bool(node, "opp-mali-errata-1485982"))
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return;
|
|
/* In kbase DevFreq, the clock will be read from 'opp-hz'
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* and translated into the actual clock by opp_translate.
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*
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* In customer DVFS, the clock will be read from 'opp-hz-real'
|
* for clk driver. If 'opp-hz-real' does not exist,
|
* read from 'opp-hz'.
|
*/
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if (IS_ENABLED(CONFIG_MALI_BIFROST_DEVFREQ))
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err = of_property_read_u64(node, "opp-hz", &freq);
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else {
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if (of_property_read_u64(node, "opp-hz-real", &freq))
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err = of_property_read_u64(node, "opp-hz", &freq);
|
}
|
|
if (WARN_ON(err || !freq))
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return;
|
|
kbdev->pm.backend.gpu_clock_suspend_freq = freq;
|
dev_info(kbdev->dev,
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"suspend clock %llu by opp-mali-errata-1485982", freq);
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}
|
|
static int kbase_devfreq_init_core_mask_table(struct kbase_device *kbdev)
|
{
|
#ifndef CONFIG_OF
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/* OPP table initialization requires at least the capability to get
|
* regulators and clocks from the device tree, as well as parsing
|
* arrays of unsigned integer values.
|
*
|
* The whole initialization process shall simply be skipped if the
|
* minimum capability is not available.
|
*/
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return 0;
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#else
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struct device_node *opp_node = of_parse_phandle(kbdev->dev->of_node,
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"operating-points-v2", 0);
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struct device_node *node;
|
int i = 0;
|
int count;
|
u64 shader_present = kbdev->gpu_props.props.raw_props.shader_present;
|
|
if (!opp_node)
|
return 0;
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if (!of_device_is_compatible(opp_node, "operating-points-v2-mali"))
|
return 0;
|
|
count = dev_pm_opp_get_opp_count(kbdev->dev);
|
kbdev->devfreq_table = kmalloc_array(count,
|
sizeof(struct kbase_devfreq_opp), GFP_KERNEL);
|
if (!kbdev->devfreq_table)
|
return -ENOMEM;
|
|
for_each_available_child_of_node(opp_node, node) {
|
const void *core_count_p;
|
u64 core_mask, opp_freq,
|
real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS];
|
int err;
|
#if IS_ENABLED(CONFIG_REGULATOR)
|
u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS];
|
#endif
|
|
/* Read suspend clock from opp table */
|
if (kbdev->pm.backend.gpu_clock_slow_down_wa)
|
kbasep_devfreq_read_suspend_clock(kbdev, node);
|
|
err = of_property_read_u64(node, "opp-hz", &opp_freq);
|
if (err) {
|
dev_warn(kbdev->dev, "Failed to read opp-hz property with error %d\n",
|
err);
|
continue;
|
}
|
|
|
#if BASE_MAX_NR_CLOCKS_REGULATORS > 1
|
err = of_property_read_u64_array(node, "opp-hz-real",
|
real_freqs, kbdev->nr_clocks);
|
#else
|
WARN_ON(kbdev->nr_clocks != 1);
|
err = of_property_read_u64(node, "opp-hz-real", real_freqs);
|
#endif
|
if (err < 0) {
|
dev_warn(kbdev->dev, "Failed to read opp-hz-real property with error %d\n",
|
err);
|
continue;
|
}
|
#if IS_ENABLED(CONFIG_REGULATOR)
|
err = of_property_read_u32_array(node,
|
"opp-microvolt", opp_volts, kbdev->nr_regulators);
|
if (err < 0) {
|
dev_warn(kbdev->dev, "Failed to read opp-microvolt property with error %d\n",
|
err);
|
continue;
|
}
|
#endif
|
|
if (of_property_read_u64(node, "opp-core-mask", &core_mask))
|
core_mask = shader_present;
|
if (core_mask != shader_present && corestack_driver_control) {
|
|
dev_warn(kbdev->dev, "Ignoring OPP %llu - Dynamic Core Scaling not supported on this GPU\n",
|
opp_freq);
|
continue;
|
}
|
|
core_count_p = of_get_property(node, "opp-core-count", NULL);
|
if (core_count_p) {
|
u64 remaining_core_mask =
|
kbdev->gpu_props.props.raw_props.shader_present;
|
int core_count = be32_to_cpup(core_count_p);
|
|
core_mask = 0;
|
|
for (; core_count > 0; core_count--) {
|
int core = ffs(remaining_core_mask);
|
|
if (!core) {
|
dev_err(kbdev->dev, "OPP has more cores than GPU\n");
|
return -ENODEV;
|
}
|
|
core_mask |= (1ull << (core-1));
|
remaining_core_mask &= ~(1ull << (core-1));
|
}
|
}
|
|
if (!core_mask) {
|
dev_err(kbdev->dev, "OPP has invalid core mask of 0\n");
|
return -ENODEV;
|
}
|
|
kbdev->devfreq_table[i].opp_freq = opp_freq;
|
kbdev->devfreq_table[i].core_mask = core_mask;
|
if (kbdev->nr_clocks > 0) {
|
int j;
|
|
for (j = 0; j < kbdev->nr_clocks; j++)
|
kbdev->devfreq_table[i].real_freqs[j] =
|
real_freqs[j];
|
}
|
#if IS_ENABLED(CONFIG_REGULATOR)
|
if (kbdev->nr_regulators > 0) {
|
int j;
|
|
for (j = 0; j < kbdev->nr_regulators; j++)
|
kbdev->devfreq_table[i].opp_volts[j] =
|
opp_volts[j];
|
}
|
#endif
|
|
dev_info(kbdev->dev, "OPP %d : opp_freq=%llu core_mask=%llx\n",
|
i, opp_freq, core_mask);
|
|
i++;
|
}
|
|
kbdev->num_opps = i;
|
|
return 0;
|
#endif /* CONFIG_OF */
|
}
|
|
static const char *kbase_devfreq_req_type_name(enum kbase_devfreq_work_type type)
|
{
|
const char *p;
|
|
switch (type) {
|
case DEVFREQ_WORK_NONE:
|
p = "devfreq_none";
|
break;
|
case DEVFREQ_WORK_SUSPEND:
|
p = "devfreq_suspend";
|
break;
|
case DEVFREQ_WORK_RESUME:
|
p = "devfreq_resume";
|
break;
|
default:
|
p = "Unknown devfreq_type";
|
}
|
return p;
|
}
|
|
static void kbase_devfreq_suspend_resume_worker(struct work_struct *work)
|
{
|
struct kbase_devfreq_queue_info *info = container_of(work,
|
struct kbase_devfreq_queue_info, work);
|
struct kbase_device *kbdev = container_of(info, struct kbase_device,
|
devfreq_queue);
|
unsigned long flags;
|
enum kbase_devfreq_work_type type, acted_type;
|
|
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
|
type = kbdev->devfreq_queue.req_type;
|
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
|
|
acted_type = kbdev->devfreq_queue.acted_type;
|
dev_dbg(kbdev->dev, "Worker handles queued req: %s (acted: %s)\n",
|
kbase_devfreq_req_type_name(type),
|
kbase_devfreq_req_type_name(acted_type));
|
switch (type) {
|
case DEVFREQ_WORK_SUSPEND:
|
case DEVFREQ_WORK_RESUME:
|
if (type != acted_type) {
|
if (type == DEVFREQ_WORK_RESUME)
|
devfreq_resume_device(kbdev->devfreq);
|
else
|
devfreq_suspend_device(kbdev->devfreq);
|
dev_dbg(kbdev->dev, "Devfreq transition occured: %s => %s\n",
|
kbase_devfreq_req_type_name(acted_type),
|
kbase_devfreq_req_type_name(type));
|
kbdev->devfreq_queue.acted_type = type;
|
}
|
break;
|
default:
|
WARN_ON(1);
|
}
|
}
|
|
void kbase_devfreq_enqueue_work(struct kbase_device *kbdev,
|
enum kbase_devfreq_work_type work_type)
|
{
|
unsigned long flags;
|
|
WARN_ON(work_type == DEVFREQ_WORK_NONE);
|
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
|
/* Skip enqueuing a work if workqueue has already been terminated. */
|
if (likely(kbdev->devfreq_queue.workq)) {
|
kbdev->devfreq_queue.req_type = work_type;
|
queue_work(kbdev->devfreq_queue.workq,
|
&kbdev->devfreq_queue.work);
|
}
|
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
|
dev_dbg(kbdev->dev, "Enqueuing devfreq req: %s\n",
|
kbase_devfreq_req_type_name(work_type));
|
}
|
|
static int kbase_devfreq_work_init(struct kbase_device *kbdev)
|
{
|
kbdev->devfreq_queue.req_type = DEVFREQ_WORK_NONE;
|
kbdev->devfreq_queue.acted_type = DEVFREQ_WORK_RESUME;
|
|
kbdev->devfreq_queue.workq = alloc_ordered_workqueue("devfreq_workq", 0);
|
if (!kbdev->devfreq_queue.workq)
|
return -ENOMEM;
|
|
INIT_WORK(&kbdev->devfreq_queue.work,
|
kbase_devfreq_suspend_resume_worker);
|
return 0;
|
}
|
|
static void kbase_devfreq_work_term(struct kbase_device *kbdev)
|
{
|
unsigned long flags;
|
struct workqueue_struct *workq;
|
|
spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
|
workq = kbdev->devfreq_queue.workq;
|
kbdev->devfreq_queue.workq = NULL;
|
spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
|
|
destroy_workqueue(workq);
|
}
|
|
static unsigned long kbase_devfreq_get_static_power(struct devfreq *devfreq,
|
unsigned long voltage)
|
{
|
struct device *dev = devfreq->dev.parent;
|
struct kbase_device *kbdev = dev_get_drvdata(dev);
|
|
return rockchip_ipa_get_static_power(kbdev->model_data, voltage);
|
}
|
|
int kbase_devfreq_init(struct kbase_device *kbdev)
|
{
|
struct devfreq_cooling_power *kbase_dcp = &kbdev->dfc_power;
|
struct device_node *np = kbdev->dev->of_node;
|
struct device_node *model_node;
|
struct devfreq_dev_profile *dp;
|
int err;
|
struct dev_pm_opp *opp;
|
unsigned int i;
|
bool free_devfreq_freq_table = true;
|
|
if (kbdev->nr_clocks == 0) {
|
dev_err(kbdev->dev, "Clock not available for devfreq\n");
|
return -ENODEV;
|
}
|
|
for (i = 0; i < kbdev->nr_clocks; i++) {
|
if (kbdev->clocks[i])
|
kbdev->current_freqs[i] =
|
clk_get_rate(kbdev->clocks[i]);
|
else
|
kbdev->current_freqs[i] = 0;
|
}
|
if (strstr(__clk_get_name(kbdev->clocks[0]), "scmi"))
|
kbdev->opp_info.scmi_clk = kbdev->clocks[0];
|
kbdev->current_nominal_freq = kbdev->current_freqs[0];
|
|
opp = devfreq_recommended_opp(kbdev->dev, &kbdev->current_nominal_freq, 0);
|
if (IS_ERR(opp))
|
return PTR_ERR(opp);
|
dev_pm_opp_put(opp);
|
|
dp = &kbdev->devfreq_profile;
|
|
dp->initial_freq = kbdev->current_nominal_freq;
|
dp->polling_ms = 100;
|
dp->target = kbase_devfreq_target;
|
dp->get_dev_status = kbase_devfreq_status;
|
dp->get_cur_freq = kbase_devfreq_cur_freq;
|
dp->exit = kbase_devfreq_exit;
|
|
if (kbase_devfreq_init_freq_table(kbdev, dp))
|
return -EFAULT;
|
|
if (dp->max_state > 0) {
|
/* Record the maximum frequency possible */
|
kbdev->gpu_props.props.core_props.gpu_freq_khz_max =
|
dp->freq_table[0] / 1000;
|
};
|
err = kbase_devfreq_init_core_mask_table(kbdev);
|
if (err)
|
goto init_core_mask_table_failed;
|
|
of_property_read_u32(np, "upthreshold",
|
&ondemand_data.upthreshold);
|
of_property_read_u32(np, "downdifferential",
|
&ondemand_data.downdifferential);
|
kbdev->devfreq = devfreq_add_device(kbdev->dev, dp,
|
"simple_ondemand", &ondemand_data);
|
if (IS_ERR(kbdev->devfreq)) {
|
err = PTR_ERR(kbdev->devfreq);
|
kbdev->devfreq = NULL;
|
dev_err(kbdev->dev, "Fail to add devfreq device(%d)", err);
|
goto devfreq_add_dev_failed;
|
}
|
|
/* Explicit free of freq table isn't needed after devfreq_add_device() */
|
free_devfreq_freq_table = false;
|
|
/* Initialize devfreq suspend/resume workqueue */
|
err = kbase_devfreq_work_init(kbdev);
|
if (err) {
|
dev_err(kbdev->dev, "Fail to init devfreq workqueue");
|
goto devfreq_work_init_failed;
|
}
|
|
/* devfreq_add_device only copies a few of kbdev->dev's fields, so
|
* set drvdata explicitly so IPA models can access kbdev.
|
*/
|
dev_set_drvdata(&kbdev->devfreq->dev, kbdev);
|
|
err = devfreq_register_opp_notifier(kbdev->dev, kbdev->devfreq);
|
if (err) {
|
dev_err(kbdev->dev,
|
"Failed to register OPP notifier (%d)", err);
|
goto opp_notifier_failed;
|
}
|
|
mali_mdevp.data = kbdev->devfreq;
|
mali_mdevp.opp_info = &kbdev->opp_info;
|
kbdev->mdev_info = rockchip_system_monitor_register(kbdev->dev,
|
&mali_mdevp);
|
if (IS_ERR(kbdev->mdev_info)) {
|
dev_dbg(kbdev->dev, "without system monitor\n");
|
kbdev->mdev_info = NULL;
|
mali_mdevp.is_checked = true;
|
}
|
#if IS_ENABLED(CONFIG_DEVFREQ_THERMAL)
|
of_property_read_u32(kbdev->dev->of_node, "dynamic-power-coefficient",
|
(u32 *)&kbase_dcp->dyn_power_coeff);
|
model_node = of_get_compatible_child(kbdev->dev->of_node,
|
"simple-power-model");
|
if (model_node) {
|
of_node_put(model_node);
|
kbdev->model_data =
|
rockchip_ipa_power_model_init(kbdev->dev,
|
"gpu_leakage");
|
if (IS_ERR_OR_NULL(kbdev->model_data)) {
|
kbdev->model_data = NULL;
|
if (kbase_dcp->dyn_power_coeff)
|
dev_info(kbdev->dev,
|
"only calculate dynamic power\n");
|
else
|
dev_err(kbdev->dev,
|
"failed to initialize power model\n");
|
} else {
|
kbase_dcp->get_static_power =
|
kbase_devfreq_get_static_power;
|
if (kbdev->model_data->dynamic_coefficient)
|
kbase_dcp->dyn_power_coeff =
|
kbdev->model_data->dynamic_coefficient;
|
}
|
}
|
|
if (kbase_dcp->dyn_power_coeff) {
|
kbdev->devfreq_cooling =
|
of_devfreq_cooling_register_power(kbdev->dev->of_node,
|
kbdev->devfreq,
|
kbase_dcp);
|
if (IS_ERR(kbdev->devfreq_cooling)) {
|
err = PTR_ERR(kbdev->devfreq_cooling);
|
dev_err(kbdev->dev, "failed to register cooling device\n");
|
goto ipa_init_failed;
|
}
|
} else {
|
err = kbase_ipa_init(kbdev);
|
if (err) {
|
dev_err(kbdev->dev, "IPA initialization failed\n");
|
goto ipa_init_failed;
|
}
|
|
kbdev->devfreq_cooling = of_devfreq_cooling_register_power(
|
kbdev->dev->of_node,
|
kbdev->devfreq,
|
&kbase_ipa_power_model_ops);
|
if (IS_ERR(kbdev->devfreq_cooling)) {
|
err = PTR_ERR(kbdev->devfreq_cooling);
|
dev_err(kbdev->dev,
|
"Failed to register cooling device (%d)\n",
|
err);
|
goto cooling_reg_failed;
|
}
|
}
|
#endif
|
|
return 0;
|
|
#if IS_ENABLED(CONFIG_DEVFREQ_THERMAL)
|
cooling_reg_failed:
|
kbase_ipa_term(kbdev);
|
ipa_init_failed:
|
devfreq_unregister_opp_notifier(kbdev->dev, kbdev->devfreq);
|
#endif /* CONFIG_DEVFREQ_THERMAL */
|
|
opp_notifier_failed:
|
kbase_devfreq_work_term(kbdev);
|
|
devfreq_work_init_failed:
|
if (devfreq_remove_device(kbdev->devfreq))
|
dev_err(kbdev->dev, "Failed to terminate devfreq (%d)", err);
|
|
kbdev->devfreq = NULL;
|
|
devfreq_add_dev_failed:
|
kbase_devfreq_term_core_mask_table(kbdev);
|
|
init_core_mask_table_failed:
|
if (free_devfreq_freq_table)
|
kbase_devfreq_term_freq_table(kbdev);
|
|
return err;
|
}
|
|
void kbase_devfreq_term(struct kbase_device *kbdev)
|
{
|
int err;
|
|
dev_dbg(kbdev->dev, "Term Mali devfreq\n");
|
|
#if IS_ENABLED(CONFIG_DEVFREQ_THERMAL)
|
if (kbdev->devfreq_cooling)
|
devfreq_cooling_unregister(kbdev->devfreq_cooling);
|
#endif
|
|
devfreq_unregister_opp_notifier(kbdev->dev, kbdev->devfreq);
|
|
kbase_devfreq_work_term(kbdev);
|
|
err = devfreq_remove_device(kbdev->devfreq);
|
if (err)
|
dev_err(kbdev->dev, "Failed to terminate devfreq (%d)\n", err);
|
else
|
kbdev->devfreq = NULL;
|
|
kbase_devfreq_term_core_mask_table(kbdev);
|
|
#if IS_ENABLED(CONFIG_DEVFREQ_THERMAL)
|
if (!kbdev->model_data)
|
kbase_ipa_term(kbdev);
|
kfree(kbdev->model_data);
|
#endif
|
}
|
