// SPDX-License-Identifier: GPL-2.0
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/*
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* Performance events support for SH-4A performance counters
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*
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* Copyright (C) 2009, 2010 Paul Mundt
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/perf_event.h>
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#include <asm/processor.h>
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#define PPC_CCBR(idx) (0xff200800 + (sizeof(u32) * idx))
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#define PPC_PMCTR(idx) (0xfc100000 + (sizeof(u32) * idx))
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#define CCBR_CIT_MASK (0x7ff << 6)
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#define CCBR_DUC (1 << 3)
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#define CCBR_CMDS (1 << 1)
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#define CCBR_PPCE (1 << 0)
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#ifdef CONFIG_CPU_SHX3
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/*
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* The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
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* and PMCTR locations remains tentatively constant. This change remains
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* wholly undocumented, and was simply found through trial and error.
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*
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* Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
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* it's unclear when this ceased to be the case. For now we always use
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* the new location (if future parts keep up with this trend then
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* scanning for them at runtime also remains a viable option.)
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*
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* The gap in the register space also suggests that there are other
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* undocumented counters, so this will need to be revisited at a later
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* point in time.
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*/
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#define PPC_PMCAT 0xfc100240
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#else
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#define PPC_PMCAT 0xfc100080
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#endif
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#define PMCAT_OVF3 (1 << 27)
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#define PMCAT_CNN3 (1 << 26)
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#define PMCAT_CLR3 (1 << 25)
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#define PMCAT_OVF2 (1 << 19)
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#define PMCAT_CLR2 (1 << 17)
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#define PMCAT_OVF1 (1 << 11)
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#define PMCAT_CNN1 (1 << 10)
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#define PMCAT_CLR1 (1 << 9)
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#define PMCAT_OVF0 (1 << 3)
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#define PMCAT_CLR0 (1 << 1)
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static struct sh_pmu sh4a_pmu;
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/*
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* Supported raw event codes:
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*
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* Event Code Description
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* ---------- -----------
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*
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* 0x0000 number of elapsed cycles
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* 0x0200 number of elapsed cycles in privileged mode
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* 0x0280 number of elapsed cycles while SR.BL is asserted
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* 0x0202 instruction execution
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* 0x0203 instruction execution in parallel
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* 0x0204 number of unconditional branches
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* 0x0208 number of exceptions
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* 0x0209 number of interrupts
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* 0x0220 UTLB miss caused by instruction fetch
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* 0x0222 UTLB miss caused by operand access
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* 0x02a0 number of ITLB misses
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* 0x0028 number of accesses to instruction memories
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* 0x0029 number of accesses to instruction cache
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* 0x002a instruction cache miss
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* 0x022e number of access to instruction X/Y memory
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* 0x0030 number of reads to operand memories
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* 0x0038 number of writes to operand memories
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* 0x0031 number of operand cache read accesses
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* 0x0039 number of operand cache write accesses
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* 0x0032 operand cache read miss
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* 0x003a operand cache write miss
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* 0x0236 number of reads to operand X/Y memory
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* 0x023e number of writes to operand X/Y memory
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* 0x0237 number of reads to operand U memory
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* 0x023f number of writes to operand U memory
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* 0x0337 number of U memory read buffer misses
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* 0x02b4 number of wait cycles due to operand read access
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* 0x02bc number of wait cycles due to operand write access
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* 0x0033 number of wait cycles due to operand cache read miss
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* 0x003b number of wait cycles due to operand cache write miss
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*/
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/*
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* Special reserved bits used by hardware emulators, read values will
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* vary, but writes must always be 0.
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*/
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#define PMCAT_EMU_CLR_MASK ((1 << 24) | (1 << 16) | (1 << 8) | (1 << 0))
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static const int sh4a_general_events[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0000,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x0202,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0029, /* I-cache */
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[PERF_COUNT_HW_CACHE_MISSES] = 0x002a, /* I-cache */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0204,
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[PERF_COUNT_HW_BRANCH_MISSES] = -1,
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[PERF_COUNT_HW_BUS_CYCLES] = -1,
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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static const int sh4a_cache_events
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0031,
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[ C(RESULT_MISS) ] = 0x0032,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0039,
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[ C(RESULT_MISS) ] = 0x003a,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(L1I) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0029,
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[ C(RESULT_MISS) ] = 0x002a,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(LL) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0030,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0038,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0222,
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[ C(RESULT_MISS) ] = 0x0220,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0x02a0,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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static int sh4a_event_map(int event)
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{
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return sh4a_general_events[event];
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}
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static u64 sh4a_pmu_read(int idx)
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{
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return __raw_readl(PPC_PMCTR(idx));
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}
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static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx)
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{
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unsigned int tmp;
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tmp = __raw_readl(PPC_CCBR(idx));
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tmp &= ~(CCBR_CIT_MASK | CCBR_DUC);
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__raw_writel(tmp, PPC_CCBR(idx));
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}
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static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx)
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{
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unsigned int tmp;
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tmp = __raw_readl(PPC_PMCAT);
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tmp &= ~PMCAT_EMU_CLR_MASK;
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tmp |= idx ? PMCAT_CLR1 : PMCAT_CLR0;
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__raw_writel(tmp, PPC_PMCAT);
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tmp = __raw_readl(PPC_CCBR(idx));
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tmp |= (hwc->config << 6) | CCBR_CMDS | CCBR_PPCE;
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__raw_writel(tmp, PPC_CCBR(idx));
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__raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx));
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}
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static void sh4a_pmu_disable_all(void)
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{
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int i;
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for (i = 0; i < sh4a_pmu.num_events; i++)
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__raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i));
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}
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static void sh4a_pmu_enable_all(void)
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{
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int i;
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for (i = 0; i < sh4a_pmu.num_events; i++)
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__raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i));
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}
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static struct sh_pmu sh4a_pmu = {
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.name = "sh4a",
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.num_events = 2,
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.event_map = sh4a_event_map,
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.max_events = ARRAY_SIZE(sh4a_general_events),
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.raw_event_mask = 0x3ff,
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.cache_events = &sh4a_cache_events,
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.read = sh4a_pmu_read,
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.disable = sh4a_pmu_disable,
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.enable = sh4a_pmu_enable,
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.disable_all = sh4a_pmu_disable_all,
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.enable_all = sh4a_pmu_enable_all,
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};
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static int __init sh4a_pmu_init(void)
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{
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/*
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* Make sure this CPU actually has perf counters.
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*/
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if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) {
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pr_notice("HW perf events unsupported, software events only.\n");
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return -ENODEV;
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}
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return register_sh_pmu(&sh4a_pmu);
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}
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early_initcall(sh4a_pmu_init);
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