* Marvell Armada 7K/8K PCIe interface
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "marvell,armada8k-pcie"
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- reg: must contain two register regions
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- the control register region
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- the config space region
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- reg-names:
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- "ctrl" for the control register region
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- "config" for the config space region
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- interrupts: Interrupt specifier for the PCIe controller
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- clocks: reference to the PCIe controller clocks
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- clock-names: mandatory if there is a second clock, in this case the
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name must be "core" for the first clock and "reg" for the second
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one
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Optional properties:
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- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
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Either 1, 2 or 4 PHYs might be needed depending on the number of
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PCIe lanes.
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- phy-names: names of the PHYs corresponding to the number of lanes.
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Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
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2 PHYs.
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Example:
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pcie@f2600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
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0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_syscon0 1 13>;
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};
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