/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __AWINIC_DATA_TYPE_H__
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#define __AWINIC_DATA_TYPE_H__
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#define AW_NAME_BUF_MAX (50)
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/******************************************************************
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* aw profile
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*******************************************************************/
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#define PROJECT_NAME_MAX (24)
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#define CUSTOMER_NAME_MAX (16)
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#define CFG_VERSION_MAX (4)
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#define DEV_NAME_MAX (16)
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#define PROFILE_STR_MAX (32)
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#define ACF_FILE_ID (0xa15f908)
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struct aw_msg_hdr {
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int32_t type;
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int32_t opcode_id;
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int32_t version;
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int32_t reseriver[3];
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};
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enum aw_cfg_hdr_version {
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AW_CFG_HDR_VER_0_0_0_1 = 0x00000001,
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AW_CFG_HDR_VER_1_0_0_0 = 0x01000000,
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};
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enum aw_cfg_dde_type {
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AW_DEV_NONE_TYPE_ID = 0xFFFFFFFF,
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AW_DEV_TYPE_ID = 0x00000000,
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AW_SKT_TYPE_ID = 0x00000001,
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AW_DEV_DEFAULT_TYPE_ID = 0x00000002,
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};
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enum aw_sec_type {
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ACF_SEC_TYPE_REG = 0,
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ACF_SEC_TYPE_DSP,
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ACF_SEC_TYPE_DSP_CFG,
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ACF_SEC_TYPE_DSP_FW,
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ACF_SEC_TYPE_HDR_REG,
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ACF_SEC_TYPE_HDR_DSP_CFG,
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ACF_SEC_TYPE_HDR_DSP_FW,
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ACF_SEC_TYPE_MUTLBIN,
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ACF_SEC_TYPE_SKT_PROJECT,
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ACF_SEC_TYPE_DSP_PROJECT,
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ACF_SEC_TYPE_MONITOR,
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ACF_SEC_TYPE_MAX,
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};
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enum profile_data_type {
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AW_DATA_TYPE_REG = 0,
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AW_DATA_TYPE_DSP_CFG,
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AW_DATA_TYPE_DSP_FW,
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AW_DATA_TYPE_MAX,
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};
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enum aw_prof_type {
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AW_PROFILE_MUSIC = 0,
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AW_PROFILE_VOICE,
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AW_PROFILE_VOIP,
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AW_PROFILE_RINGTONE,
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AW_PROFILE_RINGTONE_HS,
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AW_PROFILE_LOWPOWER,
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AW_PROFILE_BYPASS,
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AW_PROFILE_MMI,
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AW_PROFILE_FM,
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AW_PROFILE_NOTIFICATION,
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AW_PROFILE_RECEIVER,
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AW_PROFILE_MAX,
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};
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enum aw_profile_status {
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AW_PROFILE_WAIT = 0,
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AW_PROFILE_OK,
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};
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struct aw_cfg_hdr {
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uint32_t a_id; /*acf file ID 0xa15f908*/
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char a_project[PROJECT_NAME_MAX]; /*project name*/
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char a_custom[CUSTOMER_NAME_MAX]; /*custom name :huawei xiaomi vivo oppo*/
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char a_version[CFG_VERSION_MAX]; /*author update version*/
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uint32_t a_author_id; /*author id*/
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uint32_t a_ddt_size; /*sub section table entry size*/
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uint32_t a_ddt_num; /*sub section table entry num*/
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uint32_t a_hdr_offset; /*sub section table offset in file*/
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uint32_t a_hdr_version; /*sub section table version*/
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uint32_t reserve[3];
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};
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struct aw_cfg_dde {
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uint32_t type; /*DDE type id*/
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char dev_name[DEV_NAME_MAX];
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uint16_t dev_index; /*dev id*/
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uint16_t dev_bus; /*dev bus id*/
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uint16_t dev_addr; /*dev addr id*/
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uint16_t dev_profile; /*dev profile id*/
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uint32_t data_type; /*data type id*/
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uint32_t data_size;
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uint32_t data_offset;
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uint32_t data_crc;
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uint32_t reserve[5];
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};
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struct aw_cfg_dde_v_1_0_0_0 {
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uint32_t type; /*DDE type id*/
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char dev_name[DEV_NAME_MAX];
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uint16_t dev_index; /*dev id*/
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uint16_t dev_bus; /*dev bus id*/
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uint16_t dev_addr; /*dev addr id*/
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uint16_t dev_profile; /*dev profile id*/
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uint32_t data_type; /*data type id*/
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uint32_t data_size;
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uint32_t data_offset;
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uint32_t data_crc;
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char dev_profile_str[PROFILE_STR_MAX];
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uint32_t chip_id;
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uint32_t reserve[4];
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};
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struct aw_sec_data_desc {
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uint32_t len;
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unsigned char *data;
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};
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struct aw_prof_desc {
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uint32_t id;
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uint32_t prof_st;
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char *prf_str;
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uint32_t fw_ver;
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struct aw_sec_data_desc sec_desc[AW_DATA_TYPE_MAX];
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};
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struct aw_all_prof_info {
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struct aw_prof_desc prof_desc[AW_PROFILE_MAX];
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};
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struct aw_prof_info {
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int count;
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int prof_type;
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char **prof_name_list;
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struct aw_prof_desc *prof_desc;
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};
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#endif
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