// SPDX-License-Identifier: GPL-2.0
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/*
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* This file is based on code from OCTEON SDK by Cavium Networks.
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*
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* Copyright (c) 2003-2007 Cavium Networks
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*/
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#include <linux/kernel.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <net/dst.h>
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#include "octeon-ethernet.h"
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#include "ethernet-defines.h"
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#include "ethernet-util.h"
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static int number_spi_ports;
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static int need_retrain[2] = { 0, 0 };
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static void cvm_oct_spxx_int_pr(union cvmx_spxx_int_reg spx_int_reg, int index)
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{
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if (spx_int_reg.s.spf)
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pr_err("SPI%d: SRX Spi4 interface down\n", index);
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if (spx_int_reg.s.calerr)
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pr_err("SPI%d: SRX Spi4 Calendar table parity error\n", index);
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if (spx_int_reg.s.syncerr)
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pr_err("SPI%d: SRX Consecutive Spi4 DIP4 errors have exceeded SPX_ERR_CTL[ERRCNT]\n",
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index);
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if (spx_int_reg.s.diperr)
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pr_err("SPI%d: SRX Spi4 DIP4 error\n", index);
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if (spx_int_reg.s.tpaovr)
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pr_err("SPI%d: SRX Selected port has hit TPA overflow\n",
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index);
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if (spx_int_reg.s.rsverr)
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pr_err("SPI%d: SRX Spi4 reserved control word detected\n",
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index);
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if (spx_int_reg.s.drwnng)
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pr_err("SPI%d: SRX Spi4 receive FIFO drowning/overflow\n",
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index);
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if (spx_int_reg.s.clserr)
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pr_err("SPI%d: SRX Spi4 packet closed on non-16B alignment without EOP\n",
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index);
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if (spx_int_reg.s.spiovr)
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pr_err("SPI%d: SRX Spi4 async FIFO overflow\n", index);
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if (spx_int_reg.s.abnorm)
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pr_err("SPI%d: SRX Abnormal packet termination (ERR bit)\n",
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index);
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if (spx_int_reg.s.prtnxa)
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pr_err("SPI%d: SRX Port out of range\n", index);
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}
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static void cvm_oct_stxx_int_pr(union cvmx_stxx_int_reg stx_int_reg, int index)
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{
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if (stx_int_reg.s.syncerr)
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pr_err("SPI%d: STX Interface encountered a fatal error\n",
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index);
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if (stx_int_reg.s.frmerr)
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pr_err("SPI%d: STX FRMCNT has exceeded STX_DIP_CNT[MAXFRM]\n",
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index);
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if (stx_int_reg.s.unxfrm)
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pr_err("SPI%d: STX Unexpected framing sequence\n", index);
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if (stx_int_reg.s.nosync)
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pr_err("SPI%d: STX ERRCNT has exceeded STX_DIP_CNT[MAXDIP]\n",
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index);
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if (stx_int_reg.s.diperr)
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pr_err("SPI%d: STX DIP2 error on the Spi4 Status channel\n",
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index);
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if (stx_int_reg.s.datovr)
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pr_err("SPI%d: STX Spi4 FIFO overflow error\n", index);
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if (stx_int_reg.s.ovrbst)
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pr_err("SPI%d: STX Transmit packet burst too big\n", index);
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if (stx_int_reg.s.calpar1)
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pr_err("SPI%d: STX Calendar Table Parity Error Bank%d\n",
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index, 1);
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if (stx_int_reg.s.calpar0)
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pr_err("SPI%d: STX Calendar Table Parity Error Bank%d\n",
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index, 0);
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}
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static irqreturn_t cvm_oct_spi_spx_int(int index)
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{
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union cvmx_spxx_int_reg spx_int_reg;
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union cvmx_stxx_int_reg stx_int_reg;
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spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(index));
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cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64);
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if (!need_retrain[index]) {
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spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(index));
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cvm_oct_spxx_int_pr(spx_int_reg, index);
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}
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stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(index));
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cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64);
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if (!need_retrain[index]) {
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stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(index));
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cvm_oct_stxx_int_pr(stx_int_reg, index);
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}
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cvmx_write_csr(CVMX_SPXX_INT_MSK(index), 0);
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cvmx_write_csr(CVMX_STXX_INT_MSK(index), 0);
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need_retrain[index] = 1;
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return IRQ_HANDLED;
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}
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static irqreturn_t cvm_oct_spi_rml_interrupt(int cpl, void *dev_id)
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{
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irqreturn_t return_status = IRQ_NONE;
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union cvmx_npi_rsl_int_blocks rsl_int_blocks;
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/* Check and see if this interrupt was caused by the GMX block */
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rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
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if (rsl_int_blocks.s.spx1) /* 19 - SPX1_INT_REG & STX1_INT_REG */
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return_status = cvm_oct_spi_spx_int(1);
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if (rsl_int_blocks.s.spx0) /* 18 - SPX0_INT_REG & STX0_INT_REG */
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return_status = cvm_oct_spi_spx_int(0);
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return return_status;
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}
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static void cvm_oct_spi_enable_error_reporting(int interface)
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{
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union cvmx_spxx_int_msk spxx_int_msk;
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union cvmx_stxx_int_msk stxx_int_msk;
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spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
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spxx_int_msk.s.calerr = 1;
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spxx_int_msk.s.syncerr = 1;
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spxx_int_msk.s.diperr = 1;
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spxx_int_msk.s.tpaovr = 1;
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spxx_int_msk.s.rsverr = 1;
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spxx_int_msk.s.drwnng = 1;
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spxx_int_msk.s.clserr = 1;
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spxx_int_msk.s.spiovr = 1;
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spxx_int_msk.s.abnorm = 1;
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spxx_int_msk.s.prtnxa = 1;
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cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
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stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
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stxx_int_msk.s.frmerr = 1;
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stxx_int_msk.s.unxfrm = 1;
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stxx_int_msk.s.nosync = 1;
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stxx_int_msk.s.diperr = 1;
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stxx_int_msk.s.datovr = 1;
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stxx_int_msk.s.ovrbst = 1;
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stxx_int_msk.s.calpar1 = 1;
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stxx_int_msk.s.calpar0 = 1;
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cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
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}
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static void cvm_oct_spi_poll(struct net_device *dev)
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{
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static int spi4000_port;
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struct octeon_ethernet *priv = netdev_priv(dev);
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int interface;
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for (interface = 0; interface < 2; interface++) {
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if ((priv->port == interface * 16) && need_retrain[interface]) {
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if (cvmx_spi_restart_interface
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(interface, CVMX_SPI_MODE_DUPLEX, 10) == 0) {
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need_retrain[interface] = 0;
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cvm_oct_spi_enable_error_reporting(interface);
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}
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}
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/*
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* The SPI4000 TWSI interface is very slow. In order
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* not to bring the system to a crawl, we only poll a
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* single port every second. This means negotiation
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* speed changes take up to 10 seconds, but at least
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* we don't waste absurd amounts of time waiting for
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* TWSI.
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*/
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if (priv->port == spi4000_port) {
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/*
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* This function does nothing if it is called on an
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* interface without a SPI4000.
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*/
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cvmx_spi4000_check_speed(interface, priv->port);
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/*
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* Normal ordering increments. By decrementing
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* we only match once per iteration.
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*/
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spi4000_port--;
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if (spi4000_port < 0)
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spi4000_port = 10;
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}
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}
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}
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int cvm_oct_spi_init(struct net_device *dev)
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{
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int r;
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struct octeon_ethernet *priv = netdev_priv(dev);
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if (number_spi_ports == 0) {
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r = request_irq(OCTEON_IRQ_RML, cvm_oct_spi_rml_interrupt,
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IRQF_SHARED, "SPI", &number_spi_ports);
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if (r)
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return r;
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}
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number_spi_ports++;
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if ((priv->port == 0) || (priv->port == 16)) {
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cvm_oct_spi_enable_error_reporting(INTERFACE(priv->port));
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priv->poll = cvm_oct_spi_poll;
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}
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cvm_oct_common_init(dev);
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return 0;
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}
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void cvm_oct_spi_uninit(struct net_device *dev)
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{
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int interface;
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cvm_oct_common_uninit(dev);
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number_spi_ports--;
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if (number_spi_ports == 0) {
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for (interface = 0; interface < 2; interface++) {
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cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
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cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
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}
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free_irq(OCTEON_IRQ_RML, &number_spi_ports);
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}
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}
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