/*
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* Rockchip isp1 driver
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*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <media/v4l2-common.h>
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#include "regs.h"
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void disable_dcrop(struct rkisp1_stream *stream, bool async)
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{
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void __iomem *base = stream->ispdev->base_addr;
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void __iomem *dc_ctrl_addr = base + stream->config->dual_crop.ctrl;
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u32 dc_ctrl = readl(dc_ctrl_addr);
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u32 mask = ~(stream->config->dual_crop.yuvmode_mask |
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stream->config->dual_crop.rawmode_mask);
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u32 val = dc_ctrl & mask;
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if (async)
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val |= CIF_DUAL_CROP_GEN_CFG_UPD;
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else
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val |= CIF_DUAL_CROP_CFG_UPD;
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writel(val, dc_ctrl_addr);
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}
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void config_dcrop(struct rkisp1_stream *stream, struct v4l2_rect *rect, bool async)
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{
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void __iomem *base = stream->ispdev->base_addr;
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void __iomem *dc_ctrl_addr = base + stream->config->dual_crop.ctrl;
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u32 dc_ctrl = readl(dc_ctrl_addr);
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writel(rect->left, base + stream->config->dual_crop.h_offset);
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writel(rect->top, base + stream->config->dual_crop.v_offset);
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writel(rect->width, base + stream->config->dual_crop.h_size);
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writel(rect->height, base + stream->config->dual_crop.v_size);
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dc_ctrl |= stream->config->dual_crop.yuvmode_mask;
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if (async)
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dc_ctrl |= CIF_DUAL_CROP_GEN_CFG_UPD;
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else
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dc_ctrl |= CIF_DUAL_CROP_CFG_UPD;
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writel(dc_ctrl, dc_ctrl_addr);
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}
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void dump_rsz_regs(struct rkisp1_stream *stream)
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{
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void __iomem *base = stream->ispdev->base_addr;
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pr_info("RSZ_CTRL 0x%08x/0x%08x\n"
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"RSZ_SCALE_HY %d/%d\n"
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"RSZ_SCALE_HCB %d/%d\n"
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"RSZ_SCALE_HCR %d/%d\n"
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"RSZ_SCALE_VY %d/%d\n"
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"RSZ_SCALE_VC %d/%d\n"
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"RSZ_PHASE_HY %d/%d\n"
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"RSZ_PHASE_HC %d/%d\n"
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"RSZ_PHASE_VY %d/%d\n"
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"RSZ_PHASE_VC %d/%d\n",
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readl(base + stream->config->rsz.ctrl),
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readl(base + stream->config->rsz.ctrl_shd),
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readl(base + stream->config->rsz.scale_hy),
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readl(base + stream->config->rsz.scale_hy_shd),
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readl(base + stream->config->rsz.scale_hcb),
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readl(base + stream->config->rsz.scale_hcb_shd),
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readl(base + stream->config->rsz.scale_hcr),
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readl(base + stream->config->rsz.scale_hcr_shd),
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readl(base + stream->config->rsz.scale_vy),
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readl(base + stream->config->rsz.scale_vy_shd),
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readl(base + stream->config->rsz.scale_vc),
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readl(base + stream->config->rsz.scale_vc_shd),
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readl(base + stream->config->rsz.phase_hy),
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readl(base + stream->config->rsz.phase_hy_shd),
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readl(base + stream->config->rsz.phase_hc),
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readl(base + stream->config->rsz.phase_hc_shd),
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readl(base + stream->config->rsz.phase_vy),
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readl(base + stream->config->rsz.phase_vy_shd),
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readl(base + stream->config->rsz.phase_vc),
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readl(base + stream->config->rsz.phase_vc_shd));
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}
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static void update_rsz_shadow(struct rkisp1_stream *stream, bool async)
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{
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void *addr = stream->ispdev->base_addr + stream->config->rsz.ctrl;
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u32 ctrl_cfg = readl(addr);
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if (async)
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writel(CIF_RSZ_CTRL_CFG_UPD_AUTO | ctrl_cfg, addr);
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else
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writel(CIF_RSZ_CTRL_CFG_UPD | ctrl_cfg, addr);
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}
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static void set_scale(struct rkisp1_stream *stream, struct v4l2_rect *in_y,
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struct v4l2_rect *in_c, struct v4l2_rect *out_y,
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struct v4l2_rect *out_c)
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{
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void __iomem *base = stream->ispdev->base_addr;
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void __iomem *scale_hy_addr = base + stream->config->rsz.scale_hy;
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void __iomem *scale_hcr_addr = base + stream->config->rsz.scale_hcr;
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void __iomem *scale_hcb_addr = base + stream->config->rsz.scale_hcb;
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void __iomem *scale_vy_addr = base + stream->config->rsz.scale_vy;
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void __iomem *scale_vc_addr = base + stream->config->rsz.scale_vc;
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void __iomem *rsz_ctrl_addr = base + stream->config->rsz.ctrl;
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u32 scale_hy, scale_hc, scale_vy, scale_vc, rsz_ctrl = 0;
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if (in_y->width < out_y->width) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE |
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CIF_RSZ_CTRL_SCALE_HY_UP;
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scale_hy = ((in_y->width - 1) * CIF_RSZ_SCALER_FACTOR) /
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(out_y->width - 1);
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writel(scale_hy, scale_hy_addr);
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} else if (in_y->width > out_y->width) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HY_ENABLE;
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scale_hy = ((out_y->width - 1) * CIF_RSZ_SCALER_FACTOR) /
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(in_y->width - 1) + 1;
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writel(scale_hy, scale_hy_addr);
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}
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if (in_c->width < out_c->width) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HC_ENABLE |
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CIF_RSZ_CTRL_SCALE_HC_UP;
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scale_hc = ((in_c->width - 1) * CIF_RSZ_SCALER_FACTOR) /
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(out_c->width - 1);
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writel(scale_hc, scale_hcb_addr);
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writel(scale_hc, scale_hcr_addr);
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} else if (in_c->width > out_c->width) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_HC_ENABLE;
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scale_hc = ((out_c->width - 1) * CIF_RSZ_SCALER_FACTOR) /
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(in_c->width - 1) + 1;
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writel(scale_hc, scale_hcb_addr);
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writel(scale_hc, scale_hcr_addr);
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}
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if (in_y->height < out_y->height) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE |
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CIF_RSZ_CTRL_SCALE_VY_UP;
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scale_vy = ((in_y->height - 1) * CIF_RSZ_SCALER_FACTOR) /
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(out_y->height - 1);
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writel(scale_vy, scale_vy_addr);
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} else if (in_y->height > out_y->height) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VY_ENABLE;
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scale_vy = ((out_y->height - 1) * CIF_RSZ_SCALER_FACTOR) /
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(in_y->height - 1) + 1;
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writel(scale_vy, scale_vy_addr);
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}
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if (in_c->height < out_c->height) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VC_ENABLE |
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CIF_RSZ_CTRL_SCALE_VC_UP;
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scale_vc = ((in_c->height - 1) * CIF_RSZ_SCALER_FACTOR) /
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(out_c->height - 1);
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writel(scale_vc, scale_vc_addr);
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} else if (in_c->height > out_c->height) {
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rsz_ctrl |= CIF_RSZ_CTRL_SCALE_VC_ENABLE;
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scale_vc = ((out_c->height - 1) * CIF_RSZ_SCALER_FACTOR) /
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(in_c->height - 1) + 1;
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writel(scale_vc, scale_vc_addr);
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}
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writel(rsz_ctrl, rsz_ctrl_addr);
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}
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void config_rsz(struct rkisp1_stream *stream, struct v4l2_rect *in_y,
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struct v4l2_rect *in_c, struct v4l2_rect *out_y,
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struct v4l2_rect *out_c, bool async)
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{
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int i = 0;
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/* No phase offset */
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writel(0, stream->ispdev->base_addr + stream->config->rsz.phase_hy);
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writel(0, stream->ispdev->base_addr + stream->config->rsz.phase_hc);
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writel(0, stream->ispdev->base_addr + stream->config->rsz.phase_vy);
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writel(0, stream->ispdev->base_addr + stream->config->rsz.phase_vc);
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/* Linear interpolation */
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for (i = 0; i < 64; i++) {
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writel(i, stream->ispdev->base_addr + stream->config->rsz.scale_lut_addr);
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writel(i, stream->ispdev->base_addr + stream->config->rsz.scale_lut);
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}
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set_scale(stream, in_y, in_c, out_y, out_c);
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update_rsz_shadow(stream, async);
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}
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void disable_rsz(struct rkisp1_stream *stream, bool async)
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{
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writel(0, stream->ispdev->base_addr + stream->config->rsz.ctrl);
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if (!async)
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update_rsz_shadow(stream, async);
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}
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void config_mi_ctrl(struct rkisp1_stream *stream, u32 burst)
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{
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void __iomem *base = stream->ispdev->base_addr;
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void __iomem *addr = base + CIF_MI_CTRL;
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u32 reg;
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reg = readl(addr) & ~GENMASK(19, 16);
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writel(reg | burst, addr);
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reg = readl(addr);
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writel(reg | CIF_MI_CTRL_INIT_BASE_EN, addr);
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reg = readl(addr);
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writel(reg | CIF_MI_CTRL_INIT_OFFSET_EN, addr);
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}
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bool mp_is_stream_stopped(void __iomem *base)
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{
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int en;
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en = CIF_MI_CTRL_SHD_MP_IN_ENABLED | CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
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return !(readl(base + CIF_MI_CTRL_SHD) & en);
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}
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bool sp_is_stream_stopped(void __iomem *base)
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{
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return !(readl(base + CIF_MI_CTRL_SHD) & CIF_MI_CTRL_SHD_SP_IN_ENABLED);
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}
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