/*
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* Rockchip isp1 driver
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*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _RKISP1_PATH_VIDEO_H
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#define _RKISP1_PATH_VIDEO_H
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#include "common.h"
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struct rkisp1_stream;
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/*
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* @fourcc: pixel format
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* @mbus_code: pixel format over bus
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* @fmt_type: helper filed for pixel format
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* @bpp: bits per pixel
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* @bayer_pat: bayer patten type
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* @cplanes: number of colour planes
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* @mplanes: number of stored memory planes
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* @uv_swap: if cb cr swaped, for yuv
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* @write_format: defines how YCbCr self picture data is written to memory
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* @input_format: defines sp input format
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* @output_format: defines sp output format
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*/
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struct capture_fmt {
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u32 fourcc;
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u32 mbus_code;
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u8 fmt_type;
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u8 cplanes;
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u8 mplanes;
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u8 uv_swap;
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u32 write_format;
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u32 output_format;
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u8 bpp[VIDEO_MAX_PLANES];
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};
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enum rkisp1_sp_inp {
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RKISP1_SP_INP_ISP,
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RKISP1_SP_INP_DMA_SP,
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RKISP1_SP_INP_MAX
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};
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enum rkisp1_field {
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RKISP_FIELD_ODD,
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RKISP_FIELD_EVEN,
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RKISP_FIELD_INVAL,
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};
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struct rkisp1_stream_sp {
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int y_stride;
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int vir_offs;
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enum rkisp1_sp_inp input_sel;
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enum rkisp1_field field;
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enum rkisp1_field field_rec;
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};
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struct rkisp1_stream_mp {
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bool raw_enable;
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};
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struct rkisp1_stream_raw {
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u8 pre_stop;
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};
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struct rkisp1_stream_dmarx {
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int y_stride;
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};
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/* Different config between selfpath and mainpath */
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struct stream_config {
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const struct capture_fmt *fmts;
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int fmt_size;
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/* constrains */
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const int max_rsz_width;
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const int max_rsz_height;
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const int min_rsz_width;
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const int min_rsz_height;
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/* registers */
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struct {
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u32 ctrl;
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u32 ctrl_shd;
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u32 scale_hy;
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u32 scale_hcr;
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u32 scale_hcb;
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u32 scale_vy;
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u32 scale_vc;
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u32 scale_lut;
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u32 scale_lut_addr;
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u32 scale_hy_shd;
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u32 scale_hcr_shd;
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u32 scale_hcb_shd;
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u32 scale_vy_shd;
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u32 scale_vc_shd;
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u32 phase_hy;
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u32 phase_hc;
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u32 phase_vy;
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u32 phase_vc;
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u32 phase_hy_shd;
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u32 phase_hc_shd;
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u32 phase_vy_shd;
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u32 phase_vc_shd;
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} rsz;
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struct {
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u32 ctrl;
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u32 yuvmode_mask;
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u32 rawmode_mask;
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u32 h_offset;
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u32 v_offset;
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u32 h_size;
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u32 v_size;
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} dual_crop;
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struct {
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u32 y_size_init;
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u32 cb_size_init;
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u32 cr_size_init;
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u32 y_base_ad_init;
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u32 cb_base_ad_init;
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u32 cr_base_ad_init;
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u32 y_offs_cnt_init;
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u32 cb_offs_cnt_init;
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u32 cr_offs_cnt_init;
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} mi;
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};
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/* Different reg ops between selfpath and mainpath */
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struct streams_ops {
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int (*config_mi)(struct rkisp1_stream *stream);
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void (*stop_mi)(struct rkisp1_stream *stream);
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void (*enable_mi)(struct rkisp1_stream *stream);
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void (*disable_mi)(struct rkisp1_stream *stream);
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void (*set_data_path)(void __iomem *base);
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bool (*is_stream_stopped)(void __iomem *base);
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void (*update_mi)(struct rkisp1_stream *stream);
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};
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/*
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* struct rkisp1_stream - ISP capture video device
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*
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* @out_isp_fmt: output isp format
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* @out_fmt: output buffer size
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* @dcrop: coordinates of dual-crop
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*
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* @vbq_lock: lock to protect buf_queue
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* @buf_queue: queued buffer list
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* @dummy_buf: dummy space to store dropped data
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*
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* rkisp1 use shadowsock registers, so it need two buffer at a time
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* @curr_buf: the buffer used for current frame
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* @next_buf: the buffer used for next frame
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*/
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struct rkisp1_stream {
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unsigned id:2;
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unsigned interlaced:1;
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struct rkisp1_device *ispdev;
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struct rkisp1_vdev_node vnode;
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struct capture_fmt out_isp_fmt;
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struct v4l2_pix_format_mplane out_fmt;
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struct v4l2_rect dcrop;
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struct streams_ops *ops;
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struct stream_config *config;
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spinlock_t vbq_lock;
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struct list_head buf_queue;
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struct rkisp1_dummy_buffer dummy_buf;
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struct rkisp1_buffer *curr_buf;
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struct rkisp1_buffer *next_buf;
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bool streaming;
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bool stopping;
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bool frame_end;
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wait_queue_head_t done;
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unsigned int burst;
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union {
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struct rkisp1_stream_sp sp;
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struct rkisp1_stream_mp mp;
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struct rkisp1_stream_raw raw;
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struct rkisp1_stream_dmarx dmarx;
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} u;
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};
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void rkisp1_unregister_stream_vdevs(struct rkisp1_device *dev);
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int rkisp1_register_stream_vdevs(struct rkisp1_device *dev);
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void rkisp1_mi_isr(u32 mis_val, struct rkisp1_device *dev);
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void rkisp1_stream_init(struct rkisp1_device *dev, u32 id);
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void rkisp1_set_stream_def_fmt(struct rkisp1_device *dev, u32 id,
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u32 width, u32 height, u32 pixelformat);
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void rkisp1_mipi_dmatx0_end(u32 status, struct rkisp1_device *dev);
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int fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs);
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int rkisp1_fh_open(struct file *filp);
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int rkisp1_fop_release(struct file *file);
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#endif /* _RKISP1_PATH_VIDEO_H */
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