/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Intel(R) Trace Hub Memory Storage Unit (MSU) data structures
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*/
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#ifndef __INTEL_TH_MSU_H__
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#define __INTEL_TH_MSU_H__
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enum {
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REG_MSU_MSUPARAMS = 0x0000,
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REG_MSU_MSUSTS = 0x0008,
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REG_MSU_MINTCTL = 0x0004, /* MSU-global interrupt control */
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REG_MSU_MSC0CTL = 0x0100, /* MSC0 control */
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REG_MSU_MSC0STS = 0x0104, /* MSC0 status */
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REG_MSU_MSC0BAR = 0x0108, /* MSC0 output base address */
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REG_MSU_MSC0SIZE = 0x010c, /* MSC0 output size */
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REG_MSU_MSC0MWP = 0x0110, /* MSC0 write pointer */
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REG_MSU_MSC0NWSA = 0x011c, /* MSC0 next window start address */
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REG_MSU_MSC1CTL = 0x0200, /* MSC1 control */
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REG_MSU_MSC1STS = 0x0204, /* MSC1 status */
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REG_MSU_MSC1BAR = 0x0208, /* MSC1 output base address */
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REG_MSU_MSC1SIZE = 0x020c, /* MSC1 output size */
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REG_MSU_MSC1MWP = 0x0210, /* MSC1 write pointer */
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REG_MSU_MSC1NWSA = 0x021c, /* MSC1 next window start address */
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};
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/* MSUSTS bits */
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#define MSUSTS_MSU_INT BIT(0)
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#define MSUSTS_MSC0BLAST BIT(16)
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#define MSUSTS_MSC1BLAST BIT(24)
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/* MSCnCTL bits */
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#define MSC_EN BIT(0)
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#define MSC_WRAPEN BIT(1)
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#define MSC_RD_HDR_OVRD BIT(2)
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#define MSC_MODE (BIT(4) | BIT(5))
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#define MSC_LEN (BIT(8) | BIT(9) | BIT(10))
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/* MINTCTL bits */
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#define MICDE BIT(0)
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#define M0BLIE BIT(16)
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#define M1BLIE BIT(24)
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/* MSCnSTS bits */
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#define MSCSTS_WRAPSTAT BIT(1) /* Wrap occurred */
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#define MSCSTS_PLE BIT(2) /* Pipeline Empty */
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/*
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* Multiblock/multiwindow block descriptor
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*/
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struct msc_block_desc {
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u32 sw_tag;
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u32 block_sz;
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u32 next_blk;
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u32 next_win;
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u32 res0[4];
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u32 hw_tag;
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u32 valid_dw;
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u32 ts_low;
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u32 ts_high;
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u32 res1[4];
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} __packed;
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#define MSC_BDESC sizeof(struct msc_block_desc)
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#define DATA_IN_PAGE (PAGE_SIZE - MSC_BDESC)
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/* MSC multiblock sw tag bits */
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#define MSC_SW_TAG_LASTBLK BIT(0)
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#define MSC_SW_TAG_LASTWIN BIT(1)
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/* MSC multiblock hw tag bits */
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#define MSC_HW_TAG_TRIGGER BIT(0)
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#define MSC_HW_TAG_BLOCKWRAP BIT(1)
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#define MSC_HW_TAG_WINWRAP BIT(2)
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#define MSC_HW_TAG_ENDBIT BIT(3)
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static inline unsigned long msc_data_sz(struct msc_block_desc *bdesc)
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{
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if (!bdesc->valid_dw)
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return 0;
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return bdesc->valid_dw * 4 - MSC_BDESC;
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}
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static inline unsigned long msc_total_sz(struct msc_block_desc *bdesc)
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{
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return bdesc->valid_dw * 4;
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}
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static inline unsigned long msc_block_sz(struct msc_block_desc *bdesc)
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{
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return bdesc->block_sz * 64 - MSC_BDESC;
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}
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static inline bool msc_block_wrapped(struct msc_block_desc *bdesc)
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{
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if (bdesc->hw_tag & (MSC_HW_TAG_BLOCKWRAP | MSC_HW_TAG_WINWRAP))
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return true;
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return false;
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}
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static inline bool msc_block_last_written(struct msc_block_desc *bdesc)
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{
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if ((bdesc->hw_tag & MSC_HW_TAG_ENDBIT) ||
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(msc_data_sz(bdesc) != msc_block_sz(bdesc)))
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return true;
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return false;
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}
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/* waiting for Pipeline Empty bit(s) to assert for MSC */
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#define MSC_PLE_WAITLOOP_DEPTH 10000
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#endif /* __INTEL_TH_MSU_H__ */
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