/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015, NVIDIA Corporation.
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*/
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#ifndef TEGRA_VIC_H
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#define TEGRA_VIC_H
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/* VIC methods */
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#define VIC_SET_APPLICATION_ID 0x00000200
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#define VIC_SET_FCE_UCODE_SIZE 0x0000071C
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#define VIC_SET_FCE_UCODE_OFFSET 0x0000072C
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/* VIC registers */
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#define VIC_THI_STREAMID0 0x00000030
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#define VIC_THI_STREAMID1 0x00000034
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#define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0
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#define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0)
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#define CG_IDLE_CG_EN (1 << 6)
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#define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16)
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#define VIC_TFBIF_TRANSCFG 0x00002044
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#define TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4))
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#define TRANSCFG_SID_HW 0
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#define TRANSCFG_SID_PHY 1
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#define TRANSCFG_SID_FALCON 2
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/* Firmware offsets */
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#define VIC_UCODE_FCE_HEADER_OFFSET (6*4)
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#define VIC_UCODE_FCE_DATA_OFFSET (7*4)
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#define FCE_UCODE_SIZE_OFFSET (2*4)
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#endif /* TEGRA_VIC_H */
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