/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author:
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* algea cao <algea.cao@rock-chips.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ROCKCHIP_DRM_TVE_H__
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#define __ROCKCHIP_DRM_TVE_H__
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#define RK3036_GRF_SOC_CON3 0x0154
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#define RK312X_GRF_TVE_CON 0x0170
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#define m_EXTREF_EN BIT(0)
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#define m_VBG_EN BIT(1)
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#define m_DAC_EN BIT(2)
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#define m_SENSE_EN BIT(3)
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#define m_BIAS_EN (7 << 4)
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#define m_DAC_GAIN (0x3f << 7)
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#define v_DAC_GAIN(x) (((x) & 0x3f) << 7)
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#define TV_CTRL (0x00)
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#define m_CVBS_MODE BIT(24)
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#define m_CLK_UPSTREAM_EN (3 << 18)
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#define m_TIMING_EN (3 << 16)
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#define m_LUMA_FILTER_GAIN (3 << 9)
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#define m_LUMA_FILTER_BW BIT(8)
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#define m_CSC_PATH (3 << 1)
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#define v_CVBS_MODE(x) (((x) & 1) << 24)
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#define v_CLK_UPSTREAM_EN(x) (((x) & 3) << 18)
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#define v_TIMING_EN(x) (((x) & 3) << 16)
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#define v_LUMA_FILTER_GAIN(x) (((x) & 3) << 9)
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#define v_LUMA_FILTER_UPSAMPLE(x) (((x) & 1) << 8)
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#define v_CSC_PATH(x) (((x) & 3) << 1)
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#define TV_SYNC_TIMING (0x04)
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#define TV_ACT_TIMING (0x08)
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#define TV_ADJ_TIMING (0x0c)
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#define TV_FREQ_SC (0x10)
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#define TV_LUMA_FILTER0 (0x14)
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#define TV_LUMA_FILTER1 (0x18)
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#define TV_LUMA_FILTER2 (0x1C)
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#define TV_ACT_ST (0x34)
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#define TV_ROUTING (0x38)
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#define m_DAC_SENSE_EN BIT(27)
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#define m_Y_IRE_7_5 BIT(19)
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#define m_Y_AGC_PULSE_ON BIT(15)
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#define m_Y_VIDEO_ON BIT(11)
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#define m_Y_SYNC_ON BIT(7)
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#define m_YPP_MODE BIT(3)
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#define m_MONO_EN BIT(2)
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#define m_PIC_MODE BIT(1)
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#define v_DAC_SENSE_EN(x) (((x) & 1) << 27)
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#define v_Y_IRE_7_5(x) (((x) & 1) << 19)
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#define v_Y_AGC_PULSE_ON(x) (((x) & 1) << 15)
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#define v_Y_VIDEO_ON(x) (((x) & 1) << 11)
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#define v_Y_SYNC_ON(x) (((x) & 1) << 7)
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#define v_YPP_MODE(x) (((x) & 1) << 3)
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#define v_MONO_EN(x) (((x) & 1) << 2)
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#define v_PIC_MODE(x) (((x) & 1) << 1)
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#define TV_SYNC_ADJUST (0x50)
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#define TV_STATUS (0x54)
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#define TV_RESET (0x68)
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#define m_RESET BIT(1)
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#define v_RESET(x) (((x) & 1) << 1)
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#define TV_SATURATION (0x78)
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#define TV_BW_CTRL (0x8C)
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#define m_CHROMA_BW (3 << 4)
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#define m_COLOR_DIFF_BW (0xf)
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enum {
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BP_FILTER_PASS = 0,
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BP_FILTER_NTSC,
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BP_FILTER_PAL,
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};
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enum {
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COLOR_DIFF_FILTER_OFF = 0,
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COLOR_DIFF_FILTER_BW_0_6,
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COLOR_DIFF_FILTER_BW_1_3,
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COLOR_DIFF_FILTER_BW_2_0
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};
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#define v_CHROMA_BW(x) ((3 & (x)) << 4)
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#define v_COLOR_DIFF_BW(x) (0xF & (x))
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#define TV_BRIGHTNESS_CONTRAST (0x90)
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#define VDAC_VDAC0 (0x00)
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#define m_RST_ANA BIT(7)
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#define m_RST_DIG BIT(6)
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#define v_RST_ANA(x) (((x) & 1) << 7)
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#define v_RST_DIG(x) (((x) & 1) << 6)
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#define VDAC_VDAC1 (0x280)
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#define m_CUR_REG (0xf << 4)
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#define m_DR_PWR_DOWN BIT(1)
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#define m_BG_PWR_DOWN BIT(0)
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#define v_CUR_REG(x) (((x) & 0xf) << 4)
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#define v_DR_PWR_DOWN(x) (((x) & 1) << 1)
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#define v_BG_PWR_DOWN(x) (((x) & 1) << 0)
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#define VDAC_VDAC2 (0x284)
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#define m_CUR_CTR (0X3f)
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#define v_CUR_CTR(x) (((x) & 0x3f))
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#define VDAC_VDAC3 (0x288)
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#define m_CAB_EN BIT(5)
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#define m_CAB_REF BIT(4)
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#define m_CAB_FLAG BIT(0)
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#define v_CAB_EN(x) (((x) & 1) << 5)
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#define v_CAB_REF(x) (((x) & 1) << 4)
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#define v_CAB_FLAG(x) (((x) & 1) << 0)
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// RK3528 CVBS GRF
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#define RK3528_VO_GRF_CVBS_CON 0x60010
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#define m_TVE_DCLK_POL BIT(5)
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#define m_TVE_DCLK_EN BIT(4)
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#define m_DCLK_UPSAMPLE_2X4X BIT(3)
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#define m_DCLK_UPSAMPLE_EN BIT(2)
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#define m_TVE_MODE BIT(1)
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#define m_TVE_EN BIT(0)
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#define v_TVE_DCLK_POL(x) (((x) & 1) << 5)
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#define v_TVE_DCLK_EN(x) (((x) & 1) << 4)
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#define v_DCLK_UPSAMPLE_2X4X(x) (((x) & 1) << 3)
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#define v_DCLK_UPSAMPLE_EN(x) (((x) & 1) << 2)
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#define v_TVE_MODE(x) (((x) & 1) << 1)
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#define v_TVE_EN(x) (((x) & 1) << 0)
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// RK3528 CVBS BT656
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#define BT656_DECODER_CTRL (0x3D00)
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#define BT656_DECODER_CROP (0x3D04)
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#define BT656_DECODER_SIZE (0x3D08)
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#define BT656_DECODER_HTOTAL_HS_END (0x3D0C)
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#define BT656_DECODER_VACT_ST_HACT_ST (0x3D10)
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#define BT656_DECODER_VTOTAL_VS_END (0x3D14)
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#define BT656_DECODER_VS_ST_END_F1 (0x3D18)
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#define BT656_DECODER_DBG_REG (0x3D1C)
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// RK3528 CVBS TVE
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#define TVE_MODE_CTRL (0x3E00)
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#define TVE_HOR_TIMING1 (0x3E04)
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#define TVE_HOR_TIMING2 (0x3E08)
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#define TVE_HOR_TIMING3 (0x3E0C)
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#define TVE_SUB_CAR_FRQ (0x3E10)
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#define TVE_LUMA_FILTER1 (0x3E14)
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#define TVE_LUMA_FILTER2 (0x3E18)
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#define TVE_LUMA_FILTER3 (0x3E1C)
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#define TVE_LUMA_FILTER4 (0x3E20)
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#define TVE_LUMA_FILTER5 (0x3E24)
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#define TVE_LUMA_FILTER6 (0x3E28)
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#define TVE_LUMA_FILTER7 (0x3E2C)
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#define TVE_LUMA_FILTER8 (0x3E30)
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#define TVE_IMAGE_POSITION (0x3E34)
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#define TVE_ROUTING (0x3E38)
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#define TVE_SYNC_ADJUST (0x3E50)
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#define TVE_STATUS (0x3E54)
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#define TVE_CTRL (0x3E68)
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#define TVE_INTR_STATUS (0x3E6C)
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#define TVE_INTR_EN (0x3E70)
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#define TVE_INTR_CLR (0x3E74)
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#define TVE_COLOR_BUSRT_SAT (0x3E78)
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#define TVE_CHROMA_BANDWIDTH (0x3E8C)
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#define TVE_BRIGHTNESS_CONTRAST (0x3E90)
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#define TVE_ID (0x3E98)
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#define TVE_REVISION (0x3E9C)
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#define TVE_CLAMP (0x3EA0)
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// RK3528 CVBS VDAC
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#define VDAC_CLK_RST (0x0000)
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#define m_ANALOG_RST BIT(7)
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#define m_DIGITAL_RST BIT(6)
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#define m_INPUT_CLK_INV BIT(0)
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#define v_ANALOG_RST(x) (((x) & 1) << 7)
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#define v_DIGITAL_RST(x) (((x) & 1) << 6)
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#define v_INPUT_CLK_INV(x) (((x) & 1) << 0)
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#define VDAC_SINE_CTRL (0x0004)
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#define VDAC_SQUARE_CTRL (0x0008)
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#define VDAC_LEVEL_CTRL0 (0x0018)
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#define VDAC_LEVEL_CTRL1 (0x001C)
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#define VDAC_PWM_REF_CTRL (0x0280)
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#define m_REF_VOLTAGE (0xf << 4)
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#define m_REF_RESISTOR BIT(3)
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#define m_SMP_CLK_INV BIT(2)
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#define m_DAC_PWN BIT(1)
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#define m_BIAS_PWN BIT(0)
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#define v_REF_VOLTAGE(x) (((x) & 0xf) << 4)
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#define v_SMP_CLK_INV(x) (((x) & 1) << 2)
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#define v_REF_RESISTOR(x) (((x) & 1) << 3)
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#define v_DAC_PWN(x) (((x) & 1) << 1)
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#define v_BIAS_PWN(x) (((x) & 1) << 0)
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#define VDAC_CURRENT_CTRL (0x0284)
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#define m_OUT_CURRENT (0xff << 0)
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#define v_OUT_CURRENT(x) (((x) & 0xff) << 0)
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#define VDAC_CABLE_CTRL (0x0288)
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#define VDAC_VOLTAGE_CTRL (0x028C)
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#define VDAC_BIAS_CLK_CTRL0 (0x0290)
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#define VDAC_BIAS_CLK_CTRL1 (0x0294)
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#define VDAC_AUTO_CLK_CTRL0 (0x0298)
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#define VDAC_AUTO_CLK_CTRL1 (0x029C)
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enum {
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TVOUT_CVBS_NTSC = 0,
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TVOUT_CVBS_PAL,
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};
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enum {
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INPUT_FORMAT_RGB = 0,
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INPUT_FORMAT_YUV
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};
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enum {
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SOC_RK3036 = 0,
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SOC_RK312X,
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SOC_RK322X,
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SOC_RK3328,
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SOC_RK3528
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};
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enum {
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DCLK_UPSAMPLEx1 = 0,
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DCLK_UPSAMPLEx2,
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DCLK_UPSAMPLEx4
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};
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#define grf_writel(offset, v) do { \
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writel_relaxed(v, RK_GRF_VIRT + (offset)); \
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dsb(sy); \
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} while (0)
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struct rockchip_tve {
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struct device *dev;
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struct drm_device *drm_dev;
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struct drm_connector connector;
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struct drm_encoder encoder;
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u32 tv_format;
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void __iomem *regbase;
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void __iomem *vdacbase;
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struct clk *aclk;
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struct clk *hclk;
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struct clk *pclk_vdac;
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struct clk *dclk;
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struct clk *dclk_4x;
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struct regmap *dac_grf;
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u32 reg_phy_base;
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u32 len;
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int input_format;
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int soc_type;
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int upsample_mode;
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bool enable;
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u32 test_mode;
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u32 saturation;
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u32 brightcontrast;
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u32 adjtiming;
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u32 lumafilter0;
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u32 lumafilter1;
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u32 lumafilter2;
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u32 lumafilter3;
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u32 lumafilter4;
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u32 lumafilter5;
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u32 lumafilter6;
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u32 lumafilter7;
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u32 daclevel;
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u32 dac1level;
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u32 preferred_mode;
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u8 vdac_out_current;
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struct mutex suspend_lock; /* mutex for tve resume operation*/
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struct rockchip_drm_sub_dev sub_dev;
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};
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#endif /* _ROCKCHIP_DRM_TVE_ */
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