// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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* Author: Sandy Huang <hjc@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/clk-conf.h>
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#include "rockchip_drm_vop.h"
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#include "rockchip_drm_drv.h"
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#define VOP2_PLL_LIMIT_FREQ 594000000
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#define VOP2_PLL_MIN_FREQ 40000000
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static long rockchip_rk3562_drm_dclk_round_rate(struct clk *dclk, unsigned long rate)
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{
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struct clk_hw *hw;
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struct clk_hw *p_hw;
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unsigned long round_rate;
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const char *name;
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hw = __clk_get_hw(dclk);
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if (!hw)
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return -EINVAL;
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p_hw = clk_hw_get_parent(hw);
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if (!p_hw)
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return -EINVAL;
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name = clk_hw_get_name(p_hw);
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if (!strcmp(name, "vpll"))
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round_rate = rate;
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else
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round_rate = clk_round_rate(dclk, rate);
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return round_rate;
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}
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static long rockchip_rk3568_drm_dclk_round_rate(struct clk *dclk, unsigned long rate)
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{
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struct clk_hw *hw;
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struct clk_hw *p_hw;
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unsigned long round_rate;
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const char *name;
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hw = __clk_get_hw(dclk);
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if (!hw)
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return -EINVAL;
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p_hw = clk_hw_get_parent(hw);
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if (!p_hw)
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return -EINVAL;
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name = clk_hw_get_name(p_hw);
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if (!strcmp(name, "vpll"))
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round_rate = rate;
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else if (!strcmp(name, "hpll"))
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round_rate = rate;
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else
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round_rate = clk_round_rate(dclk, rate);
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return round_rate;
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}
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static long rockchip_rk3588_drm_dclk_round_rate(struct clk *dclk, unsigned long rate)
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{
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struct clk_hw *hw;
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struct clk_hw *p_hw;
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unsigned long round_rate;
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const char *name;
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hw = __clk_get_hw(dclk);
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if (!hw)
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return -EINVAL;
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name = clk_hw_get_name(hw);
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if (!strcmp(name, "dclk_vop3")) {
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p_hw = clk_hw_get_parent(hw);
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} else {
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p_hw = clk_hw_get_parent(hw);
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if (!p_hw)
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return -EINVAL;
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p_hw = clk_hw_get_parent(p_hw);
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}
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if (!p_hw)
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return -EINVAL;
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name = clk_hw_get_name(p_hw);
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if (!strcmp(name, "v0pll"))
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round_rate = rate;
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else
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round_rate = clk_round_rate(dclk, rate);
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return round_rate;
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}
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/*
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* The rk3562 is a single display, exclusive to vpll
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*/
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static int rockchip_rk3562_drm_dclk_set_rate(struct clk *dclk, unsigned long rate)
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{
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struct clk_hw *hw;
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struct clk_hw *p_hw;
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unsigned long pll_rate;
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const char *name;
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int div = 0;
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hw = __clk_get_hw(dclk);
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if (!hw)
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return -EINVAL;
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p_hw = clk_hw_get_parent(hw);
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if (!p_hw)
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return -EINVAL;
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name = clk_hw_get_name(p_hw);
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if (!strcmp(name, "vpll")) {
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pll_rate = clk_hw_get_rate(p_hw);
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if (pll_rate >= VOP2_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
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clk_set_rate(dclk, rate);
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} else {
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div = DIV_ROUND_UP(VOP2_PLL_LIMIT_FREQ, rate);
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if (div % 2)
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div += 1;
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clk_set_rate(p_hw->clk, rate * div);
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clk_set_rate(dclk, rate);
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}
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} else {
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clk_set_rate(dclk, rate);
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}
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pr_debug("%s:request rate = %ld, %s = %ld, %s = %ld\n", __func__, rate,
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clk_hw_get_name(hw), clk_hw_get_rate(hw),
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clk_hw_get_name(p_hw), clk_hw_get_rate(p_hw));
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return 0;
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}
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/*
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* The rk3568 has three ports, dclk_vop0/dclk_vop1/dclk_vop2
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* For the dclk used by hdmi, the parent clock must be specified in hpll.
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* There is also a dclk that can be specified on the vpll.
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* The last dclk can only choose the nearest frequency division,
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* and cannot support accurate frequency setting.
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*/
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static int rockchip_rk3568_drm_dclk_set_rate(struct clk *dclk, unsigned long rate)
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{
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struct clk_hw *hw;
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struct clk_hw *p_hw;
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unsigned long pll_rate;
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const char *name;
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int div = 0;
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hw = __clk_get_hw(dclk);
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if (!hw)
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return -EINVAL;
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p_hw = clk_hw_get_parent(hw);
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if (!p_hw)
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return -EINVAL;
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name = clk_hw_get_name(p_hw);
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if (!strcmp(name, "vpll")) {
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pll_rate = clk_hw_get_rate(p_hw);
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if (pll_rate >= VOP2_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
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clk_set_rate(dclk, rate);
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} else {
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div = DIV_ROUND_UP(VOP2_PLL_LIMIT_FREQ, rate);
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if (div % 2)
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div += 1;
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clk_set_rate(p_hw->clk, rate * div);
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clk_set_rate(dclk, rate);
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}
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} else if (!strcmp(name, "hpll")) {
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if (rate < VOP2_PLL_MIN_FREQ)
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pr_warn("%s: Warning: rate is low than pll min limit!\n", __func__);
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clk_set_rate(p_hw->clk, rate);
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clk_set_rate(dclk, rate);
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} else {
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clk_set_rate(dclk, rate);
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}
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pr_debug("%s:request rate = %ld, %s = %ld %s = %ld\n", __func__, rate,
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clk_hw_get_name(hw), clk_hw_get_rate(hw),
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clk_hw_get_name(p_hw), clk_hw_get_rate(p_hw));
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return 0;
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}
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/*
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* The rk3588 has four ports, dclk_vop0\1\2\3.
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* The dclk_vop0\1\2 can select 2 ports specified on clk_hdmiphy_pixelx.
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* The dclk_vop0\1\2\3 can select 1 ports specified on v0pll.
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* The last dclk can only choose the nearest frequency division,
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* and cannot support accurate frequency setting.
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*/
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static int rockchip_rk3588_drm_dclk_set_rate(struct clk *dclk, unsigned long rate)
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{
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struct clk_hw *hw;
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struct clk_hw *p_hw;
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unsigned long pll_rate;
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const char *name;
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int div = 0;
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hw = __clk_get_hw(dclk);
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if (!hw)
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return -EINVAL;
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name = clk_hw_get_name(hw);
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if (!strcmp(name, "dclk_vop3")) {
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p_hw = clk_hw_get_parent(hw);
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} else {
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p_hw = clk_hw_get_parent(hw);
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if (!p_hw)
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return -EINVAL;
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p_hw = clk_hw_get_parent(p_hw);
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}
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if (!p_hw)
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return -EINVAL;
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name = clk_hw_get_name(p_hw);
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if (!strcmp(name, "v0pll")) {
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pll_rate = clk_hw_get_rate(p_hw);
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if (pll_rate >= VOP2_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
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clk_set_rate(dclk, rate);
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} else {
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div = DIV_ROUND_UP(VOP2_PLL_LIMIT_FREQ, rate);
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if (div % 2)
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div += 1;
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clk_set_rate(p_hw->clk, rate * div);
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clk_set_rate(dclk, rate);
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}
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} else {
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clk_set_rate(dclk, rate);
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}
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pr_debug("%s:request rate = %ld, %s = %ld %s = %ld\n", __func__, rate,
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clk_hw_get_name(hw), clk_hw_get_rate(hw),
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clk_hw_get_name(p_hw), clk_hw_get_rate(p_hw));
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return 0;
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}
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long rockchip_drm_dclk_round_rate(u32 version, struct clk *dclk, unsigned long rate)
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{
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long round_rate;
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if (version == VOP_VERSION_RK3562)
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round_rate = rockchip_rk3562_drm_dclk_round_rate(dclk, rate);
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else if (version == VOP_VERSION_RK3568)
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round_rate = rockchip_rk3568_drm_dclk_round_rate(dclk, rate);
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else if (version == VOP_VERSION_RK3588)
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round_rate = rockchip_rk3588_drm_dclk_round_rate(dclk, rate);
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else
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round_rate = clk_round_rate(dclk, rate);
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if (round_rate < 0)
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pr_warn("%s:the clk_hw of dclk or parent of dclk may be NULL\n", __func__);
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return round_rate;
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}
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int rockchip_drm_dclk_set_rate(u32 version, struct clk *dclk, unsigned long rate)
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{
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int ret;
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if (version == VOP_VERSION_RK3562)
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ret = rockchip_rk3562_drm_dclk_set_rate(dclk, rate);
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else if (version == VOP_VERSION_RK3568)
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ret = rockchip_rk3568_drm_dclk_set_rate(dclk, rate);
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else if (version == VOP_VERSION_RK3588)
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ret = rockchip_rk3588_drm_dclk_set_rate(dclk, rate);
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else
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ret = clk_set_rate(dclk, rate);
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if (ret < 0)
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pr_warn("%s:the clk_hw of dclk or parent of dclk may be NULL\n", __func__);
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return ret;
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}
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