// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/mfd/rk628.h>
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#include <video/of_display_timing.h>
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#include <video/videomode.h>
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#include <drm/drm_of.h>
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enum rk628_mode_sync_pol {
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MODE_FLAG_NSYNC,
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MODE_FLAG_PSYNC,
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};
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struct rk628_post_process {
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struct drm_bridge base;
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struct drm_bridge *bridge;
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struct drm_display_mode src_mode;
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struct drm_display_mode dst_mode;
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struct device *dev;
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struct regmap *grf;
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struct clk *sclk_vop;
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struct clk *clk_rx_read;
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struct reset_control *rstc_decoder;
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struct reset_control *rstc_clk_rx;
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struct reset_control *rstc_vop;
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struct rk628 *parent;
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int sync_pol;
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};
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static inline struct rk628_post_process *bridge_to_pp(struct drm_bridge *bridge)
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{
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return container_of(bridge, struct rk628_post_process, base);
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}
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static void calc_dsp_frm_hst_vst(const struct videomode *src,
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const struct videomode *dst,
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u32 *dsp_frame_hst, u32 *dsp_frame_vst)
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{
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u32 bp_in, bp_out;
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u32 v_scale_ratio;
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u64 t_frm_st;
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u64 t_bp_in, t_bp_out, t_delta, tin;
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u32 src_pixclock, dst_pixclock;
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u32 dsp_htotal, src_htotal, src_vtotal;
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src_pixclock = div_u64(1000000000000llu, src->pixelclock);
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dst_pixclock = div_u64(1000000000000llu, dst->pixelclock);
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src_htotal = src->hsync_len + src->hback_porch + src->hactive +
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src->hfront_porch;
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src_vtotal = src->vsync_len + src->vback_porch + src->vactive +
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src->vfront_porch;
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dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
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dst->hfront_porch;
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bp_in = (src->vback_porch + src->vsync_len) * src_htotal +
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src->hsync_len + src->hback_porch;
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bp_out = (dst->vback_porch + dst->vsync_len) * dsp_htotal +
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dst->hsync_len + dst->hback_porch;
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t_bp_in = bp_in * src_pixclock;
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t_bp_out = bp_out * dst_pixclock;
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tin = src_vtotal * src_htotal * src_pixclock;
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v_scale_ratio = src->vactive / dst->vactive;
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if (v_scale_ratio <= 2)
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t_delta = 5 * src_htotal * src_pixclock;
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else
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t_delta = 12 * src_htotal * src_pixclock;
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if (t_bp_in + t_delta > t_bp_out)
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t_frm_st = (t_bp_in + t_delta - t_bp_out);
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else
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t_frm_st = tin - (t_bp_out - (t_bp_in + t_delta));
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do_div(t_frm_st, src_pixclock);
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*dsp_frame_hst = do_div(t_frm_st, src_htotal);
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*dsp_frame_vst = t_frm_st;
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}
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static void rk628_post_process_scaler_init(struct rk628_post_process *pp,
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const struct drm_display_mode *s,
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const struct drm_display_mode *d)
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{
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struct videomode src, dst;
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u32 dsp_frame_hst, dsp_frame_vst;
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u32 scl_hor_mode, scl_ver_mode;
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u32 scl_v_factor, scl_h_factor;
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u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
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u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
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u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
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u16 bor_right = 0, bor_left = 0, bor_up = 0, bor_down = 0;
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u8 hor_down_mode = 0, ver_down_mode = 0;
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drm_display_mode_to_videomode(s, &src);
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drm_display_mode_to_videomode(d, &dst);
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dsp_htotal = dst.hsync_len + dst.hback_porch + dst.hactive +
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dst.hfront_porch;
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dsp_vtotal = dst.vsync_len + dst.vback_porch + dst.vactive +
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dst.vfront_porch;
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dsp_hs_end = dst.hsync_len;
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dsp_vs_end = dst.vsync_len;
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dsp_hbor_end = dst.hsync_len + dst.hback_porch + dst.hactive;
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dsp_hbor_st = dst.hsync_len + dst.hback_porch;
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dsp_vbor_end = dst.vsync_len + dst.vback_porch + dst.vactive;
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dsp_vbor_st = dst.vsync_len + dst.vback_porch;
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dsp_hact_st = dsp_hbor_st + bor_left;
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dsp_hact_end = dsp_hbor_end - bor_right;
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dsp_vact_st = dsp_vbor_st + bor_up;
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dsp_vact_end = dsp_vbor_end - bor_down;
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calc_dsp_frm_hst_vst(&src, &dst, &dsp_frame_hst, &dsp_frame_vst);
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dev_dbg(pp->dev, "dsp_frame_vst=%d, dsp_frame_hst=%d\n",
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dsp_frame_vst, dsp_frame_hst);
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if (src.hactive > dst.hactive) {
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scl_hor_mode = 2;
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if (hor_down_mode == 0) {
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if ((src.hactive - 1) / (dst.hactive - 1) > 2)
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scl_h_factor = ((src.hactive - 1) << 14) /
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(dst.hactive - 1);
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else
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scl_h_factor = ((src.hactive - 2) << 14) /
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(dst.hactive - 1);
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} else {
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scl_h_factor = (dst.hactive << 16) /
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(src.hactive - 1);
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}
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dev_dbg(pp->dev, "horizontal scale down\n");
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} else if (src.hactive == dst.hactive) {
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scl_hor_mode = 0;
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scl_h_factor = 0;
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dev_dbg(pp->dev, "horizontal no scale\n");
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} else {
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scl_hor_mode = 1;
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scl_h_factor = ((src.hactive - 1) << 16) / (dst.hactive - 1);
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dev_dbg(pp->dev, "horizontal scale up\n");
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}
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if (src.vactive > dst.vactive) {
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scl_ver_mode = 2;
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if (ver_down_mode == 0) {
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if ((src.vactive - 1) / (dst.vactive - 1) > 2)
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scl_v_factor = ((src.vactive - 1) << 14) /
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(dst.vactive - 1);
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else
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scl_v_factor = ((src.vactive - 2) << 14) /
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(dst.vactive - 1);
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} else {
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scl_v_factor = (dst.vactive << 16) /
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(src.vactive - 1);
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}
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dev_dbg(pp->dev, "vertical scale down\n");
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} else if (src.vactive == dst.vactive) {
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scl_ver_mode = 0;
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scl_v_factor = 0;
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dev_dbg(pp->dev, "vertical no scale\n");
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} else {
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scl_ver_mode = 1;
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scl_v_factor = ((src.vactive - 1) << 16) / (dst.vactive - 1);
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dev_dbg(pp->dev, "vertical scale up\n");
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}
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regmap_update_bits(pp->grf, GRF_RGB_DEC_CON0,
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SW_HRES_MASK, SW_HRES(src.hactive));
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regmap_write(pp->grf, GRF_SCALER_CON0,
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SCL_VER_DOWN_MODE(ver_down_mode) |
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SCL_HOR_DOWN_MODE(hor_down_mode) |
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SCL_VER_MODE(scl_ver_mode) | SCL_HOR_MODE(scl_hor_mode));
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regmap_write(pp->grf, GRF_SCALER_CON1,
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SCL_V_FACTOR(scl_v_factor) | SCL_H_FACTOR(scl_h_factor));
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regmap_write(pp->grf, GRF_SCALER_CON2,
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DSP_FRAME_VST(dsp_frame_vst) |
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DSP_FRAME_HST(dsp_frame_hst));
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regmap_write(pp->grf, GRF_SCALER_CON3,
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DSP_HS_END(dsp_hs_end) | DSP_HTOTAL(dsp_htotal));
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regmap_write(pp->grf, GRF_SCALER_CON4,
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DSP_HACT_END(dsp_hact_end) | DSP_HACT_ST(dsp_hact_st));
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regmap_write(pp->grf, GRF_SCALER_CON5,
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DSP_VS_END(dsp_vs_end) | DSP_VTOTAL(dsp_vtotal));
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regmap_write(pp->grf, GRF_SCALER_CON6,
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DSP_VACT_END(dsp_vact_end) | DSP_VACT_ST(dsp_vact_st));
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regmap_write(pp->grf, GRF_SCALER_CON7,
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DSP_HBOR_END(dsp_hbor_end) | DSP_HBOR_ST(dsp_hbor_st));
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regmap_write(pp->grf, GRF_SCALER_CON8,
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DSP_VBOR_END(dsp_vbor_end) | DSP_VBOR_ST(dsp_vbor_st));
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}
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static void rk628_post_process_bridge_pre_enable(struct drm_bridge *bridge)
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{
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struct rk628_post_process *pp = bridge_to_pp(bridge);
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struct drm_display_mode *src = &pp->src_mode;
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struct drm_display_mode *dst = &pp->dst_mode;
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u64 dst_rate, src_rate;
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reset_control_assert(pp->rstc_decoder);
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udelay(10);
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reset_control_deassert(pp->rstc_decoder);
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udelay(10);
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clk_set_rate(pp->clk_rx_read, src->clock * 1000);
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clk_prepare_enable(pp->clk_rx_read);
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reset_control_assert(pp->rstc_clk_rx);
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udelay(10);
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reset_control_deassert(pp->rstc_clk_rx);
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udelay(10);
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src_rate = src->clock * 1000;
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dst_rate = src_rate * dst->vdisplay * dst->htotal;
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do_div(dst_rate, src->vdisplay * src->htotal);
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do_div(dst_rate, 1000);
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dst->clock = dst_rate;
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clk_set_rate(pp->sclk_vop, dst->clock * 1000);
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clk_prepare_enable(pp->sclk_vop);
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reset_control_assert(pp->rstc_vop);
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udelay(10);
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reset_control_deassert(pp->rstc_vop);
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udelay(10);
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regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_VSYNC_POL_MASK,
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SW_VSYNC_POL(pp->sync_pol));
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regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_HSYNC_POL_MASK,
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SW_HSYNC_POL(pp->sync_pol));
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rk628_post_process_scaler_init(pp, src, dst);
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}
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static void rk628_post_process_bridge_post_disable(struct drm_bridge *bridge)
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{
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}
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static void rk628_post_process_bridge_enable(struct drm_bridge *bridge)
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{
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struct rk628_post_process *pp = bridge_to_pp(bridge);
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regmap_write(pp->grf, GRF_SCALER_CON0, SCL_EN(1));
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}
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static void rk628_post_process_bridge_disable(struct drm_bridge *bridge)
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{
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struct rk628_post_process *pp = bridge_to_pp(bridge);
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regmap_write(pp->grf, GRF_SCALER_CON0, SCL_EN(0));
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clk_disable_unprepare(pp->sclk_vop);
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clk_disable_unprepare(pp->clk_rx_read);
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}
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static void rk628_post_process_bridge_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adj)
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{
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struct rk628_post_process *pp = bridge_to_pp(bridge);
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struct rk628 *rk628 = pp->parent;
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drm_mode_copy(&pp->src_mode, adj);
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if (rk628->dst_mode_valid)
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drm_mode_copy(&pp->dst_mode, &rk628->dst_mode);
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else
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drm_mode_copy(&pp->dst_mode, &pp->src_mode);
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/* hdmirx 4k-60Hz mode only support yuv420 */
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if (pp->src_mode.clock == 594000)
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regmap_write(pp->grf, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
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}
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static int rk628_post_process_bridge_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct rk628_post_process *pp = bridge_to_pp(bridge);
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struct device *dev = pp->dev;
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int ret;
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ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
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NULL, &pp->bridge);
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if (ret)
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return ret;
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ret = drm_bridge_attach(bridge->encoder, pp->bridge, bridge, flags);
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if (ret) {
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dev_err(dev, "failed to attach bridge\n");
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return ret;
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}
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return 0;
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}
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static bool
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rk628_post_process_bridge_mode_fixup(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adj)
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{
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struct rk628_post_process *pp = bridge_to_pp(bridge);
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if (pp->sync_pol == MODE_FLAG_NSYNC) {
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adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
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adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
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} else {
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adj->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
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adj->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
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}
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return true;
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}
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static const struct drm_bridge_funcs rk628_post_process_bridge_funcs = {
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.pre_enable = rk628_post_process_bridge_pre_enable,
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.post_disable = rk628_post_process_bridge_post_disable,
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.enable = rk628_post_process_bridge_enable,
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.disable = rk628_post_process_bridge_disable,
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.mode_set = rk628_post_process_bridge_mode_set,
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.mode_fixup = rk628_post_process_bridge_mode_fixup,
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.attach = rk628_post_process_bridge_attach,
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};
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/**
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* rk628_scaler_add_src_mode - add source mode for scaler
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* @rk628: parent device
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* @connector: DRM connector
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* If need scale, call the function at last of get_modes.
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*/
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int rk628_scaler_add_src_mode(struct rk628 *rk628,
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struct drm_connector *connector)
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{
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struct drm_display_mode *pmode;
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struct drm_display_mode *dst;
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if (!rk628 || !connector)
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return 0;
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if (drm_mode_validate_driver(connector->dev, &rk628->src_mode) !=
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MODE_OK)
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return 0;
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list_for_each_entry(pmode, &connector->probed_modes, head) {
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if (pmode->type & DRM_MODE_TYPE_PREFERRED) {
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drm_mode_copy(&rk628->dst_mode, pmode);
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drm_mode_copy(pmode, &rk628->src_mode);
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pmode->type |= DRM_MODE_TYPE_PREFERRED;
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rk628->dst_mode_valid = true;
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break;
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}
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}
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if (rk628->dst_mode_valid) {
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dst = drm_mode_duplicate(connector->dev, &rk628->dst_mode);
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dst->type &= ~DRM_MODE_TYPE_PREFERRED;
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drm_mode_probed_add(connector, dst);
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return 1;
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}
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return 0;
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}
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EXPORT_SYMBOL(rk628_scaler_add_src_mode);
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/**
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* rk628_mode_copy - rk628 mode copy
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* @rk628: parent device
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* @dst: dst mode
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* @src: src mode
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* Call the function at mode_set, replace drm_mode_copy.
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*/
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void rk628_mode_copy(struct rk628 *rk628, struct drm_display_mode *dst,
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const struct drm_display_mode *src)
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{
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if (rk628->dst_mode_valid)
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drm_mode_copy(dst, &rk628->dst_mode);
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else
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drm_mode_copy(dst, src);
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}
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EXPORT_SYMBOL(rk628_mode_copy);
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static int rk628_post_process_probe(struct platform_device *pdev)
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{
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struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
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struct device *dev = &pdev->dev;
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struct rk628_post_process *pp;
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u32 bus_flags;
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u32 val;
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int ret;
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if (!of_device_is_available(dev->of_node))
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return -ENODEV;
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pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
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if (!pp)
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return -ENOMEM;
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pp->dev = dev;
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pp->grf = rk628->grf;
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platform_set_drvdata(pdev, pp);
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pp->parent = rk628;
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pp->sclk_vop = devm_clk_get(dev, "sclk_vop");
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if (IS_ERR(pp->sclk_vop)) {
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ret = PTR_ERR(pp->sclk_vop);
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dev_err(dev, "failed to get sclk: %d\n", ret);
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return ret;
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}
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pp->clk_rx_read = devm_clk_get(dev, "rx_read");
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if (IS_ERR(pp->clk_rx_read)) {
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ret = PTR_ERR(pp->clk_rx_read);
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dev_err(dev, "failed to get clk_rx_read: %d\n", ret);
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return ret;
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}
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pp->rstc_decoder = of_reset_control_get(dev->of_node, "decoder");
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if (IS_ERR(pp->rstc_decoder)) {
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ret = PTR_ERR(pp->rstc_decoder);
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dev_err(dev, "failed to get decoder reset: %d\n", ret);
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return ret;
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}
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pp->rstc_clk_rx = of_reset_control_get(dev->of_node, "clk_rx");
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if (IS_ERR(pp->rstc_clk_rx)) {
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ret = PTR_ERR(pp->rstc_clk_rx);
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dev_err(dev, "failed to get clk_rx reset: %d\n", ret);
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return ret;
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}
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pp->rstc_vop = of_reset_control_get(dev->of_node, "vop");
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if (IS_ERR(pp->rstc_vop)) {
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ret = PTR_ERR(pp->rstc_vop);
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dev_err(dev, "failed to get vop reset: %d\n", ret);
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return ret;
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}
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ret = of_property_read_u32(dev->of_node, "mode-sync-pol", &val);
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if (ret < 0)
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pp->sync_pol = MODE_FLAG_PSYNC;
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else
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pp->sync_pol = (!val ? MODE_FLAG_NSYNC : MODE_FLAG_PSYNC);
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pp->base.funcs = &rk628_post_process_bridge_funcs;
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pp->base.of_node = dev->of_node;
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drm_bridge_add(&pp->base);
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of_get_drm_display_mode(dev->of_node, &rk628->src_mode, &bus_flags,
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OF_USE_NATIVE_MODE);
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return 0;
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}
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static int rk628_post_process_remove(struct platform_device *pdev)
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{
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struct rk628_post_process *pp = platform_get_drvdata(pdev);
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drm_bridge_remove(&pp->base);
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return 0;
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}
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static const struct of_device_id rk628_post_process_of_match[] = {
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{ .compatible = "rockchip,rk628-post-process", },
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{},
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};
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MODULE_DEVICE_TABLE(of, rk628_post_process_of_match);
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static struct platform_driver rk628_post_process_driver = {
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.driver = {
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.name = "rk628-post-process",
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.of_match_table = of_match_ptr(rk628_post_process_of_match),
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},
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.probe = rk628_post_process_probe,
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.remove = rk628_post_process_remove,
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};
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module_platform_driver(rk628_post_process_driver);
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MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip RK628 Post Process driver");
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MODULE_LICENSE("GPL v2");
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