// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#include <asm/bitsperlong.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/mfd/rk628.h>
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#include "rk628_combtxphy.h"
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#define REG(x) ((x) + 0x90000)
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#define COMBTXPHY_CON0 REG(0x0000)
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#define SW_TX_IDLE_MASK GENMASK(29, 20)
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#define SW_TX_IDLE(x) UPDATE(x, 29, 20)
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#define SW_TX_PD_MASK GENMASK(17, 8)
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#define SW_TX_PD(x) UPDATE(x, 17, 8)
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#define SW_BUS_WIDTH_MASK GENMASK(6, 5)
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#define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5)
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#define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5)
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#define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5)
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#define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5)
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#define SW_PD_PLL_MASK BIT(4)
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#define SW_PD_PLL BIT(4)
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#define SW_GVI_LVDS_EN_MASK BIT(3)
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#define SW_GVI_LVDS_EN BIT(3)
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#define SW_MIPI_DSI_EN_MASK BIT(2)
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#define SW_MIPI_DSI_EN BIT(2)
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#define SW_MODULEB_EN_MASK BIT(1)
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#define SW_MODULEB_EN BIT(1)
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#define SW_MODULEA_EN_MASK BIT(0)
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#define SW_MODULEA_EN BIT(0)
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#define COMBTXPHY_CON1 REG(0x0004)
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#define COMBTXPHY_CON2 REG(0x0008)
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#define COMBTXPHY_CON3 REG(0x000c)
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#define COMBTXPHY_CON4 REG(0x0010)
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#define COMBTXPHY_CON5 REG(0x0014)
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#define SW_RATE(x) UPDATE(x, 26, 24)
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#define SW_REF_DIV(x) UPDATE(x, 20, 16)
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#define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
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#define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
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#define COMBTXPHY_CON6 REG(0x0018)
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#define COMBTXPHY_CON7 REG(0x001c)
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#define SW_TX_RTERM_MASK GENMASK(22, 20)
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#define SW_TX_RTERM(x) UPDATE(x, 22, 20)
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#define SW_TX_MODE_MASK GENMASK(17, 16)
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#define SW_TX_MODE(x) UPDATE(x, 17, 16)
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#define SW_TX_CTL_CON5_MASK BIT(10)
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#define SW_TX_CTL_CON5(x) UPDATE(x, 10, 10)
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#define SW_TX_CTL_CON4_MASK GENMASK(9, 8)
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#define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8)
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#define BYPASS_095V_LDO_MASK BIT(3)
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#define BYPASS_095V_LDO(x) UPDATE(x, 3, 3)
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#define TX_COM_VOLT_ADJ_MASK GENMASK(2, 0)
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#define TX_COM_VOLT_ADJ(x) UPDATE(x, 2, 0)
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#define COMBTXPHY_CON8 REG(0x0020)
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#define COMBTXPHY_CON9 REG(0x0024)
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#define SW_DSI_FSET_EN_MASK BIT(29)
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#define SW_DSI_FSET_EN BIT(29)
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#define SW_DSI_RCAL_EN_MASK BIT(28)
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#define SW_DSI_RCAL_EN BIT(28)
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#define COMBTXPHY_CON10 REG(0x0028)
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#define TX9_CKDRV_EN BIT(9)
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#define TX8_CKDRV_EN BIT(8)
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#define TX7_CKDRV_EN BIT(7)
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#define TX6_CKDRV_EN BIT(6)
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#define TX5_CKDRV_EN BIT(5)
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#define TX4_CKDRV_EN BIT(4)
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#define TX3_CKDRV_EN BIT(3)
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#define TX2_CKDRV_EN BIT(2)
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#define TX1_CKDRV_EN BIT(1)
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#define TX0_CKDRV_EN BIT(0)
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#define COMBTXPHY_MAX_REGISTER COMBTXPHY_CON10
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struct rk628_combtxphy {
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struct device *dev;
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struct rk628 *parent;
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struct regmap *grf;
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struct regmap *regmap;
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struct clk *pclk;
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struct clk *ref_clk;
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struct reset_control *rstc;
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unsigned int flags;
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u16 frac_div;
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u8 ref_div;
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u8 fb_div;
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u8 rate_div;
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u8 division_mode;
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};
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static int rk628_combtxphy_dsi_power_on(struct rk628_combtxphy *combtxphy)
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{
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u32 val;
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int ret;
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
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SW_MIPI_DSI_EN_MASK,
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SW_BUS_WIDTH_8BIT | SW_MIPI_DSI_EN);
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if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_MODULEA_EN_MASK, SW_MODULEA_EN);
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if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_MODULEB_EN_MASK, SW_MODULEB_EN);
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regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
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SW_REF_DIV(combtxphy->ref_div - 1) |
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SW_PLL_FB_DIV(combtxphy->fb_div) |
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SW_PLL_FRAC_DIV(combtxphy->frac_div) |
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SW_RATE(combtxphy->rate_div / 2));
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_PD_PLL, 0);
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ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS,
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val, val & DPHY_PHYLOCK, 0, 1000);
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if (ret < 0) {
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dev_err(combtxphy->dev, "phy is not lock\n");
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return ret;
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}
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON9,
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SW_DSI_FSET_EN_MASK | SW_DSI_RCAL_EN_MASK,
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SW_DSI_FSET_EN | SW_DSI_RCAL_EN);
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usleep_range(200, 400);
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return 0;
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}
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static int rk628_combtxphy_lvds_power_on(struct rk628_combtxphy *combtxphy)
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{
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u32 val;
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int ret;
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/* Adjust terminal resistance 133 ohm, bypass 0.95v ldo for driver. */
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON7,
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SW_TX_RTERM_MASK | SW_TX_MODE_MASK |
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BYPASS_095V_LDO_MASK | TX_COM_VOLT_ADJ_MASK,
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SW_TX_RTERM(6) | SW_TX_MODE(3) |
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BYPASS_095V_LDO(1) | TX_COM_VOLT_ADJ(0));
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regmap_write(combtxphy->regmap, COMBTXPHY_CON10,
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TX7_CKDRV_EN | TX2_CKDRV_EN);
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
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SW_MIPI_DSI_EN_MASK,
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SW_BUS_WIDTH_7BIT | SW_GVI_LVDS_EN);
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if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_MODULEA_EN_MASK, SW_MODULEA_EN);
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if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_MODULEB_EN_MASK, SW_MODULEB_EN);
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regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
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SW_REF_DIV(combtxphy->ref_div - 1) |
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SW_PLL_FB_DIV(combtxphy->fb_div) |
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SW_PLL_FRAC_DIV(combtxphy->frac_div) |
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SW_RATE(combtxphy->rate_div / 2));
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_PD_PLL, 0);
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ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS,
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val, val & DPHY_PHYLOCK, 0, 1000);
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if (ret < 0) {
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dev_info(combtxphy->dev, "phy is not lock\n");
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return ret;
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}
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usleep_range(100, 200);
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_TX_IDLE_MASK | SW_TX_PD_MASK, 0);
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return 0;
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}
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static int rk628_combtxphy_gvi_power_on(struct rk628_combtxphy *combtxphy)
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{
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int ref_div = 0;
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if (combtxphy->ref_div % 2) {
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ref_div = combtxphy->ref_div - 1;
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} else {
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ref_div = BIT(4);
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ref_div |= combtxphy->ref_div / 2 - 1;
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}
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regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
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SW_REF_DIV(ref_div) |
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SW_PLL_FB_DIV(combtxphy->fb_div) |
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SW_PLL_FRAC_DIV(combtxphy->frac_div) |
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SW_RATE(combtxphy->rate_div / 2));
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
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SW_MIPI_DSI_EN_MASK |
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SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
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SW_BUS_WIDTH_10BIT | SW_GVI_LVDS_EN |
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SW_MODULEB_EN | SW_MODULEA_EN);
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_PD_PLL | SW_TX_PD_MASK, 0);
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usleep_range(100, 200);
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_TX_IDLE_MASK, 0);
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return 0;
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}
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int rk628_combtxphy_set_gvi_division_mode(struct phy *phy, u8 mode)
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{
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struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
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combtxphy->division_mode = mode;
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return 0;
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}
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EXPORT_SYMBOL(rk628_combtxphy_set_gvi_division_mode);
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static int rk628_combtxphy_power_on(struct phy *phy)
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{
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struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
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enum phy_mode mode = phy_get_mode(phy);
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clk_prepare_enable(combtxphy->pclk);
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reset_control_assert(combtxphy->rstc);
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udelay(10);
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reset_control_deassert(combtxphy->rstc);
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udelay(10);
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regcache_mark_dirty(combtxphy->regmap);
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regcache_sync(combtxphy->regmap);
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK,
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SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
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switch (mode) {
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case PHY_MODE_MIPI_DPHY:
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regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
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SW_TXPHY_REFCLK_SEL_MASK,
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SW_TXPHY_REFCLK_SEL(0));
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return rk628_combtxphy_dsi_power_on(combtxphy);
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case PHY_MODE_LVDS:
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regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
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SW_TXPHY_REFCLK_SEL_MASK,
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SW_TXPHY_REFCLK_SEL(1));
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return rk628_combtxphy_lvds_power_on(combtxphy);
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default:
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regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
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SW_TXPHY_REFCLK_SEL_MASK,
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SW_TXPHY_REFCLK_SEL(2));
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return rk628_combtxphy_gvi_power_on(combtxphy);
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}
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return 0;
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}
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static int rk628_combtxphy_power_off(struct phy *phy)
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{
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struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
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regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
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SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK |
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SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
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SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
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clk_disable_unprepare(combtxphy->pclk);
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return 0;
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}
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static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode,
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int submode)
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{
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struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
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unsigned int bus_width = phy_get_bus_width(phy);
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unsigned int frac_rate, fin = 24;
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unsigned long fvco, fpfd;
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switch (mode) {
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case PHY_MODE_MIPI_DPHY:
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{
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unsigned int fhsc = bus_width >> 8;
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unsigned int flags = bus_width & 0xff;
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fhsc = fin * (fhsc / fin);
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if (fhsc < 80 || fhsc > 1500)
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return -EINVAL;
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else if (fhsc < 375)
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combtxphy->rate_div = 4;
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else if (fhsc < 750)
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combtxphy->rate_div = 2;
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else
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combtxphy->rate_div = 1;
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combtxphy->flags = flags;
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fvco = fhsc * 2 * combtxphy->rate_div;
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combtxphy->ref_div = 1;
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combtxphy->fb_div = fvco / 8 / fin;
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frac_rate = fvco - (fin * 8 * combtxphy->fb_div);
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if (frac_rate) {
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frac_rate <<= 10;
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frac_rate /= fin * 8;
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combtxphy->frac_div = frac_rate;
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} else {
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combtxphy->frac_div = 0;
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}
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fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div);
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fvco *= 8;
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fvco = DIV_ROUND_UP(fvco, 1024 * combtxphy->ref_div);
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fhsc = fvco / 2 / combtxphy->rate_div;
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phy_set_bus_width(phy, fhsc);
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break;
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}
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case PHY_MODE_LVDS:
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{
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unsigned int flags = bus_width & 0xff;
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unsigned int rate = (bus_width >> 8) * 7;
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combtxphy->flags = flags;
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combtxphy->ref_div = 1;
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combtxphy->fb_div = 14;
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combtxphy->frac_div = 0;
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if (rate < 500)
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combtxphy->rate_div = 4;
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else if (rate < 1000)
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combtxphy->rate_div = 2;
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else
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combtxphy->rate_div = 1;
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break;
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}
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default:
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{
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unsigned int i, delta_freq, best_delta_freq, fb_div;
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unsigned long ref_clk;
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unsigned long long pre_clk;
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if (bus_width < 500000 || bus_width > 4000000)
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return -EINVAL;
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else if (bus_width < 1000000)
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combtxphy->rate_div = 4;
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else if (bus_width < 2000000)
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combtxphy->rate_div = 2;
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else
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combtxphy->rate_div = 1;
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fvco = bus_width * combtxphy->rate_div;
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ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */
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if (combtxphy->division_mode)
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ref_clk /= 2;
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if (!ref_clk)
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return -EINVAL;
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/*
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* the reference clock at PFD(FPFD = ref_clk / ref_div) about
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* 25MHz is recommende, FPFD must range from 16MHz to 35MHz,
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* here to find the best rev_div.
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*/
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best_delta_freq = ref_clk;
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for (i = 1; i <= 32; i++) {
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fpfd = ref_clk / i;
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delta_freq = abs(fpfd - 25000);
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if (delta_freq < best_delta_freq) {
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best_delta_freq = delta_freq;
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combtxphy->ref_div = i;
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}
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}
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/*
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* ref_clk / ref_div * 8 * fb_div = FVCO
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*/
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pre_clk = (unsigned long long)fvco / 8 * combtxphy->ref_div * 1024;
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do_div(pre_clk, ref_clk);
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fb_div = pre_clk / 1024;
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/*
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* get the actually frequence
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*/
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bus_width = ref_clk / combtxphy->ref_div * 8;
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bus_width *= fb_div;
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bus_width /= combtxphy->rate_div;
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combtxphy->frac_div = 0;
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combtxphy->fb_div = fb_div;
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phy_set_bus_width(phy, bus_width);
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break;
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}
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}
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return 0;
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}
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static const struct phy_ops rk628_combtxphy_ops = {
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.set_mode = rk628_combtxphy_set_mode,
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.power_on = rk628_combtxphy_power_on,
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.power_off = rk628_combtxphy_power_off,
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.owner = THIS_MODULE,
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};
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static const struct regmap_range rk628_combtxphy_readable_ranges[] = {
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regmap_reg_range(COMBTXPHY_CON0, COMBTXPHY_CON10),
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};
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static const struct regmap_access_table rk628_combtxphy_readable_table = {
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.yes_ranges = rk628_combtxphy_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_combtxphy_readable_ranges),
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};
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static const struct regmap_config rk628_combtxphy_regmap_cfg = {
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.name = "combtxphy",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.cache_type = REGCACHE_RBTREE,
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.max_register = COMBTXPHY_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_combtxphy_readable_table,
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};
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static int rk628_combtxphy_probe(struct platform_device *pdev)
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{
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struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
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struct device *dev = &pdev->dev;
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struct rk628_combtxphy *combtxphy;
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struct phy_provider *phy_provider;
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struct phy *phy;
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int ret;
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combtxphy = devm_kzalloc(dev, sizeof(*combtxphy), GFP_KERNEL);
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if (!combtxphy)
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return -ENOMEM;
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combtxphy->dev = dev;
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combtxphy->parent = rk628;
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combtxphy->grf = rk628->grf;
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platform_set_drvdata(pdev, combtxphy);
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combtxphy->pclk = devm_clk_get(dev, "pclk");
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if (IS_ERR(combtxphy->pclk))
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return PTR_ERR(combtxphy->pclk);
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combtxphy->ref_clk = devm_clk_get(dev, "ref_clk");
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if (IS_ERR(combtxphy->ref_clk)) {
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dev_err(dev, "fail to get ref clk\n");
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return PTR_ERR(combtxphy->ref_clk);
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}
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combtxphy->rstc = of_reset_control_get(dev->of_node, NULL);
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if (IS_ERR(combtxphy->rstc)) {
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ret = PTR_ERR(combtxphy->rstc);
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dev_err(dev, "failed to get reset control: %d\n", ret);
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return ret;
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}
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combtxphy->regmap = devm_regmap_init_i2c(rk628->client,
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&rk628_combtxphy_regmap_cfg);
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if (IS_ERR(combtxphy->regmap)) {
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ret = PTR_ERR(combtxphy->regmap);
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dev_err(dev, "failed to allocate register map: %d\n", ret);
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return ret;
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}
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phy = devm_phy_create(dev, NULL, &rk628_combtxphy_ops);
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if (IS_ERR(phy)) {
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ret = PTR_ERR(phy);
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dev_err(dev, "failed to create phy: %d\n", ret);
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return ret;
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}
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phy_set_drvdata(phy, combtxphy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider)) {
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ret = PTR_ERR(phy_provider);
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dev_err(dev, "failed to register phy provider: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct of_device_id rk628_combtxphy_of_match[] = {
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{ .compatible = "rockchip,rk628-combtxphy", },
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{}
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};
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MODULE_DEVICE_TABLE(of, rk628_combtxphy_of_match);
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static struct platform_driver rk628_combtxphy_driver = {
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.driver = {
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.name = "rk628-combtxphy",
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.of_match_table = of_match_ptr(rk628_combtxphy_of_match),
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},
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.probe = rk628_combtxphy_probe,
|
};
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module_platform_driver(rk628_combtxphy_driver);
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MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip RK628 GVI/LVDS/MIPI Combo TX PHY driver");
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MODULE_LICENSE("GPL v2");
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