/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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* Author: Sugar Zhang <sugar.zhang@rock-chips.com>
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*/
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#ifndef DW_HDMI_QP_AUDIO_H
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#define DW_HDMI_QP_AUDIO_H
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struct dw_hdmi_qp;
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struct dw_hdmi_qp_audio_data {
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phys_addr_t phys;
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void __iomem *base;
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int irq;
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struct dw_hdmi_qp *hdmi;
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u8 *eld;
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};
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struct dw_hdmi_qp_i2s_audio_data {
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struct dw_hdmi_qp *hdmi;
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u8 *eld;
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void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset);
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u32 (*read)(struct dw_hdmi_qp *hdmi, int offset);
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void (*mod)(struct dw_hdmi_qp *hdmi, u32 val, u32 mask, u32 reg);
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};
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#endif
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