/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef SMU_11_0_PPTABLE_H
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#define SMU_11_0_PPTABLE_H
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#define SMU_11_0_TABLE_FORMAT_REVISION 12
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//// POWERPLAYTABLE::ulPlatformCaps
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#define SMU_11_0_PP_PLATFORM_CAP_POWERPLAY 0x1
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#define SMU_11_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2
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#define SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC 0x4
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#define SMU_11_0_PP_PLATFORM_CAP_BACO 0x8
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#define SMU_11_0_PP_PLATFORM_CAP_MACO 0x10
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#define SMU_11_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20
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// SMU_11_0_PP_THERMALCONTROLLER - Thermal Controller Type
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#define SMU_11_0_PP_THERMALCONTROLLER_NONE 0
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#define SMU_11_0_PP_OVERDRIVE_VERSION 0x0800
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#define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION 0x0100
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enum SMU_11_0_ODFEATURE_CAP {
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SMU_11_0_ODCAP_GFXCLK_LIMITS = 0,
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SMU_11_0_ODCAP_GFXCLK_CURVE,
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SMU_11_0_ODCAP_UCLK_MAX,
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SMU_11_0_ODCAP_POWER_LIMIT,
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SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,
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SMU_11_0_ODCAP_FAN_SPEED_MIN,
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SMU_11_0_ODCAP_TEMPERATURE_FAN,
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SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,
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SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,
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SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,
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SMU_11_0_ODCAP_AUTO_UV_ENGINE,
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SMU_11_0_ODCAP_AUTO_OC_ENGINE,
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SMU_11_0_ODCAP_AUTO_OC_MEMORY,
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SMU_11_0_ODCAP_FAN_CURVE,
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SMU_11_0_ODCAP_COUNT,
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};
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enum SMU_11_0_ODFEATURE_ID {
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SMU_11_0_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_11_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature
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SMU_11_0_ODFEATURE_GFXCLK_CURVE = 1 << SMU_11_0_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature
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SMU_11_0_ODFEATURE_UCLK_MAX = 1 << SMU_11_0_ODCAP_UCLK_MAX, //UCLK Limit feature
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SMU_11_0_ODFEATURE_POWER_LIMIT = 1 << SMU_11_0_ODCAP_POWER_LIMIT, //Power Limit feature
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SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature
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SMU_11_0_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_11_0_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature
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SMU_11_0_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_11_0_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature
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SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_11_0_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature
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SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_11_0_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature
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SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature
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SMU_11_0_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_11_0_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature
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SMU_11_0_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_11_0_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature
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SMU_11_0_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_11_0_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature
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SMU_11_0_ODFEATURE_FAN_CURVE = 1 << SMU_11_0_ODCAP_FAN_CURVE, //Fan Curve feature
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SMU_11_0_ODFEATURE_COUNT = 14,
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};
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#define SMU_11_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
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enum SMU_11_0_ODSETTING_ID {
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SMU_11_0_ODSETTING_GFXCLKFMAX = 0,
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SMU_11_0_ODSETTING_GFXCLKFMIN,
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SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
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SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
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SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
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SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
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SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
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SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
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SMU_11_0_ODSETTING_UCLKFMAX,
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SMU_11_0_ODSETTING_POWERPERCENTAGE,
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SMU_11_0_ODSETTING_FANRPMMIN,
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SMU_11_0_ODSETTING_FANRPMACOUSTICLIMIT,
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SMU_11_0_ODSETTING_FANTARGETTEMPERATURE,
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SMU_11_0_ODSETTING_OPERATINGTEMPMAX,
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SMU_11_0_ODSETTING_ACTIMING,
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SMU_11_0_ODSETTING_FAN_ZERO_RPM_CONTROL,
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SMU_11_0_ODSETTING_AUTOUVENGINE,
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SMU_11_0_ODSETTING_AUTOOCENGINE,
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SMU_11_0_ODSETTING_AUTOOCMEMORY,
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SMU_11_0_ODSETTING_COUNT,
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};
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#define SMU_11_0_MAX_ODSETTING 32 //Maximum Number of ODSettings
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struct smu_11_0_overdrive_table
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{
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uint8_t revision; //Revision = SMU_11_0_PP_OVERDRIVE_VERSION
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uint8_t reserve[3]; //Zero filled field reserved for future use
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uint32_t feature_count; //Total number of supported features
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uint32_t setting_count; //Total number of supported settings
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uint8_t cap[SMU_11_0_MAX_ODFEATURE]; //OD feature support flags
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uint32_t max[SMU_11_0_MAX_ODSETTING]; //default maximum settings
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uint32_t min[SMU_11_0_MAX_ODSETTING]; //default minimum settings
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} __attribute__((packed));
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enum SMU_11_0_PPCLOCK_ID {
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SMU_11_0_PPCLOCK_GFXCLK = 0,
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SMU_11_0_PPCLOCK_VCLK,
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SMU_11_0_PPCLOCK_DCLK,
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SMU_11_0_PPCLOCK_ECLK,
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SMU_11_0_PPCLOCK_SOCCLK,
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SMU_11_0_PPCLOCK_UCLK,
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SMU_11_0_PPCLOCK_DCEFCLK,
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SMU_11_0_PPCLOCK_DISPCLK,
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SMU_11_0_PPCLOCK_PIXCLK,
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SMU_11_0_PPCLOCK_PHYCLK,
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SMU_11_0_PPCLOCK_COUNT,
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};
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#define SMU_11_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
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struct smu_11_0_power_saving_clock_table
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{
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uint8_t revision; //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION
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uint8_t reserve[3]; //Zero filled field reserved for future use
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uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
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uint32_t max[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz
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uint32_t min[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz
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} __attribute__((packed));
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struct smu_11_0_powerplay_table
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{
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struct atom_common_table_header header;
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uint8_t table_revision;
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uint16_t table_size; //Driver portion table size. The offset to smc_pptable including header size
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uint32_t golden_pp_id;
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uint32_t golden_revision;
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uint16_t format_id;
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uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps
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uint8_t thermal_controller_type; //one of SMU_11_0_PP_THERMALCONTROLLER
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uint16_t small_power_limit1;
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uint16_t small_power_limit2;
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uint16_t boost_power_limit;
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uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning.
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uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning.
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uint16_t software_shutdown_temp;
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uint16_t reserve[6]; //Zero filled field reserved for future use
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struct smu_11_0_power_saving_clock_table power_saving_clock;
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struct smu_11_0_overdrive_table overdrive_table;
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#ifndef SMU_11_0_PARTIAL_PPTABLE
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PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
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#endif
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} __attribute__((packed));
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#endif
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