/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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// CZ Ucode Loading Definitions
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#ifndef SMU_UCODE_XFER_CZ_H
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#define SMU_UCODE_XFER_CZ_H
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#define NUM_JOBLIST_ENTRIES 32
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#define TASK_TYPE_NO_ACTION 0
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#define TASK_TYPE_UCODE_LOAD 1
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#define TASK_TYPE_UCODE_SAVE 2
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#define TASK_TYPE_REG_LOAD 3
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#define TASK_TYPE_REG_SAVE 4
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#define TASK_TYPE_INITIALIZE 5
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#define TASK_ARG_REG_SMCIND 0
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#define TASK_ARG_REG_MMIO 1
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#define TASK_ARG_REG_FCH 2
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#define TASK_ARG_REG_UNB 3
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#define TASK_ARG_INIT_MM_PWR_LOG 0
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#define TASK_ARG_INIT_CLK_TABLE 1
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#define JOB_GFX_SAVE 0
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#define JOB_GFX_RESTORE 1
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#define JOB_FCH_SAVE 2
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#define JOB_FCH_RESTORE 3
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#define JOB_UNB_SAVE 4
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#define JOB_UNB_RESTORE 5
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#define JOB_GMC_SAVE 6
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#define JOB_GMC_RESTORE 7
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#define JOB_GNB_SAVE 8
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#define JOB_GNB_RESTORE 9
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#define IGNORE_JOB 0xff
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#define END_OF_TASK_LIST (uint16_t)0xffff
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// Size of DRAM regions (in bytes) requested by SMU:
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#define SMU_DRAM_REQ_MM_PWR_LOG 48
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#define UCODE_ID_SDMA0 0
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#define UCODE_ID_SDMA1 1
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#define UCODE_ID_CP_CE 2
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#define UCODE_ID_CP_PFP 3
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#define UCODE_ID_CP_ME 4
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#define UCODE_ID_CP_MEC_JT1 5
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#define UCODE_ID_CP_MEC_JT2 6
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#define UCODE_ID_GMCON_RENG 7
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#define UCODE_ID_RLC_G 8
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#define UCODE_ID_RLC_SCRATCH 9
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#define UCODE_ID_RLC_SRM_ARAM 10
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#define UCODE_ID_RLC_SRM_DRAM 11
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#define UCODE_ID_DMCU_ERAM 12
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#define UCODE_ID_DMCU_IRAM 13
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#define UCODE_ID_SDMA0_MASK 0x00000001
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#define UCODE_ID_SDMA1_MASK 0x00000002
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#define UCODE_ID_CP_CE_MASK 0x00000004
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#define UCODE_ID_CP_PFP_MASK 0x00000008
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#define UCODE_ID_CP_ME_MASK 0x00000010
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#define UCODE_ID_CP_MEC_JT1_MASK 0x00000020
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#define UCODE_ID_CP_MEC_JT2_MASK 0x00000040
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#define UCODE_ID_GMCON_RENG_MASK 0x00000080
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#define UCODE_ID_RLC_G_MASK 0x00000100
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#define UCODE_ID_RLC_SCRATCH_MASK 0x00000200
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#define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400
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#define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800
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#define UCODE_ID_DMCU_ERAM_MASK 0x00001000
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#define UCODE_ID_DMCU_IRAM_MASK 0x00002000
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#define UCODE_ID_SDMA0_SIZE_BYTE 10368
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#define UCODE_ID_SDMA1_SIZE_BYTE 10368
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#define UCODE_ID_CP_CE_SIZE_BYTE 8576
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#define UCODE_ID_CP_PFP_SIZE_BYTE 16768
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#define UCODE_ID_CP_ME_SIZE_BYTE 16768
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#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384
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#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384
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#define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096
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#define UCODE_ID_RLC_G_SIZE_BYTE 2048
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#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132
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#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192
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#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096
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#define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576
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#define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024
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#define NUM_UCODES 14
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typedef struct {
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uint32_t high;
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uint32_t low;
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} data_64_t;
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struct SMU_Task {
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uint8_t type;
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uint8_t arg;
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uint16_t next;
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data_64_t addr;
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uint32_t size_bytes;
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};
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typedef struct SMU_Task SMU_Task;
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struct TOC {
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uint8_t JobList[NUM_JOBLIST_ENTRIES];
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SMU_Task tasks[1];
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};
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// META DATA COMMAND Definitions
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#define METADATA_CMD_MODE0 0x00000103
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#define METADATA_CMD_MODE1 0x00000113
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#define METADATA_CMD_MODE2 0x00000123
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#define METADATA_CMD_MODE3 0x00000133
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#define METADATA_CMD_DELAY 0x00000203
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#define METADATA_CMD_CHNG_REGSPACE 0x00000303
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#define METADATA_PERFORM_ON_SAVE 0x00001000
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#define METADATA_PERFORM_ON_LOAD 0x00002000
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#define METADATA_CMD_ARG_MASK 0xFFFF0000
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#define METADATA_CMD_ARG_SHIFT 16
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// Simple register addr/data fields
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struct SMU_MetaData_Mode0 {
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uint32_t register_address;
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uint32_t register_data;
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};
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typedef struct SMU_MetaData_Mode0 SMU_MetaData_Mode0;
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// Register addr/data with mask
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struct SMU_MetaData_Mode1 {
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uint32_t register_address;
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uint32_t register_mask;
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uint32_t register_data;
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};
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typedef struct SMU_MetaData_Mode1 SMU_MetaData_Mode1;
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struct SMU_MetaData_Mode2 {
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uint32_t register_address;
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uint32_t register_mask;
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uint32_t target_value;
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};
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typedef struct SMU_MetaData_Mode2 SMU_MetaData_Mode2;
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// Always write data (even on a save operation)
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struct SMU_MetaData_Mode3 {
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uint32_t register_address;
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uint32_t register_mask;
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uint32_t register_data;
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};
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typedef struct SMU_MetaData_Mode3 SMU_MetaData_Mode3;
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#endif
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