/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_PM_H__
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#define __AMDGPU_PM_H__
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struct cg_flag_name
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{
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u32 flag;
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const char *name;
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};
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enum amdgpu_device_attr_flags {
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ATTR_FLAG_BASIC = (1 << 0),
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ATTR_FLAG_ONEVF = (1 << 16),
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};
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#define ATTR_FLAG_TYPE_MASK (0x0000ffff)
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#define ATTR_FLAG_MODE_MASK (0xffff0000)
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#define ATTR_FLAG_MASK_ALL (0xffffffff)
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enum amdgpu_device_attr_states {
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ATTR_STATE_UNSUPPORTED = 0,
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ATTR_STATE_SUPPORTED,
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};
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struct amdgpu_device_attr {
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struct device_attribute dev_attr;
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enum amdgpu_device_attr_flags flags;
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int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
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uint32_t mask, enum amdgpu_device_attr_states *states);
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};
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struct amdgpu_device_attr_entry {
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struct list_head entry;
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struct amdgpu_device_attr *attr;
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};
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#define to_amdgpu_device_attr(_dev_attr) \
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container_of(_dev_attr, struct amdgpu_device_attr, dev_attr)
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#define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \
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{ .dev_attr = __ATTR(_name, _mode, _show, _store), \
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.flags = _flags, \
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##__VA_ARGS__, }
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#define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \
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__AMDGPU_DEVICE_ATTR(_name, _mode, \
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amdgpu_get_##_name, amdgpu_set_##_name, \
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_flags, ##__VA_ARGS__)
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#define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \
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AMDGPU_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, \
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_flags, ##__VA_ARGS__)
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#define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \
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__AMDGPU_DEVICE_ATTR(_name, S_IRUGO, \
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amdgpu_get_##_name, NULL, \
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_flags, ##__VA_ARGS__)
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int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
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int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev);
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void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
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void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev);
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int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
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#endif
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