/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _dpcs_2_1_0_OFFSET_HEADER
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#define _dpcs_2_1_0_OFFSET_HEADER
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// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
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// base address: 0x0
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#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
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#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
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#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
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#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
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#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
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#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
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#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
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#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
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#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
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#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
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#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e
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#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
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// base address: 0x0
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#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
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#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
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#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
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#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
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#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
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#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
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#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
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#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
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#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
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#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937
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#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_SPARE 0x2938
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#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939
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#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c
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#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d
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#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
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#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
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#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
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#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
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#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
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#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954
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#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955
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#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956
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#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a
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#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2
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#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 0x295b
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#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
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// addressBlock: dpcssys_dpcssys_cr0_dispdec
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// base address: 0x0
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#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
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#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
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#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
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#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
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// base address: 0x360
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#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00
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#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
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#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01
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#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2
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#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02
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#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2
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#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03
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#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04
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#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
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#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05
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#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x2a06
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#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
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// base address: 0x360
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#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08
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#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09
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#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a
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#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b
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#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c
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#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2
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#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d
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#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2
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#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e
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#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f
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#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10
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#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11
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#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14
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#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15
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#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27
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#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28
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#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29
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#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a
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#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b
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#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c
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#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d
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#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e
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#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32
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#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2
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#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 0x2a33
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#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
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// addressBlock: dpcssys_dpcssys_cr1_dispdec
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// base address: 0x360
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#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
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#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
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#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
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#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
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// base address: 0x6c0
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#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x2ad8
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#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
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#define mmDPCSTX2_DPCSTX_TX_CNTL 0x2ad9
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#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX 2
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#define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x2ada
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#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX 2
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#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0x2adb
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#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x2adc
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#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
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#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add
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#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x2ade
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#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
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// base address: 0x6c0
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#define mmRDPCSTX2_RDPCSTX_CNTL 0x2ae0
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#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1
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#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2
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#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0x2ae3
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#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4
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#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2
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#define mmRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5
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#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2
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#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6
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#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7
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#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_SPARE 0x2ae8
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#define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_CNTL2 0x2ae9
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#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec
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#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed
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#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff
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#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00
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#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01
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#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02
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#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03
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#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04
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#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05
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#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06
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#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a
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#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2
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#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 0x2b0b
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#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
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// addressBlock: dpcssys_dpcssys_cr2_dispdec
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// base address: 0x6c0
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#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
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#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2
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#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
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#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
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// base address: 0xa20
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#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x2bb0
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#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
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#define mmDPCSTX3_DPCSTX_TX_CNTL 0x2bb1
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#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX 2
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#define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x2bb2
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#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX 2
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#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0x2bb3
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#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x2bb4
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#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
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#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5
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#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x2bb6
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#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
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// base address: 0xa20
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#define mmRDPCSTX3_RDPCSTX_CNTL 0x2bb8
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#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9
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#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba
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#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0x2bbb
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#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc
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#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2
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#define mmRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd
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#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2
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#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe
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#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf
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#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_SPARE 0x2bc0
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#define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_CNTL2 0x2bc1
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#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4
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#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5
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#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7
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#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8
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#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9
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#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda
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#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb
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#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc
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#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd
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#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde
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#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2
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#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2
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#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 0x2be3
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#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
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// addressBlock: dpcssys_dpcssys_cr3_dispdec
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// base address: 0xa20
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#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc
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#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2
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#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd
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#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
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// base address: 0xd80
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#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x2c88
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#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
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#define mmDPCSTX4_DPCSTX_TX_CNTL 0x2c89
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#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX 2
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#define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x2c8a
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#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX 2
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#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0x2c8b
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#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x2c8c
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#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
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#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d
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#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x2c8e
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#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
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// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
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// base address: 0xd80
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#define mmRDPCSTX4_RDPCSTX_CNTL 0x2c90
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#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91
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#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92
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#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0x2c93
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#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
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#define mmRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94
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#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2
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#define mmRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95
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#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2
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#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96
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#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_SCRATCH 0x2c97
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#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_SPARE 0x2c98
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#define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_CNTL2 0x2c99
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#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c
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#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d
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#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf
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#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0
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#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1
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#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2
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#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3
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#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4
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#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5
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#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6
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#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15 0x2cb8
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16 0x2cb9
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17 0x2cba
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#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX 2
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#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2 0x2cbb
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#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2
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// addressBlock: dpcssys_dpcssys_cr4_dispdec
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// base address: 0xd80
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#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94
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#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2
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#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95
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#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2
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#endif
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