/*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _dce_12_0_OFFSET_HEADER
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#define _dce_12_0_OFFSET_HEADER
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// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
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// base address: 0x48
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#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
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#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
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// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
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// base address: 0x4c
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#define mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
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#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
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// addressBlock: dce_dc_dc_perfmon0_dispdec
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// base address: 0x0
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#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020
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#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
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#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022
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#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_CNTL 0x0023
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#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_CNTL2 0x0024
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#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025
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#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026
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#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_HI 0x0027
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#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_LOW 0x0028
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#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon13_dispdec
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// base address: 0x30
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e
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#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CNTL 0x002f
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#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CNTL2 0x0030
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#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031
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#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032
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#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_HI 0x0033
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#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_LOW 0x0034
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#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dc_displaypllregs_dispdec
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// base address: 0x0
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#define mmPPLL_VREG_CFG 0x0038
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#define mmPPLL_VREG_CFG_BASE_IDX 2
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#define mmPPLL_MODE_CNTL 0x0039
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#define mmPPLL_MODE_CNTL_BASE_IDX 2
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#define mmPPLL_FREQ_CTRL0 0x003a
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#define mmPPLL_FREQ_CTRL0_BASE_IDX 2
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#define mmPPLL_FREQ_CTRL1 0x003b
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#define mmPPLL_FREQ_CTRL1_BASE_IDX 2
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#define mmPPLL_FREQ_CTRL2 0x003c
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#define mmPPLL_FREQ_CTRL2_BASE_IDX 2
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#define mmPPLL_FREQ_CTRL3 0x003d
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#define mmPPLL_FREQ_CTRL3_BASE_IDX 2
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#define mmPPLL_BW_CTRL_COARSE 0x003e
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#define mmPPLL_BW_CTRL_COARSE_BASE_IDX 2
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#define mmPPLL_BW_CTRL_FINE 0x0040
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#define mmPPLL_BW_CTRL_FINE_BASE_IDX 2
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#define mmPPLL_CAL_CTRL 0x0041
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#define mmPPLL_CAL_CTRL_BASE_IDX 2
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#define mmPPLL_LOOP_CTRL 0x0042
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#define mmPPLL_LOOP_CTRL_BASE_IDX 2
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#define mmPPLL_REFCLK_CNTL 0x0050
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#define mmPPLL_REFCLK_CNTL_BASE_IDX 2
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#define mmPPLL_CLKOUT_CNTL 0x0051
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#define mmPPLL_CLKOUT_CNTL_BASE_IDX 2
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#define mmPPLL_DFT_CNTL 0x0052
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#define mmPPLL_DFT_CNTL_BASE_IDX 2
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#define mmPPLL_ANALOG_CNTL 0x0053
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#define mmPPLL_ANALOG_CNTL_BASE_IDX 2
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#define mmPPLL_POSTDIV 0x0054
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#define mmPPLL_POSTDIV_BASE_IDX 2
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#define mmPPLL_OBSERVE0 0x0059
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#define mmPPLL_OBSERVE0_BASE_IDX 2
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#define mmPPLL_OBSERVE1 0x005a
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#define mmPPLL_OBSERVE1_BASE_IDX 2
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#define mmPPLL_UPDATE_CNTL 0x005c
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#define mmPPLL_UPDATE_CNTL_BASE_IDX 2
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#define mmPPLL_OBSERVE0_OUT 0x005d
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#define mmPPLL_OBSERVE0_OUT_BASE_IDX 2
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// addressBlock: dce_dc_dccg_pll0_dispdec
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// base address: 0x0
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#define mmPLL_MACRO_CNTL_RESERVED0 0x0038
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#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED1 0x0039
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#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED2 0x003a
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#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED3 0x003b
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#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED4 0x003c
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#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED5 0x003d
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#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED6 0x003e
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#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED7 0x003f
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#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED8 0x0040
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#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED9 0x0041
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#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED10 0x0042
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#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED11 0x0043
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#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED12 0x0044
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#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED13 0x0045
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#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED14 0x0046
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#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED15 0x0047
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#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED16 0x0048
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#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED17 0x0049
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#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED18 0x004a
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#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED19 0x004b
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#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED20 0x004c
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#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED21 0x004d
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#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED22 0x004e
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#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED23 0x004f
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#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED24 0x0050
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#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED25 0x0051
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#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED26 0x0052
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#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED27 0x0053
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#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED28 0x0054
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#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED29 0x0055
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#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED30 0x0056
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#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED31 0x0057
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#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED32 0x0058
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#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED33 0x0059
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#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED34 0x005a
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#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED35 0x005b
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#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED36 0x005c
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#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED37 0x005d
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#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED38 0x005e
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#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED39 0x005f
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#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED40 0x0060
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#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED41 0x0061
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#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon1_dispdec
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// base address: 0x598
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#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x0186
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#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x0187
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#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x0188
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#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_CNTL 0x0189
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#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_CNTL2 0x018a
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#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x018b
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#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x018c
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#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_HI 0x018d
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#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_LOW 0x018e
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#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_mcif_wb0_dispdec
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// base address: 0x0
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x0272
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x0273
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x0274
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x0275
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#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x0276
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#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x0277
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#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x0278
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#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x0279
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#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x027a
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#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x027b
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#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x027c
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#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x027d
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#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x027e
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#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x027f
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#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x0282
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0283
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x0284
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0285
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x0286
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0287
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x0288
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0289
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x028a
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x028b
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x028c
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x028d
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x028e
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x028f
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x0290
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0291
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x0292
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0293
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#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x0294
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#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x0295
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#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x0296
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#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x0297
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#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x0298
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#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x0299
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#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x029b
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#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x029c
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#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
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// addressBlock: dce_dc_mcif_wb1_dispdec
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// base address: 0x100
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02b4
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02b5
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#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02b6
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#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02b7
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#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02b8
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#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02b9
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#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02ba
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#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02bb
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#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02bc
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#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02bd
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#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02be
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#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02bf
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#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x02c2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x02c4
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x02c6
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x02c8
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x02ca
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x02cc
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x02ce
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x02d0
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
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#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
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#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x02d5
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#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
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#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x02d7
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#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
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#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x02d9
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#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x02db
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#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
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#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
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// addressBlock: dce_dc_mcif_wb2_dispdec
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// base address: 0x200
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#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
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#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
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#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x02f4
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#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x02f5
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#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x02f6
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#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x02f7
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#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x02f8
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#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x02f9
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#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x02fa
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#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x02fb
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#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x02fc
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#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x02fd
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#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x02fe
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#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x02ff
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#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x0302
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#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
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#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x0304
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#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
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#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x0306
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#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
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#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x0308
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#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
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#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x030a
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#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
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#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x030c
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#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
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#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x030e
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#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
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#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x0310
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#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
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#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
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#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
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#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x0314
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#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x0315
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#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
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#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x0317
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#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
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#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
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#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x0319
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#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x031b
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#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
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#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x031c
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#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
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// addressBlock: dce_dc_cwb0_dispdec
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// base address: 0x0
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#define mmCWB0_CWB_CTRL 0x0332
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#define mmCWB0_CWB_CTRL_BASE_IDX 2
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#define mmCWB0_CWB_FENCE_PAR0 0x0334
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#define mmCWB0_CWB_FENCE_PAR0_BASE_IDX 2
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#define mmCWB0_CWB_FENCE_PAR1 0x0335
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#define mmCWB0_CWB_FENCE_PAR1_BASE_IDX 2
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#define mmCWB0_CWB_CRC_CTRL 0x0339
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#define mmCWB0_CWB_CRC_CTRL_BASE_IDX 2
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#define mmCWB0_CWB_CRC_RED_GREEN_MASK 0x033a
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#define mmCWB0_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
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#define mmCWB0_CWB_CRC_BLUE_MASK 0x033b
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#define mmCWB0_CWB_CRC_BLUE_MASK_BASE_IDX 2
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#define mmCWB0_CWB_CRC_RED_GREEN_RESULT 0x033c
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#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
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#define mmCWB0_CWB_CRC_BLUE_RESULT 0x033d
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#define mmCWB0_CWB_CRC_BLUE_RESULT_BASE_IDX 2
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// addressBlock: dce_dc_cwb1_dispdec
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// base address: 0x60
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#define mmCWB1_CWB_CTRL 0x034a
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#define mmCWB1_CWB_CTRL_BASE_IDX 2
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#define mmCWB1_CWB_FENCE_PAR0 0x034c
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#define mmCWB1_CWB_FENCE_PAR0_BASE_IDX 2
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#define mmCWB1_CWB_FENCE_PAR1 0x034d
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#define mmCWB1_CWB_FENCE_PAR1_BASE_IDX 2
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#define mmCWB1_CWB_CRC_CTRL 0x0351
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#define mmCWB1_CWB_CRC_CTRL_BASE_IDX 2
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#define mmCWB1_CWB_CRC_RED_GREEN_MASK 0x0352
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#define mmCWB1_CWB_CRC_RED_GREEN_MASK_BASE_IDX 2
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#define mmCWB1_CWB_CRC_BLUE_MASK 0x0353
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#define mmCWB1_CWB_CRC_BLUE_MASK_BASE_IDX 2
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#define mmCWB1_CWB_CRC_RED_GREEN_RESULT 0x0354
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#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_BASE_IDX 2
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#define mmCWB1_CWB_CRC_BLUE_RESULT 0x0355
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#define mmCWB1_CWB_CRC_BLUE_RESULT_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon9_dispdec
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// base address: 0xd08
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0362
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0363
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0364
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#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CNTL 0x0365
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#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CNTL2 0x0366
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#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0367
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#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0368
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#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_HI 0x0369
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#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_LOW 0x036a
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#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dispdec
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// base address: 0x0
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#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
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#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
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#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
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#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
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#define mmVGA_RENDER_CONTROL 0x0000
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#define mmVGA_RENDER_CONTROL_BASE_IDX 1
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#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
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#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
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#define mmVGA_MODE_CONTROL 0x0002
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#define mmVGA_MODE_CONTROL_BASE_IDX 1
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#define mmVGA_SURFACE_PITCH_SELECT 0x0003
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#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
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#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
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#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
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#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
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#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
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#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
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#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
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#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
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#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
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#define mmVGA_HDP_CONTROL 0x000a
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#define mmVGA_HDP_CONTROL_BASE_IDX 1
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#define mmVGA_CACHE_CONTROL 0x000b
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#define mmVGA_CACHE_CONTROL_BASE_IDX 1
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#define mmD1VGA_CONTROL 0x000c
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#define mmD1VGA_CONTROL_BASE_IDX 1
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#define mmD2VGA_CONTROL 0x000e
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#define mmD2VGA_CONTROL_BASE_IDX 1
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#define mmVGA_STATUS 0x0010
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#define mmVGA_STATUS_BASE_IDX 1
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#define mmVGA_INTERRUPT_CONTROL 0x0011
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#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
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#define mmVGA_STATUS_CLEAR 0x0012
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#define mmVGA_STATUS_CLEAR_BASE_IDX 1
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#define mmVGA_INTERRUPT_STATUS 0x0013
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#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
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#define mmVGA_MAIN_CONTROL 0x0014
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#define mmVGA_MAIN_CONTROL_BASE_IDX 1
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#define mmVGA_TEST_CONTROL 0x0015
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#define mmVGA_TEST_CONTROL_BASE_IDX 1
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#define mmVGA_QOS_CTRL 0x0018
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#define mmVGA_QOS_CTRL_BASE_IDX 1
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#define mmCRTC8_IDX 0x002d
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#define mmCRTC8_IDX_BASE_IDX 1
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#define mmCRTC8_DATA 0x002d
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#define mmCRTC8_DATA_BASE_IDX 1
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#define mmGENFC_WT 0x002e
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#define mmGENFC_WT_BASE_IDX 1
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#define mmGENS1 0x002e
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#define mmGENS1_BASE_IDX 1
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#define mmATTRDW 0x0030
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#define mmATTRDW_BASE_IDX 1
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#define mmATTRX 0x0030
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#define mmATTRX_BASE_IDX 1
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#define mmATTRDR 0x0030
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#define mmATTRDR_BASE_IDX 1
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#define mmGENMO_WT 0x0030
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#define mmGENMO_WT_BASE_IDX 1
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#define mmGENS0 0x0030
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#define mmGENS0_BASE_IDX 1
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#define mmGENENB 0x0030
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#define mmGENENB_BASE_IDX 1
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#define mmSEQ8_IDX 0x0031
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#define mmSEQ8_IDX_BASE_IDX 1
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#define mmSEQ8_DATA 0x0031
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#define mmSEQ8_DATA_BASE_IDX 1
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#define mmDAC_MASK 0x0031
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#define mmDAC_MASK_BASE_IDX 1
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#define mmDAC_R_INDEX 0x0031
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#define mmDAC_R_INDEX_BASE_IDX 1
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#define mmDAC_W_INDEX 0x0032
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#define mmDAC_W_INDEX_BASE_IDX 1
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#define mmDAC_DATA 0x0032
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#define mmDAC_DATA_BASE_IDX 1
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#define mmGENFC_RD 0x0032
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#define mmGENFC_RD_BASE_IDX 1
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#define mmGENMO_RD 0x0033
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#define mmGENMO_RD_BASE_IDX 1
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#define mmGRPH8_IDX 0x0033
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#define mmGRPH8_IDX_BASE_IDX 1
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#define mmGRPH8_DATA 0x0033
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#define mmGRPH8_DATA_BASE_IDX 1
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#define mmCRTC8_IDX_1 0x0035
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#define mmCRTC8_IDX_1_BASE_IDX 1
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#define mmCRTC8_DATA_1 0x0035
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#define mmCRTC8_DATA_1_BASE_IDX 1
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#define mmGENFC_WT_1 0x0036
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#define mmGENFC_WT_1_BASE_IDX 1
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#define mmGENS1_1 0x0036
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#define mmGENS1_1_BASE_IDX 1
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#define mmD3VGA_CONTROL 0x0038
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#define mmD3VGA_CONTROL_BASE_IDX 1
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#define mmD4VGA_CONTROL 0x0039
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#define mmD4VGA_CONTROL_BASE_IDX 1
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#define mmD5VGA_CONTROL 0x003a
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#define mmD5VGA_CONTROL_BASE_IDX 1
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#define mmD6VGA_CONTROL 0x003b
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#define mmD6VGA_CONTROL_BASE_IDX 1
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#define mmVGA_SOURCE_SELECT 0x003c
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#define mmVGA_SOURCE_SELECT_BASE_IDX 1
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#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
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#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
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#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
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#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
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#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x0044
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#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL 0x0045
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#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmSYMCLKLPA_CLOCK_ENABLE 0x0046
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#define mmSYMCLKLPA_CLOCK_ENABLE_BASE_IDX 1
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#define mmSYMCLKLPB_CLOCK_ENABLE 0x0047
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#define mmSYMCLKLPB_CLOCK_ENABLE_BASE_IDX 1
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#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
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#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmREFCLK_CNTL 0x0049
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#define mmREFCLK_CNTL_BASE_IDX 1
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#define mmMIPI_CLK_CNTL 0x004a
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#define mmMIPI_CLK_CNTL_BASE_IDX 1
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#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
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#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
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#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmDCCG_PERFMON_CNTL2 0x004e
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#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
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#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
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#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmDCCG_CBUS_WRCMD_DELAY 0x0050
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#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
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#define mmDCCG_DS_DTO_INCR 0x0053
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#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
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#define mmDCCG_DS_DTO_MODULO 0x0054
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#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
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#define mmDCCG_DS_CNTL 0x0055
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#define mmDCCG_DS_CNTL_BASE_IDX 1
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#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
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#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
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#define mmSYMCLKG_CLOCK_ENABLE 0x0057
|
#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
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#define mmDPREFCLK_CNTL 0x0058
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#define mmDPREFCLK_CNTL_BASE_IDX 1
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#define mmAOMCLK0_CNTL 0x0059
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#define mmAOMCLK0_CNTL_BASE_IDX 1
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#define mmAOMCLK1_CNTL 0x005a
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#define mmAOMCLK1_CNTL_BASE_IDX 1
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#define mmAOMCLK2_CNTL 0x005b
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#define mmAOMCLK2_CNTL_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO2_PHASE 0x005c
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#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO2_MODULO 0x005d
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#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
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#define mmDCE_VERSION 0x005e
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#define mmDCE_VERSION_BASE_IDX 1
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#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
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#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmDCCG_GTC_CNTL 0x0060
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#define mmDCCG_GTC_CNTL_BASE_IDX 1
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#define mmDCCG_GTC_DTO_INCR 0x0061
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#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
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#define mmDCCG_GTC_DTO_MODULO 0x0062
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#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
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#define mmDCCG_GTC_CURRENT 0x0063
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#define mmDCCG_GTC_CURRENT_BASE_IDX 1
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#define mmDENTIST_DISPCLK_CNTL 0x0064
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#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
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#define mmMIPI_DTO_CNTL 0x0065
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#define mmMIPI_DTO_CNTL_BASE_IDX 1
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#define mmMIPI_DTO_PHASE 0x0066
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#define mmMIPI_DTO_PHASE_BASE_IDX 1
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#define mmMIPI_DTO_MODULO 0x0067
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#define mmMIPI_DTO_MODULO_BASE_IDX 1
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#define mmDAC_CLK_ENABLE 0x0068
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#define mmDAC_CLK_ENABLE_BASE_IDX 1
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#define mmDVO_CLK_ENABLE 0x0069
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#define mmDVO_CLK_ENABLE_BASE_IDX 1
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#define mmAVSYNC_COUNTER_WRITE 0x006a
|
#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
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#define mmAVSYNC_COUNTER_CONTROL 0x006b
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#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
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#define mmDMCU_SMU_INTERRUPT_CNTL 0x006c
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#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 1
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#define mmSMU_CONTROL 0x006d
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#define mmSMU_CONTROL_BASE_IDX 1
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#define mmSMU_INTERRUPT_CONTROL 0x006e
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#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 1
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#define mmAVSYNC_COUNTER_READ 0x006f
|
#define mmAVSYNC_COUNTER_READ_BASE_IDX 1
|
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
|
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
|
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
|
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
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#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
|
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
|
#define mmDCCG_PERFMON_CNTL 0x0073
|
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
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#define mmDCCG_GATE_DISABLE_CNTL 0x0074
|
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
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#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
|
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmSCLK_CGTT_BLK_CTRL_REG 0x0076
|
#define mmSCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmDCCG_CAC_STATUS 0x0077
|
#define mmDCCG_CAC_STATUS_BASE_IDX 1
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#define mmPIXCLK1_RESYNC_CNTL 0x0078
|
#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
|
#define mmPIXCLK2_RESYNC_CNTL 0x0079
|
#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
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#define mmPIXCLK0_RESYNC_CNTL 0x007a
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#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
|
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
|
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
|
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
|
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
|
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
|
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
|
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmDCCG_DISP_CNTL_REG 0x007f
|
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
|
#define mmCRTC0_PIXEL_RATE_CNTL 0x0080
|
#define mmCRTC0_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDP_DTO0_PHASE 0x0081
|
#define mmDP_DTO0_PHASE_BASE_IDX 1
|
#define mmDP_DTO0_MODULO 0x0082
|
#define mmDP_DTO0_MODULO_BASE_IDX 1
|
#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x0083
|
#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmCRTC1_PIXEL_RATE_CNTL 0x0084
|
#define mmCRTC1_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDP_DTO1_PHASE 0x0085
|
#define mmDP_DTO1_PHASE_BASE_IDX 1
|
#define mmDP_DTO1_MODULO 0x0086
|
#define mmDP_DTO1_MODULO_BASE_IDX 1
|
#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x0087
|
#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmCRTC2_PIXEL_RATE_CNTL 0x0088
|
#define mmCRTC2_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO2_PHASE 0x0089
|
#define mmDP_DTO2_PHASE_BASE_IDX 1
|
#define mmDP_DTO2_MODULO 0x008a
|
#define mmDP_DTO2_MODULO_BASE_IDX 1
|
#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x008b
|
#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmCRTC3_PIXEL_RATE_CNTL 0x008c
|
#define mmCRTC3_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO3_PHASE 0x008d
|
#define mmDP_DTO3_PHASE_BASE_IDX 1
|
#define mmDP_DTO3_MODULO 0x008e
|
#define mmDP_DTO3_MODULO_BASE_IDX 1
|
#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x008f
|
#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmCRTC4_PIXEL_RATE_CNTL 0x0090
|
#define mmCRTC4_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO4_PHASE 0x0091
|
#define mmDP_DTO4_PHASE_BASE_IDX 1
|
#define mmDP_DTO4_MODULO 0x0092
|
#define mmDP_DTO4_MODULO_BASE_IDX 1
|
#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x0093
|
#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmCRTC5_PIXEL_RATE_CNTL 0x0094
|
#define mmCRTC5_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO5_PHASE 0x0095
|
#define mmDP_DTO5_PHASE_BASE_IDX 1
|
#define mmDP_DTO5_MODULO 0x0096
|
#define mmDP_DTO5_MODULO_BASE_IDX 1
|
#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x0097
|
#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDCCG_SOFT_RESET 0x009f
|
#define mmDCCG_SOFT_RESET_BASE_IDX 1
|
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
|
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
|
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
|
#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
|
#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
|
#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
|
#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
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#define mmDVOACLKD_CNTL 0x00a8
|
#define mmDVOACLKD_CNTL_BASE_IDX 1
|
#define mmDVOACLKC_MVP_CNTL 0x00a9
|
#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
|
#define mmDVOACLKC_CNTL 0x00aa
|
#define mmDVOACLKC_CNTL_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
|
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
|
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
|
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
|
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
|
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
|
#define mmDCCG_TEST_CLK_SEL 0x00be
|
#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
|
#define mmFBC_CNTL 0x0062
|
#define mmFBC_CNTL_BASE_IDX 2
|
#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x0064
|
#define mmFBC_IDLE_FORCE_CLEAR_MASK_BASE_IDX 2
|
#define mmFBC_START_STOP_DELAY 0x0065
|
#define mmFBC_START_STOP_DELAY_BASE_IDX 2
|
#define mmFBC_COMP_CNTL 0x0066
|
#define mmFBC_COMP_CNTL_BASE_IDX 2
|
#define mmFBC_COMP_MODE 0x0067
|
#define mmFBC_COMP_MODE_BASE_IDX 2
|
#define mmFBC_IND_LUT0 0x006b
|
#define mmFBC_IND_LUT0_BASE_IDX 2
|
#define mmFBC_IND_LUT1 0x006c
|
#define mmFBC_IND_LUT1_BASE_IDX 2
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#define mmFBC_IND_LUT2 0x006d
|
#define mmFBC_IND_LUT2_BASE_IDX 2
|
#define mmFBC_IND_LUT3 0x006e
|
#define mmFBC_IND_LUT3_BASE_IDX 2
|
#define mmFBC_IND_LUT4 0x006f
|
#define mmFBC_IND_LUT4_BASE_IDX 2
|
#define mmFBC_IND_LUT5 0x0070
|
#define mmFBC_IND_LUT5_BASE_IDX 2
|
#define mmFBC_IND_LUT6 0x0071
|
#define mmFBC_IND_LUT6_BASE_IDX 2
|
#define mmFBC_IND_LUT7 0x0072
|
#define mmFBC_IND_LUT7_BASE_IDX 2
|
#define mmFBC_IND_LUT8 0x0073
|
#define mmFBC_IND_LUT8_BASE_IDX 2
|
#define mmFBC_IND_LUT9 0x0074
|
#define mmFBC_IND_LUT9_BASE_IDX 2
|
#define mmFBC_IND_LUT10 0x0075
|
#define mmFBC_IND_LUT10_BASE_IDX 2
|
#define mmFBC_IND_LUT11 0x0076
|
#define mmFBC_IND_LUT11_BASE_IDX 2
|
#define mmFBC_IND_LUT12 0x0077
|
#define mmFBC_IND_LUT12_BASE_IDX 2
|
#define mmFBC_IND_LUT13 0x0078
|
#define mmFBC_IND_LUT13_BASE_IDX 2
|
#define mmFBC_IND_LUT14 0x0079
|
#define mmFBC_IND_LUT14_BASE_IDX 2
|
#define mmFBC_IND_LUT15 0x007a
|
#define mmFBC_IND_LUT15_BASE_IDX 2
|
#define mmFBC_CSM_REGION_OFFSET_01 0x007b
|
#define mmFBC_CSM_REGION_OFFSET_01_BASE_IDX 2
|
#define mmFBC_CSM_REGION_OFFSET_23 0x007c
|
#define mmFBC_CSM_REGION_OFFSET_23_BASE_IDX 2
|
#define mmFBC_CLIENT_REGION_MASK 0x007d
|
#define mmFBC_CLIENT_REGION_MASK_BASE_IDX 2
|
#define mmFBC_DEBUG_COMP 0x007e
|
#define mmFBC_DEBUG_COMP_BASE_IDX 2
|
#define mmFBC_MISC 0x0084
|
#define mmFBC_MISC_BASE_IDX 2
|
#define mmFBC_STATUS 0x0085
|
#define mmFBC_STATUS_BASE_IDX 2
|
#define mmFBC_ALPHA_CNTL 0x0088
|
#define mmFBC_ALPHA_CNTL_BASE_IDX 2
|
#define mmFBC_ALPHA_RGB_OVERRIDE 0x0089
|
#define mmFBC_ALPHA_RGB_OVERRIDE_BASE_IDX 2
|
#define mmPIPE0_PG_CONFIG 0x008e
|
#define mmPIPE0_PG_CONFIG_BASE_IDX 2
|
#define mmPIPE0_PG_ENABLE 0x008f
|
#define mmPIPE0_PG_ENABLE_BASE_IDX 2
|
#define mmPIPE0_PG_STATUS 0x0090
|
#define mmPIPE0_PG_STATUS_BASE_IDX 2
|
#define mmPIPE1_PG_CONFIG 0x0091
|
#define mmPIPE1_PG_CONFIG_BASE_IDX 2
|
#define mmPIPE1_PG_ENABLE 0x0092
|
#define mmPIPE1_PG_ENABLE_BASE_IDX 2
|
#define mmPIPE1_PG_STATUS 0x0093
|
#define mmPIPE1_PG_STATUS_BASE_IDX 2
|
#define mmPIPE2_PG_CONFIG 0x0094
|
#define mmPIPE2_PG_CONFIG_BASE_IDX 2
|
#define mmPIPE2_PG_ENABLE 0x0095
|
#define mmPIPE2_PG_ENABLE_BASE_IDX 2
|
#define mmPIPE2_PG_STATUS 0x0096
|
#define mmPIPE2_PG_STATUS_BASE_IDX 2
|
#define mmPIPE3_PG_CONFIG 0x0097
|
#define mmPIPE3_PG_CONFIG_BASE_IDX 2
|
#define mmPIPE3_PG_ENABLE 0x0098
|
#define mmPIPE3_PG_ENABLE_BASE_IDX 2
|
#define mmPIPE3_PG_STATUS 0x0099
|
#define mmPIPE3_PG_STATUS_BASE_IDX 2
|
#define mmPIPE4_PG_CONFIG 0x009a
|
#define mmPIPE4_PG_CONFIG_BASE_IDX 2
|
#define mmPIPE4_PG_ENABLE 0x009b
|
#define mmPIPE4_PG_ENABLE_BASE_IDX 2
|
#define mmPIPE4_PG_STATUS 0x009c
|
#define mmPIPE4_PG_STATUS_BASE_IDX 2
|
#define mmPIPE5_PG_CONFIG 0x009d
|
#define mmPIPE5_PG_CONFIG_BASE_IDX 2
|
#define mmPIPE5_PG_ENABLE 0x009e
|
#define mmPIPE5_PG_ENABLE_BASE_IDX 2
|
#define mmPIPE5_PG_STATUS 0x009f
|
#define mmPIPE5_PG_STATUS_BASE_IDX 2
|
#define mmDSI_PG_CONFIG 0x00a0
|
#define mmDSI_PG_CONFIG_BASE_IDX 2
|
#define mmDSI_PG_ENABLE 0x00a1
|
#define mmDSI_PG_ENABLE_BASE_IDX 2
|
#define mmDSI_PG_STATUS 0x00a2
|
#define mmDSI_PG_STATUS_BASE_IDX 2
|
#define mmDCFEV0_PG_CONFIG 0x00a3
|
#define mmDCFEV0_PG_CONFIG_BASE_IDX 2
|
#define mmDCFEV0_PG_ENABLE 0x00a4
|
#define mmDCFEV0_PG_ENABLE_BASE_IDX 2
|
#define mmDCFEV0_PG_STATUS 0x00a5
|
#define mmDCFEV0_PG_STATUS_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_STATUS 0x00a6
|
#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_CONTROL 0x00a7
|
#define mmDCPG_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_CONTROL2 0x00a8
|
#define mmDCPG_INTERRUPT_CONTROL2_BASE_IDX 2
|
#define mmDCFEV1_PG_CONFIG 0x00a9
|
#define mmDCFEV1_PG_CONFIG_BASE_IDX 2
|
#define mmDCFEV1_PG_ENABLE 0x00aa
|
#define mmDCFEV1_PG_ENABLE_BASE_IDX 2
|
#define mmDCFEV1_PG_STATUS 0x00ab
|
#define mmDCFEV1_PG_STATUS_BASE_IDX 2
|
#define mmDC_IP_REQUEST_CNTL 0x00ac
|
#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
|
#define mmDC_PGCNTL_STATUS_REG 0x00ad
|
#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
|
#define mmDMIFV_STATUS 0x00c3
|
#define mmDMIFV_STATUS_BASE_IDX 2
|
#define mmDMIF_CONTROL 0x00c4
|
#define mmDMIF_CONTROL_BASE_IDX 2
|
#define mmDMIF_STATUS 0x00c5
|
#define mmDMIF_STATUS_BASE_IDX 2
|
#define mmDMIF_ARBITRATION_CONTROL 0x00c7
|
#define mmDMIF_ARBITRATION_CONTROL_BASE_IDX 2
|
#define mmPIPE0_ARBITRATION_CONTROL3 0x00c8
|
#define mmPIPE0_ARBITRATION_CONTROL3_BASE_IDX 2
|
#define mmPIPE1_ARBITRATION_CONTROL3 0x00c9
|
#define mmPIPE1_ARBITRATION_CONTROL3_BASE_IDX 2
|
#define mmPIPE2_ARBITRATION_CONTROL3 0x00ca
|
#define mmPIPE2_ARBITRATION_CONTROL3_BASE_IDX 2
|
#define mmPIPE3_ARBITRATION_CONTROL3 0x00cb
|
#define mmPIPE3_ARBITRATION_CONTROL3_BASE_IDX 2
|
#define mmPIPE4_ARBITRATION_CONTROL3 0x00cc
|
#define mmPIPE4_ARBITRATION_CONTROL3_BASE_IDX 2
|
#define mmPIPE5_ARBITRATION_CONTROL3 0x00cd
|
#define mmPIPE5_ARBITRATION_CONTROL3_BASE_IDX 2
|
#define mmDMIF_P_VMID 0x00ce
|
#define mmDMIF_P_VMID_BASE_IDX 2
|
#define mmDMIF_ADDR_CALC 0x00d1
|
#define mmDMIF_ADDR_CALC_BASE_IDX 2
|
#define mmDMIF_STATUS2 0x00d2
|
#define mmDMIF_STATUS2_BASE_IDX 2
|
#define mmPIPE0_MAX_REQUESTS 0x00d3
|
#define mmPIPE0_MAX_REQUESTS_BASE_IDX 2
|
#define mmPIPE1_MAX_REQUESTS 0x00d4
|
#define mmPIPE1_MAX_REQUESTS_BASE_IDX 2
|
#define mmPIPE2_MAX_REQUESTS 0x00d5
|
#define mmPIPE2_MAX_REQUESTS_BASE_IDX 2
|
#define mmPIPE3_MAX_REQUESTS 0x00d6
|
#define mmPIPE3_MAX_REQUESTS_BASE_IDX 2
|
#define mmPIPE4_MAX_REQUESTS 0x00d7
|
#define mmPIPE4_MAX_REQUESTS_BASE_IDX 2
|
#define mmPIPE5_MAX_REQUESTS 0x00d8
|
#define mmPIPE5_MAX_REQUESTS_BASE_IDX 2
|
#define mmLOW_POWER_TILING_CONTROL 0x00d9
|
#define mmLOW_POWER_TILING_CONTROL_BASE_IDX 2
|
#define mmMCIF_CONTROL 0x00da
|
#define mmMCIF_CONTROL_BASE_IDX 2
|
#define mmMCIF_WRITE_COMBINE_CONTROL 0x00db
|
#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
|
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x00de
|
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
|
#define mmCC_DC_PIPE_DIS 0x00e0
|
#define mmCC_DC_PIPE_DIS_BASE_IDX 2
|
#define mmSMU_WM_CONTROL 0x00e1
|
#define mmSMU_WM_CONTROL_BASE_IDX 2
|
#define mmRBBMIF_TIMEOUT 0x00e2
|
#define mmRBBMIF_TIMEOUT_BASE_IDX 2
|
#define mmRBBMIF_STATUS 0x00e3
|
#define mmRBBMIF_STATUS_BASE_IDX 2
|
#define mmRBBMIF_TIMEOUT_DIS 0x00e4
|
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
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#define mmDCI_MEM_PWR_STATUS 0x00e5
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#define mmDCI_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCI_MEM_PWR_STATUS2 0x00e6
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#define mmDCI_MEM_PWR_STATUS2_BASE_IDX 2
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#define mmDCI_CLK_CNTL 0x00e7
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#define mmDCI_CLK_CNTL_BASE_IDX 2
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#define mmDCI_CLK_CNTL2 0x00e8
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#define mmDCI_CLK_CNTL2_BASE_IDX 2
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#define mmDCI_MEM_PWR_CNTL 0x00e9
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#define mmDCI_MEM_PWR_CNTL_BASE_IDX 2
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#define mmDCI_MEM_PWR_CNTL2 0x00ea
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#define mmDCI_MEM_PWR_CNTL2_BASE_IDX 2
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#define mmDCI_MEM_PWR_CNTL3 0x00eb
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#define mmDCI_MEM_PWR_CNTL3_BASE_IDX 2
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#define mmPIPE0_DMIF_BUFFER_CONTROL 0x00ef
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#define mmPIPE0_DMIF_BUFFER_CONTROL_BASE_IDX 2
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#define mmPIPE1_DMIF_BUFFER_CONTROL 0x00f0
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#define mmPIPE1_DMIF_BUFFER_CONTROL_BASE_IDX 2
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#define mmPIPE2_DMIF_BUFFER_CONTROL 0x00f1
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#define mmPIPE2_DMIF_BUFFER_CONTROL_BASE_IDX 2
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#define mmPIPE3_DMIF_BUFFER_CONTROL 0x00f2
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#define mmPIPE3_DMIF_BUFFER_CONTROL_BASE_IDX 2
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#define mmPIPE4_DMIF_BUFFER_CONTROL 0x00f3
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#define mmPIPE4_DMIF_BUFFER_CONTROL_BASE_IDX 2
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#define mmPIPE5_DMIF_BUFFER_CONTROL 0x00f4
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#define mmPIPE5_DMIF_BUFFER_CONTROL_BASE_IDX 2
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#define mmRBBMIF_STATUS_FLAG 0x00f5
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#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
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#define mmDCI_SOFT_RESET 0x00f6
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#define mmDCI_SOFT_RESET_BASE_IDX 2
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#define mmDMIF_URG_OVERRIDE 0x00f7
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#define mmDMIF_URG_OVERRIDE_BASE_IDX 2
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#define mmPIPE6_ARBITRATION_CONTROL3 0x00f8
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#define mmPIPE6_ARBITRATION_CONTROL3_BASE_IDX 2
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#define mmPIPE7_ARBITRATION_CONTROL3 0x00f9
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#define mmPIPE7_ARBITRATION_CONTROL3_BASE_IDX 2
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#define mmPIPE6_MAX_REQUESTS 0x00fa
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#define mmPIPE6_MAX_REQUESTS_BASE_IDX 2
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#define mmPIPE7_MAX_REQUESTS 0x00fb
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#define mmPIPE7_MAX_REQUESTS_BASE_IDX 2
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#define mmDVMM_REG_RD_STATUS 0x00fc
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#define mmDVMM_REG_RD_STATUS_BASE_IDX 2
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#define mmDVMM_REG_RD_DATA 0x00fd
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#define mmDVMM_REG_RD_DATA_BASE_IDX 2
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#define mmDVMM_PTE_REQ 0x00fe
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#define mmDVMM_PTE_REQ_BASE_IDX 2
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#define mmDVMM_CNTL 0x00ff
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#define mmDVMM_CNTL_BASE_IDX 2
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#define mmDVMM_FAULT_STATUS 0x0100
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#define mmDVMM_FAULT_STATUS_BASE_IDX 2
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#define mmDVMM_FAULT_ADDR 0x0101
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#define mmDVMM_FAULT_ADDR_BASE_IDX 2
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#define mmFMON_CTRL 0x0102
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#define mmFMON_CTRL_BASE_IDX 2
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#define mmDVMM_PTE_PGMEM_CONTROL 0x0103
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#define mmDVMM_PTE_PGMEM_CONTROL_BASE_IDX 2
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#define mmDVMM_PTE_PGMEM_STATE 0x0104
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#define mmDVMM_PTE_PGMEM_STATE_BASE_IDX 2
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#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x0105
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#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0106
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#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER 0x0107
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#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER 0x0108
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#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmDCI_MEM_PWR_CNTL4 0x0109
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#define mmDCI_MEM_PWR_CNTL4_BASE_IDX 2
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#define mmMCIF_WB_MISC_CTRL 0x010a
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#define mmMCIF_WB_MISC_CTRL_BASE_IDX 2
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#define mmDCI_MEM_PWR_STATUS3 0x010b
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#define mmDCI_MEM_PWR_STATUS3_BASE_IDX 2
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#define mmDMIF_CURSOR_CONTROL 0x010c
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#define mmDMIF_CURSOR_CONTROL_BASE_IDX 2
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#define mmDMIF_CURSOR_MEM_CONTROL 0x010d
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#define mmDMIF_CURSOR_MEM_CONTROL_BASE_IDX 2
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#define mmDCHUB_FB_LOCATION 0x0126
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#define mmDCHUB_FB_LOCATION_BASE_IDX 2
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#define mmDCHUB_FB_OFFSET 0x0127
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#define mmDCHUB_FB_OFFSET_BASE_IDX 2
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#define mmDCHUB_AGP_BASE 0x0128
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#define mmDCHUB_AGP_BASE_BASE_IDX 2
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#define mmDCHUB_AGP_BOT 0x0129
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#define mmDCHUB_AGP_BOT_BASE_IDX 2
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#define mmDCHUB_AGP_TOP 0x012a
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#define mmDCHUB_AGP_TOP_BASE_IDX 2
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#define mmDCHUB_DRAM_APER_BASE 0x012b
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#define mmDCHUB_DRAM_APER_BASE_BASE_IDX 2
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#define mmDCHUB_DRAM_APER_DEF 0x012c
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#define mmDCHUB_DRAM_APER_DEF_BASE_IDX 2
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#define mmDCHUB_DRAM_APER_TOP 0x012d
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#define mmDCHUB_DRAM_APER_TOP_BASE_IDX 2
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#define mmDCHUB_CONTROL_STATUS 0x012e
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#define mmDCHUB_CONTROL_STATUS_BASE_IDX 2
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#define mmWB_ENABLE 0x0212
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#define mmWB_ENABLE_BASE_IDX 2
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#define mmWB_EC_CONFIG 0x0213
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#define mmWB_EC_CONFIG_BASE_IDX 2
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#define mmCNV_MODE 0x0214
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#define mmCNV_MODE_BASE_IDX 2
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#define mmCNV_WINDOW_START 0x0215
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#define mmCNV_WINDOW_START_BASE_IDX 2
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#define mmCNV_WINDOW_SIZE 0x0216
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#define mmCNV_WINDOW_SIZE_BASE_IDX 2
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#define mmCNV_UPDATE 0x0217
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#define mmCNV_UPDATE_BASE_IDX 2
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#define mmCNV_SOURCE_SIZE 0x0218
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#define mmCNV_SOURCE_SIZE_BASE_IDX 2
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#define mmCNV_CSC_CONTROL 0x0219
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#define mmCNV_CSC_CONTROL_BASE_IDX 2
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#define mmCNV_CSC_C11_C12 0x021a
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#define mmCNV_CSC_C11_C12_BASE_IDX 2
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#define mmCNV_CSC_C13_C14 0x021b
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#define mmCNV_CSC_C13_C14_BASE_IDX 2
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#define mmCNV_CSC_C21_C22 0x021c
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#define mmCNV_CSC_C21_C22_BASE_IDX 2
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#define mmCNV_CSC_C23_C24 0x021d
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#define mmCNV_CSC_C23_C24_BASE_IDX 2
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#define mmCNV_CSC_C31_C32 0x021e
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#define mmCNV_CSC_C31_C32_BASE_IDX 2
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#define mmCNV_CSC_C33_C34 0x021f
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#define mmCNV_CSC_C33_C34_BASE_IDX 2
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#define mmCNV_CSC_ROUND_OFFSET_R 0x0220
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#define mmCNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
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#define mmCNV_CSC_ROUND_OFFSET_G 0x0221
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#define mmCNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
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#define mmCNV_CSC_ROUND_OFFSET_B 0x0222
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#define mmCNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
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#define mmCNV_CSC_CLAMP_R 0x0223
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#define mmCNV_CSC_CLAMP_R_BASE_IDX 2
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#define mmCNV_CSC_CLAMP_G 0x0224
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#define mmCNV_CSC_CLAMP_G_BASE_IDX 2
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#define mmCNV_CSC_CLAMP_B 0x0225
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#define mmCNV_CSC_CLAMP_B_BASE_IDX 2
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#define mmCNV_TEST_CNTL 0x0226
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#define mmCNV_TEST_CNTL_BASE_IDX 2
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#define mmCNV_TEST_CRC_RED 0x0227
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#define mmCNV_TEST_CRC_RED_BASE_IDX 2
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#define mmCNV_TEST_CRC_GREEN 0x0228
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#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
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#define mmCNV_TEST_CRC_BLUE 0x0229
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#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
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#define mmCNV_INPUT_SELECT 0x022d
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#define mmCNV_INPUT_SELECT_BASE_IDX 2
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#define mmWB_SOFT_RESET 0x0230
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#define mmWB_SOFT_RESET_BASE_IDX 2
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#define mmWB_WARM_UP_MODE_CTL1 0x0231
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#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
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#define mmWB_WARM_UP_MODE_CTL2 0x0232
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#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
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#define mmWBSCL_COEF_RAM_SELECT 0x0242
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#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
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#define mmWBSCL_COEF_RAM_TAP_DATA 0x0243
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#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmWBSCL_MODE 0x0244
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#define mmWBSCL_MODE_BASE_IDX 2
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#define mmWBSCL_TAP_CONTROL 0x0245
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#define mmWBSCL_TAP_CONTROL_BASE_IDX 2
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#define mmWBSCL_DEST_SIZE 0x0246
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#define mmWBSCL_DEST_SIZE_BASE_IDX 2
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#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x0247
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#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0248
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#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
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#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0249
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#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
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#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x024a
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#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x024b
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#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
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#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x024c
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#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
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#define mmWBSCL_ROUND_OFFSET 0x024d
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#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
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#define mmWBSCL_CLAMP 0x024e
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#define mmWBSCL_CLAMP_BASE_IDX 2
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#define mmWBSCL_OVERFLOW_STATUS 0x024f
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#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
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#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0250
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#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
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#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0251
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#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
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#define mmWBSCL_TEST_CNTL 0x0252
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#define mmWBSCL_TEST_CNTL_BASE_IDX 2
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#define mmWBSCL_TEST_CRC_RED 0x0253
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#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
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#define mmWBSCL_TEST_CRC_GREEN 0x0254
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#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
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#define mmWBSCL_TEST_CRC_BLUE 0x0255
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#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
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#define mmWBSCL_BACKPRESSURE_CNT_EN 0x0256
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#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
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#define mmWB_MCIF_BACKPRESSURE_CNT 0x0257
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#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
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#define mmWBSCL_RAM_SHUTDOWN 0x025a
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#define mmWBSCL_RAM_SHUTDOWN_BASE_IDX 2
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#define mmDMCU_CTRL 0x03b6
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#define mmDMCU_CTRL_BASE_IDX 2
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#define mmDMCU_STATUS 0x03b7
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#define mmDMCU_STATUS_BASE_IDX 2
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#define mmDMCU_PC_START_ADDR 0x03b8
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#define mmDMCU_PC_START_ADDR_BASE_IDX 2
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#define mmDMCU_FW_START_ADDR 0x03b9
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#define mmDMCU_FW_START_ADDR_BASE_IDX 2
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#define mmDMCU_FW_END_ADDR 0x03ba
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#define mmDMCU_FW_END_ADDR_BASE_IDX 2
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#define mmDMCU_FW_ISR_START_ADDR 0x03bb
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#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
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#define mmDMCU_FW_CS_HI 0x03bc
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#define mmDMCU_FW_CS_HI_BASE_IDX 2
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#define mmDMCU_FW_CS_LO 0x03bd
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#define mmDMCU_FW_CS_LO_BASE_IDX 2
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#define mmDMCU_RAM_ACCESS_CTRL 0x03be
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#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
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#define mmDMCU_ERAM_WR_CTRL 0x03bf
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#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
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#define mmDMCU_ERAM_WR_DATA 0x03c0
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#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
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#define mmDMCU_ERAM_RD_CTRL 0x03c1
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#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
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#define mmDMCU_ERAM_RD_DATA 0x03c2
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#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
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#define mmDMCU_IRAM_WR_CTRL 0x03c3
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#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
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#define mmDMCU_IRAM_WR_DATA 0x03c4
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#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
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#define mmDMCU_IRAM_RD_CTRL 0x03c5
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#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
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#define mmDMCU_IRAM_RD_DATA 0x03c6
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#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
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#define mmDMCU_EVENT_TRIGGER 0x03c7
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#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
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#define mmDMCU_UC_INTERNAL_INT_STATUS 0x03c8
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#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
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#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x03c9
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#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
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#define mmDMCU_INTERRUPT_STATUS 0x03ca
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#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x03cb
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#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x03cc
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x03cd
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
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#define mmDC_DMCU_SCRATCH 0x03ce
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#define mmDC_DMCU_SCRATCH_BASE_IDX 2
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#define mmDMCU_INT_CNT 0x03cf
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#define mmDMCU_INT_CNT_BASE_IDX 2
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#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x03d0
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#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
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#define mmDMCU_UC_CLK_GATING_CNTL 0x03d1
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#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
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#define mmMASTER_COMM_DATA_REG1 0x03d2
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#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
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#define mmMASTER_COMM_DATA_REG2 0x03d3
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#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
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#define mmMASTER_COMM_DATA_REG3 0x03d4
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#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
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#define mmMASTER_COMM_CMD_REG 0x03d5
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#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
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#define mmMASTER_COMM_CNTL_REG 0x03d6
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#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
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#define mmSLAVE_COMM_DATA_REG1 0x03d7
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#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
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#define mmSLAVE_COMM_DATA_REG2 0x03d8
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#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
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#define mmSLAVE_COMM_DATA_REG3 0x03d9
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#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
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#define mmSLAVE_COMM_CMD_REG 0x03da
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#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
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#define mmSLAVE_COMM_CNTL_REG 0x03db
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#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
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#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x03de
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#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
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#define mmBL1_PWM_USER_LEVEL 0x03df
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#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
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#define mmBL1_PWM_TARGET_ABM_LEVEL 0x03e0
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#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
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#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x03e1
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#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
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#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x03e2
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#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
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#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x03e3
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#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
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#define mmBL1_PWM_ABM_CNTL 0x03e4
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#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
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#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x03e5
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#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
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#define mmBL1_PWM_GRP2_REG_LOCK 0x03e6
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#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x03e7
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x03e8
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
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#define mmDMCU_INTERRUPT_STATUS_1 0x03e9
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#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
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#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x03ea
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#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
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#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x03eb
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#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
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#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x03ec
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#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
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#define mmDC_ABM1_CNTL 0x03ee
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#define mmDC_ABM1_CNTL_BASE_IDX 2
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#define mmDC_ABM1_IPCSC_COEFF_SEL 0x03ef
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#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x03f0
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x03f1
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x03f2
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x03f3
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x03f4
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#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
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#define mmDC_ABM1_ACE_THRES_12 0x03f5
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#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
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#define mmDC_ABM1_ACE_THRES_34 0x03f6
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#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
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#define mmDC_ABM1_ACE_CNTL_MISC 0x03f7
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#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x03f8
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#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x03f9
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x03fa
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#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x03fb
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#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x03fc
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#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x03fd
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#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
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#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x0400
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#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
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#define mmDC_ABM1_HG_MISC_CTRL 0x0401
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#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
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#define mmDC_ABM1_LS_SUM_OF_LUMA 0x0402
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#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
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#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x0403
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#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
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#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0404
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#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
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#define mmDC_ABM1_LS_PIXEL_COUNT 0x0405
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#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
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#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x0406
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#define mmDC_ABM1_LS_OVR_SCAN_BIN_BASE_IDX 2
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#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0407
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#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
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#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0408
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#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
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#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0409
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#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
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#define mmDC_ABM1_HG_SAMPLE_RATE 0x040a
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#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
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#define mmDC_ABM1_LS_SAMPLE_RATE 0x040b
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#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
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#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x040c
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#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
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#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x040d
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#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
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#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x040e
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#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
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#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x040f
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#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
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#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0410
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#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_1 0x0411
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#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_2 0x0412
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#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_3 0x0413
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#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_4 0x0414
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#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_5 0x0415
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#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_6 0x0416
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#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_7 0x0417
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#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_8 0x0418
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#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_9 0x0419
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#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_10 0x041a
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#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_11 0x041b
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#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_12 0x041c
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#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_13 0x041d
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#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_14 0x041e
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#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_15 0x041f
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#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_16 0x0420
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#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_17 0x0421
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#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_18 0x0422
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#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_19 0x0423
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#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_20 0x0424
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#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_21 0x0425
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#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_22 0x0426
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#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_23 0x0427
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#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
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#define mmDC_ABM1_HG_RESULT_24 0x0428
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#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0429
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x042a
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x042b
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x042c
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x042d
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x042e
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x042f
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0430
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0431
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
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#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x0451
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#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_BASE_IDX 2
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#define mmDC_ABM1_BL_MASTER_LOCK 0x0452
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#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
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#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x04bc
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#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
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#define mmAZALIA_AUDIO_DTO 0x04bd
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#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
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#define mmAZALIA_AUDIO_DTO_CONTROL 0x04be
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#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
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#define mmAZALIA_SOCCLK_CONTROL 0x04bf
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#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
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#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x04c0
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#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
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#define mmAZALIA_DATA_DMA_CONTROL 0x04c1
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#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
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#define mmAZALIA_BDL_DMA_CONTROL 0x04c2
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#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
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#define mmAZALIA_RIRB_AND_DP_CONTROL 0x04c3
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#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
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#define mmAZALIA_CORB_DMA_CONTROL 0x04c4
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#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
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#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x04cb
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#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
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#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x04cc
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#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
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#define mmAZALIA_GLOBAL_CAPABILITIES 0x04cd
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#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
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#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x04ce
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#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
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#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x04cf
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#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
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#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x04d0
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#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL0 0x04d3
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#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL1 0x04d4
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#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL2 0x04d5
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#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL3 0x04d6
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#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_RESULT 0x04d7
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#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL0 0x04d8
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#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL1 0x04d9
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#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL2 0x04da
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#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL3 0x04db
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#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_RESULT 0x04dc
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#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL0 0x04dd
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#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL1 0x04de
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#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL2 0x04df
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#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL3 0x04e0
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#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
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#define mmAZALIA_CRC0_RESULT 0x04e1
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#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL0 0x04e2
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#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL1 0x04e3
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#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL2 0x04e4
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#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL3 0x04e5
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#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
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#define mmAZALIA_CRC1_RESULT 0x04e6
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#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
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#define mmAZALIA_MEM_PWR_CTRL 0x04e8
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#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
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#define mmAZALIA_MEM_PWR_STATUS 0x04e9
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#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0500
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0501
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0502
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#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0503
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#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x0504
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x0505
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x0506
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x0507
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x0508
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x0509
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x050a
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x050b
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
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#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x050c
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#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x050d
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#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x050f
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#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0510
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#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0511
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#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0512
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#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0513
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#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x0514
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#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x0515
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#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
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#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x0516
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#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0517
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#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmDAC_ENABLE 0x155a
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#define mmDAC_ENABLE_BASE_IDX 2
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#define mmDAC_SOURCE_SELECT 0x155b
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#define mmDAC_SOURCE_SELECT_BASE_IDX 2
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#define mmDAC_CRC_EN 0x155c
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#define mmDAC_CRC_EN_BASE_IDX 2
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#define mmDAC_CRC_CONTROL 0x155d
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#define mmDAC_CRC_CONTROL_BASE_IDX 2
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#define mmDAC_CRC_SIG_RGB_MASK 0x155e
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#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
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#define mmDAC_CRC_SIG_CONTROL_MASK 0x155f
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#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
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#define mmDAC_CRC_SIG_RGB 0x1560
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#define mmDAC_CRC_SIG_RGB_BASE_IDX 2
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#define mmDAC_CRC_SIG_CONTROL 0x1561
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#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
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#define mmDAC_SYNC_TRISTATE_CONTROL 0x1562
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#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
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#define mmDAC_STEREOSYNC_SELECT 0x1563
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#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
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#define mmDAC_AUTODETECT_CONTROL 0x1564
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#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
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#define mmDAC_AUTODETECT_CONTROL2 0x1565
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#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
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#define mmDAC_AUTODETECT_CONTROL3 0x1566
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#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
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#define mmDAC_AUTODETECT_STATUS 0x1567
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#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
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#define mmDAC_AUTODETECT_INT_CONTROL 0x1568
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#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
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#define mmDAC_FORCE_OUTPUT_CNTL 0x1569
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#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
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#define mmDAC_FORCE_DATA 0x156a
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#define mmDAC_FORCE_DATA_BASE_IDX 2
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#define mmDAC_POWERDOWN 0x156b
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#define mmDAC_POWERDOWN_BASE_IDX 2
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#define mmDAC_CONTROL 0x156c
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#define mmDAC_CONTROL_BASE_IDX 2
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#define mmDAC_COMPARATOR_ENABLE 0x156d
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#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
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#define mmDAC_COMPARATOR_OUTPUT 0x156e
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#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
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#define mmDAC_PWR_CNTL 0x156f
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#define mmDAC_PWR_CNTL_BASE_IDX 2
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#define mmDAC_DFT_CONFIG 0x1570
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#define mmDAC_DFT_CONFIG_BASE_IDX 2
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#define mmDAC_FIFO_STATUS 0x1571
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#define mmDAC_FIFO_STATUS_BASE_IDX 2
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#define mmDC_I2C_CONTROL 0x1584
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#define mmDC_I2C_CONTROL_BASE_IDX 2
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#define mmDC_I2C_ARBITRATION 0x1585
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#define mmDC_I2C_ARBITRATION_BASE_IDX 2
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#define mmDC_I2C_INTERRUPT_CONTROL 0x1586
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#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDC_I2C_SW_STATUS 0x1587
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#define mmDC_I2C_SW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC1_HW_STATUS 0x1588
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#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC2_HW_STATUS 0x1589
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#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC3_HW_STATUS 0x158a
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#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC4_HW_STATUS 0x158b
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#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC5_HW_STATUS 0x158c
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#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC6_HW_STATUS 0x158d
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#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC1_SPEED 0x158e
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#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC1_SETUP 0x158f
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#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC2_SPEED 0x1590
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#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC2_SETUP 0x1591
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#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC3_SPEED 0x1592
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#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC3_SETUP 0x1593
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#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC4_SPEED 0x1594
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#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC4_SETUP 0x1595
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#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC5_SPEED 0x1596
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#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC5_SETUP 0x1597
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#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC6_SPEED 0x1598
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#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC6_SETUP 0x1599
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#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
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#define mmDC_I2C_TRANSACTION0 0x159a
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#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
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#define mmDC_I2C_TRANSACTION1 0x159b
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#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
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#define mmDC_I2C_TRANSACTION2 0x159c
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#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
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#define mmDC_I2C_TRANSACTION3 0x159d
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#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
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#define mmDC_I2C_DATA 0x159e
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#define mmDC_I2C_DATA_BASE_IDX 2
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#define mmDC_I2C_DDCVGA_HW_STATUS 0x159f
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#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDCVGA_SPEED 0x15a0
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#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDCVGA_SETUP 0x15a1
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#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
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#define mmDC_I2C_EDID_DETECT_CTRL 0x15a2
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#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
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#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x15a3
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#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
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#define mmGENERIC_I2C_CONTROL 0x15a4
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#define mmGENERIC_I2C_CONTROL_BASE_IDX 2
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#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x15a5
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#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmGENERIC_I2C_STATUS 0x15a6
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#define mmGENERIC_I2C_STATUS_BASE_IDX 2
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#define mmGENERIC_I2C_SPEED 0x15a7
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#define mmGENERIC_I2C_SPEED_BASE_IDX 2
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#define mmGENERIC_I2C_SETUP 0x15a8
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#define mmGENERIC_I2C_SETUP_BASE_IDX 2
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#define mmGENERIC_I2C_TRANSACTION 0x15a9
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#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
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#define mmGENERIC_I2C_DATA 0x15aa
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#define mmGENERIC_I2C_DATA_BASE_IDX 2
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#define mmGENERIC_I2C_PIN_SELECTION 0x15ab
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#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
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#define mmDCO_SCRATCH0 0x15b6
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#define mmDCO_SCRATCH0_BASE_IDX 2
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#define mmDCO_SCRATCH1 0x15b7
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#define mmDCO_SCRATCH1_BASE_IDX 2
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#define mmDCO_SCRATCH2 0x15b8
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#define mmDCO_SCRATCH2_BASE_IDX 2
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#define mmDCO_SCRATCH3 0x15b9
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#define mmDCO_SCRATCH3_BASE_IDX 2
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#define mmDCO_SCRATCH4 0x15ba
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#define mmDCO_SCRATCH4_BASE_IDX 2
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#define mmDCO_SCRATCH5 0x15bb
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#define mmDCO_SCRATCH5_BASE_IDX 2
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#define mmDCO_SCRATCH6 0x15bc
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#define mmDCO_SCRATCH6_BASE_IDX 2
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#define mmDCO_SCRATCH7 0x15bd
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#define mmDCO_SCRATCH7_BASE_IDX 2
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#define mmDCE_VCE_CONTROL 0x15be
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#define mmDCE_VCE_CONTROL_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS 0x15bf
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#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x15c0
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#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x15c1
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#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x15c2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x15c3
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#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x15c4
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#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x15c5
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#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x15c6
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#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x15c7
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#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x15c8
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#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
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#define mmDCO_MEM_PWR_STATUS 0x15c9
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#define mmDCO_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCO_MEM_PWR_CTRL 0x15ca
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#define mmDCO_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCO_MEM_PWR_CTRL2 0x15cb
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#define mmDCO_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDCO_CLK_CNTL 0x15cc
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#define mmDCO_CLK_CNTL_BASE_IDX 2
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#define mmDCO_POWER_MANAGEMENT_CNTL 0x15d0
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#define mmDCO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
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#define mmDIG_SOFT_RESET_2 0x15d2
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#define mmDIG_SOFT_RESET_2_BASE_IDX 2
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#define mmDCO_STEREOSYNC_SEL 0x15d6
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#define mmDCO_STEREOSYNC_SEL_BASE_IDX 2
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#define mmDCO_SOFT_RESET 0x15d9
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#define mmDCO_SOFT_RESET_BASE_IDX 2
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#define mmDIG_SOFT_RESET 0x15da
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#define mmDIG_SOFT_RESET_BASE_IDX 2
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#define mmDCO_MEM_PWR_STATUS1 0x15dc
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#define mmDCO_MEM_PWR_STATUS1_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x15dd
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#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
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#define mmDCO_CLK_CNTL2 0x15de
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#define mmDCO_CLK_CNTL2_BASE_IDX 2
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#define mmDCO_CLK_CNTL3 0x15df
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#define mmDCO_CLK_CNTL3_BASE_IDX 2
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#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x15eb
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#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
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#define mmDCO_PSP_INTERRUPT_STATUS 0x15ec
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#define mmDCO_PSP_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCO_PSP_INTERRUPT_CLEAR 0x15ed
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#define mmDCO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
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#define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x15ee
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#define mmDCO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
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#define mmDCO_GENERIC_INTERRUPT_CLEAR 0x15ef
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#define mmDCO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
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#define mmFMT_MEMORY0_CONTROL 0x15f0
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#define mmFMT_MEMORY0_CONTROL_BASE_IDX 2
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#define mmFMT_MEMORY1_CONTROL 0x15f1
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#define mmFMT_MEMORY1_CONTROL_BASE_IDX 2
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#define mmFMT_MEMORY2_CONTROL 0x15f2
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#define mmFMT_MEMORY2_CONTROL_BASE_IDX 2
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#define mmFMT_MEMORY3_CONTROL 0x15f3
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#define mmFMT_MEMORY3_CONTROL_BASE_IDX 2
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#define mmFMT_MEMORY4_CONTROL 0x15f4
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#define mmFMT_MEMORY4_CONTROL_BASE_IDX 2
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#define mmFMT_MEMORY5_CONTROL 0x15f5
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#define mmFMT_MEMORY5_CONTROL_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x15f6
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#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
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#define mmDC_GENERICA 0x207e
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#define mmDC_GENERICA_BASE_IDX 2
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#define mmDC_GENERICB 0x207f
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#define mmDC_GENERICB_BASE_IDX 2
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#define mmDC_PAD_EXTERN_SIG 0x2080
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#define mmDC_PAD_EXTERN_SIG_BASE_IDX 2
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#define mmDC_REF_CLK_CNTL 0x2081
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#define mmDC_REF_CLK_CNTL_BASE_IDX 2
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#define mmDC_GPIO_DEBUG 0x2082
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#define mmDC_GPIO_DEBUG_BASE_IDX 2
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#define mmUNIPHYA_LINK_CNTL 0x2083
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#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x2084
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#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmUNIPHYB_LINK_CNTL 0x2085
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#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2086
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#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmUNIPHYC_LINK_CNTL 0x2087
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#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2088
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#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmUNIPHYD_LINK_CNTL 0x2089
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#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x208a
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#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmUNIPHYE_LINK_CNTL 0x208b
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#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x208c
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#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmUNIPHYF_LINK_CNTL 0x208d
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#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x208e
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#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmUNIPHYG_LINK_CNTL 0x208f
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#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x2090
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#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmDCIO_WRCMD_DELAY 0x2094
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#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
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#define mmDC_PINSTRAPS 0x2096
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#define mmDC_PINSTRAPS_BASE_IDX 2
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#define mmCC_DC_MISC_STRAPS 0x2097
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#define mmCC_DC_MISC_STRAPS_BASE_IDX 2
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#define mmDC_DVODATA_CONFIG 0x2098
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#define mmDC_DVODATA_CONFIG_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_CNTL 0x2099
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#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_STATE 0x209a
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#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_REF_DIV 0x209b
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#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_DELAY1 0x209c
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#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_DELAY2 0x209d
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#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
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#define mmBL_PWM_CNTL 0x209e
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#define mmBL_PWM_CNTL_BASE_IDX 2
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#define mmBL_PWM_CNTL2 0x209f
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#define mmBL_PWM_CNTL2_BASE_IDX 2
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#define mmBL_PWM_PERIOD_CNTL 0x20a0
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#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
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#define mmBL_PWM_GRP1_REG_LOCK 0x20a1
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#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
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#define mmDCIO_GSL_GENLK_PAD_CNTL 0x20a2
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#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
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#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x20a3
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#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
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#define mmDCIO_GSL0_CNTL 0x20a4
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#define mmDCIO_GSL0_CNTL_BASE_IDX 2
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#define mmDCIO_GSL1_CNTL 0x20a5
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#define mmDCIO_GSL1_CNTL_BASE_IDX 2
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#define mmDCIO_GSL2_CNTL 0x20a6
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#define mmDCIO_GSL2_CNTL_BASE_IDX 2
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#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x20a7
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#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
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#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x20a8
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#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_BASE_IDX 2
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#define mmDC_GPU_TIMER_READ 0x20a9
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#define mmDC_GPU_TIMER_READ_BASE_IDX 2
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#define mmDC_GPU_TIMER_READ_CNTL 0x20aa
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#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
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#define mmDCIO_CLOCK_CNTL 0x20ab
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#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
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#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x20ae
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#define mmDCO_DCFE_EXT_VSYNC_CNTL_BASE_IDX 2
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#define mmDCIO_SOFT_RESET 0x20b4
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#define mmDCIO_SOFT_RESET_BASE_IDX 2
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#define mmDCIO_DPHY_SEL 0x20b5
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#define mmDCIO_DPHY_SEL_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_LINKA 0x20b6
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#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_LINKB 0x20b7
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#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_PERIOD 0x20b8
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#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
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#define mmAUXP_IMPCAL 0x20b9
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#define mmAUXP_IMPCAL_BASE_IDX 2
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#define mmAUXN_IMPCAL 0x20ba
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#define mmAUXN_IMPCAL_BASE_IDX 2
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#define mmDCIO_IMPCAL_CNTL 0x20bb
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#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_PSW_AB 0x20bc
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#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_LINKC 0x20bd
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#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_LINKD 0x20be
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#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
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#define mmDCIO_IMPCAL_CNTL_CD 0x20bf
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#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_PSW_CD 0x20c0
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#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_LINKE 0x20c1
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#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_LINKF 0x20c2
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#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
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#define mmDCIO_IMPCAL_CNTL_EF 0x20c3
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#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
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#define mmUNIPHY_IMPCAL_PSW_EF 0x20c4
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#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
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#define mmUNIPHYLPA_LINK_CNTL 0x20c5
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#define mmUNIPHYLPA_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYLPB_LINK_CNTL 0x20c6
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#define mmUNIPHYLPB_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x20c7
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#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x20c8
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#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmDCIO_DPCS_TX_INTERRUPT 0x20c9
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#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
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#define mmDCIO_DPCS_RX_INTERRUPT 0x20ca
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#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
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#define mmDCIO_SEMAPHORE0 0x20cb
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#define mmDCIO_SEMAPHORE0_BASE_IDX 2
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#define mmDCIO_SEMAPHORE1 0x20cc
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#define mmDCIO_SEMAPHORE1_BASE_IDX 2
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#define mmDCIO_SEMAPHORE2 0x20cd
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#define mmDCIO_SEMAPHORE2_BASE_IDX 2
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#define mmDCIO_SEMAPHORE3 0x20ce
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#define mmDCIO_SEMAPHORE3_BASE_IDX 2
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#define mmDCIO_SEMAPHORE4 0x20cf
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#define mmDCIO_SEMAPHORE4_BASE_IDX 2
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#define mmDCIO_SEMAPHORE5 0x20d0
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#define mmDCIO_SEMAPHORE5_BASE_IDX 2
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#define mmDCIO_SEMAPHORE6 0x20d1
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#define mmDCIO_SEMAPHORE6_BASE_IDX 2
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#define mmDCIO_SEMAPHORE7 0x20d2
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#define mmDCIO_SEMAPHORE7_BASE_IDX 2
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#define mmDC_GPIO_GENERIC_MASK 0x20de
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#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
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#define mmDC_GPIO_GENERIC_A 0x20df
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#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
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#define mmDC_GPIO_GENERIC_EN 0x20e0
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#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
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#define mmDC_GPIO_GENERIC_Y 0x20e1
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#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
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#define mmDC_GPIO_DVODATA_MASK 0x20e2
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#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
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#define mmDC_GPIO_DVODATA_A 0x20e3
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#define mmDC_GPIO_DVODATA_A_BASE_IDX 2
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#define mmDC_GPIO_DVODATA_EN 0x20e4
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#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
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#define mmDC_GPIO_DVODATA_Y 0x20e5
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#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC1_MASK 0x20e6
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#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC1_A 0x20e7
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#define mmDC_GPIO_DDC1_A_BASE_IDX 2
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#define mmDC_GPIO_DDC1_EN 0x20e8
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#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC1_Y 0x20e9
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#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC2_MASK 0x20ea
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#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC2_A 0x20eb
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#define mmDC_GPIO_DDC2_A_BASE_IDX 2
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#define mmDC_GPIO_DDC2_EN 0x20ec
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#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC2_Y 0x20ed
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#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC3_MASK 0x20ee
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#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC3_A 0x20ef
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#define mmDC_GPIO_DDC3_A_BASE_IDX 2
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#define mmDC_GPIO_DDC3_EN 0x20f0
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#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC3_Y 0x20f1
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#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC4_MASK 0x20f2
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#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC4_A 0x20f3
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#define mmDC_GPIO_DDC4_A_BASE_IDX 2
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#define mmDC_GPIO_DDC4_EN 0x20f4
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#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC4_Y 0x20f5
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#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC5_MASK 0x20f6
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#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC5_A 0x20f7
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#define mmDC_GPIO_DDC5_A_BASE_IDX 2
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#define mmDC_GPIO_DDC5_EN 0x20f8
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#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC5_Y 0x20f9
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#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC6_MASK 0x20fa
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#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC6_A 0x20fb
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#define mmDC_GPIO_DDC6_A_BASE_IDX 2
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#define mmDC_GPIO_DDC6_EN 0x20fc
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#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC6_Y 0x20fd
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#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_MASK 0x20fe
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#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_A 0x20ff
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#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_EN 0x2100
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#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_Y 0x2101
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#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
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#define mmDC_GPIO_SYNCA_MASK 0x2102
|
#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
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#define mmDC_GPIO_SYNCA_A 0x2103
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#define mmDC_GPIO_SYNCA_A_BASE_IDX 2
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#define mmDC_GPIO_SYNCA_EN 0x2104
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#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
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#define mmDC_GPIO_SYNCA_Y 0x2105
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#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
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#define mmDC_GPIO_GENLK_MASK 0x2106
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#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
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#define mmDC_GPIO_GENLK_A 0x2107
|
#define mmDC_GPIO_GENLK_A_BASE_IDX 2
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#define mmDC_GPIO_GENLK_EN 0x2108
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#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
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#define mmDC_GPIO_GENLK_Y 0x2109
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#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
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#define mmDC_GPIO_HPD_MASK 0x210a
|
#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
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#define mmDC_GPIO_HPD_A 0x210b
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#define mmDC_GPIO_HPD_A_BASE_IDX 2
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#define mmDC_GPIO_HPD_EN 0x210c
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#define mmDC_GPIO_HPD_EN_BASE_IDX 2
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#define mmDC_GPIO_HPD_Y 0x210d
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#define mmDC_GPIO_HPD_Y_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_MASK 0x210e
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#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_A 0x210f
|
#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_EN 0x2110
|
#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_Y 0x2111
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#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
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#define mmDC_GPIO_PAD_STRENGTH_1 0x2112
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#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
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#define mmDC_GPIO_PAD_STRENGTH_2 0x2113
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#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
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#define mmPHY_AUX_CNTL 0x2115
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#define mmPHY_AUX_CNTL_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_MASK 0x2116
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#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_A 0x2117
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#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_EN 0x2118
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#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_Y 0x2119
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#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_STRENGTH 0x211a
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#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
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#define mmDVO_STRENGTH_CONTROL 0x211b
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#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
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#define mmDVO_VREF_CONTROL 0x211c
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#define mmDVO_VREF_CONTROL_BASE_IDX 2
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#define mmDVO_SKEW_ADJUST 0x211d
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#define mmDVO_SKEW_ADJUST_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_MASK 0x2126
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#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_A 0x2127
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#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_EN 0x2128
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#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_Y 0x2129
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#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x212a
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#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
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#define mmDC_GPIO_TX12_EN 0x212b
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#define mmDC_GPIO_TX12_EN_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_0 0x212c
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#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_1 0x212d
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#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_2 0x212e
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#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
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#define mmDC_GPIO_RXEN 0x212f
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#define mmDC_GPIO_RXEN_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_3 0x2130
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#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_4 0x2131
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#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_5 0x2132
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#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
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#define mmAUXI2C_PAD_ALL_PWR_OK 0x2133
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#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
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#define mmDC_GPIO_PULLUPEN 0x2134
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#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_6 0x2135
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#define mmDC_GPIO_AUX_CTRL_6_BASE_IDX 2
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#define mmBPHYC_DAC_MACRO_CNTL 0x2136
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#define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX 2
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#define mmDAC_MACRO_CNTL_RESERVED0 0x2136
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#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x2137
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#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_BASE_IDX 2
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#define mmDAC_MACRO_CNTL_RESERVED1 0x2137
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#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDAC_MACRO_CNTL_RESERVED2 0x2138
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#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDAC_MACRO_CNTL_RESERVED3 0x2139
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#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDISP_DSI_DUAL_CTRL 0x277e
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#define mmDISP_DSI_DUAL_CTRL_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED0 0x283e
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#define mmDPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED1 0x283f
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#define mmDPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED2 0x2840
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#define mmDPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED3 0x2841
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#define mmDPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED4 0x2842
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#define mmDPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED5 0x2843
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#define mmDPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED6 0x2844
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#define mmDPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED7 0x2845
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#define mmDPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED8 0x2846
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#define mmDPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED9 0x2847
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#define mmDPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED10 0x2848
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#define mmDPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED11 0x2849
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#define mmDPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED12 0x284a
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#define mmDPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED13 0x284b
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#define mmDPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED14 0x284c
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#define mmDPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED15 0x284d
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#define mmDPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED16 0x284e
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#define mmDPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED17 0x284f
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#define mmDPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED18 0x2850
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#define mmDPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED19 0x2851
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#define mmDPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED20 0x2852
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#define mmDPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED21 0x2853
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#define mmDPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED22 0x2854
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#define mmDPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED23 0x2855
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#define mmDPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED24 0x2856
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#define mmDPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED25 0x2857
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#define mmDPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED26 0x2858
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#define mmDPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED27 0x2859
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#define mmDPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED28 0x285a
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#define mmDPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED29 0x285b
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#define mmDPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED30 0x285c
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#define mmDPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED31 0x285d
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#define mmDPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED32 0x285e
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#define mmDPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED33 0x285f
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#define mmDPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED34 0x2860
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#define mmDPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED35 0x2861
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#define mmDPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED36 0x2862
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#define mmDPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED37 0x2863
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#define mmDPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED38 0x2864
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#define mmDPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED39 0x2865
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#define mmDPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED40 0x2866
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#define mmDPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED41 0x2867
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#define mmDPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED42 0x2868
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#define mmDPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED43 0x2869
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#define mmDPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED44 0x286a
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#define mmDPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED45 0x286b
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#define mmDPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED46 0x286c
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#define mmDPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED47 0x286d
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#define mmDPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED48 0x286e
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#define mmDPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED49 0x286f
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#define mmDPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED50 0x2870
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#define mmDPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED51 0x2871
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#define mmDPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED52 0x2872
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#define mmDPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED53 0x2873
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#define mmDPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED54 0x2874
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#define mmDPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED55 0x2875
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#define mmDPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED56 0x2876
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#define mmDPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED57 0x2877
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#define mmDPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED58 0x2878
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#define mmDPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED59 0x2879
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#define mmDPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED60 0x287a
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#define mmDPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED61 0x287b
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#define mmDPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED62 0x287c
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#define mmDPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDPHY_MACRO_CNTL_RESERVED63 0x287d
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#define mmDPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDPRX_AUX_REFERENCE_PULSE_DIV 0x2a7e
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#define mmDPRX_AUX_REFERENCE_PULSE_DIV_BASE_IDX 2
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#define mmDPRX_AUX_CONTROL 0x2a7f
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#define mmDPRX_AUX_CONTROL_BASE_IDX 2
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#define mmDPRX_AUX_HPD_CONTROL1 0x2a80
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#define mmDPRX_AUX_HPD_CONTROL1_BASE_IDX 2
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#define mmDPRX_AUX_HPD_CONTROL2 0x2a81
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#define mmDPRX_AUX_HPD_CONTROL2_BASE_IDX 2
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#define mmDPRX_AUX_RX_STATUS 0x2a82
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#define mmDPRX_AUX_RX_STATUS_BASE_IDX 2
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#define mmDPRX_AUX_RX_ERROR_MASK 0x2a83
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#define mmDPRX_AUX_RX_ERROR_MASK_BASE_IDX 2
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#define mmDPRX_AUX_DPHY_TX_REF_CONTROL 0x2a84
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#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDPRX_AUX_DPHY_TX_CONTROL 0x2a85
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#define mmDPRX_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDPRX_AUX_DPHY_RX_CONTROL0 0x2a86
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#define mmDPRX_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDPRX_AUX_DPHY_RX_CONTROL1 0x2a87
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#define mmDPRX_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDPRX_AUX_DPHY_TX_STATUS 0x2a88
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#define mmDPRX_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDPRX_AUX_DPHY_RX_STATUS 0x2a89
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#define mmDPRX_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDPRX_AUX_DMCU_HW_INT_STATUS 0x2a8a
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#define mmDPRX_AUX_DMCU_HW_INT_STATUS_BASE_IDX 2
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#define mmDPRX_AUX_DMCU_HW_INT_ACK 0x2a8b
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#define mmDPRX_AUX_DMCU_HW_INT_ACK_BASE_IDX 2
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#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1 0x2a8c
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#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_BASE_IDX 2
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#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2 0x2a8d
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#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_BASE_IDX 2
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#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1 0x2a8e
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#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_BASE_IDX 2
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#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2 0x2a8f
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#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_BASE_IDX 2
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#define mmDPRX_AUX_AUX_BUF_INDEX 0x2a90
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#define mmDPRX_AUX_AUX_BUF_INDEX_BASE_IDX 2
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#define mmDPRX_AUX_AUX_BUF_DATA 0x2a91
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#define mmDPRX_AUX_AUX_BUF_DATA_BASE_IDX 2
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#define mmDPRX_AUX_EDID_INDEX 0x2a92
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#define mmDPRX_AUX_EDID_INDEX_BASE_IDX 2
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#define mmDPRX_AUX_EDID_DATA 0x2a93
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#define mmDPRX_AUX_EDID_DATA_BASE_IDX 2
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#define mmDPRX_AUX_DPCD_INDEX1 0x2a94
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#define mmDPRX_AUX_DPCD_INDEX1_BASE_IDX 2
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#define mmDPRX_AUX_DPCD_DATA1 0x2a95
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#define mmDPRX_AUX_DPCD_DATA1_BASE_IDX 2
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#define mmDPRX_AUX_DPCD_INDEX2 0x2a96
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#define mmDPRX_AUX_DPCD_INDEX2_BASE_IDX 2
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#define mmDPRX_AUX_DPCD_DATA2 0x2a97
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#define mmDPRX_AUX_DPCD_DATA2_BASE_IDX 2
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#define mmDPRX_AUX_MSG_INDEX1 0x2a98
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#define mmDPRX_AUX_MSG_INDEX1_BASE_IDX 2
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#define mmDPRX_AUX_MSG_DATA1 0x2a99
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#define mmDPRX_AUX_MSG_DATA1_BASE_IDX 2
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#define mmDPRX_AUX_MSG_INDEX2 0x2a9a
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#define mmDPRX_AUX_MSG_INDEX2_BASE_IDX 2
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#define mmDPRX_AUX_MSG_DATA2 0x2a9b
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#define mmDPRX_AUX_MSG_DATA2_BASE_IDX 2
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#define mmDPRX_AUX_KSV_INDEX1 0x2a9c
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#define mmDPRX_AUX_KSV_INDEX1_BASE_IDX 2
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#define mmDPRX_AUX_KSV_DATA1 0x2a9d
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#define mmDPRX_AUX_KSV_DATA1_BASE_IDX 2
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#define mmDPRX_AUX_KSV_INDEX2 0x2a9e
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#define mmDPRX_AUX_KSV_INDEX2_BASE_IDX 2
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#define mmDPRX_AUX_KSV_DATA2 0x2a9f
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#define mmDPRX_AUX_KSV_DATA2_BASE_IDX 2
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#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL 0x2aa0
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#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_BASE_IDX 2
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#define mmDPRX_AUX_MSG_BUF_CONTROL1 0x2aa1
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#define mmDPRX_AUX_MSG_BUF_CONTROL1_BASE_IDX 2
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#define mmDPRX_AUX_MSG_BUF_CONTROL2 0x2aa2
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#define mmDPRX_AUX_MSG_BUF_CONTROL2_BASE_IDX 2
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#define mmDPRX_AUX_SCRATCH1 0x2aa3
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#define mmDPRX_AUX_SCRATCH1_BASE_IDX 2
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#define mmDPRX_AUX_SCRATCH2 0x2aa4
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#define mmDPRX_AUX_SCRATCH2_BASE_IDX 2
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#define mmDPRX_AUX_MSG1_PENDING 0x2aa5
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#define mmDPRX_AUX_MSG1_PENDING_BASE_IDX 2
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#define mmDPRX_AUX_MSG2_PENDING 0x2aa6
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#define mmDPRX_AUX_MSG2_PENDING_BASE_IDX 2
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#define mmDPRX_AUX_MSG3_PENDING 0x2aa7
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#define mmDPRX_AUX_MSG3_PENDING_BASE_IDX 2
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#define mmDPRX_AUX_MSG4_PENDING 0x2aa8
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#define mmDPRX_AUX_MSG4_PENDING_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET 0x2afe
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#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET 0x2aff
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#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_MSTM_CTRL 0x2b00
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#define mmDPRX_DPHY_DPCD_MSTM_CTRL_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET 0x2b01
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS 0x2b02
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET 0x2b03
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS 0x2b04
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET 0x2b05
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS 0x2b06
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET 0x2b07
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_BASE_IDX 2
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS 0x2b08
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#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_READY 0x2b09
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#define mmDPRX_DPHY_READY_BASE_IDX 2
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#define mmDPRX_DPHY_COMMA_STATUS 0x2b0b
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#define mmDPRX_DPHY_COMMA_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED 0x2b0c
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#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_BASE_IDX 2
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#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED 0x2b0d
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#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0 0x2b0f
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#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0 0x2b11
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#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0 0x2b12
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#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0 0x2b13
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#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1 0x2b14
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#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1 0x2b16
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#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1 0x2b17
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#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1 0x2b18
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#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2 0x2b19
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#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2 0x2b1b
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#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2 0x2b1c
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#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2 0x2b1d
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#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3 0x2b1e
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#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3 0x2b20
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#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3 0x2b21
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#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_BASE_IDX 2
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#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3 0x2b22
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#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_BASE_IDX 2
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#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL 0x2b24
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#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_BASE_IDX 2
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#define mmDPRX_DPHY_SR_ERROR_COUNT_A 0x2b25
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#define mmDPRX_DPHY_SR_ERROR_COUNT_A_BASE_IDX 2
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#define mmDPRX_DPHY_BS_ERROR_COUNT_A 0x2b27
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#define mmDPRX_DPHY_BS_ERROR_COUNT_A_BASE_IDX 2
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#define mmDPRX_DPHY_BS_ERROR_COUNT_B 0x2b28
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#define mmDPRX_DPHY_BS_ERROR_COUNT_B_BASE_IDX 2
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#define mmDPRX_DPHY_LANESETUP0 0x2b2d
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#define mmDPRX_DPHY_LANESETUP0_BASE_IDX 2
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#define mmDPRX_DPHY_LANESETUP1 0x2b2e
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#define mmDPRX_DPHY_LANESETUP1_BASE_IDX 2
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#define mmDPRX_DPHY_LFSRADV 0x2b31
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#define mmDPRX_DPHY_LFSRADV_BASE_IDX 2
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#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT 0x2b32
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#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_BASE_IDX 2
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#define mmDPRX_DPHY_SET_ENABLE 0x2b33
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#define mmDPRX_DPHY_SET_ENABLE_BASE_IDX 2
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#define mmDPRX_DPHY_ECF_LSB 0x2b34
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#define mmDPRX_DPHY_ECF_LSB_BASE_IDX 2
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#define mmDPRX_DPHY_ECF_MSB 0x2b35
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#define mmDPRX_DPHY_ECF_MSB_BASE_IDX 2
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#define mmDPRX_DPHY_ENHANCED_FRAME_EN 0x2b36
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#define mmDPRX_DPHY_ENHANCED_FRAME_EN_BASE_IDX 2
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#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE 0x2b3c
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#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_BASE_IDX 2
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#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA 0x2b3d
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#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_BASE_IDX 2
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#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL 0x2b3e
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#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_BASE_IDX 2
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#define mmDPRX_DPHY_BYPASS 0x2b3f
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#define mmDPRX_DPHY_BYPASS_BASE_IDX 2
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#define mmDPRX_DPHY_INT_RESET 0x2b40
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#define mmDPRX_DPHY_INT_RESET_BASE_IDX 2
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#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS 0x2b41
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#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS 0x2b43
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#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS 0x2b44
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#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS 0x2b46
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#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS 0x2b48
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#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS 0x2b49
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#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS 0x2b4a
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#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS 0x2b4b
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#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS 0x2b4c
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#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_BASE_IDX 2
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#define mmDPRX_DPHY_SPARE 0x2b4d
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#define mmDPRX_DPHY_SPARE_BASE_IDX 2
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#define mmDCRX_GATE_DISABLE_CNTL 0x2b6e
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#define mmDCRX_GATE_DISABLE_CNTL_BASE_IDX 2
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#define mmDCRX_SOFT_RESET 0x2b6f
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#define mmDCRX_SOFT_RESET_BASE_IDX 2
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#define mmDCRX_LIGHT_SLEEP_CNTL 0x2b70
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#define mmDCRX_LIGHT_SLEEP_CNTL_BASE_IDX 2
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#define mmDCRX_DISPCLK_GATE_CNTL 0x2b73
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#define mmDCRX_DISPCLK_GATE_CNTL_BASE_IDX 2
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#define mmDCRX_CLK_CNTL 0x2b74
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#define mmDCRX_CLK_CNTL_BASE_IDX 2
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#define mmDCRX_TEST_CLK_CNTL 0x2b75
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#define mmDCRX_TEST_CLK_CNTL_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x2c06
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x2c07
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x2c08
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x2c09
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x2c0a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x2c0b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x2c0c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x2c0d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x2c0e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x2c0f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x2c10
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x2c11
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x2c12
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x2c13
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x2c14
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x2c15
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x2c16
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x2c17
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x2c18
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x2c19
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x2c1a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x2c1b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x2c1c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x2c1d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x2c1e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x2c1f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x2c20
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x2c21
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x2c22
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x2c23
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x2c24
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x2c25
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x2c26
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x2c27
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x2c28
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x2c29
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x2c2a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x2c2b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x2c2c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x2c2d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x2c2e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x2c2f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x2c30
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x2c31
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x2c32
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x2c33
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x2c34
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x2c35
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x2c36
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x2c37
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x2c38
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x2c39
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x2c3a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x2c3b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x2c3c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x2c3d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x2c3e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x2c3f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x2c40
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x2c41
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x2c42
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x2c43
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x2c44
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x2c45
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x2c46
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x2c47
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x2c48
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x2c49
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x2c4a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x2c4b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x2c4c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x2c4d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x2c4e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x2c4f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x2c50
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x2c51
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x2c52
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x2c53
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x2c54
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x2c55
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x2c56
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x2c57
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x2c58
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x2c59
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x2c5a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x2c5b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x2c5c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x2c5d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x2c5e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x2c5f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x2c60
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x2c61
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x2c62
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x2c63
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x2c64
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x2c65
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x2c66
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x2c67
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x2c68
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x2c69
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x2c6a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x2c6b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x2c6c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x2c6d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x2c6e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x2c6f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x2c70
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x2c71
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x2c72
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x2c73
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x2c74
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x2c75
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x2c76
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x2c77
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x2c78
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x2c79
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x2c7a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x2c7b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x2c7c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x2c7d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x2c7e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x2c7f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x2c80
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x2c81
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x2c82
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x2c83
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x2c84
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x2c85
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x2c86
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x2c87
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x2c88
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x2c89
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x2c8a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x2c8b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x2c8c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x2c8d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x2c8e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x2c8f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x2c90
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x2c91
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x2c92
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x2c93
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x2c94
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x2c95
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x2c96
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x2c97
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x2c98
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x2c99
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x2c9a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x2c9b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x2c9c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x2c9d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x2c9e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x2c9f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x2ca0
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x2ca1
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x2ca2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x2ca3
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x2ca4
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x2ca5
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x2ca6
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x2ca7
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x2ca8
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x2ca9
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x2caa
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x2cab
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x2cac
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x2cad
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x2cae
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x2caf
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x2cb0
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x2cb1
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x2cb2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x2cb3
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x2cb4
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x2cb5
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x2cb6
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x2cb7
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x2cb8
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x2cb9
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x2cba
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x2cbb
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x2cbc
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x2cbd
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x2cbe
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x2cbf
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x2cc0
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x2cc1
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x2cc2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x2cc3
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x2cc4
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x2cc5
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x2cc6
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x2cc7
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x2cc8
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x2cc9
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x2cca
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x2ccb
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x2ccc
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x2ccd
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x2cce
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x2ccf
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x2cd0
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x2cd1
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x2cd2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x2cd3
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x2cd4
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x2cd5
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x2cd6
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x2cd7
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x2cd8
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x2cd9
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x2cda
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x2cdb
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x2cdc
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x2cdd
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x2cde
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x2cdf
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x2ce0
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x2ce1
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x2ce2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x2ce3
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x2ce4
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x2ce5
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x2ce6
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x2ce7
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x2ce8
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x2ce9
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x2cea
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x2ceb
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x2cec
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x2ced
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x2cee
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x2cef
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x2cf0
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x2cf1
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x2cf2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x2cf3
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x2cf4
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x2cf5
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x2cf6
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x2cf7
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x2cf8
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x2cf9
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x2cfa
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x2cfb
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x2cfc
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x2cfd
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x2cfe
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x2cff
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x2d00
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x2d01
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x2d02
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x2d03
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x2d04
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x2d05
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x2d06
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x2d07
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x2d08
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x2d09
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x2d0a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x2d0b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x2d0c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x2d0d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x2d0e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x2d0f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x2d10
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x2d11
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x2d12
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x2d13
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x2d14
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x2d15
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x2d16
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x2d17
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x2d18
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x2d19
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x2d1a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x2d1b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x2d1c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x2d1d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x2d1e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x2d1f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x2d20
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x2d21
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x2d22
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x2d23
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x2d24
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x2d25
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x2d26
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x2d27
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x2d28
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x2d29
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x2d2a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x2d2b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x2d2c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x2d2d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x2d2e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x2d2f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x2d30
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x2d31
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x2d32
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x2d33
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x2d34
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x2d35
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x2d36
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x2d37
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x2d38
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x2d39
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x2d3a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x2d3b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x2d3c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x2d3d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x2d3e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x2d3f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x2d40
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x2d41
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x2d42
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x2d43
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x2d44
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x2d45
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x2d46
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x2d47
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x2d48
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x2d49
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x2d4a
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x2d4b
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x2d4c
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x2d4d
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x2d4e
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x2d4f
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x2d50
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x2d51
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x2d52
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x2d53
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x2d54
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x2d55
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x2d56
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x2d57
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x2d58
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x2d59
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x2d5a
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x2d5b
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x2d5c
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x2d5d
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x2d5e
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x2d5f
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x2d60
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x2d61
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x2d62
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x2d63
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x2d64
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x2d65
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x2d66
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x2d67
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x2d68
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x2d69
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x2d6a
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x2d6b
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x2d6c
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x2d6d
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x2d6e
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x2d6f
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x2d70
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x2d71
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x2d72
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x2d73
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x2d74
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_BASE_IDX 2
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x2d75
|
#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x2d76
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x2d77
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x2d78
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x2d79
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x2d7a
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x2d7b
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x2d7c
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x2d7d
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x2d7e
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x2d7f
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x2d80
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_BASE_IDX 2
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x2d81
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#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_BASE_IDX 2
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#define mmI2S0_CNTL 0x2d82
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#define mmI2S0_CNTL_BASE_IDX 2
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#define mmSPDIF0_CNTL 0x2d83
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#define mmSPDIF0_CNTL_BASE_IDX 2
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#define mmI2S1_CNTL 0x2d84
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#define mmI2S1_CNTL_BASE_IDX 2
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#define mmSPDIF1_CNTL 0x2d85
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#define mmSPDIF1_CNTL_BASE_IDX 2
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#define mmI2S0_STATUS 0x2d86
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#define mmI2S0_STATUS_BASE_IDX 2
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#define mmI2S1_STATUS 0x2d87
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#define mmI2S1_STATUS_BASE_IDX 2
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#define mmI2S0_CRC_TEST_CNTL 0x2d8a
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#define mmI2S0_CRC_TEST_CNTL_BASE_IDX 2
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#define mmI2S0_CRC_TEST_DATA_01 0x2d8b
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#define mmI2S0_CRC_TEST_DATA_01_BASE_IDX 2
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#define mmI2S0_CRC_TEST_DATA_23 0x2d8c
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#define mmI2S0_CRC_TEST_DATA_23_BASE_IDX 2
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#define mmI2S1_CRC_TEST_CNTL 0x2d8d
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#define mmI2S1_CRC_TEST_CNTL_BASE_IDX 2
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#define mmI2S1_CRC_TEST_DATA_0 0x2d8e
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#define mmI2S1_CRC_TEST_DATA_0_BASE_IDX 2
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#define mmSPDIF0_CRC_TEST_CNTL 0x2d8f
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#define mmSPDIF0_CRC_TEST_CNTL_BASE_IDX 2
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#define mmSPDIF0_CRC_TEST_DATA_0 0x2d90
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#define mmSPDIF0_CRC_TEST_DATA_0_BASE_IDX 2
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#define mmSPDIF1_CRC_TEST_CNTL 0x2d91
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#define mmSPDIF1_CRC_TEST_CNTL_BASE_IDX 2
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#define mmSPDIF1_CRC_TEST_DATA 0x2d92
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#define mmSPDIF1_CRC_TEST_DATA_BASE_IDX 2
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#define mmCRC_I2S_CONT_REPEAT_NUM 0x2d93
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#define mmCRC_I2S_CONT_REPEAT_NUM_BASE_IDX 2
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#define mmCRC_SPDIF_CONT_REPEAT_NUM 0x2d94
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#define mmCRC_SPDIF_CONT_REPEAT_NUM_BASE_IDX 2
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#define mmZCAL_MACRO_CNTL_RESERVED0 0x2d96
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#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmZCAL_MACRO_CNTL_RESERVED1 0x2d97
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#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmZCAL_MACRO_CNTL_RESERVED2 0x2d98
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#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmZCAL_MACRO_CNTL_RESERVED3 0x2d99
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#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmZCAL_MACRO_CNTL_RESERVED4 0x2d9a
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#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream0_dispdec
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// base address: 0x0
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#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x0458
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#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x0459
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#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream1_dispdec
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// base address: 0x8
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#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x045a
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#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x045b
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#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream2_dispdec
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// base address: 0x10
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#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x045c
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#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x045d
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#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream3_dispdec
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// base address: 0x18
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#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x045e
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#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x045f
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#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream4_dispdec
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// base address: 0x20
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#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0460
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#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0461
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#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream5_dispdec
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// base address: 0x28
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#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0462
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#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0463
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#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream6_dispdec
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// base address: 0x30
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#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x0464
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#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x0465
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#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream7_dispdec
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// base address: 0x38
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#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x0466
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#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x0467
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#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0endpoint0_dispdec
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// base address: 0x0
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0480
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0481
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0endpoint1_dispdec
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// base address: 0x18
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0486
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0487
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0endpoint2_dispdec
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// base address: 0x30
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x048c
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x048d
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0endpoint3_dispdec
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// base address: 0x48
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0492
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0493
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0endpoint4_dispdec
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// base address: 0x60
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0498
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0499
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0endpoint5_dispdec
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// base address: 0x78
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x049e
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x049f
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0endpoint6_dispdec
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// base address: 0x90
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04a4
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04a5
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0endpoint7_dispdec
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// base address: 0xa8
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x04aa
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x04ab
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream8_dispdec
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// base address: 0x320
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#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0520
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#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0521
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#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream9_dispdec
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// base address: 0x328
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#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0522
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#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0523
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#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream10_dispdec
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// base address: 0x330
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#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x0524
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#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x0525
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#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream11_dispdec
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// base address: 0x338
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#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x0526
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#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x0527
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#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream12_dispdec
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// base address: 0x340
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#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x0528
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#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x0529
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#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream13_dispdec
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// base address: 0x348
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#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x052a
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#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x052b
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#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream14_dispdec
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// base address: 0x350
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#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x052c
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#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x052d
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#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0stream15_dispdec
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// base address: 0x358
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#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x052e
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#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x052f
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#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0inputendpoint0_dispdec
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// base address: 0x0
|
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0534
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#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0535
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#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0inputendpoint1_dispdec
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// base address: 0x10
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0538
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0539
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0inputendpoint2_dispdec
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// base address: 0x20
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x053c
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x053d
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0inputendpoint3_dispdec
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// base address: 0x30
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0540
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0541
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0inputendpoint4_dispdec
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// base address: 0x40
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#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0544
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#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0545
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#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0inputendpoint5_dispdec
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// base address: 0x50
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#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0548
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#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0549
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#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0inputendpoint6_dispdec
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// base address: 0x60
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#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x054c
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#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x054d
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#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_azf0inputendpoint7_dispdec
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// base address: 0x70
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0550
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0551
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dcp0_dispdec
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// base address: 0x0
|
#define mmDCP0_GRPH_ENABLE 0x055a
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#define mmDCP0_GRPH_ENABLE_BASE_IDX 2
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#define mmDCP0_GRPH_CONTROL 0x055b
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#define mmDCP0_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x055c
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#define mmDCP0_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
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#define mmDCP0_GRPH_SWAP_CNTL 0x055d
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#define mmDCP0_GRPH_SWAP_CNTL_BASE_IDX 2
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#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x055e
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#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x055f
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#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP0_GRPH_PITCH 0x0560
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#define mmDCP0_GRPH_PITCH_BASE_IDX 2
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#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0561
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#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0562
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#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x0563
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#define mmDCP0_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
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#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x0564
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#define mmDCP0_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
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#define mmDCP0_GRPH_X_START 0x0565
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#define mmDCP0_GRPH_X_START_BASE_IDX 2
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#define mmDCP0_GRPH_Y_START 0x0566
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#define mmDCP0_GRPH_Y_START_BASE_IDX 2
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#define mmDCP0_GRPH_X_END 0x0567
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#define mmDCP0_GRPH_X_END_BASE_IDX 2
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#define mmDCP0_GRPH_Y_END 0x0568
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#define mmDCP0_GRPH_Y_END_BASE_IDX 2
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#define mmDCP0_INPUT_GAMMA_CONTROL 0x0569
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#define mmDCP0_INPUT_GAMMA_CONTROL_BASE_IDX 2
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#define mmDCP0_GRPH_UPDATE 0x056a
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#define mmDCP0_GRPH_UPDATE_BASE_IDX 2
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#define mmDCP0_GRPH_FLIP_CONTROL 0x056b
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#define mmDCP0_GRPH_FLIP_CONTROL_BASE_IDX 2
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#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x056c
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#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
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#define mmDCP0_GRPH_DFQ_CONTROL 0x056d
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#define mmDCP0_GRPH_DFQ_CONTROL_BASE_IDX 2
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#define mmDCP0_GRPH_DFQ_STATUS 0x056e
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#define mmDCP0_GRPH_DFQ_STATUS_BASE_IDX 2
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#define mmDCP0_GRPH_INTERRUPT_STATUS 0x056f
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#define mmDCP0_GRPH_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x0570
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#define mmDCP0_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0571
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#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
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#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x0572
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#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP0_GRPH_COMPRESS_PITCH 0x0573
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#define mmDCP0_GRPH_COMPRESS_PITCH_BASE_IDX 2
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#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0574
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#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0575
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#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
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#define mmDCP0_PRESCALE_GRPH_CONTROL 0x0576
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#define mmDCP0_PRESCALE_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x0577
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#define mmDCP0_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
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#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x0578
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#define mmDCP0_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
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#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x0579
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#define mmDCP0_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
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#define mmDCP0_INPUT_CSC_CONTROL 0x057a
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#define mmDCP0_INPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP0_INPUT_CSC_C11_C12 0x057b
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#define mmDCP0_INPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP0_INPUT_CSC_C13_C14 0x057c
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#define mmDCP0_INPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP0_INPUT_CSC_C21_C22 0x057d
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#define mmDCP0_INPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP0_INPUT_CSC_C23_C24 0x057e
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#define mmDCP0_INPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP0_INPUT_CSC_C31_C32 0x057f
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#define mmDCP0_INPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP0_INPUT_CSC_C33_C34 0x0580
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#define mmDCP0_INPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP0_OUTPUT_CSC_CONTROL 0x0581
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#define mmDCP0_OUTPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP0_OUTPUT_CSC_C11_C12 0x0582
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#define mmDCP0_OUTPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP0_OUTPUT_CSC_C13_C14 0x0583
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#define mmDCP0_OUTPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP0_OUTPUT_CSC_C21_C22 0x0584
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#define mmDCP0_OUTPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP0_OUTPUT_CSC_C23_C24 0x0585
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#define mmDCP0_OUTPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP0_OUTPUT_CSC_C31_C32 0x0586
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#define mmDCP0_OUTPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP0_OUTPUT_CSC_C33_C34 0x0587
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#define mmDCP0_OUTPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x0588
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#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x0589
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#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x058a
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#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x058b
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#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x058c
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#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x058d
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#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x058e
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#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x058f
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#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x0590
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#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x0591
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#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x0592
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#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x0593
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#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP0_DENORM_CONTROL 0x0594
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#define mmDCP0_DENORM_CONTROL_BASE_IDX 2
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#define mmDCP0_OUT_ROUND_CONTROL 0x0595
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#define mmDCP0_OUT_ROUND_CONTROL_BASE_IDX 2
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#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x0596
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#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
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#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x0597
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#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
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#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x0598
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#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
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#define mmDCP0_KEY_CONTROL 0x0599
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#define mmDCP0_KEY_CONTROL_BASE_IDX 2
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#define mmDCP0_KEY_RANGE_ALPHA 0x059a
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#define mmDCP0_KEY_RANGE_ALPHA_BASE_IDX 2
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#define mmDCP0_KEY_RANGE_RED 0x059b
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#define mmDCP0_KEY_RANGE_RED_BASE_IDX 2
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#define mmDCP0_KEY_RANGE_GREEN 0x059c
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#define mmDCP0_KEY_RANGE_GREEN_BASE_IDX 2
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#define mmDCP0_KEY_RANGE_BLUE 0x059d
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#define mmDCP0_KEY_RANGE_BLUE_BASE_IDX 2
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#define mmDCP0_DEGAMMA_CONTROL 0x059e
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#define mmDCP0_DEGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP0_GAMUT_REMAP_CONTROL 0x059f
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#define mmDCP0_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmDCP0_GAMUT_REMAP_C11_C12 0x05a0
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#define mmDCP0_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmDCP0_GAMUT_REMAP_C13_C14 0x05a1
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#define mmDCP0_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmDCP0_GAMUT_REMAP_C21_C22 0x05a2
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#define mmDCP0_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmDCP0_GAMUT_REMAP_C23_C24 0x05a3
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#define mmDCP0_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmDCP0_GAMUT_REMAP_C31_C32 0x05a4
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#define mmDCP0_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmDCP0_GAMUT_REMAP_C33_C34 0x05a5
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#define mmDCP0_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x05a6
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#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
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#define mmDCP0_DCP_RANDOM_SEEDS 0x05a7
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#define mmDCP0_DCP_RANDOM_SEEDS_BASE_IDX 2
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#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x05a8
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#define mmDCP0_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
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#define mmDCP0_CUR_CONTROL 0x05a9
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#define mmDCP0_CUR_CONTROL_BASE_IDX 2
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#define mmDCP0_CUR_SURFACE_ADDRESS 0x05aa
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#define mmDCP0_CUR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP0_CUR_SIZE 0x05ab
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#define mmDCP0_CUR_SIZE_BASE_IDX 2
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#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x05ac
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#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP0_CUR_POSITION 0x05ad
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#define mmDCP0_CUR_POSITION_BASE_IDX 2
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#define mmDCP0_CUR_HOT_SPOT 0x05ae
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#define mmDCP0_CUR_HOT_SPOT_BASE_IDX 2
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#define mmDCP0_CUR_COLOR1 0x05af
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#define mmDCP0_CUR_COLOR1_BASE_IDX 2
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#define mmDCP0_CUR_COLOR2 0x05b0
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#define mmDCP0_CUR_COLOR2_BASE_IDX 2
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#define mmDCP0_CUR_UPDATE 0x05b1
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#define mmDCP0_CUR_UPDATE_BASE_IDX 2
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#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x05bb
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#define mmDCP0_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
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#define mmDCP0_CUR_STEREO_CONTROL 0x05bc
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#define mmDCP0_CUR_STEREO_CONTROL_BASE_IDX 2
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#define mmDCP0_DC_LUT_RW_MODE 0x05be
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#define mmDCP0_DC_LUT_RW_MODE_BASE_IDX 2
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#define mmDCP0_DC_LUT_RW_INDEX 0x05bf
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#define mmDCP0_DC_LUT_RW_INDEX_BASE_IDX 2
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#define mmDCP0_DC_LUT_SEQ_COLOR 0x05c0
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#define mmDCP0_DC_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmDCP0_DC_LUT_PWL_DATA 0x05c1
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#define mmDCP0_DC_LUT_PWL_DATA_BASE_IDX 2
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#define mmDCP0_DC_LUT_30_COLOR 0x05c2
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#define mmDCP0_DC_LUT_30_COLOR_BASE_IDX 2
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#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x05c3
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#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
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#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x05c4
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#define mmDCP0_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP0_DC_LUT_AUTOFILL 0x05c5
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#define mmDCP0_DC_LUT_AUTOFILL_BASE_IDX 2
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#define mmDCP0_DC_LUT_CONTROL 0x05c6
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#define mmDCP0_DC_LUT_CONTROL_BASE_IDX 2
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#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x05c7
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#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x05c8
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#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x05c9
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#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
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#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x05ca
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#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x05cb
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#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x05cc
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#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
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#define mmDCP0_DCP_CRC_CONTROL 0x05cd
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#define mmDCP0_DCP_CRC_CONTROL_BASE_IDX 2
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#define mmDCP0_DCP_CRC_MASK 0x05ce
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#define mmDCP0_DCP_CRC_MASK_BASE_IDX 2
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#define mmDCP0_DCP_CRC_CURRENT 0x05cf
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#define mmDCP0_DCP_CRC_CURRENT_BASE_IDX 2
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#define mmDCP0_DVMM_PTE_CONTROL 0x05d0
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#define mmDCP0_DVMM_PTE_CONTROL_BASE_IDX 2
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#define mmDCP0_DCP_CRC_LAST 0x05d1
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#define mmDCP0_DCP_CRC_LAST_BASE_IDX 2
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#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x05d2
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#define mmDCP0_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
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#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x05d4
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#define mmDCP0_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
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#define mmDCP0_DCP_GSL_CONTROL 0x05d5
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#define mmDCP0_DCP_GSL_CONTROL_BASE_IDX 2
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#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x05d6
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#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
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#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x05dc
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#define mmDCP0_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
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#define mmDCP0_HW_ROTATION 0x05de
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#define mmDCP0_HW_ROTATION_BASE_IDX 2
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#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x05df
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#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
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#define mmDCP0_REGAMMA_CONTROL 0x05e0
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#define mmDCP0_REGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP0_REGAMMA_LUT_INDEX 0x05e1
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#define mmDCP0_REGAMMA_LUT_INDEX_BASE_IDX 2
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#define mmDCP0_REGAMMA_LUT_DATA 0x05e2
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#define mmDCP0_REGAMMA_LUT_DATA_BASE_IDX 2
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#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x05e3
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#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x05e4
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#define mmDCP0_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x05e5
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#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x05e6
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#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x05e7
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#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x05e8
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#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x05e9
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#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x05ea
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#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x05eb
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#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x05ec
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#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x05ed
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#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x05ee
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#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x05ef
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#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x05f0
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#define mmDCP0_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x05f1
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#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x05f2
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#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x05f3
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#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x05f4
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#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x05f5
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#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x05f6
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#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x05f7
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#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x05f8
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#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x05f9
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#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x05fa
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#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
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#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x05fb
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#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
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#define mmDCP0_ALPHA_CONTROL 0x05fc
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#define mmDCP0_ALPHA_CONTROL_BASE_IDX 2
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#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x05fd
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#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x05fe
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#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x05ff
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#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
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#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT 0x0600
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#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
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#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY 0x0601
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#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
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#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x0602
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#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
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#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x0603
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#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
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// addressBlock: dce_dc_lb0_dispdec
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// base address: 0x0
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#define mmLB0_LB_DATA_FORMAT 0x061a
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#define mmLB0_LB_DATA_FORMAT_BASE_IDX 2
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#define mmLB0_LB_MEMORY_CTRL 0x061b
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#define mmLB0_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmLB0_LB_MEMORY_SIZE_STATUS 0x061c
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#define mmLB0_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
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#define mmLB0_LB_DESKTOP_HEIGHT 0x061d
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#define mmLB0_LB_DESKTOP_HEIGHT_BASE_IDX 2
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#define mmLB0_LB_VLINE_START_END 0x061e
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#define mmLB0_LB_VLINE_START_END_BASE_IDX 2
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#define mmLB0_LB_VLINE2_START_END 0x061f
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#define mmLB0_LB_VLINE2_START_END_BASE_IDX 2
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#define mmLB0_LB_V_COUNTER 0x0620
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#define mmLB0_LB_V_COUNTER_BASE_IDX 2
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#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x0621
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#define mmLB0_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
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#define mmLB0_LB_INTERRUPT_MASK 0x0622
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#define mmLB0_LB_INTERRUPT_MASK_BASE_IDX 2
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#define mmLB0_LB_VLINE_STATUS 0x0623
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#define mmLB0_LB_VLINE_STATUS_BASE_IDX 2
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#define mmLB0_LB_VLINE2_STATUS 0x0624
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#define mmLB0_LB_VLINE2_STATUS_BASE_IDX 2
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#define mmLB0_LB_VBLANK_STATUS 0x0625
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#define mmLB0_LB_VBLANK_STATUS_BASE_IDX 2
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#define mmLB0_LB_SYNC_RESET_SEL 0x0626
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#define mmLB0_LB_SYNC_RESET_SEL_BASE_IDX 2
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#define mmLB0_LB_BLACK_KEYER_R_CR 0x0627
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#define mmLB0_LB_BLACK_KEYER_R_CR_BASE_IDX 2
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#define mmLB0_LB_BLACK_KEYER_G_Y 0x0628
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#define mmLB0_LB_BLACK_KEYER_G_Y_BASE_IDX 2
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#define mmLB0_LB_BLACK_KEYER_B_CB 0x0629
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#define mmLB0_LB_BLACK_KEYER_B_CB_BASE_IDX 2
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#define mmLB0_LB_KEYER_COLOR_CTRL 0x062a
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#define mmLB0_LB_KEYER_COLOR_CTRL_BASE_IDX 2
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#define mmLB0_LB_KEYER_COLOR_R_CR 0x062b
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#define mmLB0_LB_KEYER_COLOR_R_CR_BASE_IDX 2
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#define mmLB0_LB_KEYER_COLOR_G_Y 0x062c
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#define mmLB0_LB_KEYER_COLOR_G_Y_BASE_IDX 2
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#define mmLB0_LB_KEYER_COLOR_B_CB 0x062d
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#define mmLB0_LB_KEYER_COLOR_B_CB_BASE_IDX 2
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#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x062e
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#define mmLB0_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
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#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x062f
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#define mmLB0_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
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#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x0630
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#define mmLB0_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
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#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x0631
|
#define mmLB0_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
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#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x0632
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#define mmLB0_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
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#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x0633
|
#define mmLB0_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
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#define mmLB0_LB_BUFFER_STATUS 0x0634
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#define mmLB0_LB_BUFFER_STATUS_BASE_IDX 2
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#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x0635
|
#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
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#define mmLB0_MVP_AFR_FLIP_MODE 0x0636
|
#define mmLB0_MVP_AFR_FLIP_MODE_BASE_IDX 2
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#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x0637
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#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
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#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x0638
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#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
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#define mmLB0_DC_MVP_LB_CONTROL 0x0639
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#define mmLB0_DC_MVP_LB_CONTROL_BASE_IDX 2
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|
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// addressBlock: dce_dc_dcfe0_dispdec
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// base address: 0x0
|
#define mmDCFE0_DCFE_CLOCK_CONTROL 0x065a
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#define mmDCFE0_DCFE_CLOCK_CONTROL_BASE_IDX 2
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#define mmDCFE0_DCFE_SOFT_RESET 0x065b
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#define mmDCFE0_DCFE_SOFT_RESET_BASE_IDX 2
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#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x065d
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#define mmDCFE0_DCFE_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x065e
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#define mmDCFE0_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x065f
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#define mmDCFE0_DCFE_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFE0_DCFE_MISC 0x0660
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#define mmDCFE0_DCFE_MISC_BASE_IDX 2
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#define mmDCFE0_DCFE_FLUSH 0x0661
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#define mmDCFE0_DCFE_FLUSH_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon3_dispdec
|
// base address: 0x1938
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#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x066e
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#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x066f
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#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0670
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#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_CNTL 0x0671
|
#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_CNTL2 0x0672
|
#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0673
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#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0674
|
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_HI 0x0675
|
#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_LOW 0x0676
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#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dmif_pg0_dispdec
|
// base address: 0x0
|
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x067a
|
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
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#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x067b
|
#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x067c
|
#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
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#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x067d
|
#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
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#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL 0x067e
|
#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
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#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x067f
|
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
|
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2 0x0680
|
#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
|
#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL 0x0681
|
#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
|
#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x0682
|
#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_BASE_IDX 2
|
#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x0686
|
#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
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#define mmDMIF_PG0_DPG_DVMM_STATUS 0x0687
|
#define mmDMIF_PG0_DPG_DVMM_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_scl0_dispdec
|
// base address: 0x0
|
#define mmSCL0_SCL_COEF_RAM_SELECT 0x069a
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#define mmSCL0_SCL_COEF_RAM_SELECT_BASE_IDX 2
|
#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x069b
|
#define mmSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmSCL0_SCL_MODE 0x069c
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#define mmSCL0_SCL_MODE_BASE_IDX 2
|
#define mmSCL0_SCL_TAP_CONTROL 0x069d
|
#define mmSCL0_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmSCL0_SCL_CONTROL 0x069e
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#define mmSCL0_SCL_CONTROL_BASE_IDX 2
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#define mmSCL0_SCL_BYPASS_CONTROL 0x069f
|
#define mmSCL0_SCL_BYPASS_CONTROL_BASE_IDX 2
|
#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x06a0
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#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x06a1
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#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
|
#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x06a2
|
#define mmSCL0_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
|
#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x06a3
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#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmSCL0_SCL_HORZ_FILTER_INIT 0x06a4
|
#define mmSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
|
#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x06a5
|
#define mmSCL0_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
|
#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x06a6
|
#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmSCL0_SCL_VERT_FILTER_INIT 0x06a7
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#define mmSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
|
#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x06a8
|
#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
|
#define mmSCL0_SCL_ROUND_OFFSET 0x06a9
|
#define mmSCL0_SCL_ROUND_OFFSET_BASE_IDX 2
|
#define mmSCL0_SCL_UPDATE 0x06aa
|
#define mmSCL0_SCL_UPDATE_BASE_IDX 2
|
#define mmSCL0_SCL_F_SHARP_CONTROL 0x06ab
|
#define mmSCL0_SCL_F_SHARP_CONTROL_BASE_IDX 2
|
#define mmSCL0_SCL_ALU_CONTROL 0x06ac
|
#define mmSCL0_SCL_ALU_CONTROL_BASE_IDX 2
|
#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x06ad
|
#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
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#define mmSCL0_VIEWPORT_START_SECONDARY 0x06ae
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#define mmSCL0_VIEWPORT_START_SECONDARY_BASE_IDX 2
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#define mmSCL0_VIEWPORT_START 0x06af
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#define mmSCL0_VIEWPORT_START_BASE_IDX 2
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#define mmSCL0_VIEWPORT_SIZE 0x06b0
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#define mmSCL0_VIEWPORT_SIZE_BASE_IDX 2
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#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x06b1
|
#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x06b2
|
#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmSCL0_SCL_MODE_CHANGE_DET1 0x06b3
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#define mmSCL0_SCL_MODE_CHANGE_DET1_BASE_IDX 2
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#define mmSCL0_SCL_MODE_CHANGE_DET2 0x06b4
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#define mmSCL0_SCL_MODE_CHANGE_DET2_BASE_IDX 2
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#define mmSCL0_SCL_MODE_CHANGE_DET3 0x06b5
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#define mmSCL0_SCL_MODE_CHANGE_DET3_BASE_IDX 2
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#define mmSCL0_SCL_MODE_CHANGE_MASK 0x06b6
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#define mmSCL0_SCL_MODE_CHANGE_MASK_BASE_IDX 2
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|
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// addressBlock: dce_dc_blnd0_dispdec
|
// base address: 0x0
|
#define mmBLND0_BLND_CONTROL 0x06c7
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#define mmBLND0_BLND_CONTROL_BASE_IDX 2
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#define mmBLND0_BLND_SM_CONTROL2 0x06c8
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#define mmBLND0_BLND_SM_CONTROL2_BASE_IDX 2
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#define mmBLND0_BLND_CONTROL2 0x06c9
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#define mmBLND0_BLND_CONTROL2_BASE_IDX 2
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#define mmBLND0_BLND_UPDATE 0x06ca
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#define mmBLND0_BLND_UPDATE_BASE_IDX 2
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#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x06cb
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#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
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#define mmBLND0_BLND_V_UPDATE_LOCK 0x06cc
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#define mmBLND0_BLND_V_UPDATE_LOCK_BASE_IDX 2
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#define mmBLND0_BLND_REG_UPDATE_STATUS 0x06cd
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#define mmBLND0_BLND_REG_UPDATE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_crtc0_dispdec
|
// base address: 0x0
|
#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x06d2
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#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
|
#define mmCRTC0_CRTC_H_TOTAL 0x06d3
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#define mmCRTC0_CRTC_H_TOTAL_BASE_IDX 2
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#define mmCRTC0_CRTC_H_BLANK_START_END 0x06d4
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#define mmCRTC0_CRTC_H_BLANK_START_END_BASE_IDX 2
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#define mmCRTC0_CRTC_H_SYNC_A 0x06d5
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#define mmCRTC0_CRTC_H_SYNC_A_BASE_IDX 2
|
#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x06d6
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#define mmCRTC0_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC0_CRTC_H_SYNC_B 0x06d7
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#define mmCRTC0_CRTC_H_SYNC_B_BASE_IDX 2
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#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x06d8
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#define mmCRTC0_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC0_CRTC_VBI_END 0x06d9
|
#define mmCRTC0_CRTC_VBI_END_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_TOTAL 0x06da
|
#define mmCRTC0_CRTC_V_TOTAL_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_TOTAL_MIN 0x06db
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#define mmCRTC0_CRTC_V_TOTAL_MIN_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_TOTAL_MAX 0x06dc
|
#define mmCRTC0_CRTC_V_TOTAL_MAX_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x06dd
|
#define mmCRTC0_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x06de
|
#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x06df
|
#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_BLANK_START_END 0x06e0
|
#define mmCRTC0_CRTC_V_BLANK_START_END_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_SYNC_A 0x06e1
|
#define mmCRTC0_CRTC_V_SYNC_A_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x06e2
|
#define mmCRTC0_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_SYNC_B 0x06e3
|
#define mmCRTC0_CRTC_V_SYNC_B_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x06e4
|
#define mmCRTC0_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
|
#define mmCRTC0_CRTC_DTMTEST_CNTL 0x06e5
|
#define mmCRTC0_CRTC_DTMTEST_CNTL_BASE_IDX 2
|
#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x06e6
|
#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
|
#define mmCRTC0_CRTC_TRIGA_CNTL 0x06e7
|
#define mmCRTC0_CRTC_TRIGA_CNTL_BASE_IDX 2
|
#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x06e8
|
#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmCRTC0_CRTC_TRIGB_CNTL 0x06e9
|
#define mmCRTC0_CRTC_TRIGB_CNTL_BASE_IDX 2
|
#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x06ea
|
#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x06eb
|
#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
|
#define mmCRTC0_CRTC_FLOW_CONTROL 0x06ec
|
#define mmCRTC0_CRTC_FLOW_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x06ed
|
#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
|
#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x06ee
|
#define mmCRTC0_CRTC_AVSYNC_COUNTER_BASE_IDX 2
|
#define mmCRTC0_CRTC_CONTROL 0x06ef
|
#define mmCRTC0_CRTC_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_BLANK_CONTROL 0x06f0
|
#define mmCRTC0_CRTC_BLANK_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x06f1
|
#define mmCRTC0_CRTC_INTERLACE_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_INTERLACE_STATUS 0x06f2
|
#define mmCRTC0_CRTC_INTERLACE_STATUS_BASE_IDX 2
|
#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x06f3
|
#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x06f4
|
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
|
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x06f5
|
#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
|
#define mmCRTC0_CRTC_STATUS 0x06f6
|
#define mmCRTC0_CRTC_STATUS_BASE_IDX 2
|
#define mmCRTC0_CRTC_STATUS_POSITION 0x06f7
|
#define mmCRTC0_CRTC_STATUS_POSITION_BASE_IDX 2
|
#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x06f8
|
#define mmCRTC0_CRTC_NOM_VERT_POSITION_BASE_IDX 2
|
#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x06f9
|
#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
|
#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x06fa
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#define mmCRTC0_CRTC_STATUS_VF_COUNT_BASE_IDX 2
|
#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x06fb
|
#define mmCRTC0_CRTC_STATUS_HV_COUNT_BASE_IDX 2
|
#define mmCRTC0_CRTC_COUNT_CONTROL 0x06fc
|
#define mmCRTC0_CRTC_COUNT_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_COUNT_RESET 0x06fd
|
#define mmCRTC0_CRTC_COUNT_RESET_BASE_IDX 2
|
#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x06fe
|
#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
|
#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x06ff
|
#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_STEREO_STATUS 0x0700
|
#define mmCRTC0_CRTC_STEREO_STATUS_BASE_IDX 2
|
#define mmCRTC0_CRTC_STEREO_CONTROL 0x0701
|
#define mmCRTC0_CRTC_STEREO_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x0702
|
#define mmCRTC0_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x0703
|
#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x0704
|
#define mmCRTC0_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x0705
|
#define mmCRTC0_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
|
#define mmCRTC0_CRTC_START_LINE_CONTROL 0x0706
|
#define mmCRTC0_CRTC_START_LINE_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x0707
|
#define mmCRTC0_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_UPDATE_LOCK 0x0708
|
#define mmCRTC0_CRTC_UPDATE_LOCK_BASE_IDX 2
|
#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x0709
|
#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x070a
|
#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
|
#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x070b
|
#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
|
#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x070c
|
#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
|
#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x070d
|
#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
|
#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x070e
|
#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
|
#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x070f
|
#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
|
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x0710
|
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
|
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0711
|
#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
|
#define mmCRTC0_CRTC_MVP_STATUS 0x0712
|
#define mmCRTC0_CRTC_MVP_STATUS_BASE_IDX 2
|
#define mmCRTC0_CRTC_MASTER_EN 0x0713
|
#define mmCRTC0_CRTC_MASTER_EN_BASE_IDX 2
|
#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x0714
|
#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
|
#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x0715
|
#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
|
#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x0717
|
#define mmCRTC0_CRTC_OVERSCAN_COLOR_BASE_IDX 2
|
#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x0718
|
#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
|
#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x0719
|
#define mmCRTC0_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
|
#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x071a
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#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmCRTC0_CRTC_BLACK_COLOR 0x071b
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#define mmCRTC0_CRTC_BLACK_COLOR_BASE_IDX 2
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#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x071c
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#define mmCRTC0_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x071d
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x071e
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x071f
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0720
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0721
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0722
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#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC_CNTL 0x0723
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#define mmCRTC0_CRTC_CRC_CNTL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x0724
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#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0725
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#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x0726
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#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0727
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#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC0_DATA_RG 0x0728
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#define mmCRTC0_CRTC_CRC0_DATA_RG_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC0_DATA_B 0x0729
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#define mmCRTC0_CRTC_CRC0_DATA_B_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x072a
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#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x072b
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#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x072c
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#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x072d
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#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC1_DATA_RG 0x072e
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#define mmCRTC0_CRTC_CRC1_DATA_RG_BASE_IDX 2
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#define mmCRTC0_CRTC_CRC1_DATA_B 0x072f
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#define mmCRTC0_CRTC_CRC1_DATA_B_BASE_IDX 2
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x0730
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0731
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0732
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0733
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0734
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0735
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#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x0736
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#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x0737
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#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x0738
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#define mmCRTC0_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmCRTC0_CRTC_GSL_WINDOW 0x0739
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#define mmCRTC0_CRTC_GSL_WINDOW_BASE_IDX 2
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#define mmCRTC0_CRTC_GSL_CONTROL 0x073a
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#define mmCRTC0_CRTC_GSL_CONTROL_BASE_IDX 2
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#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS 0x073d
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#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmCRTC0_CRTC_DRR_CONTROL 0x073e
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#define mmCRTC0_CRTC_DRR_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_fmt0_dispdec
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// base address: 0x0
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#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x0742
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#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
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#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x0743
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#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x0744
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#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x0745
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#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
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#define mmFMT0_FMT_CONTROL 0x0746
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#define mmFMT0_FMT_CONTROL_BASE_IDX 2
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#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x0747
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#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x0748
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#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x0749
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#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x074a
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#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
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#define mmFMT0_FMT_CLAMP_CNTL 0x074e
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#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT0_FMT_CRC_CNTL 0x074f
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#define mmFMT0_FMT_CRC_CNTL_BASE_IDX 2
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#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x0750
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#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0751
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#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x0752
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#define mmFMT0_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
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#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x0753
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#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
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#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0754
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#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
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#define mmFMT0_FMT_420_HBLANK_EARLY_START 0x0755
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#define mmFMT0_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
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// addressBlock: dce_dc_dcp1_dispdec
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// base address: 0x800
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#define mmDCP1_GRPH_ENABLE 0x075a
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#define mmDCP1_GRPH_ENABLE_BASE_IDX 2
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#define mmDCP1_GRPH_CONTROL 0x075b
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#define mmDCP1_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x075c
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#define mmDCP1_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
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#define mmDCP1_GRPH_SWAP_CNTL 0x075d
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#define mmDCP1_GRPH_SWAP_CNTL_BASE_IDX 2
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#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x075e
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#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x075f
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#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP1_GRPH_PITCH 0x0760
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#define mmDCP1_GRPH_PITCH_BASE_IDX 2
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#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0761
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#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0762
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#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x0763
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#define mmDCP1_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
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#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x0764
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#define mmDCP1_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
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#define mmDCP1_GRPH_X_START 0x0765
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#define mmDCP1_GRPH_X_START_BASE_IDX 2
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#define mmDCP1_GRPH_Y_START 0x0766
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#define mmDCP1_GRPH_Y_START_BASE_IDX 2
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#define mmDCP1_GRPH_X_END 0x0767
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#define mmDCP1_GRPH_X_END_BASE_IDX 2
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#define mmDCP1_GRPH_Y_END 0x0768
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#define mmDCP1_GRPH_Y_END_BASE_IDX 2
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#define mmDCP1_INPUT_GAMMA_CONTROL 0x0769
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#define mmDCP1_INPUT_GAMMA_CONTROL_BASE_IDX 2
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#define mmDCP1_GRPH_UPDATE 0x076a
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#define mmDCP1_GRPH_UPDATE_BASE_IDX 2
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#define mmDCP1_GRPH_FLIP_CONTROL 0x076b
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#define mmDCP1_GRPH_FLIP_CONTROL_BASE_IDX 2
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#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x076c
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#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
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#define mmDCP1_GRPH_DFQ_CONTROL 0x076d
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#define mmDCP1_GRPH_DFQ_CONTROL_BASE_IDX 2
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#define mmDCP1_GRPH_DFQ_STATUS 0x076e
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#define mmDCP1_GRPH_DFQ_STATUS_BASE_IDX 2
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#define mmDCP1_GRPH_INTERRUPT_STATUS 0x076f
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#define mmDCP1_GRPH_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x0770
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#define mmDCP1_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0771
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#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
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#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x0772
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#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP1_GRPH_COMPRESS_PITCH 0x0773
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#define mmDCP1_GRPH_COMPRESS_PITCH_BASE_IDX 2
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#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0774
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#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0775
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#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
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#define mmDCP1_PRESCALE_GRPH_CONTROL 0x0776
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#define mmDCP1_PRESCALE_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x0777
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#define mmDCP1_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
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#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x0778
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#define mmDCP1_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
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#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x0779
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#define mmDCP1_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
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#define mmDCP1_INPUT_CSC_CONTROL 0x077a
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#define mmDCP1_INPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP1_INPUT_CSC_C11_C12 0x077b
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#define mmDCP1_INPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP1_INPUT_CSC_C13_C14 0x077c
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#define mmDCP1_INPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP1_INPUT_CSC_C21_C22 0x077d
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#define mmDCP1_INPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP1_INPUT_CSC_C23_C24 0x077e
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#define mmDCP1_INPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP1_INPUT_CSC_C31_C32 0x077f
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#define mmDCP1_INPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP1_INPUT_CSC_C33_C34 0x0780
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#define mmDCP1_INPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP1_OUTPUT_CSC_CONTROL 0x0781
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#define mmDCP1_OUTPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP1_OUTPUT_CSC_C11_C12 0x0782
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#define mmDCP1_OUTPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP1_OUTPUT_CSC_C13_C14 0x0783
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#define mmDCP1_OUTPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP1_OUTPUT_CSC_C21_C22 0x0784
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#define mmDCP1_OUTPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP1_OUTPUT_CSC_C23_C24 0x0785
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#define mmDCP1_OUTPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP1_OUTPUT_CSC_C31_C32 0x0786
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#define mmDCP1_OUTPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP1_OUTPUT_CSC_C33_C34 0x0787
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#define mmDCP1_OUTPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x0788
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#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x0789
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#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x078a
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#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x078b
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#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x078c
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#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x078d
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#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x078e
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#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x078f
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#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x0790
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#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x0791
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#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x0792
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#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x0793
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#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP1_DENORM_CONTROL 0x0794
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#define mmDCP1_DENORM_CONTROL_BASE_IDX 2
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#define mmDCP1_OUT_ROUND_CONTROL 0x0795
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#define mmDCP1_OUT_ROUND_CONTROL_BASE_IDX 2
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#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x0796
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#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
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#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x0797
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#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
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#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x0798
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#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
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#define mmDCP1_KEY_CONTROL 0x0799
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#define mmDCP1_KEY_CONTROL_BASE_IDX 2
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#define mmDCP1_KEY_RANGE_ALPHA 0x079a
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#define mmDCP1_KEY_RANGE_ALPHA_BASE_IDX 2
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#define mmDCP1_KEY_RANGE_RED 0x079b
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#define mmDCP1_KEY_RANGE_RED_BASE_IDX 2
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#define mmDCP1_KEY_RANGE_GREEN 0x079c
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#define mmDCP1_KEY_RANGE_GREEN_BASE_IDX 2
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#define mmDCP1_KEY_RANGE_BLUE 0x079d
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#define mmDCP1_KEY_RANGE_BLUE_BASE_IDX 2
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#define mmDCP1_DEGAMMA_CONTROL 0x079e
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#define mmDCP1_DEGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP1_GAMUT_REMAP_CONTROL 0x079f
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#define mmDCP1_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmDCP1_GAMUT_REMAP_C11_C12 0x07a0
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#define mmDCP1_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmDCP1_GAMUT_REMAP_C13_C14 0x07a1
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#define mmDCP1_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmDCP1_GAMUT_REMAP_C21_C22 0x07a2
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#define mmDCP1_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmDCP1_GAMUT_REMAP_C23_C24 0x07a3
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#define mmDCP1_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmDCP1_GAMUT_REMAP_C31_C32 0x07a4
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#define mmDCP1_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmDCP1_GAMUT_REMAP_C33_C34 0x07a5
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#define mmDCP1_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x07a6
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#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
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#define mmDCP1_DCP_RANDOM_SEEDS 0x07a7
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#define mmDCP1_DCP_RANDOM_SEEDS_BASE_IDX 2
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#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x07a8
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#define mmDCP1_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
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#define mmDCP1_CUR_CONTROL 0x07a9
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#define mmDCP1_CUR_CONTROL_BASE_IDX 2
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#define mmDCP1_CUR_SURFACE_ADDRESS 0x07aa
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#define mmDCP1_CUR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP1_CUR_SIZE 0x07ab
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#define mmDCP1_CUR_SIZE_BASE_IDX 2
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#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x07ac
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#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP1_CUR_POSITION 0x07ad
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#define mmDCP1_CUR_POSITION_BASE_IDX 2
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#define mmDCP1_CUR_HOT_SPOT 0x07ae
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#define mmDCP1_CUR_HOT_SPOT_BASE_IDX 2
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#define mmDCP1_CUR_COLOR1 0x07af
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#define mmDCP1_CUR_COLOR1_BASE_IDX 2
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#define mmDCP1_CUR_COLOR2 0x07b0
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#define mmDCP1_CUR_COLOR2_BASE_IDX 2
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#define mmDCP1_CUR_UPDATE 0x07b1
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#define mmDCP1_CUR_UPDATE_BASE_IDX 2
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#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x07bb
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#define mmDCP1_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
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#define mmDCP1_CUR_STEREO_CONTROL 0x07bc
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#define mmDCP1_CUR_STEREO_CONTROL_BASE_IDX 2
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#define mmDCP1_DC_LUT_RW_MODE 0x07be
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#define mmDCP1_DC_LUT_RW_MODE_BASE_IDX 2
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#define mmDCP1_DC_LUT_RW_INDEX 0x07bf
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#define mmDCP1_DC_LUT_RW_INDEX_BASE_IDX 2
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#define mmDCP1_DC_LUT_SEQ_COLOR 0x07c0
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#define mmDCP1_DC_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmDCP1_DC_LUT_PWL_DATA 0x07c1
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#define mmDCP1_DC_LUT_PWL_DATA_BASE_IDX 2
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#define mmDCP1_DC_LUT_30_COLOR 0x07c2
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#define mmDCP1_DC_LUT_30_COLOR_BASE_IDX 2
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#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x07c3
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#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
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#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x07c4
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#define mmDCP1_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP1_DC_LUT_AUTOFILL 0x07c5
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#define mmDCP1_DC_LUT_AUTOFILL_BASE_IDX 2
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#define mmDCP1_DC_LUT_CONTROL 0x07c6
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#define mmDCP1_DC_LUT_CONTROL_BASE_IDX 2
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#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x07c7
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#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x07c8
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#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x07c9
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#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
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#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x07ca
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#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x07cb
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#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x07cc
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#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
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#define mmDCP1_DCP_CRC_CONTROL 0x07cd
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#define mmDCP1_DCP_CRC_CONTROL_BASE_IDX 2
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#define mmDCP1_DCP_CRC_MASK 0x07ce
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#define mmDCP1_DCP_CRC_MASK_BASE_IDX 2
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#define mmDCP1_DCP_CRC_CURRENT 0x07cf
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#define mmDCP1_DCP_CRC_CURRENT_BASE_IDX 2
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#define mmDCP1_DVMM_PTE_CONTROL 0x07d0
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#define mmDCP1_DVMM_PTE_CONTROL_BASE_IDX 2
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#define mmDCP1_DCP_CRC_LAST 0x07d1
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#define mmDCP1_DCP_CRC_LAST_BASE_IDX 2
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#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x07d2
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#define mmDCP1_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
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#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x07d4
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#define mmDCP1_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
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#define mmDCP1_DCP_GSL_CONTROL 0x07d5
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#define mmDCP1_DCP_GSL_CONTROL_BASE_IDX 2
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#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x07d6
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#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
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#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x07dc
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#define mmDCP1_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
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#define mmDCP1_HW_ROTATION 0x07de
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#define mmDCP1_HW_ROTATION_BASE_IDX 2
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#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x07df
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#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
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#define mmDCP1_REGAMMA_CONTROL 0x07e0
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#define mmDCP1_REGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP1_REGAMMA_LUT_INDEX 0x07e1
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#define mmDCP1_REGAMMA_LUT_INDEX_BASE_IDX 2
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#define mmDCP1_REGAMMA_LUT_DATA 0x07e2
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#define mmDCP1_REGAMMA_LUT_DATA_BASE_IDX 2
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#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x07e3
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#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x07e4
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#define mmDCP1_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x07e5
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#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x07e6
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#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x07e7
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#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x07e8
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#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x07e9
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#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x07ea
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#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x07eb
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#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x07ec
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#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x07ed
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#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x07ee
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#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x07ef
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#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x07f0
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#define mmDCP1_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x07f1
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#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x07f2
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#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x07f3
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#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x07f4
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#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x07f5
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#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x07f6
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#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x07f7
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#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x07f8
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#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x07f9
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#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x07fa
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#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
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#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x07fb
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#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
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#define mmDCP1_ALPHA_CONTROL 0x07fc
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#define mmDCP1_ALPHA_CONTROL_BASE_IDX 2
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#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x07fd
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#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x07fe
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#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x07ff
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#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
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#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT 0x0800
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#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
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#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY 0x0801
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#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
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#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x0802
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#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
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#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x0803
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#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
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// addressBlock: dce_dc_lb1_dispdec
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// base address: 0x800
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#define mmLB1_LB_DATA_FORMAT 0x081a
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#define mmLB1_LB_DATA_FORMAT_BASE_IDX 2
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#define mmLB1_LB_MEMORY_CTRL 0x081b
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#define mmLB1_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmLB1_LB_MEMORY_SIZE_STATUS 0x081c
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#define mmLB1_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
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#define mmLB1_LB_DESKTOP_HEIGHT 0x081d
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#define mmLB1_LB_DESKTOP_HEIGHT_BASE_IDX 2
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#define mmLB1_LB_VLINE_START_END 0x081e
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#define mmLB1_LB_VLINE_START_END_BASE_IDX 2
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#define mmLB1_LB_VLINE2_START_END 0x081f
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#define mmLB1_LB_VLINE2_START_END_BASE_IDX 2
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#define mmLB1_LB_V_COUNTER 0x0820
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#define mmLB1_LB_V_COUNTER_BASE_IDX 2
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#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x0821
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#define mmLB1_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
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#define mmLB1_LB_INTERRUPT_MASK 0x0822
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#define mmLB1_LB_INTERRUPT_MASK_BASE_IDX 2
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#define mmLB1_LB_VLINE_STATUS 0x0823
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#define mmLB1_LB_VLINE_STATUS_BASE_IDX 2
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#define mmLB1_LB_VLINE2_STATUS 0x0824
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#define mmLB1_LB_VLINE2_STATUS_BASE_IDX 2
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#define mmLB1_LB_VBLANK_STATUS 0x0825
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#define mmLB1_LB_VBLANK_STATUS_BASE_IDX 2
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#define mmLB1_LB_SYNC_RESET_SEL 0x0826
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#define mmLB1_LB_SYNC_RESET_SEL_BASE_IDX 2
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#define mmLB1_LB_BLACK_KEYER_R_CR 0x0827
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#define mmLB1_LB_BLACK_KEYER_R_CR_BASE_IDX 2
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#define mmLB1_LB_BLACK_KEYER_G_Y 0x0828
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#define mmLB1_LB_BLACK_KEYER_G_Y_BASE_IDX 2
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#define mmLB1_LB_BLACK_KEYER_B_CB 0x0829
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#define mmLB1_LB_BLACK_KEYER_B_CB_BASE_IDX 2
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#define mmLB1_LB_KEYER_COLOR_CTRL 0x082a
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#define mmLB1_LB_KEYER_COLOR_CTRL_BASE_IDX 2
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#define mmLB1_LB_KEYER_COLOR_R_CR 0x082b
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#define mmLB1_LB_KEYER_COLOR_R_CR_BASE_IDX 2
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#define mmLB1_LB_KEYER_COLOR_G_Y 0x082c
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#define mmLB1_LB_KEYER_COLOR_G_Y_BASE_IDX 2
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#define mmLB1_LB_KEYER_COLOR_B_CB 0x082d
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#define mmLB1_LB_KEYER_COLOR_B_CB_BASE_IDX 2
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#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x082e
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#define mmLB1_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
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#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x082f
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#define mmLB1_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
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#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x0830
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#define mmLB1_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
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#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x0831
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#define mmLB1_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
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#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x0832
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#define mmLB1_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
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#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x0833
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#define mmLB1_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
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#define mmLB1_LB_BUFFER_STATUS 0x0834
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#define mmLB1_LB_BUFFER_STATUS_BASE_IDX 2
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#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x0835
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#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
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#define mmLB1_MVP_AFR_FLIP_MODE 0x0836
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#define mmLB1_MVP_AFR_FLIP_MODE_BASE_IDX 2
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#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x0837
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#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
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#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x0838
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#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
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#define mmLB1_DC_MVP_LB_CONTROL 0x0839
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#define mmLB1_DC_MVP_LB_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dcfe1_dispdec
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// base address: 0x800
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#define mmDCFE1_DCFE_CLOCK_CONTROL 0x085a
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#define mmDCFE1_DCFE_CLOCK_CONTROL_BASE_IDX 2
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#define mmDCFE1_DCFE_SOFT_RESET 0x085b
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#define mmDCFE1_DCFE_SOFT_RESET_BASE_IDX 2
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#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x085d
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#define mmDCFE1_DCFE_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x085e
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#define mmDCFE1_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x085f
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#define mmDCFE1_DCFE_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFE1_DCFE_MISC 0x0860
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#define mmDCFE1_DCFE_MISC_BASE_IDX 2
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#define mmDCFE1_DCFE_FLUSH 0x0861
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#define mmDCFE1_DCFE_FLUSH_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon4_dispdec
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// base address: 0x2138
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#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x086e
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#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x086f
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#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0870
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#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_CNTL 0x0871
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#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_CNTL2 0x0872
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#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0873
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#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0874
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#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_HI 0x0875
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#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_LOW 0x0876
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#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dmif_pg1_dispdec
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// base address: 0x800
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#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x087a
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#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
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#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x087b
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#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x087c
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#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
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#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x087d
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#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
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#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL 0x087e
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#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
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#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x087f
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#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
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#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2 0x0880
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#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL 0x0881
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#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
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#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x0882
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#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_BASE_IDX 2
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#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x0886
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#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
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#define mmDMIF_PG1_DPG_DVMM_STATUS 0x0887
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#define mmDMIF_PG1_DPG_DVMM_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_scl1_dispdec
|
// base address: 0x800
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#define mmSCL1_SCL_COEF_RAM_SELECT 0x089a
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#define mmSCL1_SCL_COEF_RAM_SELECT_BASE_IDX 2
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#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x089b
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#define mmSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmSCL1_SCL_MODE 0x089c
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#define mmSCL1_SCL_MODE_BASE_IDX 2
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#define mmSCL1_SCL_TAP_CONTROL 0x089d
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#define mmSCL1_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_CONTROL 0x089e
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#define mmSCL1_SCL_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_BYPASS_CONTROL 0x089f
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#define mmSCL1_SCL_BYPASS_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x08a0
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#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x08a1
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#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x08a2
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#define mmSCL1_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x08a3
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#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL1_SCL_HORZ_FILTER_INIT 0x08a4
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#define mmSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x08a5
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#define mmSCL1_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x08a6
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#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL1_SCL_VERT_FILTER_INIT 0x08a7
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#define mmSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x08a8
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#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCL1_SCL_ROUND_OFFSET 0x08a9
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#define mmSCL1_SCL_ROUND_OFFSET_BASE_IDX 2
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#define mmSCL1_SCL_UPDATE 0x08aa
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#define mmSCL1_SCL_UPDATE_BASE_IDX 2
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#define mmSCL1_SCL_F_SHARP_CONTROL 0x08ab
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#define mmSCL1_SCL_F_SHARP_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_ALU_CONTROL 0x08ac
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#define mmSCL1_SCL_ALU_CONTROL_BASE_IDX 2
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#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x08ad
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#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
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#define mmSCL1_VIEWPORT_START_SECONDARY 0x08ae
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#define mmSCL1_VIEWPORT_START_SECONDARY_BASE_IDX 2
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#define mmSCL1_VIEWPORT_START 0x08af
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#define mmSCL1_VIEWPORT_START_BASE_IDX 2
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#define mmSCL1_VIEWPORT_SIZE 0x08b0
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#define mmSCL1_VIEWPORT_SIZE_BASE_IDX 2
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#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x08b1
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#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x08b2
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#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmSCL1_SCL_MODE_CHANGE_DET1 0x08b3
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#define mmSCL1_SCL_MODE_CHANGE_DET1_BASE_IDX 2
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#define mmSCL1_SCL_MODE_CHANGE_DET2 0x08b4
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#define mmSCL1_SCL_MODE_CHANGE_DET2_BASE_IDX 2
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#define mmSCL1_SCL_MODE_CHANGE_DET3 0x08b5
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#define mmSCL1_SCL_MODE_CHANGE_DET3_BASE_IDX 2
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#define mmSCL1_SCL_MODE_CHANGE_MASK 0x08b6
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#define mmSCL1_SCL_MODE_CHANGE_MASK_BASE_IDX 2
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// addressBlock: dce_dc_blnd1_dispdec
|
// base address: 0x800
|
#define mmBLND1_BLND_CONTROL 0x08c7
|
#define mmBLND1_BLND_CONTROL_BASE_IDX 2
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#define mmBLND1_BLND_SM_CONTROL2 0x08c8
|
#define mmBLND1_BLND_SM_CONTROL2_BASE_IDX 2
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#define mmBLND1_BLND_CONTROL2 0x08c9
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#define mmBLND1_BLND_CONTROL2_BASE_IDX 2
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#define mmBLND1_BLND_UPDATE 0x08ca
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#define mmBLND1_BLND_UPDATE_BASE_IDX 2
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#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x08cb
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#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
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#define mmBLND1_BLND_V_UPDATE_LOCK 0x08cc
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#define mmBLND1_BLND_V_UPDATE_LOCK_BASE_IDX 2
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#define mmBLND1_BLND_REG_UPDATE_STATUS 0x08cd
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#define mmBLND1_BLND_REG_UPDATE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_crtc1_dispdec
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// base address: 0x800
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#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x08d2
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#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
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#define mmCRTC1_CRTC_H_TOTAL 0x08d3
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#define mmCRTC1_CRTC_H_TOTAL_BASE_IDX 2
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#define mmCRTC1_CRTC_H_BLANK_START_END 0x08d4
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#define mmCRTC1_CRTC_H_BLANK_START_END_BASE_IDX 2
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#define mmCRTC1_CRTC_H_SYNC_A 0x08d5
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#define mmCRTC1_CRTC_H_SYNC_A_BASE_IDX 2
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#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x08d6
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#define mmCRTC1_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_H_SYNC_B 0x08d7
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#define mmCRTC1_CRTC_H_SYNC_B_BASE_IDX 2
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#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x08d8
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#define mmCRTC1_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_VBI_END 0x08d9
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#define mmCRTC1_CRTC_VBI_END_BASE_IDX 2
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#define mmCRTC1_CRTC_V_TOTAL 0x08da
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#define mmCRTC1_CRTC_V_TOTAL_BASE_IDX 2
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#define mmCRTC1_CRTC_V_TOTAL_MIN 0x08db
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#define mmCRTC1_CRTC_V_TOTAL_MIN_BASE_IDX 2
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#define mmCRTC1_CRTC_V_TOTAL_MAX 0x08dc
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#define mmCRTC1_CRTC_V_TOTAL_MAX_BASE_IDX 2
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#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x08dd
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#define mmCRTC1_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x08de
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#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x08df
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#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmCRTC1_CRTC_V_BLANK_START_END 0x08e0
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#define mmCRTC1_CRTC_V_BLANK_START_END_BASE_IDX 2
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#define mmCRTC1_CRTC_V_SYNC_A 0x08e1
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#define mmCRTC1_CRTC_V_SYNC_A_BASE_IDX 2
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#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x08e2
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#define mmCRTC1_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_V_SYNC_B 0x08e3
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#define mmCRTC1_CRTC_V_SYNC_B_BASE_IDX 2
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#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x08e4
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#define mmCRTC1_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_DTMTEST_CNTL 0x08e5
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#define mmCRTC1_CRTC_DTMTEST_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x08e6
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#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC1_CRTC_TRIGA_CNTL 0x08e7
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#define mmCRTC1_CRTC_TRIGA_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x08e8
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#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC1_CRTC_TRIGB_CNTL 0x08e9
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#define mmCRTC1_CRTC_TRIGB_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x08ea
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#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x08eb
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#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_FLOW_CONTROL 0x08ec
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#define mmCRTC1_CRTC_FLOW_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x08ed
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#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x08ee
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#define mmCRTC1_CRTC_AVSYNC_COUNTER_BASE_IDX 2
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#define mmCRTC1_CRTC_CONTROL 0x08ef
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#define mmCRTC1_CRTC_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_BLANK_CONTROL 0x08f0
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#define mmCRTC1_CRTC_BLANK_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x08f1
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#define mmCRTC1_CRTC_INTERLACE_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_INTERLACE_STATUS 0x08f2
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#define mmCRTC1_CRTC_INTERLACE_STATUS_BASE_IDX 2
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#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x08f3
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#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
|
#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x08f4
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#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x08f5
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#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmCRTC1_CRTC_STATUS 0x08f6
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#define mmCRTC1_CRTC_STATUS_BASE_IDX 2
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#define mmCRTC1_CRTC_STATUS_POSITION 0x08f7
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#define mmCRTC1_CRTC_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x08f8
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#define mmCRTC1_CRTC_NOM_VERT_POSITION_BASE_IDX 2
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#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x08f9
|
#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x08fa
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#define mmCRTC1_CRTC_STATUS_VF_COUNT_BASE_IDX 2
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#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x08fb
|
#define mmCRTC1_CRTC_STATUS_HV_COUNT_BASE_IDX 2
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#define mmCRTC1_CRTC_COUNT_CONTROL 0x08fc
|
#define mmCRTC1_CRTC_COUNT_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_COUNT_RESET 0x08fd
|
#define mmCRTC1_CRTC_COUNT_RESET_BASE_IDX 2
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#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x08fe
|
#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x08ff
|
#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_STEREO_STATUS 0x0900
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#define mmCRTC1_CRTC_STEREO_STATUS_BASE_IDX 2
|
#define mmCRTC1_CRTC_STEREO_CONTROL 0x0901
|
#define mmCRTC1_CRTC_STEREO_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x0902
|
#define mmCRTC1_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x0903
|
#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x0904
|
#define mmCRTC1_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x0905
|
#define mmCRTC1_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmCRTC1_CRTC_START_LINE_CONTROL 0x0906
|
#define mmCRTC1_CRTC_START_LINE_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x0907
|
#define mmCRTC1_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmCRTC1_CRTC_UPDATE_LOCK 0x0908
|
#define mmCRTC1_CRTC_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x0909
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#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x090a
|
#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
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#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x090b
|
#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x090c
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#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x090d
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#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x090e
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#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x090f
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#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x0910
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#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
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#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0911
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#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
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#define mmCRTC1_CRTC_MVP_STATUS 0x0912
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#define mmCRTC1_CRTC_MVP_STATUS_BASE_IDX 2
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#define mmCRTC1_CRTC_MASTER_EN 0x0913
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#define mmCRTC1_CRTC_MASTER_EN_BASE_IDX 2
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#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x0914
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#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
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#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x0915
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#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
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#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x0917
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#define mmCRTC1_CRTC_OVERSCAN_COLOR_BASE_IDX 2
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#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x0918
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#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
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#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x0919
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#define mmCRTC1_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x091a
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#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmCRTC1_CRTC_BLACK_COLOR 0x091b
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#define mmCRTC1_CRTC_BLACK_COLOR_BASE_IDX 2
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#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x091c
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#define mmCRTC1_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x091d
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x091e
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x091f
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0920
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0921
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0922
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#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC_CNTL 0x0923
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#define mmCRTC1_CRTC_CRC_CNTL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x0924
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#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0925
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#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x0926
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#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0927
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#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC0_DATA_RG 0x0928
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#define mmCRTC1_CRTC_CRC0_DATA_RG_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC0_DATA_B 0x0929
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#define mmCRTC1_CRTC_CRC0_DATA_B_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x092a
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#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x092b
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#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x092c
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#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x092d
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#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC1_DATA_RG 0x092e
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#define mmCRTC1_CRTC_CRC1_DATA_RG_BASE_IDX 2
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#define mmCRTC1_CRTC_CRC1_DATA_B 0x092f
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#define mmCRTC1_CRTC_CRC1_DATA_B_BASE_IDX 2
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x0930
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0931
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0932
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0933
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0934
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0935
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#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x0936
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#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x0937
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#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x0938
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#define mmCRTC1_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmCRTC1_CRTC_GSL_WINDOW 0x0939
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#define mmCRTC1_CRTC_GSL_WINDOW_BASE_IDX 2
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#define mmCRTC1_CRTC_GSL_CONTROL 0x093a
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#define mmCRTC1_CRTC_GSL_CONTROL_BASE_IDX 2
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#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS 0x093d
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#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmCRTC1_CRTC_DRR_CONTROL 0x093e
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#define mmCRTC1_CRTC_DRR_CONTROL_BASE_IDX 2
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|
|
// addressBlock: dce_dc_fmt1_dispdec
|
// base address: 0x800
|
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x0942
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#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
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#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x0943
|
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x0944
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#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x0945
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#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
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#define mmFMT1_FMT_CONTROL 0x0946
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#define mmFMT1_FMT_CONTROL_BASE_IDX 2
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#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x0947
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#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x0948
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#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x0949
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#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x094a
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#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
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#define mmFMT1_FMT_CLAMP_CNTL 0x094e
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#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT1_FMT_CRC_CNTL 0x094f
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#define mmFMT1_FMT_CRC_CNTL_BASE_IDX 2
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#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x0950
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#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0951
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#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x0952
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#define mmFMT1_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
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#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x0953
|
#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
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#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0954
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#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
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#define mmFMT1_FMT_420_HBLANK_EARLY_START 0x0955
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#define mmFMT1_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
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|
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// addressBlock: dce_dc_dcp2_dispdec
|
// base address: 0x1000
|
#define mmDCP2_GRPH_ENABLE 0x095a
|
#define mmDCP2_GRPH_ENABLE_BASE_IDX 2
|
#define mmDCP2_GRPH_CONTROL 0x095b
|
#define mmDCP2_GRPH_CONTROL_BASE_IDX 2
|
#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x095c
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#define mmDCP2_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
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#define mmDCP2_GRPH_SWAP_CNTL 0x095d
|
#define mmDCP2_GRPH_SWAP_CNTL_BASE_IDX 2
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#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x095e
|
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x095f
|
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmDCP2_GRPH_PITCH 0x0960
|
#define mmDCP2_GRPH_PITCH_BASE_IDX 2
|
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0961
|
#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0962
|
#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x0963
|
#define mmDCP2_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
|
#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x0964
|
#define mmDCP2_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
|
#define mmDCP2_GRPH_X_START 0x0965
|
#define mmDCP2_GRPH_X_START_BASE_IDX 2
|
#define mmDCP2_GRPH_Y_START 0x0966
|
#define mmDCP2_GRPH_Y_START_BASE_IDX 2
|
#define mmDCP2_GRPH_X_END 0x0967
|
#define mmDCP2_GRPH_X_END_BASE_IDX 2
|
#define mmDCP2_GRPH_Y_END 0x0968
|
#define mmDCP2_GRPH_Y_END_BASE_IDX 2
|
#define mmDCP2_INPUT_GAMMA_CONTROL 0x0969
|
#define mmDCP2_INPUT_GAMMA_CONTROL_BASE_IDX 2
|
#define mmDCP2_GRPH_UPDATE 0x096a
|
#define mmDCP2_GRPH_UPDATE_BASE_IDX 2
|
#define mmDCP2_GRPH_FLIP_CONTROL 0x096b
|
#define mmDCP2_GRPH_FLIP_CONTROL_BASE_IDX 2
|
#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x096c
|
#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
|
#define mmDCP2_GRPH_DFQ_CONTROL 0x096d
|
#define mmDCP2_GRPH_DFQ_CONTROL_BASE_IDX 2
|
#define mmDCP2_GRPH_DFQ_STATUS 0x096e
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#define mmDCP2_GRPH_DFQ_STATUS_BASE_IDX 2
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#define mmDCP2_GRPH_INTERRUPT_STATUS 0x096f
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#define mmDCP2_GRPH_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x0970
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#define mmDCP2_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0971
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#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
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#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x0972
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#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP2_GRPH_COMPRESS_PITCH 0x0973
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#define mmDCP2_GRPH_COMPRESS_PITCH_BASE_IDX 2
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#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0974
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#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0975
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#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
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#define mmDCP2_PRESCALE_GRPH_CONTROL 0x0976
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#define mmDCP2_PRESCALE_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x0977
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#define mmDCP2_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
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#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x0978
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#define mmDCP2_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
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#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x0979
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#define mmDCP2_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
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#define mmDCP2_INPUT_CSC_CONTROL 0x097a
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#define mmDCP2_INPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP2_INPUT_CSC_C11_C12 0x097b
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#define mmDCP2_INPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP2_INPUT_CSC_C13_C14 0x097c
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#define mmDCP2_INPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP2_INPUT_CSC_C21_C22 0x097d
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#define mmDCP2_INPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP2_INPUT_CSC_C23_C24 0x097e
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#define mmDCP2_INPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP2_INPUT_CSC_C31_C32 0x097f
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#define mmDCP2_INPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP2_INPUT_CSC_C33_C34 0x0980
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#define mmDCP2_INPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP2_OUTPUT_CSC_CONTROL 0x0981
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#define mmDCP2_OUTPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP2_OUTPUT_CSC_C11_C12 0x0982
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#define mmDCP2_OUTPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP2_OUTPUT_CSC_C13_C14 0x0983
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#define mmDCP2_OUTPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP2_OUTPUT_CSC_C21_C22 0x0984
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#define mmDCP2_OUTPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP2_OUTPUT_CSC_C23_C24 0x0985
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#define mmDCP2_OUTPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP2_OUTPUT_CSC_C31_C32 0x0986
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#define mmDCP2_OUTPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP2_OUTPUT_CSC_C33_C34 0x0987
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#define mmDCP2_OUTPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x0988
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#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x0989
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#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x098a
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#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x098b
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#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x098c
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#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x098d
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#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x098e
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#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x098f
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#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x0990
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#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x0991
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#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x0992
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#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x0993
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#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP2_DENORM_CONTROL 0x0994
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#define mmDCP2_DENORM_CONTROL_BASE_IDX 2
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#define mmDCP2_OUT_ROUND_CONTROL 0x0995
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#define mmDCP2_OUT_ROUND_CONTROL_BASE_IDX 2
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#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x0996
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#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
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#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x0997
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#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
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#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x0998
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#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
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#define mmDCP2_KEY_CONTROL 0x0999
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#define mmDCP2_KEY_CONTROL_BASE_IDX 2
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#define mmDCP2_KEY_RANGE_ALPHA 0x099a
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#define mmDCP2_KEY_RANGE_ALPHA_BASE_IDX 2
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#define mmDCP2_KEY_RANGE_RED 0x099b
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#define mmDCP2_KEY_RANGE_RED_BASE_IDX 2
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#define mmDCP2_KEY_RANGE_GREEN 0x099c
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#define mmDCP2_KEY_RANGE_GREEN_BASE_IDX 2
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#define mmDCP2_KEY_RANGE_BLUE 0x099d
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#define mmDCP2_KEY_RANGE_BLUE_BASE_IDX 2
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#define mmDCP2_DEGAMMA_CONTROL 0x099e
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#define mmDCP2_DEGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP2_GAMUT_REMAP_CONTROL 0x099f
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#define mmDCP2_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmDCP2_GAMUT_REMAP_C11_C12 0x09a0
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#define mmDCP2_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmDCP2_GAMUT_REMAP_C13_C14 0x09a1
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#define mmDCP2_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmDCP2_GAMUT_REMAP_C21_C22 0x09a2
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#define mmDCP2_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmDCP2_GAMUT_REMAP_C23_C24 0x09a3
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#define mmDCP2_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmDCP2_GAMUT_REMAP_C31_C32 0x09a4
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#define mmDCP2_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmDCP2_GAMUT_REMAP_C33_C34 0x09a5
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#define mmDCP2_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x09a6
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#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
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#define mmDCP2_DCP_RANDOM_SEEDS 0x09a7
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#define mmDCP2_DCP_RANDOM_SEEDS_BASE_IDX 2
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#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x09a8
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#define mmDCP2_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
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#define mmDCP2_CUR_CONTROL 0x09a9
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#define mmDCP2_CUR_CONTROL_BASE_IDX 2
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#define mmDCP2_CUR_SURFACE_ADDRESS 0x09aa
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#define mmDCP2_CUR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP2_CUR_SIZE 0x09ab
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#define mmDCP2_CUR_SIZE_BASE_IDX 2
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#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x09ac
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#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP2_CUR_POSITION 0x09ad
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#define mmDCP2_CUR_POSITION_BASE_IDX 2
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#define mmDCP2_CUR_HOT_SPOT 0x09ae
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#define mmDCP2_CUR_HOT_SPOT_BASE_IDX 2
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#define mmDCP2_CUR_COLOR1 0x09af
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#define mmDCP2_CUR_COLOR1_BASE_IDX 2
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#define mmDCP2_CUR_COLOR2 0x09b0
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#define mmDCP2_CUR_COLOR2_BASE_IDX 2
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#define mmDCP2_CUR_UPDATE 0x09b1
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#define mmDCP2_CUR_UPDATE_BASE_IDX 2
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#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x09bb
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#define mmDCP2_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
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#define mmDCP2_CUR_STEREO_CONTROL 0x09bc
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#define mmDCP2_CUR_STEREO_CONTROL_BASE_IDX 2
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#define mmDCP2_DC_LUT_RW_MODE 0x09be
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#define mmDCP2_DC_LUT_RW_MODE_BASE_IDX 2
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#define mmDCP2_DC_LUT_RW_INDEX 0x09bf
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#define mmDCP2_DC_LUT_RW_INDEX_BASE_IDX 2
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#define mmDCP2_DC_LUT_SEQ_COLOR 0x09c0
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#define mmDCP2_DC_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmDCP2_DC_LUT_PWL_DATA 0x09c1
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#define mmDCP2_DC_LUT_PWL_DATA_BASE_IDX 2
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#define mmDCP2_DC_LUT_30_COLOR 0x09c2
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#define mmDCP2_DC_LUT_30_COLOR_BASE_IDX 2
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#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x09c3
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#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
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#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x09c4
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#define mmDCP2_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP2_DC_LUT_AUTOFILL 0x09c5
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#define mmDCP2_DC_LUT_AUTOFILL_BASE_IDX 2
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#define mmDCP2_DC_LUT_CONTROL 0x09c6
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#define mmDCP2_DC_LUT_CONTROL_BASE_IDX 2
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#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x09c7
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#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x09c8
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#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x09c9
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#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
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#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x09ca
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#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x09cb
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#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x09cc
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#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
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#define mmDCP2_DCP_CRC_CONTROL 0x09cd
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#define mmDCP2_DCP_CRC_CONTROL_BASE_IDX 2
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#define mmDCP2_DCP_CRC_MASK 0x09ce
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#define mmDCP2_DCP_CRC_MASK_BASE_IDX 2
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#define mmDCP2_DCP_CRC_CURRENT 0x09cf
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#define mmDCP2_DCP_CRC_CURRENT_BASE_IDX 2
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#define mmDCP2_DVMM_PTE_CONTROL 0x09d0
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#define mmDCP2_DVMM_PTE_CONTROL_BASE_IDX 2
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#define mmDCP2_DCP_CRC_LAST 0x09d1
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#define mmDCP2_DCP_CRC_LAST_BASE_IDX 2
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#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x09d2
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#define mmDCP2_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
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#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x09d4
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#define mmDCP2_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
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#define mmDCP2_DCP_GSL_CONTROL 0x09d5
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#define mmDCP2_DCP_GSL_CONTROL_BASE_IDX 2
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#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x09d6
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#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
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#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x09dc
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#define mmDCP2_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
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#define mmDCP2_HW_ROTATION 0x09de
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#define mmDCP2_HW_ROTATION_BASE_IDX 2
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#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x09df
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#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
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#define mmDCP2_REGAMMA_CONTROL 0x09e0
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#define mmDCP2_REGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP2_REGAMMA_LUT_INDEX 0x09e1
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#define mmDCP2_REGAMMA_LUT_INDEX_BASE_IDX 2
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#define mmDCP2_REGAMMA_LUT_DATA 0x09e2
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#define mmDCP2_REGAMMA_LUT_DATA_BASE_IDX 2
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#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x09e3
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#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x09e4
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#define mmDCP2_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x09e5
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#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x09e6
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#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x09e7
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#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x09e8
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#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x09e9
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#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x09ea
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#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x09eb
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#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x09ec
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#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x09ed
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#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x09ee
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#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x09ef
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#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x09f0
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#define mmDCP2_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x09f1
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#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x09f2
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#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x09f3
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#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x09f4
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#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x09f5
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#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x09f6
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#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x09f7
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#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x09f8
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#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x09f9
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#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x09fa
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#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
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#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x09fb
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#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
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#define mmDCP2_ALPHA_CONTROL 0x09fc
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#define mmDCP2_ALPHA_CONTROL_BASE_IDX 2
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#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x09fd
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#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x09fe
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#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x09ff
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#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
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#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT 0x0a00
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#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
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#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY 0x0a01
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#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
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#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x0a02
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#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
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#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x0a03
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#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
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// addressBlock: dce_dc_lb2_dispdec
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// base address: 0x1000
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#define mmLB2_LB_DATA_FORMAT 0x0a1a
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#define mmLB2_LB_DATA_FORMAT_BASE_IDX 2
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#define mmLB2_LB_MEMORY_CTRL 0x0a1b
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#define mmLB2_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmLB2_LB_MEMORY_SIZE_STATUS 0x0a1c
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#define mmLB2_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
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#define mmLB2_LB_DESKTOP_HEIGHT 0x0a1d
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#define mmLB2_LB_DESKTOP_HEIGHT_BASE_IDX 2
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#define mmLB2_LB_VLINE_START_END 0x0a1e
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#define mmLB2_LB_VLINE_START_END_BASE_IDX 2
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#define mmLB2_LB_VLINE2_START_END 0x0a1f
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#define mmLB2_LB_VLINE2_START_END_BASE_IDX 2
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#define mmLB2_LB_V_COUNTER 0x0a20
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#define mmLB2_LB_V_COUNTER_BASE_IDX 2
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#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x0a21
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#define mmLB2_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
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#define mmLB2_LB_INTERRUPT_MASK 0x0a22
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#define mmLB2_LB_INTERRUPT_MASK_BASE_IDX 2
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#define mmLB2_LB_VLINE_STATUS 0x0a23
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#define mmLB2_LB_VLINE_STATUS_BASE_IDX 2
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#define mmLB2_LB_VLINE2_STATUS 0x0a24
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#define mmLB2_LB_VLINE2_STATUS_BASE_IDX 2
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#define mmLB2_LB_VBLANK_STATUS 0x0a25
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#define mmLB2_LB_VBLANK_STATUS_BASE_IDX 2
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#define mmLB2_LB_SYNC_RESET_SEL 0x0a26
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#define mmLB2_LB_SYNC_RESET_SEL_BASE_IDX 2
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#define mmLB2_LB_BLACK_KEYER_R_CR 0x0a27
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#define mmLB2_LB_BLACK_KEYER_R_CR_BASE_IDX 2
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#define mmLB2_LB_BLACK_KEYER_G_Y 0x0a28
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#define mmLB2_LB_BLACK_KEYER_G_Y_BASE_IDX 2
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#define mmLB2_LB_BLACK_KEYER_B_CB 0x0a29
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#define mmLB2_LB_BLACK_KEYER_B_CB_BASE_IDX 2
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#define mmLB2_LB_KEYER_COLOR_CTRL 0x0a2a
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#define mmLB2_LB_KEYER_COLOR_CTRL_BASE_IDX 2
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#define mmLB2_LB_KEYER_COLOR_R_CR 0x0a2b
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#define mmLB2_LB_KEYER_COLOR_R_CR_BASE_IDX 2
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#define mmLB2_LB_KEYER_COLOR_G_Y 0x0a2c
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#define mmLB2_LB_KEYER_COLOR_G_Y_BASE_IDX 2
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#define mmLB2_LB_KEYER_COLOR_B_CB 0x0a2d
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#define mmLB2_LB_KEYER_COLOR_B_CB_BASE_IDX 2
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#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x0a2e
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#define mmLB2_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
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#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x0a2f
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#define mmLB2_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
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#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x0a30
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#define mmLB2_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
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#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x0a31
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#define mmLB2_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
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#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x0a32
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#define mmLB2_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
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#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x0a33
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#define mmLB2_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
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#define mmLB2_LB_BUFFER_STATUS 0x0a34
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#define mmLB2_LB_BUFFER_STATUS_BASE_IDX 2
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#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x0a35
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#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
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#define mmLB2_MVP_AFR_FLIP_MODE 0x0a36
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#define mmLB2_MVP_AFR_FLIP_MODE_BASE_IDX 2
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#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x0a37
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#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
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#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x0a38
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#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
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#define mmLB2_DC_MVP_LB_CONTROL 0x0a39
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#define mmLB2_DC_MVP_LB_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dcfe2_dispdec
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// base address: 0x1000
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#define mmDCFE2_DCFE_CLOCK_CONTROL 0x0a5a
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#define mmDCFE2_DCFE_CLOCK_CONTROL_BASE_IDX 2
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#define mmDCFE2_DCFE_SOFT_RESET 0x0a5b
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#define mmDCFE2_DCFE_SOFT_RESET_BASE_IDX 2
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#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x0a5d
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#define mmDCFE2_DCFE_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x0a5e
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#define mmDCFE2_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x0a5f
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#define mmDCFE2_DCFE_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFE2_DCFE_MISC 0x0a60
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#define mmDCFE2_DCFE_MISC_BASE_IDX 2
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#define mmDCFE2_DCFE_FLUSH 0x0a61
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#define mmDCFE2_DCFE_FLUSH_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon5_dispdec
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// base address: 0x2938
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#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0a6e
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#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0a6f
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#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0a70
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#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_CNTL 0x0a71
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#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_CNTL2 0x0a72
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#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0a73
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#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0a74
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#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_HI 0x0a75
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#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_LOW 0x0a76
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#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dmif_pg2_dispdec
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// base address: 0x1000
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#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x0a7a
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#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
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#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x0a7b
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#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x0a7c
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#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
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#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x0a7d
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#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
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#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0a7e
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#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
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#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x0a7f
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#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
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#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2 0x0a80
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#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL 0x0a81
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#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
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#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x0a82
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#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_BASE_IDX 2
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#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x0a86
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#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
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#define mmDMIF_PG2_DPG_DVMM_STATUS 0x0a87
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#define mmDMIF_PG2_DPG_DVMM_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_scl2_dispdec
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// base address: 0x1000
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#define mmSCL2_SCL_COEF_RAM_SELECT 0x0a9a
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#define mmSCL2_SCL_COEF_RAM_SELECT_BASE_IDX 2
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#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x0a9b
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#define mmSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmSCL2_SCL_MODE 0x0a9c
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#define mmSCL2_SCL_MODE_BASE_IDX 2
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#define mmSCL2_SCL_TAP_CONTROL 0x0a9d
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#define mmSCL2_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_CONTROL 0x0a9e
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#define mmSCL2_SCL_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_BYPASS_CONTROL 0x0a9f
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#define mmSCL2_SCL_BYPASS_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0aa0
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#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x0aa1
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#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x0aa2
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#define mmSCL2_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0aa3
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#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL2_SCL_HORZ_FILTER_INIT 0x0aa4
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#define mmSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x0aa5
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#define mmSCL2_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0aa6
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#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL2_SCL_VERT_FILTER_INIT 0x0aa7
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#define mmSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x0aa8
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#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCL2_SCL_ROUND_OFFSET 0x0aa9
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#define mmSCL2_SCL_ROUND_OFFSET_BASE_IDX 2
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#define mmSCL2_SCL_UPDATE 0x0aaa
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#define mmSCL2_SCL_UPDATE_BASE_IDX 2
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#define mmSCL2_SCL_F_SHARP_CONTROL 0x0aab
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#define mmSCL2_SCL_F_SHARP_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_ALU_CONTROL 0x0aac
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#define mmSCL2_SCL_ALU_CONTROL_BASE_IDX 2
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#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x0aad
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#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
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#define mmSCL2_VIEWPORT_START_SECONDARY 0x0aae
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#define mmSCL2_VIEWPORT_START_SECONDARY_BASE_IDX 2
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#define mmSCL2_VIEWPORT_START 0x0aaf
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#define mmSCL2_VIEWPORT_START_BASE_IDX 2
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#define mmSCL2_VIEWPORT_SIZE 0x0ab0
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#define mmSCL2_VIEWPORT_SIZE_BASE_IDX 2
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#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x0ab1
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#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x0ab2
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#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmSCL2_SCL_MODE_CHANGE_DET1 0x0ab3
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#define mmSCL2_SCL_MODE_CHANGE_DET1_BASE_IDX 2
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#define mmSCL2_SCL_MODE_CHANGE_DET2 0x0ab4
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#define mmSCL2_SCL_MODE_CHANGE_DET2_BASE_IDX 2
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#define mmSCL2_SCL_MODE_CHANGE_DET3 0x0ab5
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#define mmSCL2_SCL_MODE_CHANGE_DET3_BASE_IDX 2
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#define mmSCL2_SCL_MODE_CHANGE_MASK 0x0ab6
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#define mmSCL2_SCL_MODE_CHANGE_MASK_BASE_IDX 2
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// addressBlock: dce_dc_blnd2_dispdec
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// base address: 0x1000
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#define mmBLND2_BLND_CONTROL 0x0ac7
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#define mmBLND2_BLND_CONTROL_BASE_IDX 2
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#define mmBLND2_BLND_SM_CONTROL2 0x0ac8
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#define mmBLND2_BLND_SM_CONTROL2_BASE_IDX 2
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#define mmBLND2_BLND_CONTROL2 0x0ac9
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#define mmBLND2_BLND_CONTROL2_BASE_IDX 2
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#define mmBLND2_BLND_UPDATE 0x0aca
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#define mmBLND2_BLND_UPDATE_BASE_IDX 2
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#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x0acb
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#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
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#define mmBLND2_BLND_V_UPDATE_LOCK 0x0acc
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#define mmBLND2_BLND_V_UPDATE_LOCK_BASE_IDX 2
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#define mmBLND2_BLND_REG_UPDATE_STATUS 0x0acd
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#define mmBLND2_BLND_REG_UPDATE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_crtc2_dispdec
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// base address: 0x1000
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#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x0ad2
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#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
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#define mmCRTC2_CRTC_H_TOTAL 0x0ad3
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#define mmCRTC2_CRTC_H_TOTAL_BASE_IDX 2
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#define mmCRTC2_CRTC_H_BLANK_START_END 0x0ad4
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#define mmCRTC2_CRTC_H_BLANK_START_END_BASE_IDX 2
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#define mmCRTC2_CRTC_H_SYNC_A 0x0ad5
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#define mmCRTC2_CRTC_H_SYNC_A_BASE_IDX 2
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#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x0ad6
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#define mmCRTC2_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_H_SYNC_B 0x0ad7
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#define mmCRTC2_CRTC_H_SYNC_B_BASE_IDX 2
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#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x0ad8
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#define mmCRTC2_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_VBI_END 0x0ad9
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#define mmCRTC2_CRTC_VBI_END_BASE_IDX 2
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#define mmCRTC2_CRTC_V_TOTAL 0x0ada
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#define mmCRTC2_CRTC_V_TOTAL_BASE_IDX 2
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#define mmCRTC2_CRTC_V_TOTAL_MIN 0x0adb
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#define mmCRTC2_CRTC_V_TOTAL_MIN_BASE_IDX 2
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#define mmCRTC2_CRTC_V_TOTAL_MAX 0x0adc
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#define mmCRTC2_CRTC_V_TOTAL_MAX_BASE_IDX 2
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#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x0add
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#define mmCRTC2_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x0ade
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#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x0adf
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#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_V_BLANK_START_END 0x0ae0
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#define mmCRTC2_CRTC_V_BLANK_START_END_BASE_IDX 2
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#define mmCRTC2_CRTC_V_SYNC_A 0x0ae1
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#define mmCRTC2_CRTC_V_SYNC_A_BASE_IDX 2
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#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x0ae2
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#define mmCRTC2_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_V_SYNC_B 0x0ae3
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#define mmCRTC2_CRTC_V_SYNC_B_BASE_IDX 2
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#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x0ae4
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#define mmCRTC2_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_DTMTEST_CNTL 0x0ae5
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#define mmCRTC2_CRTC_DTMTEST_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x0ae6
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#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC2_CRTC_TRIGA_CNTL 0x0ae7
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#define mmCRTC2_CRTC_TRIGA_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x0ae8
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#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC2_CRTC_TRIGB_CNTL 0x0ae9
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#define mmCRTC2_CRTC_TRIGB_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x0aea
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#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x0aeb
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#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_FLOW_CONTROL 0x0aec
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#define mmCRTC2_CRTC_FLOW_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x0aed
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#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x0aee
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#define mmCRTC2_CRTC_AVSYNC_COUNTER_BASE_IDX 2
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#define mmCRTC2_CRTC_CONTROL 0x0aef
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#define mmCRTC2_CRTC_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_BLANK_CONTROL 0x0af0
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#define mmCRTC2_CRTC_BLANK_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x0af1
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#define mmCRTC2_CRTC_INTERLACE_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_INTERLACE_STATUS 0x0af2
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#define mmCRTC2_CRTC_INTERLACE_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x0af3
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#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x0af4
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#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x0af5
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#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmCRTC2_CRTC_STATUS 0x0af6
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#define mmCRTC2_CRTC_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_STATUS_POSITION 0x0af7
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#define mmCRTC2_CRTC_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x0af8
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#define mmCRTC2_CRTC_NOM_VERT_POSITION_BASE_IDX 2
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#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x0af9
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#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x0afa
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#define mmCRTC2_CRTC_STATUS_VF_COUNT_BASE_IDX 2
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#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x0afb
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#define mmCRTC2_CRTC_STATUS_HV_COUNT_BASE_IDX 2
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#define mmCRTC2_CRTC_COUNT_CONTROL 0x0afc
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#define mmCRTC2_CRTC_COUNT_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_COUNT_RESET 0x0afd
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#define mmCRTC2_CRTC_COUNT_RESET_BASE_IDX 2
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#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0afe
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#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x0aff
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#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_STEREO_STATUS 0x0b00
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#define mmCRTC2_CRTC_STEREO_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_STEREO_CONTROL 0x0b01
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#define mmCRTC2_CRTC_STEREO_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x0b02
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#define mmCRTC2_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x0b03
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#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x0b04
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#define mmCRTC2_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x0b05
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#define mmCRTC2_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmCRTC2_CRTC_START_LINE_CONTROL 0x0b06
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#define mmCRTC2_CRTC_START_LINE_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x0b07
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#define mmCRTC2_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_UPDATE_LOCK 0x0b08
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#define mmCRTC2_CRTC_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x0b09
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#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0b0a
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#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
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#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x0b0b
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#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x0b0c
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#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x0b0d
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#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x0b0e
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#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x0b0f
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#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x0b10
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#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
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#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0b11
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#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
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#define mmCRTC2_CRTC_MVP_STATUS 0x0b12
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#define mmCRTC2_CRTC_MVP_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_MASTER_EN 0x0b13
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#define mmCRTC2_CRTC_MASTER_EN_BASE_IDX 2
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#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x0b14
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#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
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#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x0b15
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#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x0b17
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#define mmCRTC2_CRTC_OVERSCAN_COLOR_BASE_IDX 2
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#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x0b18
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#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
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#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x0b19
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#define mmCRTC2_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x0b1a
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#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmCRTC2_CRTC_BLACK_COLOR 0x0b1b
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#define mmCRTC2_CRTC_BLACK_COLOR_BASE_IDX 2
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#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x0b1c
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#define mmCRTC2_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0b1d
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0b1e
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0b1f
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0b20
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0b21
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0b22
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#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC_CNTL 0x0b23
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#define mmCRTC2_CRTC_CRC_CNTL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x0b24
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#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0b25
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#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x0b26
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#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0b27
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#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC0_DATA_RG 0x0b28
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#define mmCRTC2_CRTC_CRC0_DATA_RG_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC0_DATA_B 0x0b29
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#define mmCRTC2_CRTC_CRC0_DATA_B_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x0b2a
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#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0b2b
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#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x0b2c
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#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0b2d
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#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC1_DATA_RG 0x0b2e
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#define mmCRTC2_CRTC_CRC1_DATA_RG_BASE_IDX 2
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#define mmCRTC2_CRTC_CRC1_DATA_B 0x0b2f
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#define mmCRTC2_CRTC_CRC1_DATA_B_BASE_IDX 2
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x0b30
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0b31
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0b32
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0b33
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0b34
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0b35
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#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x0b36
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#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x0b37
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#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x0b38
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#define mmCRTC2_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmCRTC2_CRTC_GSL_WINDOW 0x0b39
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#define mmCRTC2_CRTC_GSL_WINDOW_BASE_IDX 2
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#define mmCRTC2_CRTC_GSL_CONTROL 0x0b3a
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#define mmCRTC2_CRTC_GSL_CONTROL_BASE_IDX 2
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#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS 0x0b3d
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#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmCRTC2_CRTC_DRR_CONTROL 0x0b3e
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#define mmCRTC2_CRTC_DRR_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_fmt2_dispdec
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// base address: 0x1000
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#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x0b42
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#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
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#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x0b43
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#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x0b44
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#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x0b45
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#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
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#define mmFMT2_FMT_CONTROL 0x0b46
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#define mmFMT2_FMT_CONTROL_BASE_IDX 2
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#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x0b47
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#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x0b48
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#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x0b49
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#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x0b4a
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#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
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#define mmFMT2_FMT_CLAMP_CNTL 0x0b4e
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#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT2_FMT_CRC_CNTL 0x0b4f
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#define mmFMT2_FMT_CRC_CNTL_BASE_IDX 2
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#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x0b50
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#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0b51
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#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x0b52
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#define mmFMT2_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
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#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x0b53
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#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
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#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0b54
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#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
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#define mmFMT2_FMT_420_HBLANK_EARLY_START 0x0b55
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#define mmFMT2_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
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// addressBlock: dce_dc_dcp3_dispdec
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// base address: 0x1800
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#define mmDCP3_GRPH_ENABLE 0x0b5a
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#define mmDCP3_GRPH_ENABLE_BASE_IDX 2
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#define mmDCP3_GRPH_CONTROL 0x0b5b
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#define mmDCP3_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x0b5c
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#define mmDCP3_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
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#define mmDCP3_GRPH_SWAP_CNTL 0x0b5d
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#define mmDCP3_GRPH_SWAP_CNTL_BASE_IDX 2
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#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x0b5e
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#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x0b5f
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#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP3_GRPH_PITCH 0x0b60
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#define mmDCP3_GRPH_PITCH_BASE_IDX 2
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#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0b61
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#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0b62
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#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x0b63
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#define mmDCP3_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
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#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x0b64
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#define mmDCP3_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
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#define mmDCP3_GRPH_X_START 0x0b65
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#define mmDCP3_GRPH_X_START_BASE_IDX 2
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#define mmDCP3_GRPH_Y_START 0x0b66
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#define mmDCP3_GRPH_Y_START_BASE_IDX 2
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#define mmDCP3_GRPH_X_END 0x0b67
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#define mmDCP3_GRPH_X_END_BASE_IDX 2
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#define mmDCP3_GRPH_Y_END 0x0b68
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#define mmDCP3_GRPH_Y_END_BASE_IDX 2
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#define mmDCP3_INPUT_GAMMA_CONTROL 0x0b69
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#define mmDCP3_INPUT_GAMMA_CONTROL_BASE_IDX 2
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#define mmDCP3_GRPH_UPDATE 0x0b6a
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#define mmDCP3_GRPH_UPDATE_BASE_IDX 2
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#define mmDCP3_GRPH_FLIP_CONTROL 0x0b6b
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#define mmDCP3_GRPH_FLIP_CONTROL_BASE_IDX 2
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#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x0b6c
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#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
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#define mmDCP3_GRPH_DFQ_CONTROL 0x0b6d
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#define mmDCP3_GRPH_DFQ_CONTROL_BASE_IDX 2
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#define mmDCP3_GRPH_DFQ_STATUS 0x0b6e
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#define mmDCP3_GRPH_DFQ_STATUS_BASE_IDX 2
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#define mmDCP3_GRPH_INTERRUPT_STATUS 0x0b6f
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#define mmDCP3_GRPH_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x0b70
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#define mmDCP3_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0b71
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#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
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#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x0b72
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#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP3_GRPH_COMPRESS_PITCH 0x0b73
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#define mmDCP3_GRPH_COMPRESS_PITCH_BASE_IDX 2
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#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0b74
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#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0b75
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#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
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#define mmDCP3_PRESCALE_GRPH_CONTROL 0x0b76
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#define mmDCP3_PRESCALE_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x0b77
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#define mmDCP3_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
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#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x0b78
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#define mmDCP3_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
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#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x0b79
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#define mmDCP3_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
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#define mmDCP3_INPUT_CSC_CONTROL 0x0b7a
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#define mmDCP3_INPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP3_INPUT_CSC_C11_C12 0x0b7b
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#define mmDCP3_INPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP3_INPUT_CSC_C13_C14 0x0b7c
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#define mmDCP3_INPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP3_INPUT_CSC_C21_C22 0x0b7d
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#define mmDCP3_INPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP3_INPUT_CSC_C23_C24 0x0b7e
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#define mmDCP3_INPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP3_INPUT_CSC_C31_C32 0x0b7f
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#define mmDCP3_INPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP3_INPUT_CSC_C33_C34 0x0b80
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#define mmDCP3_INPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP3_OUTPUT_CSC_CONTROL 0x0b81
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#define mmDCP3_OUTPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP3_OUTPUT_CSC_C11_C12 0x0b82
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#define mmDCP3_OUTPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP3_OUTPUT_CSC_C13_C14 0x0b83
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#define mmDCP3_OUTPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP3_OUTPUT_CSC_C21_C22 0x0b84
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#define mmDCP3_OUTPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP3_OUTPUT_CSC_C23_C24 0x0b85
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#define mmDCP3_OUTPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP3_OUTPUT_CSC_C31_C32 0x0b86
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#define mmDCP3_OUTPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP3_OUTPUT_CSC_C33_C34 0x0b87
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#define mmDCP3_OUTPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x0b88
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#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x0b89
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#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x0b8a
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#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x0b8b
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#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x0b8c
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#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x0b8d
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#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x0b8e
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#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x0b8f
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#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x0b90
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#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x0b91
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#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x0b92
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#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x0b93
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#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP3_DENORM_CONTROL 0x0b94
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#define mmDCP3_DENORM_CONTROL_BASE_IDX 2
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#define mmDCP3_OUT_ROUND_CONTROL 0x0b95
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#define mmDCP3_OUT_ROUND_CONTROL_BASE_IDX 2
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#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x0b96
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#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
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#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x0b97
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#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
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#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x0b98
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#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
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#define mmDCP3_KEY_CONTROL 0x0b99
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#define mmDCP3_KEY_CONTROL_BASE_IDX 2
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#define mmDCP3_KEY_RANGE_ALPHA 0x0b9a
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#define mmDCP3_KEY_RANGE_ALPHA_BASE_IDX 2
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#define mmDCP3_KEY_RANGE_RED 0x0b9b
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#define mmDCP3_KEY_RANGE_RED_BASE_IDX 2
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#define mmDCP3_KEY_RANGE_GREEN 0x0b9c
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#define mmDCP3_KEY_RANGE_GREEN_BASE_IDX 2
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#define mmDCP3_KEY_RANGE_BLUE 0x0b9d
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#define mmDCP3_KEY_RANGE_BLUE_BASE_IDX 2
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#define mmDCP3_DEGAMMA_CONTROL 0x0b9e
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#define mmDCP3_DEGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP3_GAMUT_REMAP_CONTROL 0x0b9f
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#define mmDCP3_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmDCP3_GAMUT_REMAP_C11_C12 0x0ba0
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#define mmDCP3_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmDCP3_GAMUT_REMAP_C13_C14 0x0ba1
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#define mmDCP3_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmDCP3_GAMUT_REMAP_C21_C22 0x0ba2
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#define mmDCP3_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmDCP3_GAMUT_REMAP_C23_C24 0x0ba3
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#define mmDCP3_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmDCP3_GAMUT_REMAP_C31_C32 0x0ba4
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#define mmDCP3_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmDCP3_GAMUT_REMAP_C33_C34 0x0ba5
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#define mmDCP3_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x0ba6
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#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
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#define mmDCP3_DCP_RANDOM_SEEDS 0x0ba7
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#define mmDCP3_DCP_RANDOM_SEEDS_BASE_IDX 2
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#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x0ba8
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#define mmDCP3_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
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#define mmDCP3_CUR_CONTROL 0x0ba9
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#define mmDCP3_CUR_CONTROL_BASE_IDX 2
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#define mmDCP3_CUR_SURFACE_ADDRESS 0x0baa
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#define mmDCP3_CUR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP3_CUR_SIZE 0x0bab
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#define mmDCP3_CUR_SIZE_BASE_IDX 2
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#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x0bac
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#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP3_CUR_POSITION 0x0bad
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#define mmDCP3_CUR_POSITION_BASE_IDX 2
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#define mmDCP3_CUR_HOT_SPOT 0x0bae
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#define mmDCP3_CUR_HOT_SPOT_BASE_IDX 2
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#define mmDCP3_CUR_COLOR1 0x0baf
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#define mmDCP3_CUR_COLOR1_BASE_IDX 2
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#define mmDCP3_CUR_COLOR2 0x0bb0
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#define mmDCP3_CUR_COLOR2_BASE_IDX 2
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#define mmDCP3_CUR_UPDATE 0x0bb1
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#define mmDCP3_CUR_UPDATE_BASE_IDX 2
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#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x0bbb
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#define mmDCP3_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
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#define mmDCP3_CUR_STEREO_CONTROL 0x0bbc
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#define mmDCP3_CUR_STEREO_CONTROL_BASE_IDX 2
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#define mmDCP3_DC_LUT_RW_MODE 0x0bbe
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#define mmDCP3_DC_LUT_RW_MODE_BASE_IDX 2
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#define mmDCP3_DC_LUT_RW_INDEX 0x0bbf
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#define mmDCP3_DC_LUT_RW_INDEX_BASE_IDX 2
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#define mmDCP3_DC_LUT_SEQ_COLOR 0x0bc0
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#define mmDCP3_DC_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmDCP3_DC_LUT_PWL_DATA 0x0bc1
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#define mmDCP3_DC_LUT_PWL_DATA_BASE_IDX 2
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#define mmDCP3_DC_LUT_30_COLOR 0x0bc2
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#define mmDCP3_DC_LUT_30_COLOR_BASE_IDX 2
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#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x0bc3
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#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
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#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x0bc4
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#define mmDCP3_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP3_DC_LUT_AUTOFILL 0x0bc5
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#define mmDCP3_DC_LUT_AUTOFILL_BASE_IDX 2
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#define mmDCP3_DC_LUT_CONTROL 0x0bc6
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#define mmDCP3_DC_LUT_CONTROL_BASE_IDX 2
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#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x0bc7
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#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x0bc8
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#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x0bc9
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#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
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#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x0bca
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#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x0bcb
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#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x0bcc
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#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
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#define mmDCP3_DCP_CRC_CONTROL 0x0bcd
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#define mmDCP3_DCP_CRC_CONTROL_BASE_IDX 2
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#define mmDCP3_DCP_CRC_MASK 0x0bce
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#define mmDCP3_DCP_CRC_MASK_BASE_IDX 2
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#define mmDCP3_DCP_CRC_CURRENT 0x0bcf
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#define mmDCP3_DCP_CRC_CURRENT_BASE_IDX 2
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#define mmDCP3_DVMM_PTE_CONTROL 0x0bd0
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#define mmDCP3_DVMM_PTE_CONTROL_BASE_IDX 2
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#define mmDCP3_DCP_CRC_LAST 0x0bd1
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#define mmDCP3_DCP_CRC_LAST_BASE_IDX 2
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#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x0bd2
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#define mmDCP3_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
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#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x0bd4
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#define mmDCP3_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
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#define mmDCP3_DCP_GSL_CONTROL 0x0bd5
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#define mmDCP3_DCP_GSL_CONTROL_BASE_IDX 2
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#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0bd6
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#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
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#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x0bdc
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#define mmDCP3_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
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#define mmDCP3_HW_ROTATION 0x0bde
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#define mmDCP3_HW_ROTATION_BASE_IDX 2
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#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0bdf
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#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
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#define mmDCP3_REGAMMA_CONTROL 0x0be0
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#define mmDCP3_REGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP3_REGAMMA_LUT_INDEX 0x0be1
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#define mmDCP3_REGAMMA_LUT_INDEX_BASE_IDX 2
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#define mmDCP3_REGAMMA_LUT_DATA 0x0be2
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#define mmDCP3_REGAMMA_LUT_DATA_BASE_IDX 2
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#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x0be3
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#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x0be4
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#define mmDCP3_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x0be5
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#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x0be6
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#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x0be7
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#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x0be8
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#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x0be9
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#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x0bea
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#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x0beb
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#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x0bec
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#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x0bed
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#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x0bee
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#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x0bef
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#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x0bf0
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#define mmDCP3_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x0bf1
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#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x0bf2
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#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x0bf3
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#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x0bf4
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#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x0bf5
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#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x0bf6
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#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x0bf7
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#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x0bf8
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#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x0bf9
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#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x0bfa
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#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
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#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x0bfb
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#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
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#define mmDCP3_ALPHA_CONTROL 0x0bfc
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#define mmDCP3_ALPHA_CONTROL_BASE_IDX 2
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#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0bfd
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#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0bfe
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#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0bff
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#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
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#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT 0x0c00
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#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
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#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY 0x0c01
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#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
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#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x0c02
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#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
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#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x0c03
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#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
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// addressBlock: dce_dc_lb3_dispdec
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// base address: 0x1800
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#define mmLB3_LB_DATA_FORMAT 0x0c1a
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#define mmLB3_LB_DATA_FORMAT_BASE_IDX 2
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#define mmLB3_LB_MEMORY_CTRL 0x0c1b
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#define mmLB3_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmLB3_LB_MEMORY_SIZE_STATUS 0x0c1c
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#define mmLB3_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
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#define mmLB3_LB_DESKTOP_HEIGHT 0x0c1d
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#define mmLB3_LB_DESKTOP_HEIGHT_BASE_IDX 2
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#define mmLB3_LB_VLINE_START_END 0x0c1e
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#define mmLB3_LB_VLINE_START_END_BASE_IDX 2
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#define mmLB3_LB_VLINE2_START_END 0x0c1f
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#define mmLB3_LB_VLINE2_START_END_BASE_IDX 2
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#define mmLB3_LB_V_COUNTER 0x0c20
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#define mmLB3_LB_V_COUNTER_BASE_IDX 2
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#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x0c21
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#define mmLB3_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
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#define mmLB3_LB_INTERRUPT_MASK 0x0c22
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#define mmLB3_LB_INTERRUPT_MASK_BASE_IDX 2
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#define mmLB3_LB_VLINE_STATUS 0x0c23
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#define mmLB3_LB_VLINE_STATUS_BASE_IDX 2
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#define mmLB3_LB_VLINE2_STATUS 0x0c24
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#define mmLB3_LB_VLINE2_STATUS_BASE_IDX 2
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#define mmLB3_LB_VBLANK_STATUS 0x0c25
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#define mmLB3_LB_VBLANK_STATUS_BASE_IDX 2
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#define mmLB3_LB_SYNC_RESET_SEL 0x0c26
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#define mmLB3_LB_SYNC_RESET_SEL_BASE_IDX 2
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#define mmLB3_LB_BLACK_KEYER_R_CR 0x0c27
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#define mmLB3_LB_BLACK_KEYER_R_CR_BASE_IDX 2
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#define mmLB3_LB_BLACK_KEYER_G_Y 0x0c28
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#define mmLB3_LB_BLACK_KEYER_G_Y_BASE_IDX 2
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#define mmLB3_LB_BLACK_KEYER_B_CB 0x0c29
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#define mmLB3_LB_BLACK_KEYER_B_CB_BASE_IDX 2
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#define mmLB3_LB_KEYER_COLOR_CTRL 0x0c2a
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#define mmLB3_LB_KEYER_COLOR_CTRL_BASE_IDX 2
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#define mmLB3_LB_KEYER_COLOR_R_CR 0x0c2b
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#define mmLB3_LB_KEYER_COLOR_R_CR_BASE_IDX 2
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#define mmLB3_LB_KEYER_COLOR_G_Y 0x0c2c
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#define mmLB3_LB_KEYER_COLOR_G_Y_BASE_IDX 2
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#define mmLB3_LB_KEYER_COLOR_B_CB 0x0c2d
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#define mmLB3_LB_KEYER_COLOR_B_CB_BASE_IDX 2
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#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x0c2e
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#define mmLB3_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
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#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x0c2f
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#define mmLB3_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
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#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x0c30
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#define mmLB3_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
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#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x0c31
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#define mmLB3_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
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#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x0c32
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#define mmLB3_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
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#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x0c33
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#define mmLB3_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
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#define mmLB3_LB_BUFFER_STATUS 0x0c34
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#define mmLB3_LB_BUFFER_STATUS_BASE_IDX 2
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#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x0c35
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#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
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#define mmLB3_MVP_AFR_FLIP_MODE 0x0c36
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#define mmLB3_MVP_AFR_FLIP_MODE_BASE_IDX 2
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#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x0c37
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#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
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#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x0c38
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#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
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#define mmLB3_DC_MVP_LB_CONTROL 0x0c39
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#define mmLB3_DC_MVP_LB_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dcfe3_dispdec
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// base address: 0x1800
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#define mmDCFE3_DCFE_CLOCK_CONTROL 0x0c5a
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#define mmDCFE3_DCFE_CLOCK_CONTROL_BASE_IDX 2
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#define mmDCFE3_DCFE_SOFT_RESET 0x0c5b
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#define mmDCFE3_DCFE_SOFT_RESET_BASE_IDX 2
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#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x0c5d
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#define mmDCFE3_DCFE_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x0c5e
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#define mmDCFE3_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x0c5f
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#define mmDCFE3_DCFE_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFE3_DCFE_MISC 0x0c60
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#define mmDCFE3_DCFE_MISC_BASE_IDX 2
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#define mmDCFE3_DCFE_FLUSH 0x0c61
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#define mmDCFE3_DCFE_FLUSH_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon6_dispdec
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// base address: 0x3138
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x0c6e
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x0c6f
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x0c70
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#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CNTL 0x0c71
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#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CNTL2 0x0c72
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#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0c73
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#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0c74
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#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_HI 0x0c75
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#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_LOW 0x0c76
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#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dmif_pg3_dispdec
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// base address: 0x1800
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#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x0c7a
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#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
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#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x0c7b
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#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x0c7c
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#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
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#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x0c7d
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#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
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#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0c7e
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#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
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#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x0c7f
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#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
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#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2 0x0c80
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#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL 0x0c81
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#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
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#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x0c82
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#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_BASE_IDX 2
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#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x0c86
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#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
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#define mmDMIF_PG3_DPG_DVMM_STATUS 0x0c87
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#define mmDMIF_PG3_DPG_DVMM_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_scl3_dispdec
|
// base address: 0x1800
|
#define mmSCL3_SCL_COEF_RAM_SELECT 0x0c9a
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#define mmSCL3_SCL_COEF_RAM_SELECT_BASE_IDX 2
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#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x0c9b
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#define mmSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmSCL3_SCL_MODE 0x0c9c
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#define mmSCL3_SCL_MODE_BASE_IDX 2
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#define mmSCL3_SCL_TAP_CONTROL 0x0c9d
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#define mmSCL3_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmSCL3_SCL_CONTROL 0x0c9e
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#define mmSCL3_SCL_CONTROL_BASE_IDX 2
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#define mmSCL3_SCL_BYPASS_CONTROL 0x0c9f
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#define mmSCL3_SCL_BYPASS_CONTROL_BASE_IDX 2
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#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0ca0
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#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x0ca1
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#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
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#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x0ca2
|
#define mmSCL3_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0ca3
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#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL3_SCL_HORZ_FILTER_INIT 0x0ca4
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#define mmSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x0ca5
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#define mmSCL3_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0ca6
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#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL3_SCL_VERT_FILTER_INIT 0x0ca7
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#define mmSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x0ca8
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#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCL3_SCL_ROUND_OFFSET 0x0ca9
|
#define mmSCL3_SCL_ROUND_OFFSET_BASE_IDX 2
|
#define mmSCL3_SCL_UPDATE 0x0caa
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#define mmSCL3_SCL_UPDATE_BASE_IDX 2
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#define mmSCL3_SCL_F_SHARP_CONTROL 0x0cab
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#define mmSCL3_SCL_F_SHARP_CONTROL_BASE_IDX 2
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#define mmSCL3_SCL_ALU_CONTROL 0x0cac
|
#define mmSCL3_SCL_ALU_CONTROL_BASE_IDX 2
|
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x0cad
|
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
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#define mmSCL3_VIEWPORT_START_SECONDARY 0x0cae
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#define mmSCL3_VIEWPORT_START_SECONDARY_BASE_IDX 2
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#define mmSCL3_VIEWPORT_START 0x0caf
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#define mmSCL3_VIEWPORT_START_BASE_IDX 2
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#define mmSCL3_VIEWPORT_SIZE 0x0cb0
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#define mmSCL3_VIEWPORT_SIZE_BASE_IDX 2
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#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x0cb1
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#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x0cb2
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#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmSCL3_SCL_MODE_CHANGE_DET1 0x0cb3
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#define mmSCL3_SCL_MODE_CHANGE_DET1_BASE_IDX 2
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#define mmSCL3_SCL_MODE_CHANGE_DET2 0x0cb4
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#define mmSCL3_SCL_MODE_CHANGE_DET2_BASE_IDX 2
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#define mmSCL3_SCL_MODE_CHANGE_DET3 0x0cb5
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#define mmSCL3_SCL_MODE_CHANGE_DET3_BASE_IDX 2
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#define mmSCL3_SCL_MODE_CHANGE_MASK 0x0cb6
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#define mmSCL3_SCL_MODE_CHANGE_MASK_BASE_IDX 2
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// addressBlock: dce_dc_blnd3_dispdec
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// base address: 0x1800
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#define mmBLND3_BLND_CONTROL 0x0cc7
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#define mmBLND3_BLND_CONTROL_BASE_IDX 2
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#define mmBLND3_BLND_SM_CONTROL2 0x0cc8
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#define mmBLND3_BLND_SM_CONTROL2_BASE_IDX 2
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#define mmBLND3_BLND_CONTROL2 0x0cc9
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#define mmBLND3_BLND_CONTROL2_BASE_IDX 2
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#define mmBLND3_BLND_UPDATE 0x0cca
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#define mmBLND3_BLND_UPDATE_BASE_IDX 2
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#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x0ccb
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#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
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#define mmBLND3_BLND_V_UPDATE_LOCK 0x0ccc
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#define mmBLND3_BLND_V_UPDATE_LOCK_BASE_IDX 2
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#define mmBLND3_BLND_REG_UPDATE_STATUS 0x0ccd
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#define mmBLND3_BLND_REG_UPDATE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_crtc3_dispdec
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// base address: 0x1800
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#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x0cd2
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#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
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#define mmCRTC3_CRTC_H_TOTAL 0x0cd3
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#define mmCRTC3_CRTC_H_TOTAL_BASE_IDX 2
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#define mmCRTC3_CRTC_H_BLANK_START_END 0x0cd4
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#define mmCRTC3_CRTC_H_BLANK_START_END_BASE_IDX 2
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#define mmCRTC3_CRTC_H_SYNC_A 0x0cd5
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#define mmCRTC3_CRTC_H_SYNC_A_BASE_IDX 2
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#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x0cd6
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#define mmCRTC3_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_H_SYNC_B 0x0cd7
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#define mmCRTC3_CRTC_H_SYNC_B_BASE_IDX 2
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#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x0cd8
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#define mmCRTC3_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_VBI_END 0x0cd9
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#define mmCRTC3_CRTC_VBI_END_BASE_IDX 2
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#define mmCRTC3_CRTC_V_TOTAL 0x0cda
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#define mmCRTC3_CRTC_V_TOTAL_BASE_IDX 2
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#define mmCRTC3_CRTC_V_TOTAL_MIN 0x0cdb
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#define mmCRTC3_CRTC_V_TOTAL_MIN_BASE_IDX 2
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#define mmCRTC3_CRTC_V_TOTAL_MAX 0x0cdc
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#define mmCRTC3_CRTC_V_TOTAL_MAX_BASE_IDX 2
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#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x0cdd
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#define mmCRTC3_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x0cde
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#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x0cdf
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#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_V_BLANK_START_END 0x0ce0
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#define mmCRTC3_CRTC_V_BLANK_START_END_BASE_IDX 2
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#define mmCRTC3_CRTC_V_SYNC_A 0x0ce1
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#define mmCRTC3_CRTC_V_SYNC_A_BASE_IDX 2
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#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x0ce2
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#define mmCRTC3_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_V_SYNC_B 0x0ce3
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#define mmCRTC3_CRTC_V_SYNC_B_BASE_IDX 2
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#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x0ce4
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#define mmCRTC3_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_DTMTEST_CNTL 0x0ce5
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#define mmCRTC3_CRTC_DTMTEST_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x0ce6
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#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC3_CRTC_TRIGA_CNTL 0x0ce7
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#define mmCRTC3_CRTC_TRIGA_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x0ce8
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#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC3_CRTC_TRIGB_CNTL 0x0ce9
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#define mmCRTC3_CRTC_TRIGB_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x0cea
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#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x0ceb
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#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_FLOW_CONTROL 0x0cec
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#define mmCRTC3_CRTC_FLOW_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x0ced
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#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x0cee
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#define mmCRTC3_CRTC_AVSYNC_COUNTER_BASE_IDX 2
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#define mmCRTC3_CRTC_CONTROL 0x0cef
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#define mmCRTC3_CRTC_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_BLANK_CONTROL 0x0cf0
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#define mmCRTC3_CRTC_BLANK_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x0cf1
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#define mmCRTC3_CRTC_INTERLACE_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_INTERLACE_STATUS 0x0cf2
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#define mmCRTC3_CRTC_INTERLACE_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x0cf3
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#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x0cf4
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#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x0cf5
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#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmCRTC3_CRTC_STATUS 0x0cf6
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#define mmCRTC3_CRTC_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_STATUS_POSITION 0x0cf7
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#define mmCRTC3_CRTC_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x0cf8
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#define mmCRTC3_CRTC_NOM_VERT_POSITION_BASE_IDX 2
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#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x0cf9
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#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x0cfa
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#define mmCRTC3_CRTC_STATUS_VF_COUNT_BASE_IDX 2
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#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x0cfb
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#define mmCRTC3_CRTC_STATUS_HV_COUNT_BASE_IDX 2
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#define mmCRTC3_CRTC_COUNT_CONTROL 0x0cfc
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#define mmCRTC3_CRTC_COUNT_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_COUNT_RESET 0x0cfd
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#define mmCRTC3_CRTC_COUNT_RESET_BASE_IDX 2
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#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0cfe
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#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x0cff
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#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_STEREO_STATUS 0x0d00
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#define mmCRTC3_CRTC_STEREO_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_STEREO_CONTROL 0x0d01
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#define mmCRTC3_CRTC_STEREO_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x0d02
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#define mmCRTC3_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x0d03
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#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x0d04
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#define mmCRTC3_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x0d05
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#define mmCRTC3_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmCRTC3_CRTC_START_LINE_CONTROL 0x0d06
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#define mmCRTC3_CRTC_START_LINE_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x0d07
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#define mmCRTC3_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_UPDATE_LOCK 0x0d08
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#define mmCRTC3_CRTC_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x0d09
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#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0d0a
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#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
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#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x0d0b
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#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x0d0c
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#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x0d0d
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#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x0d0e
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#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x0d0f
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#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x0d10
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#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
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#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0d11
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#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
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#define mmCRTC3_CRTC_MVP_STATUS 0x0d12
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#define mmCRTC3_CRTC_MVP_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_MASTER_EN 0x0d13
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#define mmCRTC3_CRTC_MASTER_EN_BASE_IDX 2
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#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x0d14
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#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
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#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x0d15
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#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x0d17
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#define mmCRTC3_CRTC_OVERSCAN_COLOR_BASE_IDX 2
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#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x0d18
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#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
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#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x0d19
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#define mmCRTC3_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x0d1a
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#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmCRTC3_CRTC_BLACK_COLOR 0x0d1b
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#define mmCRTC3_CRTC_BLACK_COLOR_BASE_IDX 2
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#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x0d1c
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#define mmCRTC3_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0d1d
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0d1e
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0d1f
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0d20
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0d21
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0d22
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#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC_CNTL 0x0d23
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#define mmCRTC3_CRTC_CRC_CNTL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x0d24
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#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0d25
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#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x0d26
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#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0d27
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#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC0_DATA_RG 0x0d28
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#define mmCRTC3_CRTC_CRC0_DATA_RG_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC0_DATA_B 0x0d29
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#define mmCRTC3_CRTC_CRC0_DATA_B_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x0d2a
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#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0d2b
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#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x0d2c
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#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0d2d
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#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC1_DATA_RG 0x0d2e
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#define mmCRTC3_CRTC_CRC1_DATA_RG_BASE_IDX 2
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#define mmCRTC3_CRTC_CRC1_DATA_B 0x0d2f
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#define mmCRTC3_CRTC_CRC1_DATA_B_BASE_IDX 2
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x0d30
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0d31
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0d32
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0d33
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0d34
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0d35
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#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x0d36
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#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x0d37
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#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x0d38
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#define mmCRTC3_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmCRTC3_CRTC_GSL_WINDOW 0x0d39
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#define mmCRTC3_CRTC_GSL_WINDOW_BASE_IDX 2
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#define mmCRTC3_CRTC_GSL_CONTROL 0x0d3a
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#define mmCRTC3_CRTC_GSL_CONTROL_BASE_IDX 2
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#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS 0x0d3d
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#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmCRTC3_CRTC_DRR_CONTROL 0x0d3e
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#define mmCRTC3_CRTC_DRR_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_fmt3_dispdec
|
// base address: 0x1800
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#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x0d42
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#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
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#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x0d43
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#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x0d44
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#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x0d45
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#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
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#define mmFMT3_FMT_CONTROL 0x0d46
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#define mmFMT3_FMT_CONTROL_BASE_IDX 2
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#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x0d47
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#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x0d48
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#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x0d49
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#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x0d4a
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#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
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#define mmFMT3_FMT_CLAMP_CNTL 0x0d4e
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#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT3_FMT_CRC_CNTL 0x0d4f
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#define mmFMT3_FMT_CRC_CNTL_BASE_IDX 2
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#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x0d50
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#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0d51
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#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x0d52
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#define mmFMT3_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
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#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x0d53
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#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
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#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0d54
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#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
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#define mmFMT3_FMT_420_HBLANK_EARLY_START 0x0d55
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#define mmFMT3_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
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// addressBlock: dce_dc_dcp4_dispdec
|
// base address: 0x2000
|
#define mmDCP4_GRPH_ENABLE 0x0d5a
|
#define mmDCP4_GRPH_ENABLE_BASE_IDX 2
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#define mmDCP4_GRPH_CONTROL 0x0d5b
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#define mmDCP4_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x0d5c
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#define mmDCP4_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
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#define mmDCP4_GRPH_SWAP_CNTL 0x0d5d
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#define mmDCP4_GRPH_SWAP_CNTL_BASE_IDX 2
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#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x0d5e
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#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x0d5f
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#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP4_GRPH_PITCH 0x0d60
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#define mmDCP4_GRPH_PITCH_BASE_IDX 2
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#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0d61
|
#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0d62
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#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x0d63
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#define mmDCP4_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
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#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x0d64
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#define mmDCP4_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
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#define mmDCP4_GRPH_X_START 0x0d65
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#define mmDCP4_GRPH_X_START_BASE_IDX 2
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#define mmDCP4_GRPH_Y_START 0x0d66
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#define mmDCP4_GRPH_Y_START_BASE_IDX 2
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#define mmDCP4_GRPH_X_END 0x0d67
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#define mmDCP4_GRPH_X_END_BASE_IDX 2
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#define mmDCP4_GRPH_Y_END 0x0d68
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#define mmDCP4_GRPH_Y_END_BASE_IDX 2
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#define mmDCP4_INPUT_GAMMA_CONTROL 0x0d69
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#define mmDCP4_INPUT_GAMMA_CONTROL_BASE_IDX 2
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#define mmDCP4_GRPH_UPDATE 0x0d6a
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#define mmDCP4_GRPH_UPDATE_BASE_IDX 2
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#define mmDCP4_GRPH_FLIP_CONTROL 0x0d6b
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#define mmDCP4_GRPH_FLIP_CONTROL_BASE_IDX 2
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#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x0d6c
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#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
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#define mmDCP4_GRPH_DFQ_CONTROL 0x0d6d
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#define mmDCP4_GRPH_DFQ_CONTROL_BASE_IDX 2
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#define mmDCP4_GRPH_DFQ_STATUS 0x0d6e
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#define mmDCP4_GRPH_DFQ_STATUS_BASE_IDX 2
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#define mmDCP4_GRPH_INTERRUPT_STATUS 0x0d6f
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#define mmDCP4_GRPH_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x0d70
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#define mmDCP4_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0d71
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#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
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#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x0d72
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#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP4_GRPH_COMPRESS_PITCH 0x0d73
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#define mmDCP4_GRPH_COMPRESS_PITCH_BASE_IDX 2
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#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0d74
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#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0d75
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#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
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#define mmDCP4_PRESCALE_GRPH_CONTROL 0x0d76
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#define mmDCP4_PRESCALE_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x0d77
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#define mmDCP4_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
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#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x0d78
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#define mmDCP4_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
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#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x0d79
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#define mmDCP4_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
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#define mmDCP4_INPUT_CSC_CONTROL 0x0d7a
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#define mmDCP4_INPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP4_INPUT_CSC_C11_C12 0x0d7b
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#define mmDCP4_INPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP4_INPUT_CSC_C13_C14 0x0d7c
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#define mmDCP4_INPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP4_INPUT_CSC_C21_C22 0x0d7d
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#define mmDCP4_INPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP4_INPUT_CSC_C23_C24 0x0d7e
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#define mmDCP4_INPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP4_INPUT_CSC_C31_C32 0x0d7f
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#define mmDCP4_INPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP4_INPUT_CSC_C33_C34 0x0d80
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#define mmDCP4_INPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP4_OUTPUT_CSC_CONTROL 0x0d81
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#define mmDCP4_OUTPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP4_OUTPUT_CSC_C11_C12 0x0d82
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#define mmDCP4_OUTPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP4_OUTPUT_CSC_C13_C14 0x0d83
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#define mmDCP4_OUTPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP4_OUTPUT_CSC_C21_C22 0x0d84
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#define mmDCP4_OUTPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP4_OUTPUT_CSC_C23_C24 0x0d85
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#define mmDCP4_OUTPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP4_OUTPUT_CSC_C31_C32 0x0d86
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#define mmDCP4_OUTPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP4_OUTPUT_CSC_C33_C34 0x0d87
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#define mmDCP4_OUTPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x0d88
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#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x0d89
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#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x0d8a
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#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x0d8b
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#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x0d8c
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#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x0d8d
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#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x0d8e
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#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x0d8f
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#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x0d90
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#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x0d91
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#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x0d92
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#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x0d93
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#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP4_DENORM_CONTROL 0x0d94
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#define mmDCP4_DENORM_CONTROL_BASE_IDX 2
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#define mmDCP4_OUT_ROUND_CONTROL 0x0d95
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#define mmDCP4_OUT_ROUND_CONTROL_BASE_IDX 2
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#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x0d96
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#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
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#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x0d97
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#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
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#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x0d98
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#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
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#define mmDCP4_KEY_CONTROL 0x0d99
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#define mmDCP4_KEY_CONTROL_BASE_IDX 2
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#define mmDCP4_KEY_RANGE_ALPHA 0x0d9a
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#define mmDCP4_KEY_RANGE_ALPHA_BASE_IDX 2
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#define mmDCP4_KEY_RANGE_RED 0x0d9b
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#define mmDCP4_KEY_RANGE_RED_BASE_IDX 2
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#define mmDCP4_KEY_RANGE_GREEN 0x0d9c
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#define mmDCP4_KEY_RANGE_GREEN_BASE_IDX 2
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#define mmDCP4_KEY_RANGE_BLUE 0x0d9d
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#define mmDCP4_KEY_RANGE_BLUE_BASE_IDX 2
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#define mmDCP4_DEGAMMA_CONTROL 0x0d9e
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#define mmDCP4_DEGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP4_GAMUT_REMAP_CONTROL 0x0d9f
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#define mmDCP4_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmDCP4_GAMUT_REMAP_C11_C12 0x0da0
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#define mmDCP4_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmDCP4_GAMUT_REMAP_C13_C14 0x0da1
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#define mmDCP4_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmDCP4_GAMUT_REMAP_C21_C22 0x0da2
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#define mmDCP4_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmDCP4_GAMUT_REMAP_C23_C24 0x0da3
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#define mmDCP4_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmDCP4_GAMUT_REMAP_C31_C32 0x0da4
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#define mmDCP4_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmDCP4_GAMUT_REMAP_C33_C34 0x0da5
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#define mmDCP4_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x0da6
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#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
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#define mmDCP4_DCP_RANDOM_SEEDS 0x0da7
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#define mmDCP4_DCP_RANDOM_SEEDS_BASE_IDX 2
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#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x0da8
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#define mmDCP4_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
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#define mmDCP4_CUR_CONTROL 0x0da9
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#define mmDCP4_CUR_CONTROL_BASE_IDX 2
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#define mmDCP4_CUR_SURFACE_ADDRESS 0x0daa
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#define mmDCP4_CUR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP4_CUR_SIZE 0x0dab
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#define mmDCP4_CUR_SIZE_BASE_IDX 2
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#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x0dac
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#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP4_CUR_POSITION 0x0dad
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#define mmDCP4_CUR_POSITION_BASE_IDX 2
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#define mmDCP4_CUR_HOT_SPOT 0x0dae
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#define mmDCP4_CUR_HOT_SPOT_BASE_IDX 2
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#define mmDCP4_CUR_COLOR1 0x0daf
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#define mmDCP4_CUR_COLOR1_BASE_IDX 2
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#define mmDCP4_CUR_COLOR2 0x0db0
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#define mmDCP4_CUR_COLOR2_BASE_IDX 2
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#define mmDCP4_CUR_UPDATE 0x0db1
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#define mmDCP4_CUR_UPDATE_BASE_IDX 2
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#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x0dbb
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#define mmDCP4_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
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#define mmDCP4_CUR_STEREO_CONTROL 0x0dbc
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#define mmDCP4_CUR_STEREO_CONTROL_BASE_IDX 2
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#define mmDCP4_DC_LUT_RW_MODE 0x0dbe
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#define mmDCP4_DC_LUT_RW_MODE_BASE_IDX 2
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#define mmDCP4_DC_LUT_RW_INDEX 0x0dbf
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#define mmDCP4_DC_LUT_RW_INDEX_BASE_IDX 2
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#define mmDCP4_DC_LUT_SEQ_COLOR 0x0dc0
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#define mmDCP4_DC_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmDCP4_DC_LUT_PWL_DATA 0x0dc1
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#define mmDCP4_DC_LUT_PWL_DATA_BASE_IDX 2
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#define mmDCP4_DC_LUT_30_COLOR 0x0dc2
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#define mmDCP4_DC_LUT_30_COLOR_BASE_IDX 2
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#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x0dc3
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#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
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#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x0dc4
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#define mmDCP4_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP4_DC_LUT_AUTOFILL 0x0dc5
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#define mmDCP4_DC_LUT_AUTOFILL_BASE_IDX 2
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#define mmDCP4_DC_LUT_CONTROL 0x0dc6
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#define mmDCP4_DC_LUT_CONTROL_BASE_IDX 2
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#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x0dc7
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#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x0dc8
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#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x0dc9
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#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
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#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x0dca
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#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x0dcb
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#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x0dcc
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#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
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#define mmDCP4_DCP_CRC_CONTROL 0x0dcd
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#define mmDCP4_DCP_CRC_CONTROL_BASE_IDX 2
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#define mmDCP4_DCP_CRC_MASK 0x0dce
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#define mmDCP4_DCP_CRC_MASK_BASE_IDX 2
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#define mmDCP4_DCP_CRC_CURRENT 0x0dcf
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#define mmDCP4_DCP_CRC_CURRENT_BASE_IDX 2
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#define mmDCP4_DVMM_PTE_CONTROL 0x0dd0
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#define mmDCP4_DVMM_PTE_CONTROL_BASE_IDX 2
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#define mmDCP4_DCP_CRC_LAST 0x0dd1
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#define mmDCP4_DCP_CRC_LAST_BASE_IDX 2
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#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x0dd2
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#define mmDCP4_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
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#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x0dd4
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#define mmDCP4_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
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#define mmDCP4_DCP_GSL_CONTROL 0x0dd5
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#define mmDCP4_DCP_GSL_CONTROL_BASE_IDX 2
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#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0dd6
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#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
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#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x0ddc
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#define mmDCP4_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
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#define mmDCP4_HW_ROTATION 0x0dde
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#define mmDCP4_HW_ROTATION_BASE_IDX 2
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#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0ddf
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#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
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#define mmDCP4_REGAMMA_CONTROL 0x0de0
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#define mmDCP4_REGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP4_REGAMMA_LUT_INDEX 0x0de1
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#define mmDCP4_REGAMMA_LUT_INDEX_BASE_IDX 2
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#define mmDCP4_REGAMMA_LUT_DATA 0x0de2
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#define mmDCP4_REGAMMA_LUT_DATA_BASE_IDX 2
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#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x0de3
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#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x0de4
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#define mmDCP4_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x0de5
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#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x0de6
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#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x0de7
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#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x0de8
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#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x0de9
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#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x0dea
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#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x0deb
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#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x0dec
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#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x0ded
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#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x0dee
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#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x0def
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#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x0df0
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#define mmDCP4_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x0df1
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#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x0df2
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#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x0df3
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#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x0df4
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#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x0df5
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#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x0df6
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#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x0df7
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#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x0df8
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#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x0df9
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#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x0dfa
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#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
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#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x0dfb
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#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
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#define mmDCP4_ALPHA_CONTROL 0x0dfc
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#define mmDCP4_ALPHA_CONTROL_BASE_IDX 2
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#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0dfd
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#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0dfe
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#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0dff
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#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
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#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT 0x0e00
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#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
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#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY 0x0e01
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#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
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#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x0e02
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#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
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#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x0e03
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#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
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// addressBlock: dce_dc_lb4_dispdec
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// base address: 0x2000
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#define mmLB4_LB_DATA_FORMAT 0x0e1a
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#define mmLB4_LB_DATA_FORMAT_BASE_IDX 2
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#define mmLB4_LB_MEMORY_CTRL 0x0e1b
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#define mmLB4_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmLB4_LB_MEMORY_SIZE_STATUS 0x0e1c
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#define mmLB4_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
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#define mmLB4_LB_DESKTOP_HEIGHT 0x0e1d
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#define mmLB4_LB_DESKTOP_HEIGHT_BASE_IDX 2
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#define mmLB4_LB_VLINE_START_END 0x0e1e
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#define mmLB4_LB_VLINE_START_END_BASE_IDX 2
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#define mmLB4_LB_VLINE2_START_END 0x0e1f
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#define mmLB4_LB_VLINE2_START_END_BASE_IDX 2
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#define mmLB4_LB_V_COUNTER 0x0e20
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#define mmLB4_LB_V_COUNTER_BASE_IDX 2
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#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x0e21
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#define mmLB4_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
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#define mmLB4_LB_INTERRUPT_MASK 0x0e22
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#define mmLB4_LB_INTERRUPT_MASK_BASE_IDX 2
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#define mmLB4_LB_VLINE_STATUS 0x0e23
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#define mmLB4_LB_VLINE_STATUS_BASE_IDX 2
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#define mmLB4_LB_VLINE2_STATUS 0x0e24
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#define mmLB4_LB_VLINE2_STATUS_BASE_IDX 2
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#define mmLB4_LB_VBLANK_STATUS 0x0e25
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#define mmLB4_LB_VBLANK_STATUS_BASE_IDX 2
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#define mmLB4_LB_SYNC_RESET_SEL 0x0e26
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#define mmLB4_LB_SYNC_RESET_SEL_BASE_IDX 2
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#define mmLB4_LB_BLACK_KEYER_R_CR 0x0e27
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#define mmLB4_LB_BLACK_KEYER_R_CR_BASE_IDX 2
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#define mmLB4_LB_BLACK_KEYER_G_Y 0x0e28
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#define mmLB4_LB_BLACK_KEYER_G_Y_BASE_IDX 2
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#define mmLB4_LB_BLACK_KEYER_B_CB 0x0e29
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#define mmLB4_LB_BLACK_KEYER_B_CB_BASE_IDX 2
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#define mmLB4_LB_KEYER_COLOR_CTRL 0x0e2a
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#define mmLB4_LB_KEYER_COLOR_CTRL_BASE_IDX 2
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#define mmLB4_LB_KEYER_COLOR_R_CR 0x0e2b
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#define mmLB4_LB_KEYER_COLOR_R_CR_BASE_IDX 2
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#define mmLB4_LB_KEYER_COLOR_G_Y 0x0e2c
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#define mmLB4_LB_KEYER_COLOR_G_Y_BASE_IDX 2
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#define mmLB4_LB_KEYER_COLOR_B_CB 0x0e2d
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#define mmLB4_LB_KEYER_COLOR_B_CB_BASE_IDX 2
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#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x0e2e
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#define mmLB4_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
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#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x0e2f
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#define mmLB4_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
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#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x0e30
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#define mmLB4_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
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#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x0e31
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#define mmLB4_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
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#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x0e32
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#define mmLB4_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
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#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x0e33
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#define mmLB4_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
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#define mmLB4_LB_BUFFER_STATUS 0x0e34
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#define mmLB4_LB_BUFFER_STATUS_BASE_IDX 2
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#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x0e35
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#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
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#define mmLB4_MVP_AFR_FLIP_MODE 0x0e36
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#define mmLB4_MVP_AFR_FLIP_MODE_BASE_IDX 2
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#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x0e37
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#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
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#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x0e38
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#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
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#define mmLB4_DC_MVP_LB_CONTROL 0x0e39
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#define mmLB4_DC_MVP_LB_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dcfe4_dispdec
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// base address: 0x2000
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#define mmDCFE4_DCFE_CLOCK_CONTROL 0x0e5a
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#define mmDCFE4_DCFE_CLOCK_CONTROL_BASE_IDX 2
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#define mmDCFE4_DCFE_SOFT_RESET 0x0e5b
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#define mmDCFE4_DCFE_SOFT_RESET_BASE_IDX 2
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#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x0e5d
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#define mmDCFE4_DCFE_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x0e5e
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#define mmDCFE4_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x0e5f
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#define mmDCFE4_DCFE_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFE4_DCFE_MISC 0x0e60
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#define mmDCFE4_DCFE_MISC_BASE_IDX 2
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#define mmDCFE4_DCFE_FLUSH 0x0e61
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#define mmDCFE4_DCFE_FLUSH_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon7_dispdec
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// base address: 0x3938
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#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0e6e
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#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x0e6f
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#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x0e70
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#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_CNTL 0x0e71
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#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_CNTL2 0x0e72
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#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0e73
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#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0e74
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#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_HI 0x0e75
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#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_LOW 0x0e76
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#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dmif_pg4_dispdec
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// base address: 0x2000
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#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x0e7a
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#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
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#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x0e7b
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#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x0e7c
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#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
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#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x0e7d
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#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
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#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL 0x0e7e
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#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
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#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x0e7f
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#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
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#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2 0x0e80
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#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL 0x0e81
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#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
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#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x0e82
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#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_BASE_IDX 2
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#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x0e86
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#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
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#define mmDMIF_PG4_DPG_DVMM_STATUS 0x0e87
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#define mmDMIF_PG4_DPG_DVMM_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_scl4_dispdec
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// base address: 0x2000
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#define mmSCL4_SCL_COEF_RAM_SELECT 0x0e9a
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#define mmSCL4_SCL_COEF_RAM_SELECT_BASE_IDX 2
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#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x0e9b
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#define mmSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmSCL4_SCL_MODE 0x0e9c
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#define mmSCL4_SCL_MODE_BASE_IDX 2
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#define mmSCL4_SCL_TAP_CONTROL 0x0e9d
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#define mmSCL4_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_CONTROL 0x0e9e
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#define mmSCL4_SCL_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_BYPASS_CONTROL 0x0e9f
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#define mmSCL4_SCL_BYPASS_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x0ea0
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#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x0ea1
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#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x0ea2
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#define mmSCL4_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x0ea3
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#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL4_SCL_HORZ_FILTER_INIT 0x0ea4
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#define mmSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x0ea5
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#define mmSCL4_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x0ea6
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#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL4_SCL_VERT_FILTER_INIT 0x0ea7
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#define mmSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x0ea8
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#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCL4_SCL_ROUND_OFFSET 0x0ea9
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#define mmSCL4_SCL_ROUND_OFFSET_BASE_IDX 2
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#define mmSCL4_SCL_UPDATE 0x0eaa
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#define mmSCL4_SCL_UPDATE_BASE_IDX 2
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#define mmSCL4_SCL_F_SHARP_CONTROL 0x0eab
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#define mmSCL4_SCL_F_SHARP_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_ALU_CONTROL 0x0eac
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#define mmSCL4_SCL_ALU_CONTROL_BASE_IDX 2
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#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x0ead
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#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
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#define mmSCL4_VIEWPORT_START_SECONDARY 0x0eae
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#define mmSCL4_VIEWPORT_START_SECONDARY_BASE_IDX 2
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#define mmSCL4_VIEWPORT_START 0x0eaf
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#define mmSCL4_VIEWPORT_START_BASE_IDX 2
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#define mmSCL4_VIEWPORT_SIZE 0x0eb0
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#define mmSCL4_VIEWPORT_SIZE_BASE_IDX 2
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#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x0eb1
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#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x0eb2
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#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmSCL4_SCL_MODE_CHANGE_DET1 0x0eb3
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#define mmSCL4_SCL_MODE_CHANGE_DET1_BASE_IDX 2
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#define mmSCL4_SCL_MODE_CHANGE_DET2 0x0eb4
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#define mmSCL4_SCL_MODE_CHANGE_DET2_BASE_IDX 2
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#define mmSCL4_SCL_MODE_CHANGE_DET3 0x0eb5
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#define mmSCL4_SCL_MODE_CHANGE_DET3_BASE_IDX 2
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#define mmSCL4_SCL_MODE_CHANGE_MASK 0x0eb6
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#define mmSCL4_SCL_MODE_CHANGE_MASK_BASE_IDX 2
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// addressBlock: dce_dc_blnd4_dispdec
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// base address: 0x2000
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#define mmBLND4_BLND_CONTROL 0x0ec7
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#define mmBLND4_BLND_CONTROL_BASE_IDX 2
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#define mmBLND4_BLND_SM_CONTROL2 0x0ec8
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#define mmBLND4_BLND_SM_CONTROL2_BASE_IDX 2
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#define mmBLND4_BLND_CONTROL2 0x0ec9
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#define mmBLND4_BLND_CONTROL2_BASE_IDX 2
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#define mmBLND4_BLND_UPDATE 0x0eca
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#define mmBLND4_BLND_UPDATE_BASE_IDX 2
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#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x0ecb
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#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
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#define mmBLND4_BLND_V_UPDATE_LOCK 0x0ecc
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#define mmBLND4_BLND_V_UPDATE_LOCK_BASE_IDX 2
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#define mmBLND4_BLND_REG_UPDATE_STATUS 0x0ecd
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#define mmBLND4_BLND_REG_UPDATE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_crtc4_dispdec
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// base address: 0x2000
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#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x0ed2
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#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
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#define mmCRTC4_CRTC_H_TOTAL 0x0ed3
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#define mmCRTC4_CRTC_H_TOTAL_BASE_IDX 2
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#define mmCRTC4_CRTC_H_BLANK_START_END 0x0ed4
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#define mmCRTC4_CRTC_H_BLANK_START_END_BASE_IDX 2
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#define mmCRTC4_CRTC_H_SYNC_A 0x0ed5
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#define mmCRTC4_CRTC_H_SYNC_A_BASE_IDX 2
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#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x0ed6
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#define mmCRTC4_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_H_SYNC_B 0x0ed7
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#define mmCRTC4_CRTC_H_SYNC_B_BASE_IDX 2
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#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x0ed8
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#define mmCRTC4_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_VBI_END 0x0ed9
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#define mmCRTC4_CRTC_VBI_END_BASE_IDX 2
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#define mmCRTC4_CRTC_V_TOTAL 0x0eda
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#define mmCRTC4_CRTC_V_TOTAL_BASE_IDX 2
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#define mmCRTC4_CRTC_V_TOTAL_MIN 0x0edb
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#define mmCRTC4_CRTC_V_TOTAL_MIN_BASE_IDX 2
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#define mmCRTC4_CRTC_V_TOTAL_MAX 0x0edc
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#define mmCRTC4_CRTC_V_TOTAL_MAX_BASE_IDX 2
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#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x0edd
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#define mmCRTC4_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x0ede
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#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x0edf
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#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_V_BLANK_START_END 0x0ee0
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#define mmCRTC4_CRTC_V_BLANK_START_END_BASE_IDX 2
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#define mmCRTC4_CRTC_V_SYNC_A 0x0ee1
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#define mmCRTC4_CRTC_V_SYNC_A_BASE_IDX 2
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#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x0ee2
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#define mmCRTC4_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_V_SYNC_B 0x0ee3
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#define mmCRTC4_CRTC_V_SYNC_B_BASE_IDX 2
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#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x0ee4
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#define mmCRTC4_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_DTMTEST_CNTL 0x0ee5
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#define mmCRTC4_CRTC_DTMTEST_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x0ee6
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#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC4_CRTC_TRIGA_CNTL 0x0ee7
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#define mmCRTC4_CRTC_TRIGA_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x0ee8
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#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC4_CRTC_TRIGB_CNTL 0x0ee9
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#define mmCRTC4_CRTC_TRIGB_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x0eea
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#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x0eeb
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#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_FLOW_CONTROL 0x0eec
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#define mmCRTC4_CRTC_FLOW_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x0eed
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#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x0eee
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#define mmCRTC4_CRTC_AVSYNC_COUNTER_BASE_IDX 2
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#define mmCRTC4_CRTC_CONTROL 0x0eef
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#define mmCRTC4_CRTC_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_BLANK_CONTROL 0x0ef0
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#define mmCRTC4_CRTC_BLANK_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x0ef1
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#define mmCRTC4_CRTC_INTERLACE_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_INTERLACE_STATUS 0x0ef2
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#define mmCRTC4_CRTC_INTERLACE_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x0ef3
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#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x0ef4
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#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x0ef5
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#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmCRTC4_CRTC_STATUS 0x0ef6
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#define mmCRTC4_CRTC_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_STATUS_POSITION 0x0ef7
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#define mmCRTC4_CRTC_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x0ef8
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#define mmCRTC4_CRTC_NOM_VERT_POSITION_BASE_IDX 2
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#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x0ef9
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#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x0efa
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#define mmCRTC4_CRTC_STATUS_VF_COUNT_BASE_IDX 2
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#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x0efb
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#define mmCRTC4_CRTC_STATUS_HV_COUNT_BASE_IDX 2
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#define mmCRTC4_CRTC_COUNT_CONTROL 0x0efc
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#define mmCRTC4_CRTC_COUNT_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_COUNT_RESET 0x0efd
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#define mmCRTC4_CRTC_COUNT_RESET_BASE_IDX 2
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#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x0efe
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#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x0eff
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#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_STEREO_STATUS 0x0f00
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#define mmCRTC4_CRTC_STEREO_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_STEREO_CONTROL 0x0f01
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#define mmCRTC4_CRTC_STEREO_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x0f02
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#define mmCRTC4_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x0f03
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#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x0f04
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#define mmCRTC4_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x0f05
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#define mmCRTC4_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmCRTC4_CRTC_START_LINE_CONTROL 0x0f06
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#define mmCRTC4_CRTC_START_LINE_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x0f07
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#define mmCRTC4_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_UPDATE_LOCK 0x0f08
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#define mmCRTC4_CRTC_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x0f09
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#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x0f0a
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#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
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#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x0f0b
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#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x0f0c
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#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x0f0d
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#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x0f0e
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#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x0f0f
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#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x0f10
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#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
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#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x0f11
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#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
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#define mmCRTC4_CRTC_MVP_STATUS 0x0f12
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#define mmCRTC4_CRTC_MVP_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_MASTER_EN 0x0f13
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#define mmCRTC4_CRTC_MASTER_EN_BASE_IDX 2
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#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x0f14
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#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
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#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x0f15
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#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x0f17
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#define mmCRTC4_CRTC_OVERSCAN_COLOR_BASE_IDX 2
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#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x0f18
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#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
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#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x0f19
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#define mmCRTC4_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x0f1a
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#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmCRTC4_CRTC_BLACK_COLOR 0x0f1b
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#define mmCRTC4_CRTC_BLACK_COLOR_BASE_IDX 2
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#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x0f1c
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#define mmCRTC4_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x0f1d
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x0f1e
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x0f1f
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x0f20
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x0f21
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x0f22
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#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC_CNTL 0x0f23
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#define mmCRTC4_CRTC_CRC_CNTL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x0f24
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#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x0f25
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#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x0f26
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#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x0f27
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#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC0_DATA_RG 0x0f28
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#define mmCRTC4_CRTC_CRC0_DATA_RG_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC0_DATA_B 0x0f29
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#define mmCRTC4_CRTC_CRC0_DATA_B_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x0f2a
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#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x0f2b
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#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x0f2c
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#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x0f2d
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#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC1_DATA_RG 0x0f2e
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#define mmCRTC4_CRTC_CRC1_DATA_RG_BASE_IDX 2
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#define mmCRTC4_CRTC_CRC1_DATA_B 0x0f2f
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#define mmCRTC4_CRTC_CRC1_DATA_B_BASE_IDX 2
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x0f30
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x0f31
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x0f32
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x0f33
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x0f34
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x0f35
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#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x0f36
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#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x0f37
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#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x0f38
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#define mmCRTC4_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmCRTC4_CRTC_GSL_WINDOW 0x0f39
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#define mmCRTC4_CRTC_GSL_WINDOW_BASE_IDX 2
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#define mmCRTC4_CRTC_GSL_CONTROL 0x0f3a
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#define mmCRTC4_CRTC_GSL_CONTROL_BASE_IDX 2
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#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS 0x0f3d
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#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmCRTC4_CRTC_DRR_CONTROL 0x0f3e
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#define mmCRTC4_CRTC_DRR_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_fmt4_dispdec
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// base address: 0x2000
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#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x0f42
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#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
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#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x0f43
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#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x0f44
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#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x0f45
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#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
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#define mmFMT4_FMT_CONTROL 0x0f46
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#define mmFMT4_FMT_CONTROL_BASE_IDX 2
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#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x0f47
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#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x0f48
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#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x0f49
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#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x0f4a
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#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
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#define mmFMT4_FMT_CLAMP_CNTL 0x0f4e
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#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT4_FMT_CRC_CNTL 0x0f4f
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#define mmFMT4_FMT_CRC_CNTL_BASE_IDX 2
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#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x0f50
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#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x0f51
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#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x0f52
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#define mmFMT4_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
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#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x0f53
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#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
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#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x0f54
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#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
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#define mmFMT4_FMT_420_HBLANK_EARLY_START 0x0f55
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#define mmFMT4_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
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// addressBlock: dce_dc_dcp5_dispdec
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// base address: 0x2800
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#define mmDCP5_GRPH_ENABLE 0x0f5a
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#define mmDCP5_GRPH_ENABLE_BASE_IDX 2
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#define mmDCP5_GRPH_CONTROL 0x0f5b
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#define mmDCP5_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x0f5c
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#define mmDCP5_GRPH_LUT_10BIT_BYPASS_BASE_IDX 2
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#define mmDCP5_GRPH_SWAP_CNTL 0x0f5d
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#define mmDCP5_GRPH_SWAP_CNTL_BASE_IDX 2
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#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x0f5e
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#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x0f5f
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#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP5_GRPH_PITCH 0x0f60
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#define mmDCP5_GRPH_PITCH_BASE_IDX 2
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#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x0f61
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#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x0f62
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#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x0f63
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#define mmDCP5_GRPH_SURFACE_OFFSET_X_BASE_IDX 2
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#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x0f64
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#define mmDCP5_GRPH_SURFACE_OFFSET_Y_BASE_IDX 2
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#define mmDCP5_GRPH_X_START 0x0f65
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#define mmDCP5_GRPH_X_START_BASE_IDX 2
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#define mmDCP5_GRPH_Y_START 0x0f66
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#define mmDCP5_GRPH_Y_START_BASE_IDX 2
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#define mmDCP5_GRPH_X_END 0x0f67
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#define mmDCP5_GRPH_X_END_BASE_IDX 2
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#define mmDCP5_GRPH_Y_END 0x0f68
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#define mmDCP5_GRPH_Y_END_BASE_IDX 2
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#define mmDCP5_INPUT_GAMMA_CONTROL 0x0f69
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#define mmDCP5_INPUT_GAMMA_CONTROL_BASE_IDX 2
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#define mmDCP5_GRPH_UPDATE 0x0f6a
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#define mmDCP5_GRPH_UPDATE_BASE_IDX 2
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#define mmDCP5_GRPH_FLIP_CONTROL 0x0f6b
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#define mmDCP5_GRPH_FLIP_CONTROL_BASE_IDX 2
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#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x0f6c
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#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_BASE_IDX 2
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#define mmDCP5_GRPH_DFQ_CONTROL 0x0f6d
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#define mmDCP5_GRPH_DFQ_CONTROL_BASE_IDX 2
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#define mmDCP5_GRPH_DFQ_STATUS 0x0f6e
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#define mmDCP5_GRPH_DFQ_STATUS_BASE_IDX 2
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#define mmDCP5_GRPH_INTERRUPT_STATUS 0x0f6f
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#define mmDCP5_GRPH_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x0f70
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#define mmDCP5_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x0f71
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#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_BASE_IDX 2
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#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x0f72
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#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP5_GRPH_COMPRESS_PITCH 0x0f73
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#define mmDCP5_GRPH_COMPRESS_PITCH_BASE_IDX 2
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#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x0f74
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#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x0f75
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#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
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#define mmDCP5_PRESCALE_GRPH_CONTROL 0x0f76
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#define mmDCP5_PRESCALE_GRPH_CONTROL_BASE_IDX 2
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#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x0f77
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#define mmDCP5_PRESCALE_VALUES_GRPH_R_BASE_IDX 2
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#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x0f78
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#define mmDCP5_PRESCALE_VALUES_GRPH_G_BASE_IDX 2
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#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x0f79
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#define mmDCP5_PRESCALE_VALUES_GRPH_B_BASE_IDX 2
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#define mmDCP5_INPUT_CSC_CONTROL 0x0f7a
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#define mmDCP5_INPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP5_INPUT_CSC_C11_C12 0x0f7b
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#define mmDCP5_INPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP5_INPUT_CSC_C13_C14 0x0f7c
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#define mmDCP5_INPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP5_INPUT_CSC_C21_C22 0x0f7d
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#define mmDCP5_INPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP5_INPUT_CSC_C23_C24 0x0f7e
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#define mmDCP5_INPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP5_INPUT_CSC_C31_C32 0x0f7f
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#define mmDCP5_INPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP5_INPUT_CSC_C33_C34 0x0f80
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#define mmDCP5_INPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP5_OUTPUT_CSC_CONTROL 0x0f81
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#define mmDCP5_OUTPUT_CSC_CONTROL_BASE_IDX 2
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#define mmDCP5_OUTPUT_CSC_C11_C12 0x0f82
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#define mmDCP5_OUTPUT_CSC_C11_C12_BASE_IDX 2
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#define mmDCP5_OUTPUT_CSC_C13_C14 0x0f83
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#define mmDCP5_OUTPUT_CSC_C13_C14_BASE_IDX 2
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#define mmDCP5_OUTPUT_CSC_C21_C22 0x0f84
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#define mmDCP5_OUTPUT_CSC_C21_C22_BASE_IDX 2
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#define mmDCP5_OUTPUT_CSC_C23_C24 0x0f85
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#define mmDCP5_OUTPUT_CSC_C23_C24_BASE_IDX 2
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#define mmDCP5_OUTPUT_CSC_C31_C32 0x0f86
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#define mmDCP5_OUTPUT_CSC_C31_C32_BASE_IDX 2
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#define mmDCP5_OUTPUT_CSC_C33_C34 0x0f87
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#define mmDCP5_OUTPUT_CSC_C33_C34_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x0f88
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#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x0f89
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#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x0f8a
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#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x0f8b
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#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x0f8c
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#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x0f8d
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#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x0f8e
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#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x0f8f
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#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x0f90
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#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x0f91
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#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x0f92
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#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_BASE_IDX 2
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#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x0f93
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#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_BASE_IDX 2
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#define mmDCP5_DENORM_CONTROL 0x0f94
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#define mmDCP5_DENORM_CONTROL_BASE_IDX 2
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#define mmDCP5_OUT_ROUND_CONTROL 0x0f95
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#define mmDCP5_OUT_ROUND_CONTROL_BASE_IDX 2
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#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x0f96
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#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_BASE_IDX 2
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#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x0f97
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#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_BASE_IDX 2
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#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x0f98
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#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_BASE_IDX 2
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#define mmDCP5_KEY_CONTROL 0x0f99
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#define mmDCP5_KEY_CONTROL_BASE_IDX 2
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#define mmDCP5_KEY_RANGE_ALPHA 0x0f9a
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#define mmDCP5_KEY_RANGE_ALPHA_BASE_IDX 2
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#define mmDCP5_KEY_RANGE_RED 0x0f9b
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#define mmDCP5_KEY_RANGE_RED_BASE_IDX 2
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#define mmDCP5_KEY_RANGE_GREEN 0x0f9c
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#define mmDCP5_KEY_RANGE_GREEN_BASE_IDX 2
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#define mmDCP5_KEY_RANGE_BLUE 0x0f9d
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#define mmDCP5_KEY_RANGE_BLUE_BASE_IDX 2
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#define mmDCP5_DEGAMMA_CONTROL 0x0f9e
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#define mmDCP5_DEGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP5_GAMUT_REMAP_CONTROL 0x0f9f
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#define mmDCP5_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmDCP5_GAMUT_REMAP_C11_C12 0x0fa0
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#define mmDCP5_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmDCP5_GAMUT_REMAP_C13_C14 0x0fa1
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#define mmDCP5_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmDCP5_GAMUT_REMAP_C21_C22 0x0fa2
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#define mmDCP5_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmDCP5_GAMUT_REMAP_C23_C24 0x0fa3
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#define mmDCP5_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmDCP5_GAMUT_REMAP_C31_C32 0x0fa4
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#define mmDCP5_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmDCP5_GAMUT_REMAP_C33_C34 0x0fa5
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#define mmDCP5_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x0fa6
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#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_BASE_IDX 2
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#define mmDCP5_DCP_RANDOM_SEEDS 0x0fa7
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#define mmDCP5_DCP_RANDOM_SEEDS_BASE_IDX 2
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#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x0fa8
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#define mmDCP5_DCP_FP_CONVERTED_FIELD_BASE_IDX 2
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#define mmDCP5_CUR_CONTROL 0x0fa9
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#define mmDCP5_CUR_CONTROL_BASE_IDX 2
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#define mmDCP5_CUR_SURFACE_ADDRESS 0x0faa
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#define mmDCP5_CUR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP5_CUR_SIZE 0x0fab
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#define mmDCP5_CUR_SIZE_BASE_IDX 2
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#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x0fac
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#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP5_CUR_POSITION 0x0fad
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#define mmDCP5_CUR_POSITION_BASE_IDX 2
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#define mmDCP5_CUR_HOT_SPOT 0x0fae
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#define mmDCP5_CUR_HOT_SPOT_BASE_IDX 2
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#define mmDCP5_CUR_COLOR1 0x0faf
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#define mmDCP5_CUR_COLOR1_BASE_IDX 2
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#define mmDCP5_CUR_COLOR2 0x0fb0
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#define mmDCP5_CUR_COLOR2_BASE_IDX 2
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#define mmDCP5_CUR_UPDATE 0x0fb1
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#define mmDCP5_CUR_UPDATE_BASE_IDX 2
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#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x0fbb
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#define mmDCP5_CUR_REQUEST_FILTER_CNTL_BASE_IDX 2
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#define mmDCP5_CUR_STEREO_CONTROL 0x0fbc
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#define mmDCP5_CUR_STEREO_CONTROL_BASE_IDX 2
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#define mmDCP5_DC_LUT_RW_MODE 0x0fbe
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#define mmDCP5_DC_LUT_RW_MODE_BASE_IDX 2
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#define mmDCP5_DC_LUT_RW_INDEX 0x0fbf
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#define mmDCP5_DC_LUT_RW_INDEX_BASE_IDX 2
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#define mmDCP5_DC_LUT_SEQ_COLOR 0x0fc0
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#define mmDCP5_DC_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmDCP5_DC_LUT_PWL_DATA 0x0fc1
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#define mmDCP5_DC_LUT_PWL_DATA_BASE_IDX 2
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#define mmDCP5_DC_LUT_30_COLOR 0x0fc2
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#define mmDCP5_DC_LUT_30_COLOR_BASE_IDX 2
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#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x0fc3
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#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_BASE_IDX 2
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#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x0fc4
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#define mmDCP5_DC_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP5_DC_LUT_AUTOFILL 0x0fc5
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#define mmDCP5_DC_LUT_AUTOFILL_BASE_IDX 2
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#define mmDCP5_DC_LUT_CONTROL 0x0fc6
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#define mmDCP5_DC_LUT_CONTROL_BASE_IDX 2
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#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x0fc7
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#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x0fc8
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#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x0fc9
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#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_BASE_IDX 2
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#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x0fca
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#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_BASE_IDX 2
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#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x0fcb
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#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_BASE_IDX 2
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#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x0fcc
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#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_BASE_IDX 2
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#define mmDCP5_DCP_CRC_CONTROL 0x0fcd
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#define mmDCP5_DCP_CRC_CONTROL_BASE_IDX 2
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#define mmDCP5_DCP_CRC_MASK 0x0fce
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#define mmDCP5_DCP_CRC_MASK_BASE_IDX 2
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#define mmDCP5_DCP_CRC_CURRENT 0x0fcf
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#define mmDCP5_DCP_CRC_CURRENT_BASE_IDX 2
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#define mmDCP5_DVMM_PTE_CONTROL 0x0fd0
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#define mmDCP5_DVMM_PTE_CONTROL_BASE_IDX 2
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#define mmDCP5_DCP_CRC_LAST 0x0fd1
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#define mmDCP5_DCP_CRC_LAST_BASE_IDX 2
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#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x0fd2
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#define mmDCP5_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
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#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x0fd4
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#define mmDCP5_GRPH_FLIP_RATE_CNTL_BASE_IDX 2
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#define mmDCP5_DCP_GSL_CONTROL 0x0fd5
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#define mmDCP5_DCP_GSL_CONTROL_BASE_IDX 2
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#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x0fd6
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#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
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#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x0fdc
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#define mmDCP5_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
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#define mmDCP5_HW_ROTATION 0x0fde
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#define mmDCP5_HW_ROTATION_BASE_IDX 2
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#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x0fdf
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#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_BASE_IDX 2
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#define mmDCP5_REGAMMA_CONTROL 0x0fe0
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#define mmDCP5_REGAMMA_CONTROL_BASE_IDX 2
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#define mmDCP5_REGAMMA_LUT_INDEX 0x0fe1
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#define mmDCP5_REGAMMA_LUT_INDEX_BASE_IDX 2
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#define mmDCP5_REGAMMA_LUT_DATA 0x0fe2
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#define mmDCP5_REGAMMA_LUT_DATA_BASE_IDX 2
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#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x0fe3
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#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x0fe4
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#define mmDCP5_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x0fe5
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#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x0fe6
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#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x0fe7
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#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x0fe8
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#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x0fe9
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#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x0fea
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#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x0feb
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#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x0fec
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#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x0fed
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#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x0fee
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#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x0fef
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#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x0ff0
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#define mmDCP5_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x0ff1
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#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x0ff2
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#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x0ff3
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#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x0ff4
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#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x0ff5
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#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x0ff6
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#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x0ff7
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#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x0ff8
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#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x0ff9
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#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x0ffa
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#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
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#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x0ffb
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#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
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#define mmDCP5_ALPHA_CONTROL 0x0ffc
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#define mmDCP5_ALPHA_CONTROL_BASE_IDX 2
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#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x0ffd
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#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x0ffe
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#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x0fff
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#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_BASE_IDX 2
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#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT 0x1000
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#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_BASE_IDX 2
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#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY 0x1001
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#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_BASE_IDX 2
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#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x1002
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#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_BASE_IDX 2
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#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x1003
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#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_BASE_IDX 2
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// addressBlock: dce_dc_lb5_dispdec
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// base address: 0x2800
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#define mmLB5_LB_DATA_FORMAT 0x101a
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#define mmLB5_LB_DATA_FORMAT_BASE_IDX 2
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#define mmLB5_LB_MEMORY_CTRL 0x101b
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#define mmLB5_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmLB5_LB_MEMORY_SIZE_STATUS 0x101c
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#define mmLB5_LB_MEMORY_SIZE_STATUS_BASE_IDX 2
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#define mmLB5_LB_DESKTOP_HEIGHT 0x101d
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#define mmLB5_LB_DESKTOP_HEIGHT_BASE_IDX 2
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#define mmLB5_LB_VLINE_START_END 0x101e
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#define mmLB5_LB_VLINE_START_END_BASE_IDX 2
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#define mmLB5_LB_VLINE2_START_END 0x101f
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#define mmLB5_LB_VLINE2_START_END_BASE_IDX 2
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#define mmLB5_LB_V_COUNTER 0x1020
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#define mmLB5_LB_V_COUNTER_BASE_IDX 2
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#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x1021
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#define mmLB5_LB_SNAPSHOT_V_COUNTER_BASE_IDX 2
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#define mmLB5_LB_INTERRUPT_MASK 0x1022
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#define mmLB5_LB_INTERRUPT_MASK_BASE_IDX 2
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#define mmLB5_LB_VLINE_STATUS 0x1023
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#define mmLB5_LB_VLINE_STATUS_BASE_IDX 2
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#define mmLB5_LB_VLINE2_STATUS 0x1024
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#define mmLB5_LB_VLINE2_STATUS_BASE_IDX 2
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#define mmLB5_LB_VBLANK_STATUS 0x1025
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#define mmLB5_LB_VBLANK_STATUS_BASE_IDX 2
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#define mmLB5_LB_SYNC_RESET_SEL 0x1026
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#define mmLB5_LB_SYNC_RESET_SEL_BASE_IDX 2
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#define mmLB5_LB_BLACK_KEYER_R_CR 0x1027
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#define mmLB5_LB_BLACK_KEYER_R_CR_BASE_IDX 2
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#define mmLB5_LB_BLACK_KEYER_G_Y 0x1028
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#define mmLB5_LB_BLACK_KEYER_G_Y_BASE_IDX 2
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#define mmLB5_LB_BLACK_KEYER_B_CB 0x1029
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#define mmLB5_LB_BLACK_KEYER_B_CB_BASE_IDX 2
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#define mmLB5_LB_KEYER_COLOR_CTRL 0x102a
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#define mmLB5_LB_KEYER_COLOR_CTRL_BASE_IDX 2
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#define mmLB5_LB_KEYER_COLOR_R_CR 0x102b
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#define mmLB5_LB_KEYER_COLOR_R_CR_BASE_IDX 2
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#define mmLB5_LB_KEYER_COLOR_G_Y 0x102c
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#define mmLB5_LB_KEYER_COLOR_G_Y_BASE_IDX 2
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#define mmLB5_LB_KEYER_COLOR_B_CB 0x102d
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#define mmLB5_LB_KEYER_COLOR_B_CB_BASE_IDX 2
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#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x102e
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#define mmLB5_LB_KEYER_COLOR_REP_R_CR_BASE_IDX 2
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#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x102f
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#define mmLB5_LB_KEYER_COLOR_REP_G_Y_BASE_IDX 2
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#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x1030
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#define mmLB5_LB_KEYER_COLOR_REP_B_CB_BASE_IDX 2
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#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x1031
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#define mmLB5_LB_BUFFER_LEVEL_STATUS_BASE_IDX 2
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#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x1032
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#define mmLB5_LB_BUFFER_URGENCY_CTRL_BASE_IDX 2
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#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x1033
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#define mmLB5_LB_BUFFER_URGENCY_STATUS_BASE_IDX 2
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#define mmLB5_LB_BUFFER_STATUS 0x1034
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#define mmLB5_LB_BUFFER_STATUS_BASE_IDX 2
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#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x1035
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#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
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#define mmLB5_MVP_AFR_FLIP_MODE 0x1036
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#define mmLB5_MVP_AFR_FLIP_MODE_BASE_IDX 2
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#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x1037
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#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_BASE_IDX 2
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#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x1038
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#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_BASE_IDX 2
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#define mmLB5_DC_MVP_LB_CONTROL 0x1039
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#define mmLB5_DC_MVP_LB_CONTROL_BASE_IDX 2
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|
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// addressBlock: dce_dc_dcfe5_dispdec
|
// base address: 0x2800
|
#define mmDCFE5_DCFE_CLOCK_CONTROL 0x105a
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#define mmDCFE5_DCFE_CLOCK_CONTROL_BASE_IDX 2
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#define mmDCFE5_DCFE_SOFT_RESET 0x105b
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#define mmDCFE5_DCFE_SOFT_RESET_BASE_IDX 2
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#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x105d
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#define mmDCFE5_DCFE_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x105e
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#define mmDCFE5_DCFE_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x105f
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#define mmDCFE5_DCFE_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFE5_DCFE_MISC 0x1060
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#define mmDCFE5_DCFE_MISC_BASE_IDX 2
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#define mmDCFE5_DCFE_FLUSH 0x1061
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#define mmDCFE5_DCFE_FLUSH_BASE_IDX 2
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|
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// addressBlock: dce_dc_dc_perfmon8_dispdec
|
// base address: 0x4138
|
#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x106e
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x106f
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x1070
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#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CNTL 0x1071
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#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CNTL2 0x1072
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#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x1073
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#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x1074
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#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_HI 0x1075
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#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_LOW 0x1076
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#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
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|
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// addressBlock: dce_dc_dmif_pg5_dispdec
|
// base address: 0x2800
|
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x107a
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#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
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#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x107b
|
#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
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#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x107c
|
#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_BASE_IDX 2
|
#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x107d
|
#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_BASE_IDX 2
|
#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL 0x107e
|
#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_BASE_IDX 2
|
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x107f
|
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_BASE_IDX 2
|
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2 0x1080
|
#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_BASE_IDX 2
|
#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL 0x1081
|
#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_BASE_IDX 2
|
#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x1082
|
#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_BASE_IDX 2
|
#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x1086
|
#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_BASE_IDX 2
|
#define mmDMIF_PG5_DPG_DVMM_STATUS 0x1087
|
#define mmDMIF_PG5_DPG_DVMM_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_scl5_dispdec
|
// base address: 0x2800
|
#define mmSCL5_SCL_COEF_RAM_SELECT 0x109a
|
#define mmSCL5_SCL_COEF_RAM_SELECT_BASE_IDX 2
|
#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x109b
|
#define mmSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmSCL5_SCL_MODE 0x109c
|
#define mmSCL5_SCL_MODE_BASE_IDX 2
|
#define mmSCL5_SCL_TAP_CONTROL 0x109d
|
#define mmSCL5_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmSCL5_SCL_CONTROL 0x109e
|
#define mmSCL5_SCL_CONTROL_BASE_IDX 2
|
#define mmSCL5_SCL_BYPASS_CONTROL 0x109f
|
#define mmSCL5_SCL_BYPASS_CONTROL_BASE_IDX 2
|
#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x10a0
|
#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x10a1
|
#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
|
#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x10a2
|
#define mmSCL5_SCL_HORZ_FILTER_CONTROL_BASE_IDX 2
|
#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x10a3
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#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL5_SCL_HORZ_FILTER_INIT 0x10a4
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#define mmSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x10a5
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#define mmSCL5_SCL_VERT_FILTER_CONTROL_BASE_IDX 2
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#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x10a6
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#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCL5_SCL_VERT_FILTER_INIT 0x10a7
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#define mmSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x10a8
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#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCL5_SCL_ROUND_OFFSET 0x10a9
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#define mmSCL5_SCL_ROUND_OFFSET_BASE_IDX 2
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#define mmSCL5_SCL_UPDATE 0x10aa
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#define mmSCL5_SCL_UPDATE_BASE_IDX 2
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#define mmSCL5_SCL_F_SHARP_CONTROL 0x10ab
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#define mmSCL5_SCL_F_SHARP_CONTROL_BASE_IDX 2
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#define mmSCL5_SCL_ALU_CONTROL 0x10ac
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#define mmSCL5_SCL_ALU_CONTROL_BASE_IDX 2
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#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x10ad
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#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
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#define mmSCL5_VIEWPORT_START_SECONDARY 0x10ae
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#define mmSCL5_VIEWPORT_START_SECONDARY_BASE_IDX 2
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#define mmSCL5_VIEWPORT_START 0x10af
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#define mmSCL5_VIEWPORT_START_BASE_IDX 2
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#define mmSCL5_VIEWPORT_SIZE 0x10b0
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#define mmSCL5_VIEWPORT_SIZE_BASE_IDX 2
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#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x10b1
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#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x10b2
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#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmSCL5_SCL_MODE_CHANGE_DET1 0x10b3
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#define mmSCL5_SCL_MODE_CHANGE_DET1_BASE_IDX 2
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#define mmSCL5_SCL_MODE_CHANGE_DET2 0x10b4
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#define mmSCL5_SCL_MODE_CHANGE_DET2_BASE_IDX 2
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#define mmSCL5_SCL_MODE_CHANGE_DET3 0x10b5
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#define mmSCL5_SCL_MODE_CHANGE_DET3_BASE_IDX 2
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#define mmSCL5_SCL_MODE_CHANGE_MASK 0x10b6
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#define mmSCL5_SCL_MODE_CHANGE_MASK_BASE_IDX 2
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// addressBlock: dce_dc_blnd5_dispdec
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// base address: 0x2800
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#define mmBLND5_BLND_CONTROL 0x10c7
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#define mmBLND5_BLND_CONTROL_BASE_IDX 2
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#define mmBLND5_BLND_SM_CONTROL2 0x10c8
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#define mmBLND5_BLND_SM_CONTROL2_BASE_IDX 2
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#define mmBLND5_BLND_CONTROL2 0x10c9
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#define mmBLND5_BLND_CONTROL2_BASE_IDX 2
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#define mmBLND5_BLND_UPDATE 0x10ca
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#define mmBLND5_BLND_UPDATE_BASE_IDX 2
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#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x10cb
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#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_BASE_IDX 2
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#define mmBLND5_BLND_V_UPDATE_LOCK 0x10cc
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#define mmBLND5_BLND_V_UPDATE_LOCK_BASE_IDX 2
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#define mmBLND5_BLND_REG_UPDATE_STATUS 0x10cd
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#define mmBLND5_BLND_REG_UPDATE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_crtc5_dispdec
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// base address: 0x2800
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#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x10d2
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#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_BASE_IDX 2
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#define mmCRTC5_CRTC_H_TOTAL 0x10d3
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#define mmCRTC5_CRTC_H_TOTAL_BASE_IDX 2
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#define mmCRTC5_CRTC_H_BLANK_START_END 0x10d4
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#define mmCRTC5_CRTC_H_BLANK_START_END_BASE_IDX 2
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#define mmCRTC5_CRTC_H_SYNC_A 0x10d5
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#define mmCRTC5_CRTC_H_SYNC_A_BASE_IDX 2
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#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x10d6
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#define mmCRTC5_CRTC_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_H_SYNC_B 0x10d7
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#define mmCRTC5_CRTC_H_SYNC_B_BASE_IDX 2
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#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x10d8
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#define mmCRTC5_CRTC_H_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_VBI_END 0x10d9
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#define mmCRTC5_CRTC_VBI_END_BASE_IDX 2
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#define mmCRTC5_CRTC_V_TOTAL 0x10da
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#define mmCRTC5_CRTC_V_TOTAL_BASE_IDX 2
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#define mmCRTC5_CRTC_V_TOTAL_MIN 0x10db
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#define mmCRTC5_CRTC_V_TOTAL_MIN_BASE_IDX 2
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#define mmCRTC5_CRTC_V_TOTAL_MAX 0x10dc
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#define mmCRTC5_CRTC_V_TOTAL_MAX_BASE_IDX 2
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#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x10dd
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#define mmCRTC5_CRTC_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x10de
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#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x10df
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#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_V_BLANK_START_END 0x10e0
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#define mmCRTC5_CRTC_V_BLANK_START_END_BASE_IDX 2
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#define mmCRTC5_CRTC_V_SYNC_A 0x10e1
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#define mmCRTC5_CRTC_V_SYNC_A_BASE_IDX 2
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#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x10e2
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#define mmCRTC5_CRTC_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_V_SYNC_B 0x10e3
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#define mmCRTC5_CRTC_V_SYNC_B_BASE_IDX 2
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#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x10e4
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#define mmCRTC5_CRTC_V_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_DTMTEST_CNTL 0x10e5
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#define mmCRTC5_CRTC_DTMTEST_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x10e6
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#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC5_CRTC_TRIGA_CNTL 0x10e7
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#define mmCRTC5_CRTC_TRIGA_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x10e8
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#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC5_CRTC_TRIGB_CNTL 0x10e9
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#define mmCRTC5_CRTC_TRIGB_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x10ea
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#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x10eb
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#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_FLOW_CONTROL 0x10ec
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#define mmCRTC5_CRTC_FLOW_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x10ed
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#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x10ee
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#define mmCRTC5_CRTC_AVSYNC_COUNTER_BASE_IDX 2
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#define mmCRTC5_CRTC_CONTROL 0x10ef
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#define mmCRTC5_CRTC_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_BLANK_CONTROL 0x10f0
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#define mmCRTC5_CRTC_BLANK_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x10f1
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#define mmCRTC5_CRTC_INTERLACE_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_INTERLACE_STATUS 0x10f2
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#define mmCRTC5_CRTC_INTERLACE_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x10f3
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#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x10f4
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#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x10f5
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#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmCRTC5_CRTC_STATUS 0x10f6
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#define mmCRTC5_CRTC_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_STATUS_POSITION 0x10f7
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#define mmCRTC5_CRTC_STATUS_POSITION_BASE_IDX 2
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#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x10f8
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#define mmCRTC5_CRTC_NOM_VERT_POSITION_BASE_IDX 2
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#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x10f9
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#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x10fa
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#define mmCRTC5_CRTC_STATUS_VF_COUNT_BASE_IDX 2
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#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x10fb
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#define mmCRTC5_CRTC_STATUS_HV_COUNT_BASE_IDX 2
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#define mmCRTC5_CRTC_COUNT_CONTROL 0x10fc
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#define mmCRTC5_CRTC_COUNT_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_COUNT_RESET 0x10fd
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#define mmCRTC5_CRTC_COUNT_RESET_BASE_IDX 2
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#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x10fe
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#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x10ff
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#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_STEREO_STATUS 0x1100
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#define mmCRTC5_CRTC_STEREO_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_STEREO_CONTROL 0x1101
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#define mmCRTC5_CRTC_STEREO_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x1102
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#define mmCRTC5_CRTC_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x1103
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#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x1104
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#define mmCRTC5_CRTC_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x1105
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#define mmCRTC5_CRTC_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmCRTC5_CRTC_START_LINE_CONTROL 0x1106
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#define mmCRTC5_CRTC_START_LINE_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x1107
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#define mmCRTC5_CRTC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_UPDATE_LOCK 0x1108
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#define mmCRTC5_CRTC_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x1109
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#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x110a
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#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
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#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x110b
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#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x110c
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#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x110d
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#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x110e
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#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x110f
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#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x1110
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#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
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#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1111
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#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
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#define mmCRTC5_CRTC_MVP_STATUS 0x1112
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#define mmCRTC5_CRTC_MVP_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_MASTER_EN 0x1113
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#define mmCRTC5_CRTC_MASTER_EN_BASE_IDX 2
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#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x1114
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#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
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#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x1115
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#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x1117
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#define mmCRTC5_CRTC_OVERSCAN_COLOR_BASE_IDX 2
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#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x1118
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#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_BASE_IDX 2
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#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x1119
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#define mmCRTC5_CRTC_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x111a
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#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmCRTC5_CRTC_BLACK_COLOR 0x111b
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#define mmCRTC5_CRTC_BLACK_COLOR_BASE_IDX 2
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#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x111c
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#define mmCRTC5_CRTC_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x111d
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x111e
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x111f
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1120
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1121
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1122
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#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC_CNTL 0x1123
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#define mmCRTC5_CRTC_CRC_CNTL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x1124
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#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1125
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#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x1126
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#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1127
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#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC0_DATA_RG 0x1128
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#define mmCRTC5_CRTC_CRC0_DATA_RG_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC0_DATA_B 0x1129
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#define mmCRTC5_CRTC_CRC0_DATA_B_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x112a
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#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x112b
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#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x112c
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#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x112d
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#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC1_DATA_RG 0x112e
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#define mmCRTC5_CRTC_CRC1_DATA_RG_BASE_IDX 2
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#define mmCRTC5_CRTC_CRC1_DATA_B 0x112f
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#define mmCRTC5_CRTC_CRC1_DATA_B_BASE_IDX 2
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x1130
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1131
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1132
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1133
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1134
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1135
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#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x1136
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#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x1137
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#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x1138
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#define mmCRTC5_CRTC_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmCRTC5_CRTC_GSL_WINDOW 0x1139
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#define mmCRTC5_CRTC_GSL_WINDOW_BASE_IDX 2
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#define mmCRTC5_CRTC_GSL_CONTROL 0x113a
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#define mmCRTC5_CRTC_GSL_CONTROL_BASE_IDX 2
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#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS 0x113d
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#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmCRTC5_CRTC_DRR_CONTROL 0x113e
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#define mmCRTC5_CRTC_DRR_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_fmt5_dispdec
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// base address: 0x2800
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#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x1142
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#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
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#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x1143
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#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1144
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#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1145
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#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
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#define mmFMT5_FMT_CONTROL 0x1146
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#define mmFMT5_FMT_CONTROL_BASE_IDX 2
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#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1147
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#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1148
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#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1149
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#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x114a
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#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
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#define mmFMT5_FMT_CLAMP_CNTL 0x114e
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#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT5_FMT_CRC_CNTL 0x114f
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#define mmFMT5_FMT_CRC_CNTL_BASE_IDX 2
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#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x1150
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#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1151
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#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x1152
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#define mmFMT5_FMT_CRC_SIG_RED_GREEN_BASE_IDX 2
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#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x1153
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#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_BASE_IDX 2
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#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1154
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#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
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#define mmFMT5_FMT_420_HBLANK_EARLY_START 0x1155
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#define mmFMT5_FMT_420_HBLANK_EARLY_START_BASE_IDX 2
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// addressBlock: dce_dc_unp0_dispdec
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// base address: 0x0
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#define mmUNP0_UNP_GRPH_ENABLE 0x115a
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#define mmUNP0_UNP_GRPH_ENABLE_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_CONTROL 0x115b
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#define mmUNP0_UNP_GRPH_CONTROL_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_CONTROL_C 0x115c
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#define mmUNP0_UNP_GRPH_CONTROL_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_CONTROL_EXP 0x115d
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#define mmUNP0_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SWAP_CNTL 0x115e
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#define mmUNP0_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x115f
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#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1160
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#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1161
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#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1162
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#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1163
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#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1164
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#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1165
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#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1166
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#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1167
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#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1168
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#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1169
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#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x116a
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#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x116b
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#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x116c
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#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x116d
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#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x116e
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#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PITCH_L 0x116f
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#define mmUNP0_UNP_GRPH_PITCH_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_PITCH_C 0x1170
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#define mmUNP0_UNP_GRPH_PITCH_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x1171
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#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x1172
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#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1173
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#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1174
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#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_X_START_L 0x1175
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#define mmUNP0_UNP_GRPH_X_START_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_X_START_C 0x1176
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#define mmUNP0_UNP_GRPH_X_START_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_Y_START_L 0x1177
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#define mmUNP0_UNP_GRPH_Y_START_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_Y_START_C 0x1178
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#define mmUNP0_UNP_GRPH_Y_START_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_X_END_L 0x1179
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#define mmUNP0_UNP_GRPH_X_END_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_X_END_C 0x117a
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#define mmUNP0_UNP_GRPH_X_END_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_Y_END_L 0x117b
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#define mmUNP0_UNP_GRPH_Y_END_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_Y_END_C 0x117c
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#define mmUNP0_UNP_GRPH_Y_END_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_UPDATE 0x117d
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#define mmUNP0_UNP_GRPH_UPDATE_BASE_IDX 2
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#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x117e
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#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x117f
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#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1180
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#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1181
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#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1182
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#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
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#define mmUNP0_UNP_DVMM_PTE_CONTROL 0x1183
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#define mmUNP0_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
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#define mmUNP0_UNP_DVMM_PTE_CONTROL_C 0x1184
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#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
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#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL 0x1185
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#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
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#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C 0x1186
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#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x1187
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#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x1188
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#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x1189
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#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
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#define mmUNP0_UNP_FLIP_CONTROL 0x118a
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#define mmUNP0_UNP_FLIP_CONTROL_BASE_IDX 2
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#define mmUNP0_UNP_CRC_CONTROL 0x118b
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#define mmUNP0_UNP_CRC_CONTROL_BASE_IDX 2
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#define mmUNP0_UNP_CRC_MASK 0x118c
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#define mmUNP0_UNP_CRC_MASK_BASE_IDX 2
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#define mmUNP0_UNP_CRC_CURRENT 0x118d
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#define mmUNP0_UNP_CRC_CURRENT_BASE_IDX 2
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#define mmUNP0_UNP_CRC_LAST 0x118e
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#define mmUNP0_UNP_CRC_LAST_BASE_IDX 2
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#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x118f
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#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
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#define mmUNP0_UNP_HW_ROTATION 0x1190
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#define mmUNP0_UNP_HW_ROTATION_BASE_IDX 2
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// addressBlock: dce_dc_lbv0_dispdec
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// base address: 0x0
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#define mmLBV0_LBV_DATA_FORMAT 0x1196
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#define mmLBV0_LBV_DATA_FORMAT_BASE_IDX 2
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#define mmLBV0_LBV_MEMORY_CTRL 0x1197
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#define mmLBV0_LBV_MEMORY_CTRL_BASE_IDX 2
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#define mmLBV0_LBV_MEMORY_SIZE_STATUS 0x1198
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#define mmLBV0_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
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#define mmLBV0_LBV_DESKTOP_HEIGHT 0x1199
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#define mmLBV0_LBV_DESKTOP_HEIGHT_BASE_IDX 2
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#define mmLBV0_LBV_VLINE_START_END 0x119a
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#define mmLBV0_LBV_VLINE_START_END_BASE_IDX 2
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#define mmLBV0_LBV_VLINE2_START_END 0x119b
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#define mmLBV0_LBV_VLINE2_START_END_BASE_IDX 2
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#define mmLBV0_LBV_V_COUNTER 0x119c
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#define mmLBV0_LBV_V_COUNTER_BASE_IDX 2
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#define mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x119d
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#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
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#define mmLBV0_LBV_V_COUNTER_CHROMA 0x119e
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#define mmLBV0_LBV_V_COUNTER_CHROMA_BASE_IDX 2
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#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x119f
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#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
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#define mmLBV0_LBV_INTERRUPT_MASK 0x11a0
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#define mmLBV0_LBV_INTERRUPT_MASK_BASE_IDX 2
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#define mmLBV0_LBV_VLINE_STATUS 0x11a1
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#define mmLBV0_LBV_VLINE_STATUS_BASE_IDX 2
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#define mmLBV0_LBV_VLINE2_STATUS 0x11a2
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#define mmLBV0_LBV_VLINE2_STATUS_BASE_IDX 2
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#define mmLBV0_LBV_VBLANK_STATUS 0x11a3
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#define mmLBV0_LBV_VBLANK_STATUS_BASE_IDX 2
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#define mmLBV0_LBV_SYNC_RESET_SEL 0x11a4
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#define mmLBV0_LBV_SYNC_RESET_SEL_BASE_IDX 2
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#define mmLBV0_LBV_BLACK_KEYER_R_CR 0x11a5
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#define mmLBV0_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
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#define mmLBV0_LBV_BLACK_KEYER_G_Y 0x11a6
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#define mmLBV0_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
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#define mmLBV0_LBV_BLACK_KEYER_B_CB 0x11a7
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#define mmLBV0_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
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#define mmLBV0_LBV_KEYER_COLOR_CTRL 0x11a8
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#define mmLBV0_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
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#define mmLBV0_LBV_KEYER_COLOR_R_CR 0x11a9
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#define mmLBV0_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
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#define mmLBV0_LBV_KEYER_COLOR_G_Y 0x11aa
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#define mmLBV0_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
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#define mmLBV0_LBV_KEYER_COLOR_B_CB 0x11ab
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#define mmLBV0_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
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#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x11ac
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#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
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#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x11ad
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#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
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#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x11ae
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#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
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#define mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x11af
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#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
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#define mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x11b0
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#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
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#define mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x11b1
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#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
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#define mmLBV0_LBV_BUFFER_STATUS 0x11b2
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#define mmLBV0_LBV_BUFFER_STATUS_BASE_IDX 2
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#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x11b3
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#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_sclv0_dispdec
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// base address: 0x0
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#define mmSCLV0_SCLV_COEF_RAM_SELECT 0x11ca
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#define mmSCLV0_SCLV_COEF_RAM_SELECT_BASE_IDX 2
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#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x11cb
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#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmSCLV0_SCLV_MODE 0x11cc
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#define mmSCLV0_SCLV_MODE_BASE_IDX 2
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#define mmSCLV0_SCLV_TAP_CONTROL 0x11cd
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#define mmSCLV0_SCLV_TAP_CONTROL_BASE_IDX 2
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#define mmSCLV0_SCLV_CONTROL 0x11ce
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#define mmSCLV0_SCLV_CONTROL_BASE_IDX 2
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#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x11cf
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#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x11d0
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#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
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#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x11d1
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#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
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#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x11d2
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#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCLV0_SCLV_HORZ_FILTER_INIT 0x11d3
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#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x11d4
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#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x11d5
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#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x11d6
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#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
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#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x11d7
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#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCLV0_SCLV_VERT_FILTER_INIT 0x11d8
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#define mmSCLV0_SCLV_VERT_FILTER_INIT_BASE_IDX 2
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#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x11d9
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#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x11da
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#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x11db
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#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x11dc
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#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmSCLV0_SCLV_ROUND_OFFSET 0x11dd
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#define mmSCLV0_SCLV_ROUND_OFFSET_BASE_IDX 2
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#define mmSCLV0_SCLV_UPDATE 0x11de
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#define mmSCLV0_SCLV_UPDATE_BASE_IDX 2
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#define mmSCLV0_SCLV_ALU_CONTROL 0x11df
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#define mmSCLV0_SCLV_ALU_CONTROL_BASE_IDX 2
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#define mmSCLV0_SCLV_VIEWPORT_START 0x11e0
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#define mmSCLV0_SCLV_VIEWPORT_START_BASE_IDX 2
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#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x11e1
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#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
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#define mmSCLV0_SCLV_VIEWPORT_SIZE 0x11e2
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#define mmSCLV0_SCLV_VIEWPORT_SIZE_BASE_IDX 2
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#define mmSCLV0_SCLV_VIEWPORT_START_C 0x11e3
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#define mmSCLV0_SCLV_VIEWPORT_START_C_BASE_IDX 2
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#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x11e4
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#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
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#define mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x11e5
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#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
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#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x11e6
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#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x11e7
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#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmSCLV0_SCLV_MODE_CHANGE_DET1 0x11e8
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#define mmSCLV0_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
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#define mmSCLV0_SCLV_MODE_CHANGE_DET2 0x11e9
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#define mmSCLV0_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
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#define mmSCLV0_SCLV_MODE_CHANGE_DET3 0x11ea
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#define mmSCLV0_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
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#define mmSCLV0_SCLV_MODE_CHANGE_MASK 0x11eb
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#define mmSCLV0_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
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#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x11ec
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#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x11ed
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#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
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// addressBlock: dce_dc_col_man0_dispdec
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// base address: 0x0
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#define mmCOL_MAN0_COL_MAN_UPDATE 0x11fe
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#define mmCOL_MAN0_COL_MAN_UPDATE_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x11ff
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#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x1200
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#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x1201
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#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x1202
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#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x1203
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#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x1204
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#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x1205
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#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x1206
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#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x1207
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#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x1208
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#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x1209
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#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x120a
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#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x120b
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#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_BASE_IDX 2
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#define mmCOL_MAN0_PRESCALE_CONTROL 0x120c
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#define mmCOL_MAN0_PRESCALE_CONTROL_BASE_IDX 2
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#define mmCOL_MAN0_PRESCALE_VALUES_R 0x120d
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#define mmCOL_MAN0_PRESCALE_VALUES_R_BASE_IDX 2
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#define mmCOL_MAN0_PRESCALE_VALUES_G 0x120e
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#define mmCOL_MAN0_PRESCALE_VALUES_G_BASE_IDX 2
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#define mmCOL_MAN0_PRESCALE_VALUES_B 0x120f
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#define mmCOL_MAN0_PRESCALE_VALUES_B_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x1210
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#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x1211
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#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x1212
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#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x1213
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#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x1214
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#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x1215
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#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x1216
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#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x1217
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#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x1218
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#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x1219
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#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x121a
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#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x121b
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#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x121c
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#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
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#define mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x121d
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#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_BASE_IDX 2
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#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x121e
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#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
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#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x121f
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#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
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#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x1220
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#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x1221
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#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL 0x1222
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX 0x1223
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#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA 0x1224
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#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1225
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#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1226
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1227
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1228
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1229
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x122a
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x122b
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x122c
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x122d
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x122e
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x122f
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1230
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1231
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1232
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1233
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1234
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1235
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1236
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1237
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1238
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1239
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x123a
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x123b
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x123c
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x123d
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#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
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#define mmCOL_MAN0_PACK_FIFO_ERROR 0x123e
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#define mmCOL_MAN0_PACK_FIFO_ERROR_BASE_IDX 2
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#define mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x123f
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#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x1240
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x1241
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x1242
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x1243
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x1244
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#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x1245
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#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x1246
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#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x1247
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#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x1248
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#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
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#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x1249
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#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL 0x124a
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#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL 0x124b
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12 0x124c
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14 0x124d
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22 0x124e
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24 0x124f
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32 0x1250
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34 0x1251
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#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
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// addressBlock: dce_dc_dcfev0_dispdec
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// base address: 0x0
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#define mmDCFEV0_DCFEV_CLOCK_CONTROL 0x127e
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#define mmDCFEV0_DCFEV_CLOCK_CONTROL_BASE_IDX 2
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#define mmDCFEV0_DCFEV_SOFT_RESET 0x127f
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#define mmDCFEV0_DCFEV_SOFT_RESET_BASE_IDX 2
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#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x1280
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#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
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#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x1282
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#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x1283
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#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x1284
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#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x1285
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#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x1286
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#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFEV0_DCFEV_L_FLUSH 0x1287
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#define mmDCFEV0_DCFEV_L_FLUSH_BASE_IDX 2
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#define mmDCFEV0_DCFEV_C_FLUSH 0x1288
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#define mmDCFEV0_DCFEV_C_FLUSH_BASE_IDX 2
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#define mmDCFEV0_DCFEV_MISC 0x128a
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#define mmDCFEV0_DCFEV_MISC_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon11_dispdec
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// base address: 0x49c8
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x1292
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x1293
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x1294
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#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CNTL 0x1295
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#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CNTL2 0x1296
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#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x1297
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#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x1298
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#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_HI 0x1299
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#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_LOW 0x129a
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#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dmifv_pg0_dispdec
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// base address: 0x0
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#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x129e
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#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x129f
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#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x12a0
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#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x12a1
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#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x12a2
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#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x12a3
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#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12a4
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#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x12a5
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#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x12a6
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#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x12aa
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#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x12ab
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#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x12ac
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#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x12ad
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#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x12ae
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#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x12af
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#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x12b0
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#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x12b1
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#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x12b2
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#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x12b3
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#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
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#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x12b7
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#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_blndv0_dispdec
|
// base address: 0x0
|
#define mmBLNDV0_BLNDV_CONTROL 0x12db
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#define mmBLNDV0_BLNDV_CONTROL_BASE_IDX 2
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#define mmBLNDV0_BLNDV_SM_CONTROL2 0x12dc
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#define mmBLNDV0_BLNDV_SM_CONTROL2_BASE_IDX 2
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#define mmBLNDV0_BLNDV_CONTROL2 0x12dd
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#define mmBLNDV0_BLNDV_CONTROL2_BASE_IDX 2
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#define mmBLNDV0_BLNDV_UPDATE 0x12de
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#define mmBLNDV0_BLNDV_UPDATE_BASE_IDX 2
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#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x12df
|
#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
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#define mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x12e0
|
#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
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#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x12e1
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#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_crtcv0_dispdec
|
// base address: 0x0
|
#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM 0x12e6
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#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
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#define mmCRTCV0_CRTCV_H_TOTAL 0x12e7
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#define mmCRTCV0_CRTCV_H_TOTAL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_H_BLANK_START_END 0x12e8
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#define mmCRTCV0_CRTCV_H_BLANK_START_END_BASE_IDX 2
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#define mmCRTCV0_CRTCV_H_SYNC_A 0x12e9
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#define mmCRTCV0_CRTCV_H_SYNC_A_BASE_IDX 2
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#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL 0x12ea
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#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_H_SYNC_B 0x12eb
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#define mmCRTCV0_CRTCV_H_SYNC_B_BASE_IDX 2
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#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL 0x12ec
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#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VBI_END 0x12ed
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#define mmCRTCV0_CRTCV_VBI_END_BASE_IDX 2
|
#define mmCRTCV0_CRTCV_V_TOTAL 0x12ee
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#define mmCRTCV0_CRTCV_V_TOTAL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_TOTAL_MIN 0x12ef
|
#define mmCRTCV0_CRTCV_V_TOTAL_MIN_BASE_IDX 2
|
#define mmCRTCV0_CRTCV_V_TOTAL_MAX 0x12f0
|
#define mmCRTCV0_CRTCV_V_TOTAL_MAX_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL 0x12f1
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#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS 0x12f2
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#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS 0x12f3
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#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_BLANK_START_END 0x12f4
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#define mmCRTCV0_CRTCV_V_BLANK_START_END_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_SYNC_A 0x12f5
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#define mmCRTCV0_CRTCV_V_SYNC_A_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL 0x12f6
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#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_SYNC_B 0x12f7
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#define mmCRTCV0_CRTCV_V_SYNC_B_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL 0x12f8
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#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_DTMTEST_CNTL 0x12f9
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#define mmCRTCV0_CRTCV_DTMTEST_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION 0x12fa
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#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
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#define mmCRTCV0_CRTCV_TRIGA_CNTL 0x12fb
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#define mmCRTCV0_CRTCV_TRIGA_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG 0x12fc
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#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTCV0_CRTCV_TRIGB_CNTL 0x12fd
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#define mmCRTCV0_CRTCV_TRIGB_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG 0x12fe
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#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL 0x12ff
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#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_FLOW_CONTROL 0x1300
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#define mmCRTCV0_CRTCV_FLOW_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE 0x1301
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#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmCRTCV0_CRTCV_AVSYNC_COUNTER 0x1302
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#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CONTROL 0x1303
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#define mmCRTCV0_CRTCV_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_BLANK_CONTROL 0x1304
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#define mmCRTCV0_CRTCV_BLANK_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_INTERLACE_CONTROL 0x1305
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#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_INTERLACE_STATUS 0x1306
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#define mmCRTCV0_CRTCV_INTERLACE_STATUS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL 0x1307
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#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0 0x1308
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#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1 0x1309
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#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STATUS 0x130a
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#define mmCRTCV0_CRTCV_STATUS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STATUS_POSITION 0x130b
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#define mmCRTCV0_CRTCV_STATUS_POSITION_BASE_IDX 2
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#define mmCRTCV0_CRTCV_NOM_VERT_POSITION 0x130c
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#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT 0x130d
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#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STATUS_VF_COUNT 0x130e
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#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STATUS_HV_COUNT 0x130f
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#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
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#define mmCRTCV0_CRTCV_COUNT_CONTROL 0x1310
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#define mmCRTCV0_CRTCV_COUNT_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_COUNT_RESET 0x1311
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#define mmCRTCV0_CRTCV_COUNT_RESET_BASE_IDX 2
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#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1312
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#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL 0x1313
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#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STEREO_STATUS 0x1314
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#define mmCRTCV0_CRTCV_STEREO_STATUS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STEREO_CONTROL 0x1315
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#define mmCRTCV0_CRTCV_STEREO_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS 0x1316
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#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL 0x1317
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#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION 0x1318
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#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME 0x1319
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#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmCRTCV0_CRTCV_START_LINE_CONTROL 0x131a
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#define mmCRTCV0_CRTCV_START_LINE_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL 0x131b
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#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_UPDATE_LOCK 0x131c
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#define mmCRTCV0_CRTCV_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL 0x131d
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#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x131e
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#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
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#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL 0x131f
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#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS 0x1320
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#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR 0x1321
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#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK 0x1322
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#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE 0x1323
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#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT 0x1324
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#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
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#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1325
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#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
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#define mmCRTCV0_CRTCV_MVP_STATUS 0x1326
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#define mmCRTCV0_CRTCV_MVP_STATUS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_MASTER_EN 0x1327
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#define mmCRTCV0_CRTCV_MASTER_EN_BASE_IDX 2
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#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1328
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#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
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#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS 0x1329
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#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
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#define mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x132b
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#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
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#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x132c
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#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
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#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR 0x132d
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#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT 0x132e
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#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmCRTCV0_CRTCV_BLACK_COLOR 0x132f
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#define mmCRTCV0_CRTCV_BLACK_COLOR_BASE_IDX 2
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#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x1330
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#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1331
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1332
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1333
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1334
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1335
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1336
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#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC_CNTL 0x1337
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#define mmCRTCV0_CRTCV_CRC_CNTL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1338
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#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1339
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#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x133a
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#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x133b
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#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC0_DATA_RG 0x133c
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#define mmCRTCV0_CRTCV_CRC0_DATA_RG_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC0_DATA_B 0x133d
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#define mmCRTCV0_CRTCV_CRC0_DATA_B_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x133e
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#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x133f
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#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1340
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#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1341
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#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC1_DATA_RG 0x1342
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#define mmCRTCV0_CRTCV_CRC1_DATA_RG_BASE_IDX 2
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#define mmCRTCV0_CRTCV_CRC1_DATA_B 0x1343
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#define mmCRTCV0_CRTCV_CRC1_DATA_B_BASE_IDX 2
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1344
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1345
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1346
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1347
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1348
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1349
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#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL 0x134a
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#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL 0x134b
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#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP 0x134c
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#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmCRTCV0_CRTCV_GSL_WINDOW 0x134d
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#define mmCRTCV0_CRTCV_GSL_WINDOW_BASE_IDX 2
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#define mmCRTCV0_CRTCV_GSL_CONTROL 0x134e
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#define mmCRTCV0_CRTCV_GSL_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_unp1_dispdec
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// base address: 0x800
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#define mmUNP1_UNP_GRPH_ENABLE 0x135a
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#define mmUNP1_UNP_GRPH_ENABLE_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_CONTROL 0x135b
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#define mmUNP1_UNP_GRPH_CONTROL_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_CONTROL_C 0x135c
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#define mmUNP1_UNP_GRPH_CONTROL_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_CONTROL_EXP 0x135d
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#define mmUNP1_UNP_GRPH_CONTROL_EXP_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SWAP_CNTL 0x135e
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#define mmUNP1_UNP_GRPH_SWAP_CNTL_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x135f
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#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x1360
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#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x1361
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#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x1362
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#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x1363
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#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x1364
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#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x1365
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#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x1366
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#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x1367
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#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x1368
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#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x1369
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#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x136a
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#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x136b
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#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x136c
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#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x136d
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#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x136e
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#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PITCH_L 0x136f
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#define mmUNP1_UNP_GRPH_PITCH_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_PITCH_C 0x1370
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#define mmUNP1_UNP_GRPH_PITCH_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x1371
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#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x1372
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#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x1373
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#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x1374
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#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_X_START_L 0x1375
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#define mmUNP1_UNP_GRPH_X_START_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_X_START_C 0x1376
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#define mmUNP1_UNP_GRPH_X_START_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_Y_START_L 0x1377
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#define mmUNP1_UNP_GRPH_Y_START_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_Y_START_C 0x1378
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#define mmUNP1_UNP_GRPH_Y_START_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_X_END_L 0x1379
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#define mmUNP1_UNP_GRPH_X_END_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_X_END_C 0x137a
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#define mmUNP1_UNP_GRPH_X_END_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_Y_END_L 0x137b
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#define mmUNP1_UNP_GRPH_Y_END_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_Y_END_C 0x137c
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#define mmUNP1_UNP_GRPH_Y_END_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_UPDATE 0x137d
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#define mmUNP1_UNP_GRPH_UPDATE_BASE_IDX 2
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#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x137e
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#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x137f
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#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x1380
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#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x1381
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#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x1382
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#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_BASE_IDX 2
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#define mmUNP1_UNP_DVMM_PTE_CONTROL 0x1383
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#define mmUNP1_UNP_DVMM_PTE_CONTROL_BASE_IDX 2
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#define mmUNP1_UNP_DVMM_PTE_CONTROL_C 0x1384
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#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_BASE_IDX 2
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#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL 0x1385
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#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_BASE_IDX 2
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#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C 0x1386
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#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x1387
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#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x1388
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#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x1389
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#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_BASE_IDX 2
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#define mmUNP1_UNP_FLIP_CONTROL 0x138a
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#define mmUNP1_UNP_FLIP_CONTROL_BASE_IDX 2
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#define mmUNP1_UNP_CRC_CONTROL 0x138b
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#define mmUNP1_UNP_CRC_CONTROL_BASE_IDX 2
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#define mmUNP1_UNP_CRC_MASK 0x138c
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#define mmUNP1_UNP_CRC_MASK_BASE_IDX 2
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#define mmUNP1_UNP_CRC_CURRENT 0x138d
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#define mmUNP1_UNP_CRC_CURRENT_BASE_IDX 2
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#define mmUNP1_UNP_CRC_LAST 0x138e
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#define mmUNP1_UNP_CRC_LAST_BASE_IDX 2
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#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x138f
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#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_BASE_IDX 2
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#define mmUNP1_UNP_HW_ROTATION 0x1390
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#define mmUNP1_UNP_HW_ROTATION_BASE_IDX 2
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// addressBlock: dce_dc_lbv1_dispdec
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// base address: 0x800
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#define mmLBV1_LBV_DATA_FORMAT 0x1396
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#define mmLBV1_LBV_DATA_FORMAT_BASE_IDX 2
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#define mmLBV1_LBV_MEMORY_CTRL 0x1397
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#define mmLBV1_LBV_MEMORY_CTRL_BASE_IDX 2
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#define mmLBV1_LBV_MEMORY_SIZE_STATUS 0x1398
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#define mmLBV1_LBV_MEMORY_SIZE_STATUS_BASE_IDX 2
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#define mmLBV1_LBV_DESKTOP_HEIGHT 0x1399
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#define mmLBV1_LBV_DESKTOP_HEIGHT_BASE_IDX 2
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#define mmLBV1_LBV_VLINE_START_END 0x139a
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#define mmLBV1_LBV_VLINE_START_END_BASE_IDX 2
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#define mmLBV1_LBV_VLINE2_START_END 0x139b
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#define mmLBV1_LBV_VLINE2_START_END_BASE_IDX 2
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#define mmLBV1_LBV_V_COUNTER 0x139c
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#define mmLBV1_LBV_V_COUNTER_BASE_IDX 2
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#define mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x139d
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#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_BASE_IDX 2
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#define mmLBV1_LBV_V_COUNTER_CHROMA 0x139e
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#define mmLBV1_LBV_V_COUNTER_CHROMA_BASE_IDX 2
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#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x139f
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#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_BASE_IDX 2
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#define mmLBV1_LBV_INTERRUPT_MASK 0x13a0
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#define mmLBV1_LBV_INTERRUPT_MASK_BASE_IDX 2
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#define mmLBV1_LBV_VLINE_STATUS 0x13a1
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#define mmLBV1_LBV_VLINE_STATUS_BASE_IDX 2
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#define mmLBV1_LBV_VLINE2_STATUS 0x13a2
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#define mmLBV1_LBV_VLINE2_STATUS_BASE_IDX 2
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#define mmLBV1_LBV_VBLANK_STATUS 0x13a3
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#define mmLBV1_LBV_VBLANK_STATUS_BASE_IDX 2
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#define mmLBV1_LBV_SYNC_RESET_SEL 0x13a4
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#define mmLBV1_LBV_SYNC_RESET_SEL_BASE_IDX 2
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#define mmLBV1_LBV_BLACK_KEYER_R_CR 0x13a5
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#define mmLBV1_LBV_BLACK_KEYER_R_CR_BASE_IDX 2
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#define mmLBV1_LBV_BLACK_KEYER_G_Y 0x13a6
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#define mmLBV1_LBV_BLACK_KEYER_G_Y_BASE_IDX 2
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#define mmLBV1_LBV_BLACK_KEYER_B_CB 0x13a7
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#define mmLBV1_LBV_BLACK_KEYER_B_CB_BASE_IDX 2
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#define mmLBV1_LBV_KEYER_COLOR_CTRL 0x13a8
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#define mmLBV1_LBV_KEYER_COLOR_CTRL_BASE_IDX 2
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#define mmLBV1_LBV_KEYER_COLOR_R_CR 0x13a9
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#define mmLBV1_LBV_KEYER_COLOR_R_CR_BASE_IDX 2
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#define mmLBV1_LBV_KEYER_COLOR_G_Y 0x13aa
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#define mmLBV1_LBV_KEYER_COLOR_G_Y_BASE_IDX 2
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#define mmLBV1_LBV_KEYER_COLOR_B_CB 0x13ab
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#define mmLBV1_LBV_KEYER_COLOR_B_CB_BASE_IDX 2
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#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x13ac
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#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_BASE_IDX 2
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#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x13ad
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#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_BASE_IDX 2
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#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x13ae
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#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_BASE_IDX 2
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#define mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x13af
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#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_BASE_IDX 2
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#define mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x13b0
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#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_BASE_IDX 2
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#define mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x13b1
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#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_BASE_IDX 2
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#define mmLBV1_LBV_BUFFER_STATUS 0x13b2
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#define mmLBV1_LBV_BUFFER_STATUS_BASE_IDX 2
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#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x13b3
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#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_sclv1_dispdec
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// base address: 0x800
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#define mmSCLV1_SCLV_COEF_RAM_SELECT 0x13ca
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#define mmSCLV1_SCLV_COEF_RAM_SELECT_BASE_IDX 2
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#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x13cb
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#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmSCLV1_SCLV_MODE 0x13cc
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#define mmSCLV1_SCLV_MODE_BASE_IDX 2
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#define mmSCLV1_SCLV_TAP_CONTROL 0x13cd
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#define mmSCLV1_SCLV_TAP_CONTROL_BASE_IDX 2
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#define mmSCLV1_SCLV_CONTROL 0x13ce
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#define mmSCLV1_SCLV_CONTROL_BASE_IDX 2
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#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x13cf
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#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x13d0
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#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_BASE_IDX 2
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#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x13d1
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#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_BASE_IDX 2
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#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x13d2
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#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCLV1_SCLV_HORZ_FILTER_INIT 0x13d3
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#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x13d4
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#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x13d5
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#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x13d6
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#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_BASE_IDX 2
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#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x13d7
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#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmSCLV1_SCLV_VERT_FILTER_INIT 0x13d8
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#define mmSCLV1_SCLV_VERT_FILTER_INIT_BASE_IDX 2
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#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x13d9
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#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x13da
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#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x13db
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#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x13dc
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#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmSCLV1_SCLV_ROUND_OFFSET 0x13dd
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#define mmSCLV1_SCLV_ROUND_OFFSET_BASE_IDX 2
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#define mmSCLV1_SCLV_UPDATE 0x13de
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#define mmSCLV1_SCLV_UPDATE_BASE_IDX 2
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#define mmSCLV1_SCLV_ALU_CONTROL 0x13df
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#define mmSCLV1_SCLV_ALU_CONTROL_BASE_IDX 2
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#define mmSCLV1_SCLV_VIEWPORT_START 0x13e0
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#define mmSCLV1_SCLV_VIEWPORT_START_BASE_IDX 2
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#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x13e1
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#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_BASE_IDX 2
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#define mmSCLV1_SCLV_VIEWPORT_SIZE 0x13e2
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#define mmSCLV1_SCLV_VIEWPORT_SIZE_BASE_IDX 2
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#define mmSCLV1_SCLV_VIEWPORT_START_C 0x13e3
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#define mmSCLV1_SCLV_VIEWPORT_START_C_BASE_IDX 2
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#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x13e4
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#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_BASE_IDX 2
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#define mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x13e5
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#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_BASE_IDX 2
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#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x13e6
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#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x13e7
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#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmSCLV1_SCLV_MODE_CHANGE_DET1 0x13e8
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#define mmSCLV1_SCLV_MODE_CHANGE_DET1_BASE_IDX 2
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#define mmSCLV1_SCLV_MODE_CHANGE_DET2 0x13e9
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#define mmSCLV1_SCLV_MODE_CHANGE_DET2_BASE_IDX 2
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#define mmSCLV1_SCLV_MODE_CHANGE_DET3 0x13ea
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#define mmSCLV1_SCLV_MODE_CHANGE_DET3_BASE_IDX 2
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#define mmSCLV1_SCLV_MODE_CHANGE_MASK 0x13eb
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#define mmSCLV1_SCLV_MODE_CHANGE_MASK_BASE_IDX 2
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#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x13ec
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#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_BASE_IDX 2
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#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x13ed
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#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_BASE_IDX 2
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// addressBlock: dce_dc_col_man1_dispdec
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// base address: 0x800
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#define mmCOL_MAN1_COL_MAN_UPDATE 0x13fe
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#define mmCOL_MAN1_COL_MAN_UPDATE_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x13ff
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#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x1400
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#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x1401
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#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x1402
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#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x1403
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#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x1404
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#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x1405
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#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x1406
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#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x1407
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#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x1408
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#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x1409
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#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x140a
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#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x140b
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#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_BASE_IDX 2
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#define mmCOL_MAN1_PRESCALE_CONTROL 0x140c
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#define mmCOL_MAN1_PRESCALE_CONTROL_BASE_IDX 2
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#define mmCOL_MAN1_PRESCALE_VALUES_R 0x140d
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#define mmCOL_MAN1_PRESCALE_VALUES_R_BASE_IDX 2
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#define mmCOL_MAN1_PRESCALE_VALUES_G 0x140e
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#define mmCOL_MAN1_PRESCALE_VALUES_G_BASE_IDX 2
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#define mmCOL_MAN1_PRESCALE_VALUES_B 0x140f
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#define mmCOL_MAN1_PRESCALE_VALUES_B_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x1410
|
#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x1411
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#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x1412
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#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x1413
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#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x1414
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#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x1415
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#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x1416
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#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x1417
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#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x1418
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#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x1419
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#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x141a
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#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x141b
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#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_BASE_IDX 2
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#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x141c
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#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_BASE_IDX 2
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#define mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x141d
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#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_BASE_IDX 2
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#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x141e
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#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_BASE_IDX 2
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#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x141f
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#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_BASE_IDX 2
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#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x1420
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#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x1421
|
#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL 0x1422
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX 0x1423
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#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA 0x1424
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#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK 0x1425
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#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL 0x1426
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL 0x1427
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1 0x1428
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2 0x1429
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1 0x142a
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3 0x142b
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5 0x142c
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7 0x142d
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9 0x142e
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11 0x142f
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13 0x1430
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15 0x1431
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL 0x1432
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL 0x1433
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1 0x1434
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2 0x1435
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1 0x1436
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3 0x1437
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5 0x1438
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7 0x1439
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9 0x143a
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11 0x143b
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13 0x143c
|
#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15 0x143d
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#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_BASE_IDX 2
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#define mmCOL_MAN1_PACK_FIFO_ERROR 0x143e
|
#define mmCOL_MAN1_PACK_FIFO_ERROR_BASE_IDX 2
|
#define mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x143f
|
#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x1440
|
#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_BASE_IDX 2
|
#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x1441
|
#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_BASE_IDX 2
|
#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x1442
|
#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x1443
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#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x1444
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#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x1445
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#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x1446
|
#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x1447
|
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_BASE_IDX 2
|
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x1448
|
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_BASE_IDX 2
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#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x1449
|
#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL 0x144a
|
#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL 0x144b
|
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12 0x144c
|
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14 0x144d
|
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22 0x144e
|
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24 0x144f
|
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32 0x1450
|
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34 0x1451
|
#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_BASE_IDX 2
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|
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// addressBlock: dce_dc_dcfev1_dispdec
|
// base address: 0x800
|
#define mmDCFEV1_DCFEV_CLOCK_CONTROL 0x147e
|
#define mmDCFEV1_DCFEV_CLOCK_CONTROL_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_SOFT_RESET 0x147f
|
#define mmDCFEV1_DCFEV_SOFT_RESET_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x1480
|
#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x1482
|
#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x1483
|
#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x1484
|
#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x1485
|
#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x1486
|
#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_L_FLUSH 0x1487
|
#define mmDCFEV1_DCFEV_L_FLUSH_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_C_FLUSH 0x1488
|
#define mmDCFEV1_DCFEV_C_FLUSH_BASE_IDX 2
|
#define mmDCFEV1_DCFEV_MISC 0x148a
|
#define mmDCFEV1_DCFEV_MISC_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dc_perfmon12_dispdec
|
// base address: 0x51c8
|
#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x1492
|
#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x1493
|
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x1494
|
#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_CNTL 0x1495
|
#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_CNTL2 0x1496
|
#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x1497
|
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x1498
|
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_HI 0x1499
|
#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_LOW 0x149a
|
#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmifv_pg1_dispdec
|
// base address: 0x800
|
#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x149e
|
#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x149f
|
#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x14a0
|
#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x14a1
|
#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x14a2
|
#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x14a3
|
#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14a4
|
#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x14a5
|
#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x14a6
|
#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x14aa
|
#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x14ab
|
#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x14ac
|
#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x14ad
|
#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x14ae
|
#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x14af
|
#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_BASE_IDX 2
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#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x14b0
|
#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x14b1
|
#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x14b2
|
#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x14b3
|
#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_BASE_IDX 2
|
#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x14b7
|
#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_blndv1_dispdec
|
// base address: 0x800
|
#define mmBLNDV1_BLNDV_CONTROL 0x14db
|
#define mmBLNDV1_BLNDV_CONTROL_BASE_IDX 2
|
#define mmBLNDV1_BLNDV_SM_CONTROL2 0x14dc
|
#define mmBLNDV1_BLNDV_SM_CONTROL2_BASE_IDX 2
|
#define mmBLNDV1_BLNDV_CONTROL2 0x14dd
|
#define mmBLNDV1_BLNDV_CONTROL2_BASE_IDX 2
|
#define mmBLNDV1_BLNDV_UPDATE 0x14de
|
#define mmBLNDV1_BLNDV_UPDATE_BASE_IDX 2
|
#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x14df
|
#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_BASE_IDX 2
|
#define mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x14e0
|
#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_BASE_IDX 2
|
#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x14e1
|
#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_crtcv1_dispdec
|
// base address: 0x800
|
#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM 0x14e6
|
#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_H_TOTAL 0x14e7
|
#define mmCRTCV1_CRTCV_H_TOTAL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_H_BLANK_START_END 0x14e8
|
#define mmCRTCV1_CRTCV_H_BLANK_START_END_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_H_SYNC_A 0x14e9
|
#define mmCRTCV1_CRTCV_H_SYNC_A_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL 0x14ea
|
#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_H_SYNC_B 0x14eb
|
#define mmCRTCV1_CRTCV_H_SYNC_B_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL 0x14ec
|
#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_VBI_END 0x14ed
|
#define mmCRTCV1_CRTCV_VBI_END_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_TOTAL 0x14ee
|
#define mmCRTCV1_CRTCV_V_TOTAL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_TOTAL_MIN 0x14ef
|
#define mmCRTCV1_CRTCV_V_TOTAL_MIN_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_TOTAL_MAX 0x14f0
|
#define mmCRTCV1_CRTCV_V_TOTAL_MAX_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL 0x14f1
|
#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS 0x14f2
|
#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS 0x14f3
|
#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_BLANK_START_END 0x14f4
|
#define mmCRTCV1_CRTCV_V_BLANK_START_END_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_SYNC_A 0x14f5
|
#define mmCRTCV1_CRTCV_V_SYNC_A_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL 0x14f6
|
#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_SYNC_B 0x14f7
|
#define mmCRTCV1_CRTCV_V_SYNC_B_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL 0x14f8
|
#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_DTMTEST_CNTL 0x14f9
|
#define mmCRTCV1_CRTCV_DTMTEST_CNTL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION 0x14fa
|
#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_TRIGA_CNTL 0x14fb
|
#define mmCRTCV1_CRTCV_TRIGA_CNTL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG 0x14fc
|
#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_TRIGB_CNTL 0x14fd
|
#define mmCRTCV1_CRTCV_TRIGB_CNTL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG 0x14fe
|
#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL 0x14ff
|
#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_FLOW_CONTROL 0x1500
|
#define mmCRTCV1_CRTCV_FLOW_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE 0x1501
|
#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_AVSYNC_COUNTER 0x1502
|
#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_CONTROL 0x1503
|
#define mmCRTCV1_CRTCV_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_BLANK_CONTROL 0x1504
|
#define mmCRTCV1_CRTCV_BLANK_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_INTERLACE_CONTROL 0x1505
|
#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_INTERLACE_STATUS 0x1506
|
#define mmCRTCV1_CRTCV_INTERLACE_STATUS_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL 0x1507
|
#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0 0x1508
|
#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1 0x1509
|
#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_STATUS 0x150a
|
#define mmCRTCV1_CRTCV_STATUS_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_STATUS_POSITION 0x150b
|
#define mmCRTCV1_CRTCV_STATUS_POSITION_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_NOM_VERT_POSITION 0x150c
|
#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT 0x150d
|
#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_STATUS_VF_COUNT 0x150e
|
#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_STATUS_HV_COUNT 0x150f
|
#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_COUNT_CONTROL 0x1510
|
#define mmCRTCV1_CRTCV_COUNT_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_COUNT_RESET 0x1511
|
#define mmCRTCV1_CRTCV_COUNT_RESET_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1512
|
#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL 0x1513
|
#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_STEREO_STATUS 0x1514
|
#define mmCRTCV1_CRTCV_STEREO_STATUS_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_STEREO_CONTROL 0x1515
|
#define mmCRTCV1_CRTCV_STEREO_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS 0x1516
|
#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL 0x1517
|
#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION 0x1518
|
#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME 0x1519
|
#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_START_LINE_CONTROL 0x151a
|
#define mmCRTCV1_CRTCV_START_LINE_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL 0x151b
|
#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_UPDATE_LOCK 0x151c
|
#define mmCRTCV1_CRTCV_UPDATE_LOCK_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL 0x151d
|
#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE 0x151e
|
#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL 0x151f
|
#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS 0x1520
|
#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR 0x1521
|
#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_BASE_IDX 2
|
#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK 0x1522
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#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE 0x1523
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#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT 0x1524
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#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_BASE_IDX 2
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#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x1525
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#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_BASE_IDX 2
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#define mmCRTCV1_CRTCV_MVP_STATUS 0x1526
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#define mmCRTCV1_CRTCV_MVP_STATUS_BASE_IDX 2
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#define mmCRTCV1_CRTCV_MASTER_EN 0x1527
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#define mmCRTCV1_CRTCV_MASTER_EN_BASE_IDX 2
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#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT 0x1528
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#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_BASE_IDX 2
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#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS 0x1529
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#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_BASE_IDX 2
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#define mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x152b
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#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_BASE_IDX 2
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#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x152c
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#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_BASE_IDX 2
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#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR 0x152d
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#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT 0x152e
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#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmCRTCV1_CRTCV_BLACK_COLOR 0x152f
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#define mmCRTCV1_CRTCV_BLACK_COLOR_BASE_IDX 2
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#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x1530
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#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION 0x1531
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL 0x1532
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION 0x1533
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL 0x1534
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION 0x1535
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL 0x1536
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#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC_CNTL 0x1537
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#define mmCRTCV1_CRTCV_CRC_CNTL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x1538
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#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x1539
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#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x153a
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#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x153b
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#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC0_DATA_RG 0x153c
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#define mmCRTCV1_CRTCV_CRC0_DATA_RG_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC0_DATA_B 0x153d
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#define mmCRTCV1_CRTCV_CRC0_DATA_B_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x153e
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#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x153f
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#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x1540
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#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x1541
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#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC1_DATA_RG 0x1542
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#define mmCRTCV1_CRTCV_CRC1_DATA_RG_BASE_IDX 2
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#define mmCRTCV1_CRTCV_CRC1_DATA_B 0x1543
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#define mmCRTCV1_CRTCV_CRC1_DATA_B_BASE_IDX 2
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL 0x1544
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START 0x1545
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_BASE_IDX 2
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END 0x1546
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_BASE_IDX 2
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1547
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1548
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1549
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#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL 0x154a
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#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL 0x154b
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#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP 0x154c
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#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmCRTCV1_CRTCV_GSL_WINDOW 0x154d
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#define mmCRTCV1_CRTCV_GSL_WINDOW_BASE_IDX 2
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#define mmCRTCV1_CRTCV_GSL_CONTROL 0x154e
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#define mmCRTCV1_CRTCV_GSL_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_hpd0_dispdec
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// base address: 0x0
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#define mmHPD0_DC_HPD_INT_STATUS 0x1600
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#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD0_DC_HPD_INT_CONTROL 0x1601
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#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD0_DC_HPD_CONTROL 0x1602
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#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1603
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#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1604
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#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_hpd1_dispdec
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// base address: 0x20
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#define mmHPD1_DC_HPD_INT_STATUS 0x1608
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#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD1_DC_HPD_INT_CONTROL 0x1609
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#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD1_DC_HPD_CONTROL 0x160a
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#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x160b
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#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x160c
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#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_hpd2_dispdec
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// base address: 0x40
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#define mmHPD2_DC_HPD_INT_STATUS 0x1610
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#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD2_DC_HPD_INT_CONTROL 0x1611
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#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD2_DC_HPD_CONTROL 0x1612
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#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1613
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#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1614
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#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_hpd3_dispdec
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// base address: 0x60
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#define mmHPD3_DC_HPD_INT_STATUS 0x1618
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#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD3_DC_HPD_INT_CONTROL 0x1619
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#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD3_DC_HPD_CONTROL 0x161a
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#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x161b
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#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x161c
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#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_hpd4_dispdec
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// base address: 0x80
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#define mmHPD4_DC_HPD_INT_STATUS 0x1620
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#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD4_DC_HPD_INT_CONTROL 0x1621
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#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD4_DC_HPD_CONTROL 0x1622
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#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1623
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#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1624
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#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_hpd5_dispdec
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// base address: 0xa0
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#define mmHPD5_DC_HPD_INT_STATUS 0x1628
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#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD5_DC_HPD_INT_CONTROL 0x1629
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#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD5_DC_HPD_CONTROL 0x162a
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#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x162b
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#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x162c
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#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon2_dispdec
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// base address: 0x5840
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1630
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x1631
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1632
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#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CNTL 0x1633
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#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CNTL2 0x1634
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#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1635
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#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1636
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#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_HI 0x1637
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#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_LOW 0x1638
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#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dp_aux0_dispdec
|
// base address: 0x0
|
#define mmDP_AUX0_AUX_CONTROL 0x1766
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#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_SW_CONTROL 0x1767
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#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_ARB_CONTROL 0x1768
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#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1769
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#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_SW_STATUS 0x176a
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#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_LS_STATUS 0x176b
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#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_SW_DATA 0x176c
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#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX0_AUX_LS_DATA 0x176d
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#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x176e
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#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x176f
|
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1770
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#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1771
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#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1772
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#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1773
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#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1775
|
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1776
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#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1777
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#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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|
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// addressBlock: dce_dc_dp_aux1_dispdec
|
// base address: 0x70
|
#define mmDP_AUX1_AUX_CONTROL 0x1782
|
#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_SW_CONTROL 0x1783
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#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_ARB_CONTROL 0x1784
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#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1785
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#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_SW_STATUS 0x1786
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#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX1_AUX_LS_STATUS 0x1787
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#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_SW_DATA 0x1788
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#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX1_AUX_LS_DATA 0x1789
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#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x178a
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#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x178b
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#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x178c
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x178d
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x178e
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#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x178f
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#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1791
|
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1792
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#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1793
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#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dp_aux2_dispdec
|
// base address: 0xe0
|
#define mmDP_AUX2_AUX_CONTROL 0x179e
|
#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_SW_CONTROL 0x179f
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#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_ARB_CONTROL 0x17a0
|
#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x17a1
|
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_SW_STATUS 0x17a2
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#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_LS_STATUS 0x17a3
|
#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_SW_DATA 0x17a4
|
#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX2_AUX_LS_DATA 0x17a5
|
#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x17a6
|
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x17a7
|
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x17a8
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x17a9
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x17aa
|
#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x17ab
|
#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x17ad
|
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ae
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x17af
|
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dp_aux3_dispdec
|
// base address: 0x150
|
#define mmDP_AUX3_AUX_CONTROL 0x17ba
|
#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_SW_CONTROL 0x17bb
|
#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_ARB_CONTROL 0x17bc
|
#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x17bd
|
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_SW_STATUS 0x17be
|
#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_LS_STATUS 0x17bf
|
#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_SW_DATA 0x17c0
|
#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX3_AUX_LS_DATA 0x17c1
|
#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x17c2
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#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x17c3
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#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x17c4
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x17c5
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x17c6
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#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x17c7
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#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x17c9
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#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17ca
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#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x17cb
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#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dp_aux4_dispdec
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// base address: 0x1c0
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#define mmDP_AUX4_AUX_CONTROL 0x17d6
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#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_SW_CONTROL 0x17d7
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#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_ARB_CONTROL 0x17d8
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#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x17d9
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#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_SW_STATUS 0x17da
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#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_LS_STATUS 0x17db
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#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_SW_DATA 0x17dc
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#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX4_AUX_LS_DATA 0x17dd
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#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x17de
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#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x17df
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#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x17e0
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#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x17e1
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#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x17e2
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#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x17e3
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#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x17e5
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#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x17e6
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#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x17e7
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#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dp_aux5_dispdec
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// base address: 0x230
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#define mmDP_AUX5_AUX_CONTROL 0x17f2
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#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_SW_CONTROL 0x17f3
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#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_ARB_CONTROL 0x17f4
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#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x17f5
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#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_SW_STATUS 0x17f6
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#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_LS_STATUS 0x17f7
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#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_SW_DATA 0x17f8
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#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX5_AUX_LS_DATA 0x17f9
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#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x17fa
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#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x17fb
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#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x17fc
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#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x17fd
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#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x17fe
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#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x17ff
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#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1801
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#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1802
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#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1803
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#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dig0_dispdec
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// base address: 0x0
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#define mmDIG0_DIG_FE_CNTL 0x187e
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#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x187f
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#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1880
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#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG0_DIG_CLOCK_PATTERN 0x1881
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#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG0_DIG_TEST_PATTERN 0x1882
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#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1883
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#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG0_DIG_FIFO_STATUS 0x1884
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#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG0_HDMI_CONTROL 0x1887
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#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_STATUS 0x1888
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#define mmDIG0_HDMI_STATUS_BASE_IDX 2
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#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1889
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#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x188a
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#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x188b
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#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x188c
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#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x188d
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#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x188e
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG0_AFMT_INTERRUPT_STATUS 0x188f
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#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG0_HDMI_GC 0x1891
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#define mmDIG0_HDMI_GC_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1892
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#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_0 0x1893
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#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_1 0x1894
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#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_2 0x1895
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#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_3 0x1896
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#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_4 0x1897
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#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC2_0 0x1898
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#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC2_1 0x1899
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#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC2_2 0x189a
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#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC2_3 0x189b
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#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG0_AFMT_AVI_INFO0 0x189c
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#define mmDIG0_AFMT_AVI_INFO0_BASE_IDX 2
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#define mmDIG0_AFMT_AVI_INFO1 0x189d
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#define mmDIG0_AFMT_AVI_INFO1_BASE_IDX 2
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#define mmDIG0_AFMT_AVI_INFO2 0x189e
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#define mmDIG0_AFMT_AVI_INFO2_BASE_IDX 2
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#define mmDIG0_AFMT_AVI_INFO3 0x189f
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#define mmDIG0_AFMT_AVI_INFO3_BASE_IDX 2
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#define mmDIG0_AFMT_MPEG_INFO0 0x18a0
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#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG0_AFMT_MPEG_INFO1 0x18a1
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#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_HDR 0x18a2
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#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_0 0x18a3
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#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_1 0x18a4
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#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_2 0x18a5
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#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_3 0x18a6
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#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_4 0x18a7
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#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_5 0x18a8
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#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_6 0x18a9
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#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_7 0x18aa
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#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x18ab
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_32_0 0x18ac
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#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_32_1 0x18ad
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#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_44_0 0x18ae
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#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_44_1 0x18af
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#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_48_0 0x18b0
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#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_48_1 0x18b1
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#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_STATUS_0 0x18b2
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#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_STATUS_1 0x18b3
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#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_INFO0 0x18b4
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#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_INFO1 0x18b5
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#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG0_AFMT_60958_0 0x18b6
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#define mmDIG0_AFMT_60958_0_BASE_IDX 2
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#define mmDIG0_AFMT_60958_1 0x18b7
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#define mmDIG0_AFMT_60958_1_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x18b8
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#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG0_AFMT_RAMP_CONTROL0 0x18b9
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#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG0_AFMT_RAMP_CONTROL1 0x18ba
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#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG0_AFMT_RAMP_CONTROL2 0x18bb
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#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG0_AFMT_RAMP_CONTROL3 0x18bc
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#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG0_AFMT_60958_2 0x18bd
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#define mmDIG0_AFMT_60958_2_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x18be
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#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG0_AFMT_STATUS 0x18bf
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#define mmDIG0_AFMT_STATUS_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x18c0
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#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x18c1
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#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x18c2
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#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x18c3
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#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG0_DIG_BE_CNTL 0x18c5
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#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_BE_EN_CNTL 0x18c6
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#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CNTL 0x18e9
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#define mmDIG0_TMDS_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CONTROL_CHAR 0x18ea
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#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x18eb
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#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x18ec
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#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x18ed
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x18ee
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG0_TMDS_CTL_BITS 0x18f0
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#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x18f1
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#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x18f3
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#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x18f4
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#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_VERSION 0x18f6
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#define mmDIG0_DIG_VERSION_BASE_IDX 2
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#define mmDIG0_DIG_LANE_ENABLE 0x18f7
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#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG0_AFMT_CNTL 0x18fc
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#define mmDIG0_AFMT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dp0_dispdec
|
// base address: 0x0
|
#define mmDP0_DP_LINK_CNTL 0x191e
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#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP0_DP_PIXEL_FORMAT 0x191f
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#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP0_DP_MSA_COLORIMETRY 0x1920
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#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP0_DP_CONFIG 0x1921
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#define mmDP0_DP_CONFIG_BASE_IDX 2
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#define mmDP0_DP_VID_STREAM_CNTL 0x1922
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#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP0_DP_STEER_FIFO 0x1923
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#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP0_DP_MSA_MISC 0x1924
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#define mmDP0_DP_MSA_MISC_BASE_IDX 2
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#define mmDP0_DP_VID_TIMING 0x1926
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#define mmDP0_DP_VID_TIMING_BASE_IDX 2
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#define mmDP0_DP_VID_N 0x1927
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#define mmDP0_DP_VID_N_BASE_IDX 2
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#define mmDP0_DP_VID_M 0x1928
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#define mmDP0_DP_VID_M_BASE_IDX 2
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#define mmDP0_DP_LINK_FRAMING_CNTL 0x1929
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#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP0_DP_HBR2_EYE_PATTERN 0x192a
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#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP0_DP_VID_MSA_VBID 0x192b
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#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP0_DP_VID_INTERRUPT_CNTL 0x192c
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#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CNTL 0x192d
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#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x192e
|
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM0 0x192f
|
#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM1 0x1930
|
#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM2 0x1931
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#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP0_DP_DPHY_8B10B_CNTL 0x1932
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#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_PRBS_CNTL 0x1933
|
#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_SCRAM_CNTL 0x1934
|
#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_EN 0x1935
|
#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_CNTL 0x1936
|
#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_RESULT 0x1937
|
#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1938
|
#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1939
|
#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP0_DP_DPHY_FAST_TRAINING 0x193a
|
#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x193b
|
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x193c
|
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
|
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x193d
|
#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL 0x1941
|
#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL1 0x1942
|
#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP0_DP_SEC_FRAMING1 0x1943
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#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING2 0x1944
|
#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP0_DP_SEC_FRAMING3 0x1945
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#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING4 0x1946
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#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_N 0x1947
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#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_N_READBACK 0x1948
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#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_M 0x1949
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#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_M_READBACK 0x194a
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#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP0_DP_SEC_TIMESTAMP 0x194b
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#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP0_DP_SEC_PACKET_CNTL 0x194c
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#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSE_RATE_CNTL 0x194d
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#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSE_RATE_UPDATE 0x194f
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#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT0 0x1950
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#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT1 0x1951
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#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT2 0x1952
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#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT_UPDATE 0x1953
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#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP0_DP_MSE_LINK_TIMING 0x1954
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#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP0_DP_MSE_MISC_CNTL 0x1955
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#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x195a
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#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x195b
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#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT0_STATUS 0x195d
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#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT1_STATUS 0x195e
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#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT2_STATUS 0x195f
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#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
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|
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// addressBlock: dce_dc_dig1_dispdec
|
// base address: 0x400
|
#define mmDIG1_DIG_FE_CNTL 0x197e
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#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x197f
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#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1980
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#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG1_DIG_CLOCK_PATTERN 0x1981
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#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG1_DIG_TEST_PATTERN 0x1982
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#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1983
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#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG1_DIG_FIFO_STATUS 0x1984
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#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG1_HDMI_CONTROL 0x1987
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#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_STATUS 0x1988
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#define mmDIG1_HDMI_STATUS_BASE_IDX 2
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#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1989
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#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x198a
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#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x198b
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#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x198c
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#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x198d
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#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x198e
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG1_AFMT_INTERRUPT_STATUS 0x198f
|
#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG1_HDMI_GC 0x1991
|
#define mmDIG1_HDMI_GC_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1992
|
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC1_0 0x1993
|
#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC1_1 0x1994
|
#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC1_2 0x1995
|
#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC1_3 0x1996
|
#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC1_4 0x1997
|
#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC2_0 0x1998
|
#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC2_1 0x1999
|
#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC2_2 0x199a
|
#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC2_3 0x199b
|
#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG1_AFMT_AVI_INFO0 0x199c
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#define mmDIG1_AFMT_AVI_INFO0_BASE_IDX 2
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#define mmDIG1_AFMT_AVI_INFO1 0x199d
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#define mmDIG1_AFMT_AVI_INFO1_BASE_IDX 2
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#define mmDIG1_AFMT_AVI_INFO2 0x199e
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#define mmDIG1_AFMT_AVI_INFO2_BASE_IDX 2
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#define mmDIG1_AFMT_AVI_INFO3 0x199f
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#define mmDIG1_AFMT_AVI_INFO3_BASE_IDX 2
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#define mmDIG1_AFMT_MPEG_INFO0 0x19a0
|
#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG1_AFMT_MPEG_INFO1 0x19a1
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#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_HDR 0x19a2
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#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_0 0x19a3
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#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_1 0x19a4
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#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_2 0x19a5
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#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_3 0x19a6
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#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_4 0x19a7
|
#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_5 0x19a8
|
#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_6 0x19a9
|
#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_7 0x19aa
|
#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x19ab
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_32_0 0x19ac
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#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_32_1 0x19ad
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#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_44_0 0x19ae
|
#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_44_1 0x19af
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#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_48_0 0x19b0
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#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_48_1 0x19b1
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#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_STATUS_0 0x19b2
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#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_STATUS_1 0x19b3
|
#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_INFO0 0x19b4
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#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_INFO1 0x19b5
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#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG1_AFMT_60958_0 0x19b6
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#define mmDIG1_AFMT_60958_0_BASE_IDX 2
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#define mmDIG1_AFMT_60958_1 0x19b7
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#define mmDIG1_AFMT_60958_1_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x19b8
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#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG1_AFMT_RAMP_CONTROL0 0x19b9
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#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG1_AFMT_RAMP_CONTROL1 0x19ba
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#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG1_AFMT_RAMP_CONTROL2 0x19bb
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#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG1_AFMT_RAMP_CONTROL3 0x19bc
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#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG1_AFMT_60958_2 0x19bd
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#define mmDIG1_AFMT_60958_2_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x19be
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#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG1_AFMT_STATUS 0x19bf
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#define mmDIG1_AFMT_STATUS_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x19c0
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#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x19c1
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#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x19c2
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#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x19c3
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#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG1_DIG_BE_CNTL 0x19c5
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#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_BE_EN_CNTL 0x19c6
|
#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG1_TMDS_CNTL 0x19e9
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#define mmDIG1_TMDS_CNTL_BASE_IDX 2
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#define mmDIG1_TMDS_CONTROL_CHAR 0x19ea
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#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x19eb
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#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x19ec
|
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x19ed
|
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x19ee
|
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG1_TMDS_CTL_BITS 0x19f0
|
#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x19f1
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#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x19f3
|
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x19f4
|
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_VERSION 0x19f6
|
#define mmDIG1_DIG_VERSION_BASE_IDX 2
|
#define mmDIG1_DIG_LANE_ENABLE 0x19f7
|
#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG1_AFMT_CNTL 0x19fc
|
#define mmDIG1_AFMT_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dp1_dispdec
|
// base address: 0x400
|
#define mmDP1_DP_LINK_CNTL 0x1a1e
|
#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP1_DP_PIXEL_FORMAT 0x1a1f
|
#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP1_DP_MSA_COLORIMETRY 0x1a20
|
#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP1_DP_CONFIG 0x1a21
|
#define mmDP1_DP_CONFIG_BASE_IDX 2
|
#define mmDP1_DP_VID_STREAM_CNTL 0x1a22
|
#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP1_DP_STEER_FIFO 0x1a23
|
#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP1_DP_MSA_MISC 0x1a24
|
#define mmDP1_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP1_DP_VID_TIMING 0x1a26
|
#define mmDP1_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP1_DP_VID_N 0x1a27
|
#define mmDP1_DP_VID_N_BASE_IDX 2
|
#define mmDP1_DP_VID_M 0x1a28
|
#define mmDP1_DP_VID_M_BASE_IDX 2
|
#define mmDP1_DP_LINK_FRAMING_CNTL 0x1a29
|
#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP1_DP_HBR2_EYE_PATTERN 0x1a2a
|
#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP1_DP_VID_MSA_VBID 0x1a2b
|
#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1a2c
|
#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CNTL 0x1a2d
|
#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1a2e
|
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SYM0 0x1a2f
|
#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SYM1 0x1a30
|
#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SYM2 0x1a31
|
#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP1_DP_DPHY_8B10B_CNTL 0x1a32
|
#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_PRBS_CNTL 0x1a33
|
#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x1a34
|
#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_EN 0x1a35
|
#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_CNTL 0x1a36
|
#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_RESULT 0x1a37
|
#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1a38
|
#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1a39
|
#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP1_DP_DPHY_FAST_TRAINING 0x1a3a
|
#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1a3b
|
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1a3c
|
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
|
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1a3d
|
#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL 0x1a41
|
#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL1 0x1a42
|
#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING1 0x1a43
|
#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING2 0x1a44
|
#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING3 0x1a45
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#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP1_DP_SEC_FRAMING4 0x1a46
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#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_N 0x1a47
|
#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP1_DP_SEC_AUD_N_READBACK 0x1a48
|
#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP1_DP_SEC_AUD_M 0x1a49
|
#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP1_DP_SEC_AUD_M_READBACK 0x1a4a
|
#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP1_DP_SEC_TIMESTAMP 0x1a4b
|
#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP1_DP_SEC_PACKET_CNTL 0x1a4c
|
#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP1_DP_MSE_RATE_CNTL 0x1a4d
|
#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP1_DP_MSE_RATE_UPDATE 0x1a4f
|
#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT0 0x1a50
|
#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT1 0x1a51
|
#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT2 0x1a52
|
#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT_UPDATE 0x1a53
|
#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP1_DP_MSE_LINK_TIMING 0x1a54
|
#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP1_DP_MSE_MISC_CNTL 0x1a55
|
#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x1a5a
|
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x1a5b
|
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT0_STATUS 0x1a5d
|
#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT1_STATUS 0x1a5e
|
#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT2_STATUS 0x1a5f
|
#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dig2_dispdec
|
// base address: 0x800
|
#define mmDIG2_DIG_FE_CNTL 0x1a7e
|
#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x1a7f
|
#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x1a80
|
#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG2_DIG_CLOCK_PATTERN 0x1a81
|
#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG2_DIG_TEST_PATTERN 0x1a82
|
#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x1a83
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#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG2_DIG_FIFO_STATUS 0x1a84
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#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG2_HDMI_CONTROL 0x1a87
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#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_STATUS 0x1a88
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#define mmDIG2_HDMI_STATUS_BASE_IDX 2
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#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x1a89
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#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x1a8a
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#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x1a8b
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#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x1a8c
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#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x1a8d
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#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x1a8e
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG2_AFMT_INTERRUPT_STATUS 0x1a8f
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#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG2_HDMI_GC 0x1a91
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#define mmDIG2_HDMI_GC_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x1a92
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#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_0 0x1a93
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#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_1 0x1a94
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#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_2 0x1a95
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#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_3 0x1a96
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#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_4 0x1a97
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#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC2_0 0x1a98
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#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC2_1 0x1a99
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#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC2_2 0x1a9a
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#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC2_3 0x1a9b
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#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG2_AFMT_AVI_INFO0 0x1a9c
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#define mmDIG2_AFMT_AVI_INFO0_BASE_IDX 2
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#define mmDIG2_AFMT_AVI_INFO1 0x1a9d
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#define mmDIG2_AFMT_AVI_INFO1_BASE_IDX 2
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#define mmDIG2_AFMT_AVI_INFO2 0x1a9e
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#define mmDIG2_AFMT_AVI_INFO2_BASE_IDX 2
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#define mmDIG2_AFMT_AVI_INFO3 0x1a9f
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#define mmDIG2_AFMT_AVI_INFO3_BASE_IDX 2
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#define mmDIG2_AFMT_MPEG_INFO0 0x1aa0
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#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG2_AFMT_MPEG_INFO1 0x1aa1
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#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_HDR 0x1aa2
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#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_0 0x1aa3
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#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_1 0x1aa4
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#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_2 0x1aa5
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#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_3 0x1aa6
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#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_4 0x1aa7
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#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_5 0x1aa8
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#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_6 0x1aa9
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#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_7 0x1aaa
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#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x1aab
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_32_0 0x1aac
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#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_32_1 0x1aad
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#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_44_0 0x1aae
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#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_44_1 0x1aaf
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#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_48_0 0x1ab0
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#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_48_1 0x1ab1
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#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_STATUS_0 0x1ab2
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#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_STATUS_1 0x1ab3
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#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_INFO0 0x1ab4
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#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_INFO1 0x1ab5
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#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG2_AFMT_60958_0 0x1ab6
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#define mmDIG2_AFMT_60958_0_BASE_IDX 2
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#define mmDIG2_AFMT_60958_1 0x1ab7
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#define mmDIG2_AFMT_60958_1_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x1ab8
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#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG2_AFMT_RAMP_CONTROL0 0x1ab9
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#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG2_AFMT_RAMP_CONTROL1 0x1aba
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#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG2_AFMT_RAMP_CONTROL2 0x1abb
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#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG2_AFMT_RAMP_CONTROL3 0x1abc
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#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG2_AFMT_60958_2 0x1abd
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#define mmDIG2_AFMT_60958_2_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x1abe
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#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG2_AFMT_STATUS 0x1abf
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#define mmDIG2_AFMT_STATUS_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x1ac0
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#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x1ac1
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#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x1ac2
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#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x1ac3
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#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG2_DIG_BE_CNTL 0x1ac5
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#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_BE_EN_CNTL 0x1ac6
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#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CNTL 0x1ae9
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#define mmDIG2_TMDS_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CONTROL_CHAR 0x1aea
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#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x1aeb
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#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x1aec
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#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x1aed
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x1aee
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG2_TMDS_CTL_BITS 0x1af0
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#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x1af1
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#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x1af3
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#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x1af4
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#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_VERSION 0x1af6
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#define mmDIG2_DIG_VERSION_BASE_IDX 2
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#define mmDIG2_DIG_LANE_ENABLE 0x1af7
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#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG2_AFMT_CNTL 0x1afc
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#define mmDIG2_AFMT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dp2_dispdec
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// base address: 0x800
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#define mmDP2_DP_LINK_CNTL 0x1b1e
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#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP2_DP_PIXEL_FORMAT 0x1b1f
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#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP2_DP_MSA_COLORIMETRY 0x1b20
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#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP2_DP_CONFIG 0x1b21
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#define mmDP2_DP_CONFIG_BASE_IDX 2
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#define mmDP2_DP_VID_STREAM_CNTL 0x1b22
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#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP2_DP_STEER_FIFO 0x1b23
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#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP2_DP_MSA_MISC 0x1b24
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#define mmDP2_DP_MSA_MISC_BASE_IDX 2
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#define mmDP2_DP_VID_TIMING 0x1b26
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#define mmDP2_DP_VID_TIMING_BASE_IDX 2
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#define mmDP2_DP_VID_N 0x1b27
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#define mmDP2_DP_VID_N_BASE_IDX 2
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#define mmDP2_DP_VID_M 0x1b28
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#define mmDP2_DP_VID_M_BASE_IDX 2
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#define mmDP2_DP_LINK_FRAMING_CNTL 0x1b29
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#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP2_DP_HBR2_EYE_PATTERN 0x1b2a
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#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP2_DP_VID_MSA_VBID 0x1b2b
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#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP2_DP_VID_INTERRUPT_CNTL 0x1b2c
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#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CNTL 0x1b2d
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#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x1b2e
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#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM0 0x1b2f
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#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM1 0x1b30
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#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM2 0x1b31
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#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP2_DP_DPHY_8B10B_CNTL 0x1b32
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#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_PRBS_CNTL 0x1b33
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#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_SCRAM_CNTL 0x1b34
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#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_EN 0x1b35
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#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_CNTL 0x1b36
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#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_RESULT 0x1b37
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#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x1b38
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#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x1b39
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#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP2_DP_DPHY_FAST_TRAINING 0x1b3a
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#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x1b3b
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#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x1b3c
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#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
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#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x1b3d
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#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL 0x1b41
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#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL1 0x1b42
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#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING1 0x1b43
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#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING2 0x1b44
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#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING3 0x1b45
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#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING4 0x1b46
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#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_N 0x1b47
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#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_N_READBACK 0x1b48
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#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_M 0x1b49
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#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_M_READBACK 0x1b4a
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#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP2_DP_SEC_TIMESTAMP 0x1b4b
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#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP2_DP_SEC_PACKET_CNTL 0x1b4c
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#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSE_RATE_CNTL 0x1b4d
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#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSE_RATE_UPDATE 0x1b4f
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#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT0 0x1b50
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#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT1 0x1b51
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#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT2 0x1b52
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#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT_UPDATE 0x1b53
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#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP2_DP_MSE_LINK_TIMING 0x1b54
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#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP2_DP_MSE_MISC_CNTL 0x1b55
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#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x1b5a
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#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x1b5b
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#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT0_STATUS 0x1b5d
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#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT1_STATUS 0x1b5e
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#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT2_STATUS 0x1b5f
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#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dig3_dispdec
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// base address: 0xc00
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#define mmDIG3_DIG_FE_CNTL 0x1b7e
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#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x1b7f
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#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x1b80
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#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG3_DIG_CLOCK_PATTERN 0x1b81
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#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG3_DIG_TEST_PATTERN 0x1b82
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#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x1b83
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#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG3_DIG_FIFO_STATUS 0x1b84
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#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG3_HDMI_CONTROL 0x1b87
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#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_STATUS 0x1b88
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#define mmDIG3_HDMI_STATUS_BASE_IDX 2
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#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x1b89
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#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x1b8a
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#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x1b8b
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#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x1b8c
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#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x1b8d
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#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x1b8e
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG3_AFMT_INTERRUPT_STATUS 0x1b8f
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#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG3_HDMI_GC 0x1b91
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#define mmDIG3_HDMI_GC_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x1b92
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#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_0 0x1b93
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#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_1 0x1b94
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#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_2 0x1b95
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#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_3 0x1b96
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#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_4 0x1b97
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#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC2_0 0x1b98
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#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC2_1 0x1b99
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#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC2_2 0x1b9a
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#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC2_3 0x1b9b
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#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG3_AFMT_AVI_INFO0 0x1b9c
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#define mmDIG3_AFMT_AVI_INFO0_BASE_IDX 2
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#define mmDIG3_AFMT_AVI_INFO1 0x1b9d
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#define mmDIG3_AFMT_AVI_INFO1_BASE_IDX 2
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#define mmDIG3_AFMT_AVI_INFO2 0x1b9e
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#define mmDIG3_AFMT_AVI_INFO2_BASE_IDX 2
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#define mmDIG3_AFMT_AVI_INFO3 0x1b9f
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#define mmDIG3_AFMT_AVI_INFO3_BASE_IDX 2
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#define mmDIG3_AFMT_MPEG_INFO0 0x1ba0
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#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG3_AFMT_MPEG_INFO1 0x1ba1
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#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_HDR 0x1ba2
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#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_0 0x1ba3
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#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_1 0x1ba4
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#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_2 0x1ba5
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#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_3 0x1ba6
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#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_4 0x1ba7
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#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_5 0x1ba8
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#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_6 0x1ba9
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#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_7 0x1baa
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#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x1bab
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_32_0 0x1bac
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#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_32_1 0x1bad
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#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_44_0 0x1bae
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#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_44_1 0x1baf
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#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_48_0 0x1bb0
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#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_48_1 0x1bb1
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#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_STATUS_0 0x1bb2
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#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_STATUS_1 0x1bb3
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#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_INFO0 0x1bb4
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#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_INFO1 0x1bb5
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#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG3_AFMT_60958_0 0x1bb6
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#define mmDIG3_AFMT_60958_0_BASE_IDX 2
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#define mmDIG3_AFMT_60958_1 0x1bb7
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#define mmDIG3_AFMT_60958_1_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x1bb8
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#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG3_AFMT_RAMP_CONTROL0 0x1bb9
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#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG3_AFMT_RAMP_CONTROL1 0x1bba
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#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG3_AFMT_RAMP_CONTROL2 0x1bbb
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#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG3_AFMT_RAMP_CONTROL3 0x1bbc
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#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG3_AFMT_60958_2 0x1bbd
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#define mmDIG3_AFMT_60958_2_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x1bbe
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#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG3_AFMT_STATUS 0x1bbf
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#define mmDIG3_AFMT_STATUS_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x1bc0
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#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x1bc1
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#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x1bc2
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#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x1bc3
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#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG3_DIG_BE_CNTL 0x1bc5
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#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_BE_EN_CNTL 0x1bc6
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#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CNTL 0x1be9
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#define mmDIG3_TMDS_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CONTROL_CHAR 0x1bea
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#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x1beb
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#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x1bec
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#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x1bed
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x1bee
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG3_TMDS_CTL_BITS 0x1bf0
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#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x1bf1
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#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x1bf3
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#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x1bf4
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#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_VERSION 0x1bf6
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#define mmDIG3_DIG_VERSION_BASE_IDX 2
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#define mmDIG3_DIG_LANE_ENABLE 0x1bf7
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#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG3_AFMT_CNTL 0x1bfc
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#define mmDIG3_AFMT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dp3_dispdec
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// base address: 0xc00
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#define mmDP3_DP_LINK_CNTL 0x1c1e
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#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP3_DP_PIXEL_FORMAT 0x1c1f
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#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP3_DP_MSA_COLORIMETRY 0x1c20
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#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP3_DP_CONFIG 0x1c21
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#define mmDP3_DP_CONFIG_BASE_IDX 2
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#define mmDP3_DP_VID_STREAM_CNTL 0x1c22
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#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP3_DP_STEER_FIFO 0x1c23
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#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP3_DP_MSA_MISC 0x1c24
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#define mmDP3_DP_MSA_MISC_BASE_IDX 2
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#define mmDP3_DP_VID_TIMING 0x1c26
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#define mmDP3_DP_VID_TIMING_BASE_IDX 2
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#define mmDP3_DP_VID_N 0x1c27
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#define mmDP3_DP_VID_N_BASE_IDX 2
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#define mmDP3_DP_VID_M 0x1c28
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#define mmDP3_DP_VID_M_BASE_IDX 2
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#define mmDP3_DP_LINK_FRAMING_CNTL 0x1c29
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#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP3_DP_HBR2_EYE_PATTERN 0x1c2a
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#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP3_DP_VID_MSA_VBID 0x1c2b
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#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP3_DP_VID_INTERRUPT_CNTL 0x1c2c
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#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CNTL 0x1c2d
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#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x1c2e
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#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM0 0x1c2f
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#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM1 0x1c30
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#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM2 0x1c31
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#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP3_DP_DPHY_8B10B_CNTL 0x1c32
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#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_PRBS_CNTL 0x1c33
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#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_SCRAM_CNTL 0x1c34
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#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_EN 0x1c35
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#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_CNTL 0x1c36
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#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_RESULT 0x1c37
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#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x1c38
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#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x1c39
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#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP3_DP_DPHY_FAST_TRAINING 0x1c3a
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#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x1c3b
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#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x1c3c
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#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
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#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x1c3d
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#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL 0x1c41
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#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL1 0x1c42
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#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING1 0x1c43
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#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING2 0x1c44
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#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING3 0x1c45
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#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING4 0x1c46
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#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_N 0x1c47
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#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_N_READBACK 0x1c48
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#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_M 0x1c49
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#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_M_READBACK 0x1c4a
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#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP3_DP_SEC_TIMESTAMP 0x1c4b
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#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP3_DP_SEC_PACKET_CNTL 0x1c4c
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#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSE_RATE_CNTL 0x1c4d
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#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSE_RATE_UPDATE 0x1c4f
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#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT0 0x1c50
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#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT1 0x1c51
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#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT2 0x1c52
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#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT_UPDATE 0x1c53
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#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP3_DP_MSE_LINK_TIMING 0x1c54
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#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP3_DP_MSE_MISC_CNTL 0x1c55
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#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x1c5a
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#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x1c5b
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#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT0_STATUS 0x1c5d
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#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT1_STATUS 0x1c5e
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#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT2_STATUS 0x1c5f
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#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dig4_dispdec
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// base address: 0x1000
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#define mmDIG4_DIG_FE_CNTL 0x1c7e
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#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x1c7f
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#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x1c80
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#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG4_DIG_CLOCK_PATTERN 0x1c81
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#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG4_DIG_TEST_PATTERN 0x1c82
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#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x1c83
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#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG4_DIG_FIFO_STATUS 0x1c84
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#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG4_HDMI_CONTROL 0x1c87
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#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_STATUS 0x1c88
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#define mmDIG4_HDMI_STATUS_BASE_IDX 2
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#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x1c89
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#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x1c8a
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#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x1c8b
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#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x1c8c
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#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x1c8d
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#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x1c8e
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG4_AFMT_INTERRUPT_STATUS 0x1c8f
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#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG4_HDMI_GC 0x1c91
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#define mmDIG4_HDMI_GC_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x1c92
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#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_0 0x1c93
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#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_1 0x1c94
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#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_2 0x1c95
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#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_3 0x1c96
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#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_4 0x1c97
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#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC2_0 0x1c98
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#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC2_1 0x1c99
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#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC2_2 0x1c9a
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#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC2_3 0x1c9b
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#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG4_AFMT_AVI_INFO0 0x1c9c
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#define mmDIG4_AFMT_AVI_INFO0_BASE_IDX 2
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#define mmDIG4_AFMT_AVI_INFO1 0x1c9d
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#define mmDIG4_AFMT_AVI_INFO1_BASE_IDX 2
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#define mmDIG4_AFMT_AVI_INFO2 0x1c9e
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#define mmDIG4_AFMT_AVI_INFO2_BASE_IDX 2
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#define mmDIG4_AFMT_AVI_INFO3 0x1c9f
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#define mmDIG4_AFMT_AVI_INFO3_BASE_IDX 2
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#define mmDIG4_AFMT_MPEG_INFO0 0x1ca0
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#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG4_AFMT_MPEG_INFO1 0x1ca1
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#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_HDR 0x1ca2
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#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_0 0x1ca3
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#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_1 0x1ca4
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#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_2 0x1ca5
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#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_3 0x1ca6
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#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_4 0x1ca7
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#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_5 0x1ca8
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#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_6 0x1ca9
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#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_7 0x1caa
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#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x1cab
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_32_0 0x1cac
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#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_32_1 0x1cad
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#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_44_0 0x1cae
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#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_44_1 0x1caf
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#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_48_0 0x1cb0
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#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_48_1 0x1cb1
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#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_STATUS_0 0x1cb2
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#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_STATUS_1 0x1cb3
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#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_INFO0 0x1cb4
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#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_INFO1 0x1cb5
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#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG4_AFMT_60958_0 0x1cb6
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#define mmDIG4_AFMT_60958_0_BASE_IDX 2
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#define mmDIG4_AFMT_60958_1 0x1cb7
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#define mmDIG4_AFMT_60958_1_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x1cb8
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#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG4_AFMT_RAMP_CONTROL0 0x1cb9
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#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG4_AFMT_RAMP_CONTROL1 0x1cba
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#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG4_AFMT_RAMP_CONTROL2 0x1cbb
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#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG4_AFMT_RAMP_CONTROL3 0x1cbc
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#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG4_AFMT_60958_2 0x1cbd
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#define mmDIG4_AFMT_60958_2_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x1cbe
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#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG4_AFMT_STATUS 0x1cbf
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#define mmDIG4_AFMT_STATUS_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x1cc0
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#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x1cc1
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#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x1cc2
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#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x1cc3
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#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG4_DIG_BE_CNTL 0x1cc5
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#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_BE_EN_CNTL 0x1cc6
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#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CNTL 0x1ce9
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#define mmDIG4_TMDS_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CONTROL_CHAR 0x1cea
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#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x1ceb
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#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x1cec
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#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ced
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x1cee
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG4_TMDS_CTL_BITS 0x1cf0
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#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x1cf1
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#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x1cf3
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#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x1cf4
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#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_VERSION 0x1cf6
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#define mmDIG4_DIG_VERSION_BASE_IDX 2
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#define mmDIG4_DIG_LANE_ENABLE 0x1cf7
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#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG4_AFMT_CNTL 0x1cfc
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#define mmDIG4_AFMT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dp4_dispdec
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// base address: 0x1000
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#define mmDP4_DP_LINK_CNTL 0x1d1e
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#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP4_DP_PIXEL_FORMAT 0x1d1f
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#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP4_DP_MSA_COLORIMETRY 0x1d20
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#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP4_DP_CONFIG 0x1d21
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#define mmDP4_DP_CONFIG_BASE_IDX 2
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#define mmDP4_DP_VID_STREAM_CNTL 0x1d22
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#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP4_DP_STEER_FIFO 0x1d23
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#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP4_DP_MSA_MISC 0x1d24
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#define mmDP4_DP_MSA_MISC_BASE_IDX 2
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#define mmDP4_DP_VID_TIMING 0x1d26
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#define mmDP4_DP_VID_TIMING_BASE_IDX 2
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#define mmDP4_DP_VID_N 0x1d27
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#define mmDP4_DP_VID_N_BASE_IDX 2
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#define mmDP4_DP_VID_M 0x1d28
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#define mmDP4_DP_VID_M_BASE_IDX 2
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#define mmDP4_DP_LINK_FRAMING_CNTL 0x1d29
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#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP4_DP_HBR2_EYE_PATTERN 0x1d2a
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#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP4_DP_VID_MSA_VBID 0x1d2b
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#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP4_DP_VID_INTERRUPT_CNTL 0x1d2c
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#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CNTL 0x1d2d
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#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x1d2e
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#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM0 0x1d2f
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#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM1 0x1d30
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#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM2 0x1d31
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#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP4_DP_DPHY_8B10B_CNTL 0x1d32
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#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_PRBS_CNTL 0x1d33
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#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_SCRAM_CNTL 0x1d34
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#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_EN 0x1d35
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#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_CNTL 0x1d36
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#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_RESULT 0x1d37
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#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x1d38
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#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x1d39
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#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP4_DP_DPHY_FAST_TRAINING 0x1d3a
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#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x1d3b
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#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x1d3c
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#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
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#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x1d3d
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#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL 0x1d41
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#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL1 0x1d42
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#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING1 0x1d43
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#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING2 0x1d44
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#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING3 0x1d45
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#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING4 0x1d46
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#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_N 0x1d47
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#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_N_READBACK 0x1d48
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#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_M 0x1d49
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#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_M_READBACK 0x1d4a
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#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP4_DP_SEC_TIMESTAMP 0x1d4b
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#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP4_DP_SEC_PACKET_CNTL 0x1d4c
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#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSE_RATE_CNTL 0x1d4d
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#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSE_RATE_UPDATE 0x1d4f
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#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT0 0x1d50
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#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT1 0x1d51
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#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT2 0x1d52
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#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT_UPDATE 0x1d53
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#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP4_DP_MSE_LINK_TIMING 0x1d54
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#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP4_DP_MSE_MISC_CNTL 0x1d55
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#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x1d5a
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#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x1d5b
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#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT0_STATUS 0x1d5d
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#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT1_STATUS 0x1d5e
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#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT2_STATUS 0x1d5f
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#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dig5_dispdec
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// base address: 0x1400
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#define mmDIG5_DIG_FE_CNTL 0x1d7e
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#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x1d7f
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#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x1d80
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#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG5_DIG_CLOCK_PATTERN 0x1d81
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#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG5_DIG_TEST_PATTERN 0x1d82
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#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x1d83
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#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG5_DIG_FIFO_STATUS 0x1d84
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#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG5_HDMI_CONTROL 0x1d87
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#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG5_HDMI_STATUS 0x1d88
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#define mmDIG5_HDMI_STATUS_BASE_IDX 2
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#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x1d89
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#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x1d8a
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#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x1d8b
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#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x1d8c
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#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x1d8d
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#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x1d8e
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#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG5_AFMT_INTERRUPT_STATUS 0x1d8f
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#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG5_HDMI_GC 0x1d91
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#define mmDIG5_HDMI_GC_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x1d92
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#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC1_0 0x1d93
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#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC1_1 0x1d94
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#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC1_2 0x1d95
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#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC1_3 0x1d96
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#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC1_4 0x1d97
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#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC2_0 0x1d98
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#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC2_1 0x1d99
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#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC2_2 0x1d9a
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#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG5_AFMT_ISRC2_3 0x1d9b
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#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG5_AFMT_AVI_INFO0 0x1d9c
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#define mmDIG5_AFMT_AVI_INFO0_BASE_IDX 2
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#define mmDIG5_AFMT_AVI_INFO1 0x1d9d
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#define mmDIG5_AFMT_AVI_INFO1_BASE_IDX 2
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#define mmDIG5_AFMT_AVI_INFO2 0x1d9e
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#define mmDIG5_AFMT_AVI_INFO2_BASE_IDX 2
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#define mmDIG5_AFMT_AVI_INFO3 0x1d9f
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#define mmDIG5_AFMT_AVI_INFO3_BASE_IDX 2
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#define mmDIG5_AFMT_MPEG_INFO0 0x1da0
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#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG5_AFMT_MPEG_INFO1 0x1da1
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#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_HDR 0x1da2
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#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_0 0x1da3
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#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_1 0x1da4
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#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_2 0x1da5
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#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_3 0x1da6
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#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_4 0x1da7
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#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_5 0x1da8
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#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_6 0x1da9
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#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG5_AFMT_GENERIC_7 0x1daa
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#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x1dab
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#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_32_0 0x1dac
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#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_32_1 0x1dad
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#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_44_0 0x1dae
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#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_44_1 0x1daf
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#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_48_0 0x1db0
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#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_48_1 0x1db1
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#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_STATUS_0 0x1db2
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#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_STATUS_1 0x1db3
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#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_INFO0 0x1db4
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#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_INFO1 0x1db5
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#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG5_AFMT_60958_0 0x1db6
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#define mmDIG5_AFMT_60958_0_BASE_IDX 2
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#define mmDIG5_AFMT_60958_1 0x1db7
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#define mmDIG5_AFMT_60958_1_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x1db8
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#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG5_AFMT_RAMP_CONTROL0 0x1db9
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#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG5_AFMT_RAMP_CONTROL1 0x1dba
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#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG5_AFMT_RAMP_CONTROL2 0x1dbb
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#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG5_AFMT_RAMP_CONTROL3 0x1dbc
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#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG5_AFMT_60958_2 0x1dbd
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#define mmDIG5_AFMT_60958_2_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x1dbe
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#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG5_AFMT_STATUS 0x1dbf
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#define mmDIG5_AFMT_STATUS_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x1dc0
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#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x1dc1
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#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x1dc2
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#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x1dc3
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#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG5_DIG_BE_CNTL 0x1dc5
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#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG5_DIG_BE_EN_CNTL 0x1dc6
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#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG5_TMDS_CNTL 0x1de9
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#define mmDIG5_TMDS_CNTL_BASE_IDX 2
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#define mmDIG5_TMDS_CONTROL_CHAR 0x1dea
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#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x1deb
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#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x1dec
|
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x1ded
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#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x1dee
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#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG5_TMDS_CTL_BITS 0x1df0
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#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x1df1
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#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x1df3
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#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x1df4
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#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG5_DIG_VERSION 0x1df6
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#define mmDIG5_DIG_VERSION_BASE_IDX 2
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#define mmDIG5_DIG_LANE_ENABLE 0x1df7
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#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG5_AFMT_CNTL 0x1dfc
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#define mmDIG5_AFMT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dp5_dispdec
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// base address: 0x1400
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#define mmDP5_DP_LINK_CNTL 0x1e1e
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#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP5_DP_PIXEL_FORMAT 0x1e1f
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#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP5_DP_MSA_COLORIMETRY 0x1e20
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#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP5_DP_CONFIG 0x1e21
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#define mmDP5_DP_CONFIG_BASE_IDX 2
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#define mmDP5_DP_VID_STREAM_CNTL 0x1e22
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#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP5_DP_STEER_FIFO 0x1e23
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#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP5_DP_MSA_MISC 0x1e24
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#define mmDP5_DP_MSA_MISC_BASE_IDX 2
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#define mmDP5_DP_VID_TIMING 0x1e26
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#define mmDP5_DP_VID_TIMING_BASE_IDX 2
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#define mmDP5_DP_VID_N 0x1e27
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#define mmDP5_DP_VID_N_BASE_IDX 2
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#define mmDP5_DP_VID_M 0x1e28
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#define mmDP5_DP_VID_M_BASE_IDX 2
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#define mmDP5_DP_LINK_FRAMING_CNTL 0x1e29
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#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP5_DP_HBR2_EYE_PATTERN 0x1e2a
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#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP5_DP_VID_MSA_VBID 0x1e2b
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#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP5_DP_VID_INTERRUPT_CNTL 0x1e2c
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#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_CNTL 0x1e2d
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#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x1e2e
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#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP5_DP_DPHY_SYM0 0x1e2f
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#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP5_DP_DPHY_SYM1 0x1e30
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#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP5_DP_DPHY_SYM2 0x1e31
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#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP5_DP_DPHY_8B10B_CNTL 0x1e32
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#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_PRBS_CNTL 0x1e33
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#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_SCRAM_CNTL 0x1e34
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#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_CRC_EN 0x1e35
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#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP5_DP_DPHY_CRC_CNTL 0x1e36
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#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_CRC_RESULT 0x1e37
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#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x1e38
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#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x1e39
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#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP5_DP_DPHY_FAST_TRAINING 0x1e3a
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#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x1e3b
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#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x1e3c
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#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
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#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x1e3d
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#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
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#define mmDP5_DP_SEC_CNTL 0x1e41
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#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP5_DP_SEC_CNTL1 0x1e42
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#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP5_DP_SEC_FRAMING1 0x1e43
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#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP5_DP_SEC_FRAMING2 0x1e44
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#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP5_DP_SEC_FRAMING3 0x1e45
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#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP5_DP_SEC_FRAMING4 0x1e46
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#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP5_DP_SEC_AUD_N 0x1e47
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#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP5_DP_SEC_AUD_N_READBACK 0x1e48
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#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP5_DP_SEC_AUD_M 0x1e49
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#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP5_DP_SEC_AUD_M_READBACK 0x1e4a
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#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP5_DP_SEC_TIMESTAMP 0x1e4b
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#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP5_DP_SEC_PACKET_CNTL 0x1e4c
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#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP5_DP_MSE_RATE_CNTL 0x1e4d
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#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP5_DP_MSE_RATE_UPDATE 0x1e4f
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#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT0 0x1e50
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#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT1 0x1e51
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#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT2 0x1e52
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#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT_UPDATE 0x1e53
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#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP5_DP_MSE_LINK_TIMING 0x1e54
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#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP5_DP_MSE_MISC_CNTL 0x1e55
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#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x1e5a
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#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x1e5b
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#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT0_STATUS 0x1e5d
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#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT1_STATUS 0x1e5e
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#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT2_STATUS 0x1e5f
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#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dig6_dispdec
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// base address: 0x1800
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#define mmDIG6_DIG_FE_CNTL 0x1e7e
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#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x1e7f
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#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x1e80
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#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG6_DIG_CLOCK_PATTERN 0x1e81
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#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG6_DIG_TEST_PATTERN 0x1e82
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#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x1e83
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#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG6_DIG_FIFO_STATUS 0x1e84
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#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG6_HDMI_CONTROL 0x1e87
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#define mmDIG6_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG6_HDMI_STATUS 0x1e88
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#define mmDIG6_HDMI_STATUS_BASE_IDX 2
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#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x1e89
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#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x1e8a
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#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x1e8b
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#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x1e8c
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#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x1e8d
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#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x1e8e
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#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG6_AFMT_INTERRUPT_STATUS 0x1e8f
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#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG6_HDMI_GC 0x1e91
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#define mmDIG6_HDMI_GC_BASE_IDX 2
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#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x1e92
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#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC1_0 0x1e93
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#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC1_1 0x1e94
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#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC1_2 0x1e95
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#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC1_3 0x1e96
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#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC1_4 0x1e97
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#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC2_0 0x1e98
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#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC2_1 0x1e99
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#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC2_2 0x1e9a
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#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG6_AFMT_ISRC2_3 0x1e9b
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#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG6_AFMT_AVI_INFO0 0x1e9c
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#define mmDIG6_AFMT_AVI_INFO0_BASE_IDX 2
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#define mmDIG6_AFMT_AVI_INFO1 0x1e9d
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#define mmDIG6_AFMT_AVI_INFO1_BASE_IDX 2
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#define mmDIG6_AFMT_AVI_INFO2 0x1e9e
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#define mmDIG6_AFMT_AVI_INFO2_BASE_IDX 2
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#define mmDIG6_AFMT_AVI_INFO3 0x1e9f
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#define mmDIG6_AFMT_AVI_INFO3_BASE_IDX 2
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#define mmDIG6_AFMT_MPEG_INFO0 0x1ea0
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#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG6_AFMT_MPEG_INFO1 0x1ea1
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#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_HDR 0x1ea2
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#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_0 0x1ea3
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#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_1 0x1ea4
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#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_2 0x1ea5
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#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_3 0x1ea6
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#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_4 0x1ea7
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#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_5 0x1ea8
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#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_6 0x1ea9
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#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG6_AFMT_GENERIC_7 0x1eaa
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#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x1eab
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#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_32_0 0x1eac
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#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_32_1 0x1ead
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#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_44_0 0x1eae
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#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_44_1 0x1eaf
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#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_48_0 0x1eb0
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#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_48_1 0x1eb1
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#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_STATUS_0 0x1eb2
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#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG6_HDMI_ACR_STATUS_1 0x1eb3
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#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG6_AFMT_AUDIO_INFO0 0x1eb4
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#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG6_AFMT_AUDIO_INFO1 0x1eb5
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#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG6_AFMT_60958_0 0x1eb6
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#define mmDIG6_AFMT_60958_0_BASE_IDX 2
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#define mmDIG6_AFMT_60958_1 0x1eb7
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#define mmDIG6_AFMT_60958_1_BASE_IDX 2
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#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x1eb8
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#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG6_AFMT_RAMP_CONTROL0 0x1eb9
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#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG6_AFMT_RAMP_CONTROL1 0x1eba
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#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG6_AFMT_RAMP_CONTROL2 0x1ebb
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#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG6_AFMT_RAMP_CONTROL3 0x1ebc
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#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG6_AFMT_60958_2 0x1ebd
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#define mmDIG6_AFMT_60958_2_BASE_IDX 2
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#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x1ebe
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#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG6_AFMT_STATUS 0x1ebf
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#define mmDIG6_AFMT_STATUS_BASE_IDX 2
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#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x1ec0
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#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x1ec1
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#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x1ec2
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#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x1ec3
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#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG6_DIG_BE_CNTL 0x1ec5
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#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG6_DIG_BE_EN_CNTL 0x1ec6
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#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG6_TMDS_CNTL 0x1ee9
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#define mmDIG6_TMDS_CNTL_BASE_IDX 2
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#define mmDIG6_TMDS_CONTROL_CHAR 0x1eea
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#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x1eeb
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#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x1eec
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#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x1eed
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#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x1eee
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#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG6_TMDS_CTL_BITS 0x1ef0
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#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x1ef1
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#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x1ef3
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#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x1ef4
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#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG6_DIG_VERSION 0x1ef6
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#define mmDIG6_DIG_VERSION_BASE_IDX 2
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#define mmDIG6_DIG_LANE_ENABLE 0x1ef7
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#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG6_AFMT_CNTL 0x1efc
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#define mmDIG6_AFMT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dp6_dispdec
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// base address: 0x1800
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#define mmDP6_DP_LINK_CNTL 0x1f1e
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#define mmDP6_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP6_DP_PIXEL_FORMAT 0x1f1f
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#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP6_DP_MSA_COLORIMETRY 0x1f20
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#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP6_DP_CONFIG 0x1f21
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#define mmDP6_DP_CONFIG_BASE_IDX 2
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#define mmDP6_DP_VID_STREAM_CNTL 0x1f22
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#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP6_DP_STEER_FIFO 0x1f23
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#define mmDP6_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP6_DP_MSA_MISC 0x1f24
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#define mmDP6_DP_MSA_MISC_BASE_IDX 2
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#define mmDP6_DP_VID_TIMING 0x1f26
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#define mmDP6_DP_VID_TIMING_BASE_IDX 2
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#define mmDP6_DP_VID_N 0x1f27
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#define mmDP6_DP_VID_N_BASE_IDX 2
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#define mmDP6_DP_VID_M 0x1f28
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#define mmDP6_DP_VID_M_BASE_IDX 2
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#define mmDP6_DP_LINK_FRAMING_CNTL 0x1f29
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#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP6_DP_HBR2_EYE_PATTERN 0x1f2a
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#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP6_DP_VID_MSA_VBID 0x1f2b
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#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP6_DP_VID_INTERRUPT_CNTL 0x1f2c
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#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_CNTL 0x1f2d
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#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x1f2e
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#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP6_DP_DPHY_SYM0 0x1f2f
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#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP6_DP_DPHY_SYM1 0x1f30
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#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP6_DP_DPHY_SYM2 0x1f31
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#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP6_DP_DPHY_8B10B_CNTL 0x1f32
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#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_PRBS_CNTL 0x1f33
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#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_SCRAM_CNTL 0x1f34
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#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_CRC_EN 0x1f35
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#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP6_DP_DPHY_CRC_CNTL 0x1f36
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#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_CRC_RESULT 0x1f37
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#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x1f38
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#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x1f39
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#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP6_DP_DPHY_FAST_TRAINING 0x1f3a
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#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x1f3b
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#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x1f3c
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#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_BASE_IDX 2
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#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x1f3d
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#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_BASE_IDX 2
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#define mmDP6_DP_SEC_CNTL 0x1f41
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#define mmDP6_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP6_DP_SEC_CNTL1 0x1f42
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#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP6_DP_SEC_FRAMING1 0x1f43
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#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP6_DP_SEC_FRAMING2 0x1f44
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#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP6_DP_SEC_FRAMING3 0x1f45
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#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP6_DP_SEC_FRAMING4 0x1f46
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#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP6_DP_SEC_AUD_N 0x1f47
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#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP6_DP_SEC_AUD_N_READBACK 0x1f48
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#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP6_DP_SEC_AUD_M 0x1f49
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#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP6_DP_SEC_AUD_M_READBACK 0x1f4a
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#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP6_DP_SEC_TIMESTAMP 0x1f4b
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#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP6_DP_SEC_PACKET_CNTL 0x1f4c
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#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP6_DP_MSE_RATE_CNTL 0x1f4d
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#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP6_DP_MSE_RATE_UPDATE 0x1f4f
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#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP6_DP_MSE_SAT0 0x1f50
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#define mmDP6_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP6_DP_MSE_SAT1 0x1f51
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#define mmDP6_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP6_DP_MSE_SAT2 0x1f52
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#define mmDP6_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP6_DP_MSE_SAT_UPDATE 0x1f53
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#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP6_DP_MSE_LINK_TIMING 0x1f54
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#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP6_DP_MSE_MISC_CNTL 0x1f55
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#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x1f5a
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#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x1f5b
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#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP6_DP_MSE_SAT0_STATUS 0x1f5d
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#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP6_DP_MSE_SAT1_STATUS 0x1f5e
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#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP6_DP_MSE_SAT2_STATUS 0x1f5f
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#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcio_uniphy0_dispdec
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// base address: 0x0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x213e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x213f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x2140
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x2141
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x2142
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x2143
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x2144
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x2145
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2146
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2147
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2148
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2149
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x214a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x214b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x214c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x214d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x214e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x214f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x2150
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x2151
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x2152
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x2153
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x2154
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x2155
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2156
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2157
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2158
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2159
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x215a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x215b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x215c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x215d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x215e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x215f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x2160
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x2161
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x2162
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x2163
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x2164
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x2165
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2166
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2167
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2168
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2169
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x216a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x216b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x216c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x216d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x216e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x216f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x2170
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x2171
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x2172
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x2173
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x2174
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x2175
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2176
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2177
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2178
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2179
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x217a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x217b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x217c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x217d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x217e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x217f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x2180
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x2181
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x2182
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x2183
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x2184
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x2185
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2186
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2187
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2188
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2189
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x218a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x218b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x218c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x218d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x218e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x218f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x2190
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x2191
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x2192
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x2193
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x2194
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x2195
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2196
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2197
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2198
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2199
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x219a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x219b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x219c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x219d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x219e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x219f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x21a0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x21a1
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x21a2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x21a3
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x21a4
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x21a5
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x21a6
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x21a7
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x21a8
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x21a9
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x21aa
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x21ab
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x21ac
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x21ad
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x21ae
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x21af
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x21b0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x21b1
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x21b2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x21b3
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x21b4
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x21b5
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x21b6
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x21b7
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x21b8
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x21b9
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x21ba
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x21bb
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x21bc
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x21bd
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x21be
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x21bf
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x21c0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x21c1
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x21c2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x21c3
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x21c4
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x21c5
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x21c6
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x21c7
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x21c8
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x21c9
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x21ca
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x21cb
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x21cc
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x21cd
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x21ce
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x21cf
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x21d0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x21d1
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x21d2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x21d3
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x21d4
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x21d5
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x21d6
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x21d7
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x21d8
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x21d9
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x21da
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x21db
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x21dc
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x21dd
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophycmregs0_dispdec
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// base address: 0x0
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x213e
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x213f
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x2140
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x2141
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#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x2142
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#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x2143
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#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x2144
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#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x2145
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#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2146
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#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2147
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2148
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2149
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x214a
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x214b
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x214c
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x214d
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophytxregs0_dispdec
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// base address: 0x0
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x215e
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x215f
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2160
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x2161
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x2162
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x2163
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x2164
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x2165
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2166
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2167
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2168
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2169
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x216a
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x216b
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x216c
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x216d
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x216e
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x216f
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2170
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x2171
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x2172
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x2173
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x2174
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x2175
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2176
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2177
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2178
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2179
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x217a
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x217b
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x217c
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x217d
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x217e
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x217f
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2180
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x2181
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x2182
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x2183
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x2184
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x2185
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2186
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2187
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2188
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2189
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x218a
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x218b
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x218c
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x218d
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x218e
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x218f
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2190
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x2191
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x2192
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x2193
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x2194
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x2195
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2196
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2197
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2198
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2199
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x219a
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x219b
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x219c
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x219d
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophypllregs0_dispdec
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// base address: 0x0
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x219e
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x219f
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x21a0
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x21a1
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x21a2
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#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x21a3
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#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x21a4
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#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x21a5
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#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x21a7
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#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x21a8
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#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x21a9
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#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x21aa
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#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2
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// addressBlock: dce_dc_dcio_uniphy1_dispdec
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// base address: 0x320
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2206
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2207
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2208
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2209
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x220a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x220b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x220c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x220d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x220e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x220f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2210
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2211
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2212
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2213
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2214
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2215
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2216
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2217
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2218
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2219
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x221a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x221b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x221c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x221d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x221e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x221f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2220
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2221
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2222
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2223
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2224
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2225
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2226
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2227
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2228
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2229
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x222a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x222b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x222c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x222d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x222e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x222f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2230
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2231
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2232
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2233
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2234
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2235
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2236
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2237
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2238
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2239
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x223a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x223b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x223c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x223d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x223e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x223f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2240
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2241
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2242
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2243
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2244
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2245
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2246
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2247
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2248
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2249
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x224a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x224b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x224c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x224d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x224e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x224f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2250
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2251
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2252
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2253
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2254
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2255
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2256
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2257
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2258
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2259
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x225a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x225b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x225c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x225d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x225e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x225f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2260
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2261
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2262
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2263
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2264
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2265
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2266
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2267
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2268
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2269
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x226a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x226b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x226c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x226d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x226e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x226f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2270
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2271
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2272
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2273
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2274
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2275
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2276
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2277
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2278
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2279
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x227a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x227b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x227c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x227d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x227e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x227f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2280
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2281
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2282
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2283
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2284
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2285
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2286
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2287
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2288
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2289
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x228a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x228b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x228c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x228d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x228e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x228f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2290
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2291
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2292
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2293
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2294
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2295
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2296
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2297
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2298
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2299
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x229a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x229b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x229c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x229d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x229e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x229f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x22a0
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x22a1
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x22a2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x22a3
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x22a4
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x22a5
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophycmregs1_dispdec
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// base address: 0x320
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2206
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2207
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2208
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2209
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#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x220a
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#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x220b
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#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x220c
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#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x220d
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#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x220e
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#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x220f
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2210
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2211
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2212
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2213
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2214
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2215
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophytxregs1_dispdec
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// base address: 0x320
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2226
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2227
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2228
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2229
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x222a
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x222b
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x222c
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x222d
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x222e
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x222f
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2230
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2231
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2232
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2233
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2234
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2235
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2236
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2237
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2238
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2239
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x223a
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x223b
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x223c
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x223d
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x223e
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x223f
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2240
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2241
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2242
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2243
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2244
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2245
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2246
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2247
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2248
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2249
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x224a
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x224b
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x224c
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x224d
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x224e
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x224f
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2250
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2251
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2252
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2253
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2254
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2255
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2256
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2257
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2258
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2259
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x225a
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x225b
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x225c
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x225d
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x225e
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x225f
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2260
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2261
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2262
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2263
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2264
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2265
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophypllregs1_dispdec
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// base address: 0x320
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2266
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2267
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2268
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2269
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x226a
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#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x226b
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#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x226c
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#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x226d
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#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x226f
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#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2270
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#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2271
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#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2272
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#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2
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// addressBlock: dce_dc_dcio_uniphy2_dispdec
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// base address: 0x640
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x22ce
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x22cf
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x22d0
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x22d1
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x22d2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x22d3
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x22d4
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x22d5
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x22d6
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x22d7
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x22d8
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x22d9
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x22da
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x22db
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x22dc
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x22dd
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x22de
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x22df
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x22e0
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x22e1
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x22e2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x22e3
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x22e4
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x22e5
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x22e6
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x22e7
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x22e8
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x22e9
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x22ea
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x22eb
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x22ec
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x22ed
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x22ee
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x22ef
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x22f0
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x22f1
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x22f2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x22f3
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x22f4
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x22f5
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x22f6
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x22f7
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x22f8
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x22f9
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x22fa
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x22fb
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x22fc
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x22fd
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x22fe
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x22ff
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2300
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2301
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2302
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2303
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2304
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2305
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2306
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2307
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2308
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2309
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x230a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x230b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x230c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x230d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x230e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x230f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2310
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2311
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2312
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2313
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2314
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2315
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2316
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2317
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2318
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2319
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x231a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x231b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x231c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x231d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x231e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x231f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2320
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2321
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2322
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2323
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2324
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2325
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2326
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2327
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2328
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2329
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x232a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x232b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x232c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x232d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x232e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x232f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2330
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2331
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2332
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2333
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2334
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2335
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2336
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2337
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2338
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2339
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x233a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x233b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x233c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x233d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x233e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x233f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2340
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2341
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2342
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2343
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2344
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2345
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2346
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2347
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2348
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2349
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x234a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x234b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x234c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x234d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x234e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x234f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2350
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2351
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2352
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2353
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2354
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2355
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2356
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2357
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2358
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2359
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x235a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x235b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x235c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x235d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x235e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x235f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2360
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2361
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2362
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2363
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2364
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2365
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2366
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2367
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2368
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2369
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x236a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x236b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x236c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x236d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophycmregs2_dispdec
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// base address: 0x640
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x22ce
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x22cf
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x22d0
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x22d1
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#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x22d2
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#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x22d3
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#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x22d4
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#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x22d5
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#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x22d6
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#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x22d7
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x22d8
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x22d9
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x22da
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x22db
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x22dc
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x22dd
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophytxregs2_dispdec
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// base address: 0x640
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x22ee
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x22ef
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x22f0
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x22f1
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x22f2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x22f3
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x22f4
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x22f5
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x22f6
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x22f7
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x22f8
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x22f9
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x22fa
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x22fb
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x22fc
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x22fd
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x22fe
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x22ff
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2300
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2301
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2302
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2303
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2304
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2305
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2306
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2307
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2308
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2309
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x230a
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x230b
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x230c
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x230d
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x230e
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x230f
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2310
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2311
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2312
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2313
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2314
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2315
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2316
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2317
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2318
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2319
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x231a
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x231b
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x231c
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x231d
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x231e
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x231f
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2320
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2321
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2322
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2323
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2324
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2325
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2326
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2327
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2328
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2329
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x232a
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x232b
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x232c
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x232d
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophypllregs2_dispdec
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// base address: 0x640
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x232e
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x232f
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2330
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2331
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2332
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#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2333
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#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2334
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#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2335
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#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2337
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#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2338
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#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2339
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#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x233a
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#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2
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// addressBlock: dce_dc_dcio_uniphy3_dispdec
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// base address: 0x960
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2396
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2397
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2398
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2399
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x239a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x239b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x239c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x239d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x239e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x239f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x23a0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x23a1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x23a2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x23a3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x23a4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x23a5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x23a6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x23a7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x23a8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x23a9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x23aa
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x23ab
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x23ac
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x23ad
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x23ae
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x23af
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x23b0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x23b1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x23b2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x23b3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x23b4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x23b5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x23b6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x23b7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x23b8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x23b9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x23ba
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x23bb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x23bc
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x23bd
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x23be
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x23bf
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x23c0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x23c1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x23c2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x23c3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x23c4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x23c5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x23c6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x23c7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x23c8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x23c9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x23ca
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x23cb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x23cc
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x23cd
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x23ce
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x23cf
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x23d0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x23d1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x23d2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x23d3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x23d4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x23d5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x23d6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x23d7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x23d8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x23d9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x23da
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x23db
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x23dc
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x23dd
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x23de
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x23df
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x23e0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x23e1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x23e2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x23e3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x23e4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x23e5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x23e6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x23e7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x23e8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x23e9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x23ea
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x23eb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x23ec
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x23ed
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x23ee
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x23ef
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x23f0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x23f1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x23f2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x23f3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x23f4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x23f5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x23f6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x23f7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x23f8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x23f9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x23fa
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x23fb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x23fc
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x23fd
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x23fe
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x23ff
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2400
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2401
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2402
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2403
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2404
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2405
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2406
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2407
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2408
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2409
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x240a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x240b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x240c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x240d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x240e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x240f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2410
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2411
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2412
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2413
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2414
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2415
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2416
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2417
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2418
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2419
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x241a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x241b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x241c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x241d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x241e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x241f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2420
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2421
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2422
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2423
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2424
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2425
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2426
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2427
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2428
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2429
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x242a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x242b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x242c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x242d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x242e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x242f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2430
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2431
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2432
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2433
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2434
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2435
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophycmregs3_dispdec
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// base address: 0x960
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2396
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2397
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2398
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2399
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#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x239a
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#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x239b
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#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x239c
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#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x239d
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#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x239e
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#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x239f
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x23a0
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x23a1
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x23a2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x23a3
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x23a4
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x23a5
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophytxregs3_dispdec
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// base address: 0x960
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x23b6
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x23b7
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x23b8
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x23b9
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x23ba
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x23bb
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x23bc
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x23bd
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x23be
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x23bf
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x23c0
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x23c1
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x23c2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x23c3
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x23c4
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x23c5
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x23c6
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x23c7
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x23c8
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x23c9
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x23ca
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x23cb
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x23cc
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x23cd
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x23ce
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x23cf
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x23d0
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x23d1
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x23d2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x23d3
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x23d4
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x23d5
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x23d6
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x23d7
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x23d8
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x23d9
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x23da
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x23db
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x23dc
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x23dd
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x23de
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x23df
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x23e0
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x23e1
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x23e2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x23e3
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x23e4
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x23e5
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x23e6
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x23e7
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x23e8
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x23e9
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x23ea
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x23eb
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x23ec
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x23ed
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x23ee
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x23ef
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x23f0
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x23f1
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x23f2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x23f3
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x23f4
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x23f5
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophypllregs3_dispdec
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// base address: 0x960
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x23f6
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x23f7
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x23f8
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x23f9
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x23fa
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#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x23fb
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#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x23fc
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#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x23fd
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#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x23ff
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#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2400
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#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2401
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#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2402
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#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2
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// addressBlock: dce_dc_dcio_uniphy4_dispdec
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// base address: 0xc80
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x245e
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x245f
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2460
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2461
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2462
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2463
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2464
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2465
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2466
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2467
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2468
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2469
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x246a
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x246b
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x246c
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x246d
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x246e
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x246f
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2470
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2471
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2472
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2473
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2474
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2475
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2476
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2477
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2478
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2479
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x247a
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x247b
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x247c
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x247d
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x247e
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x247f
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2480
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2481
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2482
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2483
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2484
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2485
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2486
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2487
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2488
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2489
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x248a
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x248b
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x248c
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x248d
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x248e
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x248f
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2490
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2491
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2492
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2493
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2494
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2495
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2496
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2497
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x2498
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x2499
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x249a
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x249b
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x249c
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x249d
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x249e
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x249f
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x24a0
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x24a1
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x24a2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x24a3
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x24a4
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x24a5
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x24a6
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x24a7
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x24a8
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x24a9
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x24aa
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x24ab
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x24ac
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x24ad
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x24ae
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x24af
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x24b0
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x24b1
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x24b2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x24b3
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x24b4
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x24b5
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x24b6
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x24b7
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x24b8
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x24b9
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x24ba
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x24bb
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x24bc
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x24bd
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x24be
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x24bf
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x24c0
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x24c1
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x24c2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x24c3
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x24c4
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x24c5
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x24c6
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x24c7
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x24c8
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x24c9
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x24ca
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x24cb
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x24cc
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x24cd
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x24ce
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x24cf
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x24d0
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x24d1
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x24d2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x24d3
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x24d4
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x24d5
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x24d6
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x24d7
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x24d8
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x24d9
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x24da
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x24db
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x24dc
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x24dd
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x24de
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x24df
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x24e0
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x24e1
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x24e2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x24e3
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x24e4
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x24e5
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x24e6
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x24e7
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x24e8
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x24e9
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x24ea
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x24eb
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x24ec
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x24ed
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x24ee
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x24ef
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x24f0
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x24f1
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x24f2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x24f3
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x24f4
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x24f5
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x24f6
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x24f7
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x24f8
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x24f9
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x24fa
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x24fb
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x24fc
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x24fd
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#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophycmregs4_dispdec
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// base address: 0xc80
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#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1 0x245e
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#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2 0x245f
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#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3 0x2460
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#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x2461
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#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x2462
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#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x2463
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#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x2464
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#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x2465
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#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x2466
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#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x2467
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x2468
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x2469
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x246a
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x246b
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x246c
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x246d
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#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophytxregs4_dispdec
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// base address: 0xc80
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x247e
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x247f
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#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2480
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x2481
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x2482
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x2483
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x2484
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x2485
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x2486
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x2487
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x2488
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x2489
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x248a
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x248b
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x248c
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x248d
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x248e
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x248f
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#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2490
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x2491
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x2492
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x2493
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x2494
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x2495
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x2496
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x2497
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x2498
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x2499
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x249a
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x249b
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x249c
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x249d
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x249e
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x249f
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#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x24a0
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x24a1
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x24a2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x24a3
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x24a4
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x24a5
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x24a6
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x24a7
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x24a8
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x24a9
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x24aa
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x24ab
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x24ac
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x24ad
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x24ae
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x24af
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#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x24b0
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#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x24b1
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x24b2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x24b3
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x24b4
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x24b5
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x24b6
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x24b7
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x24b8
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x24b9
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x24ba
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x24bb
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x24bc
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x24bd
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#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_BASE_IDX 2
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|
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// addressBlock: dce_dc_dc_combophypllregs4_dispdec
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// base address: 0xc80
|
#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x24be
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#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x24bf
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#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x24c0
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#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x24c1
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#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x24c2
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#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x24c3
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#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x24c4
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#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x24c5
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#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x24c7
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#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x24c8
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#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x24c9
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#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x24ca
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#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_BASE_IDX 2
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|
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// addressBlock: dce_dc_dcio_uniphy5_dispdec
|
// base address: 0xfa0
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2526
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2527
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2528
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2529
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x252a
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x252b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x252c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x252d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x252e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x252f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2530
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2531
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2532
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2533
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2534
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2535
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2536
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2537
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2538
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2539
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x253a
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x253b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x253c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x253d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x253e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x253f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2540
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2541
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2542
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2543
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2544
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2545
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2546
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2547
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2548
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2549
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x254a
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x254b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x254c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x254d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x254e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x254f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2550
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2551
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2552
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2553
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2554
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2555
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x2556
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x2557
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x2558
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x2559
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x255a
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x255b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x255c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x255d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x255e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x255f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x2560
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x2561
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x2562
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x2563
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x2564
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x2565
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x2566
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x2567
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x2568
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x2569
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x256a
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x256b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x256c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x256d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x256e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x256f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x2570
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x2571
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x2572
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x2573
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x2574
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x2575
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x2576
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x2577
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x2578
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x2579
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x257a
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x257b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x257c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x257d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x257e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x257f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x2580
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x2581
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x2582
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x2583
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x2584
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x2585
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x2586
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x2587
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x2588
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x2589
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x258a
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x258b
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x258c
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x258d
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x258e
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x258f
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x2590
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x2591
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x2592
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x2593
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x2594
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x2595
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x2596
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x2597
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x2598
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x2599
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x259a
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x259b
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x259c
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x259d
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x259e
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x259f
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x25a0
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x25a1
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x25a2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x25a3
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x25a4
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x25a5
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x25a6
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x25a7
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x25a8
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x25a9
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x25aa
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x25ab
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x25ac
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x25ad
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x25ae
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x25af
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x25b0
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x25b1
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x25b2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x25b3
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x25b4
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x25b5
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x25b6
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x25b7
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x25b8
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x25b9
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x25ba
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x25bb
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x25bc
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x25bd
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x25be
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x25bf
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x25c0
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x25c1
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x25c2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x25c3
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x25c4
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x25c5
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#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophycmregs5_dispdec
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// base address: 0xfa0
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#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1 0x2526
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#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2 0x2527
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#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3 0x2528
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#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x2529
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#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x252a
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#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x252b
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#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x252c
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#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x252d
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#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x252e
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#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x252f
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x2530
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x2531
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x2532
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x2533
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x2534
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x2535
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#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophytxregs5_dispdec
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// base address: 0xfa0
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x2546
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x2547
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#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2548
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x2549
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x254a
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x254b
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x254c
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x254d
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x254e
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x254f
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x2550
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x2551
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x2552
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x2553
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x2554
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x2555
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x2556
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x2557
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#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2558
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x2559
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x255a
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x255b
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x255c
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x255d
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x255e
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x255f
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x2560
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x2561
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x2562
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x2563
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x2564
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x2565
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x2566
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x2567
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#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2568
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x2569
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x256a
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x256b
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x256c
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x256d
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x256e
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x256f
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x2570
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x2571
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x2572
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x2573
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x2574
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x2575
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x2576
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x2577
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#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2578
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#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x2579
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x257a
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x257b
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x257c
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x257d
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x257e
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x257f
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x2580
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x2581
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x2582
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x2583
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x2584
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x2585
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#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophypllregs5_dispdec
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// base address: 0xfa0
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#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x2586
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#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x2587
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#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x2588
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#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x2589
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#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x258a
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#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x258b
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#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x258c
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#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x258d
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#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x258f
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#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x2590
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#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x2591
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#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x2592
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#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_BASE_IDX 2
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// addressBlock: dce_dc_dcio_uniphy6_dispdec
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// base address: 0x12c0
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x25ee
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x25ef
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x25f0
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x25f1
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x25f2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x25f3
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x25f4
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x25f5
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x25f6
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x25f7
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x25f8
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x25f9
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x25fa
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x25fb
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x25fc
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x25fd
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x25fe
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x25ff
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2600
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2601
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2602
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2603
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2604
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2605
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2606
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2607
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2608
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2609
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x260a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x260b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x260c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x260d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x260e
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x260f
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2610
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2611
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2612
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2613
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2614
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2615
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2616
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2617
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2618
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2619
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x261a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x261b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x261c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x261d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x261e
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x261f
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x2620
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x2621
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x2622
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x2623
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x2624
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x2625
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x2626
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x2627
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0x2628
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0x2629
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0x262a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0x262b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0x262c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0x262d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0x262e
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0x262f
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0x2630
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0x2631
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0x2632
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0x2633
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0x2634
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0x2635
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0x2636
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0x2637
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0x2638
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0x2639
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0x263a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0x263b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0x263c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0x263d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0x263e
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0x263f
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0x2640
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0x2641
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0x2642
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0x2643
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0x2644
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0x2645
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0x2646
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0x2647
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0x2648
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0x2649
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0x264a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0x264b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0x264c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0x264d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0x264e
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0x264f
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0x2650
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0x2651
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0x2652
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0x2653
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0x2654
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0x2655
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0x2656
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0x2657
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0x2658
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0x2659
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0x265a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0x265b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0x265c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0x265d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0x265e
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0x265f
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0x2660
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0x2661
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0x2662
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0x2663
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0x2664
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0x2665
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0x2666
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0x2667
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0x2668
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0x2669
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0x266a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0x266b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0x266c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0x266d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0x266e
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0x266f
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0x2670
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0x2671
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0x2672
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0x2673
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0x2674
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0x2675
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0x2676
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0x2677
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0x2678
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0x2679
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0x267a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0x267b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0x267c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0x267d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0x267e
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0x267f
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0x2680
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0x2681
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0x2682
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0x2683
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0x2684
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0x2685
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0x2686
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0x2687
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0x2688
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0x2689
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0x268a
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0x268b
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0x268c
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0x268d
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#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophycmregs6_dispdec
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// base address: 0x12c0
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#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1 0x25ee
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#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2 0x25ef
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#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3 0x25f0
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#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0x25f1
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#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0x25f2
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#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0x25f3
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#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0x25f4
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#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0x25f5
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#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0x25f6
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#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0x25f7
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0x25f8
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0x25f9
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0x25fa
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0x25fb
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0x25fc
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0x25fd
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#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophytxregs6_dispdec
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// base address: 0x12c0
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#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0x260e
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#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0x260f
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#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2610
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#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0x2611
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0x2612
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0x2613
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0x2614
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0x2615
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0x2616
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0x2617
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0x2618
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0x2619
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0x261a
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0x261b
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0x261c
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0x261d
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0x261e
|
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0x261f
|
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2620
|
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0x2621
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0x2622
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0x2623
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0x2624
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0x2625
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0x2626
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0x2627
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0x2628
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0x2629
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0x262a
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0x262b
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0x262c
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0x262d
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0x262e
|
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0x262f
|
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2630
|
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0x2631
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0x2632
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0x2633
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0x2634
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0x2635
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0x2636
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0x2637
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0x2638
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0x2639
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0x263a
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0x263b
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0x263c
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0x263d
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0x263e
|
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0x263f
|
#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2640
|
#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0x2641
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0x2642
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0x2643
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0x2644
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0x2645
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0x2646
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0x2647
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0x2648
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0x2649
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0x264a
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0x264b
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0x264c
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0x264d
|
#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dc_combophypllregs6_dispdec
|
// base address: 0x12c0
|
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0x264e
|
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0x264f
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#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_BASE_IDX 2
|
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0x2650
|
#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0x2651
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#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0x2652
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#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0x2653
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#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0x2654
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#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0x2655
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#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_VREG_CFG 0x2657
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#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_OBSERVE0 0x2658
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#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_OBSERVE1 0x2659
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#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS6_DFT_OUT 0x265a
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#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dcio_uniphy8_dispdec
|
// base address: 0x15e0
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x26b6
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x26b7
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x26b8
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x26b9
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x26ba
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x26bb
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x26bc
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x26bd
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x26be
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x26bf
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x26c0
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x26c1
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x26c2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x26c3
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x26c4
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x26c5
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x26c6
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x26c7
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x26c8
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x26c9
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x26ca
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x26cb
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x26cc
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x26cd
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x26ce
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x26cf
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x26d0
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x26d1
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x26d2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x26d3
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x26d4
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x26d5
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32 0x26d6
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33 0x26d7
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34 0x26d8
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35 0x26d9
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36 0x26da
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37 0x26db
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38 0x26dc
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39 0x26dd
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40 0x26de
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41 0x26df
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42 0x26e0
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43 0x26e1
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44 0x26e2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45 0x26e3
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46 0x26e4
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47 0x26e5
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48 0x26e6
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49 0x26e7
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50 0x26e8
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51 0x26e9
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52 0x26ea
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53 0x26eb
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
|
#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54 0x26ec
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55 0x26ed
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56 0x26ee
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57 0x26ef
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58 0x26f0
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59 0x26f1
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60 0x26f2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61 0x26f3
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62 0x26f4
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63 0x26f5
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64 0x26f6
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65 0x26f7
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66 0x26f8
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67 0x26f9
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68 0x26fa
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69 0x26fb
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70 0x26fc
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71 0x26fd
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72 0x26fe
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73 0x26ff
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74 0x2700
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75 0x2701
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76 0x2702
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77 0x2703
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78 0x2704
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79 0x2705
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80 0x2706
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81 0x2707
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82 0x2708
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83 0x2709
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84 0x270a
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85 0x270b
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86 0x270c
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87 0x270d
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88 0x270e
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89 0x270f
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90 0x2710
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91 0x2711
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92 0x2712
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93 0x2713
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94 0x2714
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95 0x2715
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96 0x2716
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97 0x2717
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98 0x2718
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99 0x2719
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100 0x271a
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101 0x271b
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102 0x271c
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103 0x271d
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104 0x271e
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105 0x271f
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106 0x2720
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107 0x2721
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108 0x2722
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109 0x2723
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110 0x2724
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111 0x2725
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112 0x2726
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113 0x2727
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114 0x2728
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115 0x2729
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116 0x272a
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117 0x272b
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118 0x272c
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119 0x272d
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120 0x272e
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121 0x272f
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122 0x2730
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123 0x2731
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124 0x2732
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125 0x2733
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126 0x2734
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127 0x2735
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128 0x2736
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129 0x2737
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130 0x2738
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131 0x2739
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132 0x273a
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133 0x273b
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134 0x273c
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135 0x273d
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136 0x273e
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137 0x273f
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138 0x2740
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139 0x2741
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140 0x2742
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141 0x2743
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142 0x2744
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143 0x2745
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144 0x2746
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145 0x2747
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146 0x2748
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147 0x2749
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148 0x274a
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149 0x274b
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150 0x274c
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151 0x274d
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152 0x274e
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153 0x274f
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154 0x2750
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155 0x2751
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156 0x2752
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157 0x2753
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158 0x2754
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159 0x2755
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#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophycmregs8_dispdec
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// base address: 0x15e0
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#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1 0x26b6
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#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2 0x26b7
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#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3 0x26b8
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#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM 0x26b9
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#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT 0x26ba
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#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL 0x26bb
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#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP 0x26bc
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#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS 0x26bd
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#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL 0x26be
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#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1 0x26bf
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2 0x26c0
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3 0x26c1
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4 0x26c2
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5 0x26c3
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6 0x26c4
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7 0x26c5
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#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophytxregs8_dispdec
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// base address: 0x15e0
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0 0x26d6
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0 0x26d7
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#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x26d8
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0 0x26d9
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0 0x26da
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0 0x26db
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0 0x26dc
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0 0x26dd
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0 0x26de
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0 0x26df
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0 0x26e0
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0 0x26e1
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0 0x26e2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0 0x26e3
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0 0x26e4
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0 0x26e5
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1 0x26e6
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1 0x26e7
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#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x26e8
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1 0x26e9
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1 0x26ea
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1 0x26eb
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1 0x26ec
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1 0x26ed
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1 0x26ee
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1 0x26ef
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1 0x26f0
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1 0x26f1
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1 0x26f2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1 0x26f3
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1 0x26f4
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1 0x26f5
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2 0x26f6
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2 0x26f7
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#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x26f8
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2 0x26f9
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2 0x26fa
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2 0x26fb
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2 0x26fc
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2 0x26fd
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2 0x26fe
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2 0x26ff
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2 0x2700
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2 0x2701
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2 0x2702
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2 0x2703
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2 0x2704
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2 0x2705
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3 0x2706
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3 0x2707
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#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2708
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#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3 0x2709
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3 0x270a
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3 0x270b
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3 0x270c
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3 0x270d
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3 0x270e
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3 0x270f
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3 0x2710
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3 0x2711
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3 0x2712
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3 0x2713
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3 0x2714
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3 0x2715
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#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_dc_combophypllregs8_dispdec
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// base address: 0x15e0
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#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0 0x2716
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#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1 0x2717
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#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2 0x2718
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#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3 0x2719
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#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE 0x271a
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#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE 0x271b
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#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL 0x271c
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#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL 0x271d
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#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_VREG_CFG 0x271f
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#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_OBSERVE0 0x2720
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#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_OBSERVE1 0x2721
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#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS8_DFT_OUT 0x2722
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#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_BASE_IDX 2
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// addressBlock: dce_dc_dsi0_dispdec
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// base address: 0x0
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#define mmDSI0_DISP_DSI_CTRL 0x27be
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#define mmDSI0_DISP_DSI_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_STATUS 0x27bf
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#define mmDSI0_DISP_DSI_STATUS_BASE_IDX 2
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#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL 0x27c0
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#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x27c1
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#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
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#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x27c2
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#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
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#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x27c3
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#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
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#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x27c4
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#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
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#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x27c5
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#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
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#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x27c6
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#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL 0x27c7
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#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x27c8
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#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x27c9
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#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET 0x27ca
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#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH 0x27cb
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#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0 0x27cc
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#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1 0x27cd
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#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_DATA_PITCH 0x27ce
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#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH 0x27cf
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#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT 0x27d0
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#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL 0x27d1
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#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA 0x27d2
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#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH 0x27d3
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#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
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#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT 0x27d4
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#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
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#define mmDSI0_DISP_DSI_RDBK_DATA0 0x27d5
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#define mmDSI0_DISP_DSI_RDBK_DATA0_BASE_IDX 2
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#define mmDSI0_DISP_DSI_RDBK_DATA1 0x27d6
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#define mmDSI0_DISP_DSI_RDBK_DATA1_BASE_IDX 2
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#define mmDSI0_DISP_DSI_RDBK_DATA2 0x27d7
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#define mmDSI0_DISP_DSI_RDBK_DATA2_BASE_IDX 2
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#define mmDSI0_DISP_DSI_RDBK_DATA3 0x27d8
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#define mmDSI0_DISP_DSI_RDBK_DATA3_BASE_IDX 2
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#define mmDSI0_DISP_DSI_RDBK_DATATYPE0 0x27d9
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#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
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#define mmDSI0_DISP_DSI_RDBK_DATATYPE1 0x27da
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#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
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#define mmDSI0_DISP_DSI_TRIG_CTRL 0x27db
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#define mmDSI0_DISP_DSI_TRIG_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_EXT_MUX 0x27dc
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#define mmDSI0_DISP_DSI_EXT_MUX_BASE_IDX 2
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#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x27dd
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#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x27de
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#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
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#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x27df
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#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
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#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x27e0
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#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
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#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER 0x27e1
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#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
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#define mmDSI0_DISP_DSI_EXT_RESET 0x27e2
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#define mmDSI0_DISP_DSI_EXT_RESET_BASE_IDX 2
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#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE 0x27e3
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#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
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#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE 0x27e4
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#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
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#define mmDSI0_DISP_DSI_LANE_CRC_CTRL 0x27e5
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#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL 0x27e6
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#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_LANE_CTRL 0x27e7
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#define mmDSI0_DISP_DSI_LANE_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR 0x27e8
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#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
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#define mmDSI0_DISP_DSI_LP_TIMER_CTRL 0x27e9
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#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_HS_TIMER_CTRL 0x27ea
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#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_TIMEOUT_STATUS 0x27eb
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#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
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#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL 0x27ec
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#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x27ed
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#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
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#define mmDSI0_DISP_DSI_EOT_PACKET 0x27ee
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#define mmDSI0_DISP_DSI_EOT_PACKET_BASE_IDX 2
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#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL 0x27ef
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#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x27f0
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#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
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#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL 0x27f1
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#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x27f2
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#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
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#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x27f3
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#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
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#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x27f4
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#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
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#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x27f5
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#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT 0x27f6
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#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
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#define mmDSI0_DISP_DSI_MIPI_BIST_START 0x27f7
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#define mmDSI0_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
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#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS 0x27f8
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#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
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#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK 0x27f9
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#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
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#define mmDSI0_DISP_DSI_INTERRUPT_CTRL 0x27fa
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#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_CLK_CTRL 0x27fb
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#define mmDSI0_DISP_DSI_CLK_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_CLK_STATUS 0x27fc
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#define mmDSI0_DISP_DSI_CLK_STATUS_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS 0x27fd
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#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
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#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL 0x27fe
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#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_CMD_FIFO_DATA 0x27ff
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#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
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#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL 0x2800
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#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_TE_CTRL 0x2801
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#define mmDSI0_DISP_DSI_TE_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_LANE_STATUS 0x2805
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#define mmDSI0_DISP_DSI_LANE_STATUS_BASE_IDX 2
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#define mmDSI0_DISP_DSI_PERF_CTRL 0x2806
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#define mmDSI0_DISP_DSI_PERF_CTRL_BASE_IDX 2
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#define mmDSI0_DISP_DSI_HSYNC_LENGTH 0x2807
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#define mmDSI0_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
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#define mmDSI0_DISP_DSI_RDBK_NUM 0x2808
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#define mmDSI0_DISP_DSI_RDBK_NUM_BASE_IDX 2
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#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL 0x2809
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#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dsi1_dispdec
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// base address: 0x400
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#define mmDSI1_DISP_DSI_CTRL 0x28be
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#define mmDSI1_DISP_DSI_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_STATUS 0x28bf
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#define mmDSI1_DISP_DSI_STATUS_BASE_IDX 2
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#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL 0x28c0
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#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE 0x28c1
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#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_BASE_IDX 2
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#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD 0x28c2
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#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_BASE_IDX 2
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#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD 0x28c3
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#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_BASE_IDX 2
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#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE 0x28c4
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#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_BASE_IDX 2
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#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE 0x28c5
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#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_BASE_IDX 2
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#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL 0x28c6
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#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL 0x28c7
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#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL 0x28c8
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#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL 0x28c9
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#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET 0x28ca
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#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH 0x28cb
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#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0 0x28cc
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#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1 0x28cd
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#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_DATA_PITCH 0x28ce
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#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH 0x28cf
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#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT 0x28d0
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#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL 0x28d1
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#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA 0x28d2
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#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH 0x28d3
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#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_BASE_IDX 2
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#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT 0x28d4
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#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_BASE_IDX 2
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#define mmDSI1_DISP_DSI_RDBK_DATA0 0x28d5
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#define mmDSI1_DISP_DSI_RDBK_DATA0_BASE_IDX 2
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#define mmDSI1_DISP_DSI_RDBK_DATA1 0x28d6
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#define mmDSI1_DISP_DSI_RDBK_DATA1_BASE_IDX 2
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#define mmDSI1_DISP_DSI_RDBK_DATA2 0x28d7
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#define mmDSI1_DISP_DSI_RDBK_DATA2_BASE_IDX 2
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#define mmDSI1_DISP_DSI_RDBK_DATA3 0x28d8
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#define mmDSI1_DISP_DSI_RDBK_DATA3_BASE_IDX 2
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#define mmDSI1_DISP_DSI_RDBK_DATATYPE0 0x28d9
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#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_BASE_IDX 2
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#define mmDSI1_DISP_DSI_RDBK_DATATYPE1 0x28da
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#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_BASE_IDX 2
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#define mmDSI1_DISP_DSI_TRIG_CTRL 0x28db
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#define mmDSI1_DISP_DSI_TRIG_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_EXT_MUX 0x28dc
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#define mmDSI1_DISP_DSI_EXT_MUX_BASE_IDX 2
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#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL 0x28dd
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#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER 0x28de
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#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_BASE_IDX 2
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#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER 0x28df
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#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_BASE_IDX 2
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#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER 0x28e0
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#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_BASE_IDX 2
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#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER 0x28e1
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#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_BASE_IDX 2
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#define mmDSI1_DISP_DSI_EXT_RESET 0x28e2
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#define mmDSI1_DISP_DSI_EXT_RESET_BASE_IDX 2
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#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE 0x28e3
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#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_BASE_IDX 2
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#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE 0x28e4
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#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_BASE_IDX 2
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#define mmDSI1_DISP_DSI_LANE_CRC_CTRL 0x28e5
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#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL 0x28e6
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#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_LANE_CTRL 0x28e7
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#define mmDSI1_DISP_DSI_LANE_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR 0x28e8
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#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_BASE_IDX 2
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#define mmDSI1_DISP_DSI_LP_TIMER_CTRL 0x28e9
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#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_HS_TIMER_CTRL 0x28ea
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#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_TIMEOUT_STATUS 0x28eb
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#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_BASE_IDX 2
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#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL 0x28ec
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#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2 0x28ed
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#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_BASE_IDX 2
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#define mmDSI1_DISP_DSI_EOT_PACKET 0x28ee
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#define mmDSI1_DISP_DSI_EOT_PACKET_BASE_IDX 2
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#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL 0x28ef
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#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER 0x28f0
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#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_BASE_IDX 2
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#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL 0x28f1
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#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE 0x28f2
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#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_BASE_IDX 2
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#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE 0x28f3
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#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_BASE_IDX 2
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#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG 0x28f4
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#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_BASE_IDX 2
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#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL 0x28f5
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#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT 0x28f6
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#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_BASE_IDX 2
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#define mmDSI1_DISP_DSI_MIPI_BIST_START 0x28f7
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#define mmDSI1_DISP_DSI_MIPI_BIST_START_BASE_IDX 2
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#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS 0x28f8
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#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_BASE_IDX 2
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#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK 0x28f9
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#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_BASE_IDX 2
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#define mmDSI1_DISP_DSI_INTERRUPT_CTRL 0x28fa
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#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_CLK_CTRL 0x28fb
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#define mmDSI1_DISP_DSI_CLK_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_CLK_STATUS 0x28fc
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#define mmDSI1_DISP_DSI_CLK_STATUS_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS 0x28fd
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#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_BASE_IDX 2
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#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL 0x28fe
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#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_CMD_FIFO_DATA 0x28ff
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#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_BASE_IDX 2
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#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL 0x2900
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#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_TE_CTRL 0x2901
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#define mmDSI1_DISP_DSI_TE_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_LANE_STATUS 0x2905
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#define mmDSI1_DISP_DSI_LANE_STATUS_BASE_IDX 2
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#define mmDSI1_DISP_DSI_PERF_CTRL 0x2906
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#define mmDSI1_DISP_DSI_PERF_CTRL_BASE_IDX 2
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#define mmDSI1_DISP_DSI_HSYNC_LENGTH 0x2907
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#define mmDSI1_DISP_DSI_HSYNC_LENGTH_BASE_IDX 2
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#define mmDSI1_DISP_DSI_RDBK_NUM 0x2908
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#define mmDSI1_DISP_DSI_RDBK_NUM_BASE_IDX 2
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#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL 0x2909
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#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dprx_sd0_dispdec
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// base address: 0x0
|
#define mmDPRX_SD0_DPRX_SD_CONTROL 0x29be
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#define mmDPRX_SD0_DPRX_SD_CONTROL_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE 0x29bf
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#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA0 0x29c0
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#define mmDPRX_SD0_DPRX_SD_MSA0_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA1 0x29c1
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#define mmDPRX_SD0_DPRX_SD_MSA1_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA2 0x29c2
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#define mmDPRX_SD0_DPRX_SD_MSA2_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA3 0x29c3
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#define mmDPRX_SD0_DPRX_SD_MSA3_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA4 0x29c4
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#define mmDPRX_SD0_DPRX_SD_MSA4_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA5 0x29c5
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#define mmDPRX_SD0_DPRX_SD_MSA5_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA6 0x29c6
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#define mmDPRX_SD0_DPRX_SD_MSA6_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA7 0x29c7
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#define mmDPRX_SD0_DPRX_SD_MSA7_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA8 0x29c8
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#define mmDPRX_SD0_DPRX_SD_MSA8_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_VBID 0x29c9
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#define mmDPRX_SD0_DPRX_SD_VBID_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE 0x29ca
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#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x29cb
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#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE 0x29cc
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#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSE_SAT 0x29ce
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#define mmDPRX_SD0_DPRX_SD_MSE_SAT_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE 0x29cf
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#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE 0x29d0
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#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_V_PARAMETER 0x29d1
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#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT 0x29d2
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#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS 0x29d3
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#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x29d4
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#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS 0x29d5
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#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL 0x29d6
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#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS 0x29d7
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#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL 0x29d8
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#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR 0x29d9
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#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE 0x29da
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#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x29db
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#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED 0x29dc
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#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR 0x29dd
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#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR 0x29de
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#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR 0x29df
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#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x29e1
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#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_SDP_STEER 0x29e3
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#define mmDPRX_SD0_DPRX_SD_SDP_STEER_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS 0x29e4
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#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL 0x29e5
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#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_SDP_DATA 0x29e6
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#define mmDPRX_SD0_DPRX_SD_SDP_DATA_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_SDP_ERROR 0x29e7
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#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER 0x29e8
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#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR 0x29e9
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#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL 0x29ea
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#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED 0x29eb
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#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED 0x29ec
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#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_BS_COUNTER 0x29ed
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#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_BASE_IDX 2
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#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED 0x29ee
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#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
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// addressBlock: dce_dc_dprx_sd1_dispdec
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// base address: 0x180
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#define mmDPRX_SD1_DPRX_SD_CONTROL 0x2a1e
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#define mmDPRX_SD1_DPRX_SD_CONTROL_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE 0x2a1f
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#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA0 0x2a20
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#define mmDPRX_SD1_DPRX_SD_MSA0_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA1 0x2a21
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#define mmDPRX_SD1_DPRX_SD_MSA1_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA2 0x2a22
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#define mmDPRX_SD1_DPRX_SD_MSA2_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA3 0x2a23
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#define mmDPRX_SD1_DPRX_SD_MSA3_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA4 0x2a24
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#define mmDPRX_SD1_DPRX_SD_MSA4_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA5 0x2a25
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#define mmDPRX_SD1_DPRX_SD_MSA5_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA6 0x2a26
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#define mmDPRX_SD1_DPRX_SD_MSA6_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA7 0x2a27
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#define mmDPRX_SD1_DPRX_SD_MSA7_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA8 0x2a28
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#define mmDPRX_SD1_DPRX_SD_MSA8_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_VBID 0x2a29
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#define mmDPRX_SD1_DPRX_SD_VBID_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE 0x2a2a
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#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT 0x2a2b
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#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE 0x2a2c
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#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSE_SAT 0x2a2e
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#define mmDPRX_SD1_DPRX_SD_MSE_SAT_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE 0x2a2f
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#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE 0x2a30
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#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_V_PARAMETER 0x2a31
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#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT 0x2a32
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#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS 0x2a33
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#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED 0x2a34
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#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS 0x2a35
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#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL 0x2a36
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#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS 0x2a37
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#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL 0x2a38
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#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR 0x2a39
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#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE 0x2a3a
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#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR 0x2a3b
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#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED 0x2a3c
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#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR 0x2a3d
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#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR 0x2a3e
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#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR 0x2a3f
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#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH 0x2a41
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#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_SDP_STEER 0x2a43
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#define mmDPRX_SD1_DPRX_SD_SDP_STEER_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS 0x2a44
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#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL 0x2a45
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#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_SDP_DATA 0x2a46
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#define mmDPRX_SD1_DPRX_SD_SDP_DATA_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_SDP_ERROR 0x2a47
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#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER 0x2a48
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#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR 0x2a49
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#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL 0x2a4a
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#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED 0x2a4b
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#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED 0x2a4c
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#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_BS_COUNTER 0x2a4d
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#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_BASE_IDX 2
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#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED 0x2a4e
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#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_BASE_IDX 2
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// addressBlock: dce_dc_dc_perfmon10_dispdec
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// base address: 0xacf8
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x2b5e
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x2b5f
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x2b60
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#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CNTL 0x2b61
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#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CNTL2 0x2b62
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#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x2b63
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#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x2b64
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#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_HI 0x2b65
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#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_LOW 0x2b66
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#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dc_zcalregs_dispdec
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// base address: 0x0
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#define mmCOMP_EN_CTL 0x2d96
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#define mmCOMP_EN_CTL_BASE_IDX 2
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#define mmCOMP_EN_DFX 0x2d97
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#define mmCOMP_EN_DFX_BASE_IDX 2
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#define mmZCAL_FUSES 0x2d98
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#define mmZCAL_FUSES_BASE_IDX 2
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// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
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// base address: 0x48
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//#define mmVGA_dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
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// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
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// base address: 0x4c
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//#define mmVGA_dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
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// addressBlock: dce_dc_dispdec[948..986]
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// base address: 0x3b4
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//#define mmVGA_CRTC8_IDX 0x002d
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//#define mmVGA_CRTC8_DATA 0x002d
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//#define mmVGA_GENFC_WT 0x002e
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//#define mmVGA_GENS1 0x002e
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//#define mmVGA_ATTRDW 0x0030
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//#define mmVGA_ATTRX 0x0030
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//#define mmVGA_ATTRDR 0x0030
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//#define mmVGA_GENMO_WT 0x0030
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//#define mmVGA_GENS0 0x0030
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//#define mmVGA_GENENB 0x0030
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//#define mmVGA_SEQ8_IDX 0x0031
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//#define mmVGA_SEQ8_DATA 0x0031
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//#define mmVGA_DAC_MASK 0x0031
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//#define mmVGA_DAC_R_INDEX 0x0031
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//#define mmVGA_DAC_W_INDEX 0x0032
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//#define mmVGA_DAC_DATA 0x0032
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//#define mmVGA_GENFC_RD 0x0032
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//#define mmVGA_GENMO_RD 0x0033
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//#define mmVGA_GRPH8_IDX 0x0033
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//#define mmVGA_GRPH8_DATA 0x0033
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//#define mmVGA_CRTC8_IDX_1 0x0035
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//#define mmVGA_CRTC8_DATA_1 0x0035
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//#define mmVGA_GENFC_WT_1 0x0036
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//#define mmVGA_GENS1_1 0x0036
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// addressBlock: dce_dc_azdec
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// base address: 0x0
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#define mmCORB_WRITE_POINTER 0x0000
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#define mmCORB_WRITE_POINTER_BASE_IDX 0
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#define mmCORB_READ_POINTER 0x0000
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#define mmCORB_READ_POINTER_BASE_IDX 0
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#define mmCORB_CONTROL 0x0001
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#define mmCORB_CONTROL_BASE_IDX 0
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#define mmCORB_STATUS 0x0001
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#define mmCORB_STATUS_BASE_IDX 0
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#define mmCORB_SIZE 0x0001
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#define mmCORB_SIZE_BASE_IDX 0
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#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
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#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
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#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmRIRB_WRITE_POINTER 0x0004
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#define mmRIRB_WRITE_POINTER_BASE_IDX 0
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#define mmRESPONSE_INTERRUPT_COUNT 0x0004
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#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
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#define mmRIRB_CONTROL 0x0005
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#define mmRIRB_CONTROL_BASE_IDX 0
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#define mmRIRB_STATUS 0x0005
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#define mmRIRB_STATUS_BASE_IDX 0
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#define mmRIRB_SIZE 0x0005
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#define mmRIRB_SIZE_BASE_IDX 0
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
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#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
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#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
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#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
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#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
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#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
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#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
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#define mmIMMEDIATE_COMMAND_STATUS 0x0008
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#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
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#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
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#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
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#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
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#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_azstream0_azdec
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// base address: 0x0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
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#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_azstream1_azdec
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// base address: 0x20
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
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#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_azstream2_azdec
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// base address: 0x40
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
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#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_azstream3_azdec
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// base address: 0x60
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
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#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_azstream4_azdec
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// base address: 0x80
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
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#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_azstream5_azdec
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// base address: 0xa0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
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#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_azstream6_azdec
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// base address: 0xc0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
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#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_azstream7_azdec
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// base address: 0xe0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
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#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: azf0stream0_streamind
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// base address: 0x0
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#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream1_streamind
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// base address: 0x0
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#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream2_streamind
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// base address: 0x0
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#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream3_streamind
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// base address: 0x0
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#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream4_streamind
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// base address: 0x0
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#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream5_streamind
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// base address: 0x0
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#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream6_streamind
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// base address: 0x0
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#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream7_streamind
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// base address: 0x0
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#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream8_streamind
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// base address: 0x0
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#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream9_streamind
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// base address: 0x0
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#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream10_streamind
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// base address: 0x0
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#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream11_streamind
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// base address: 0x0
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#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream12_streamind
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// base address: 0x0
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#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream13_streamind
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// base address: 0x0
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#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream14_streamind
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// base address: 0x0
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#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream15_streamind
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// base address: 0x0
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#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0endpoint0_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint1_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint2_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint3_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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|
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// addressBlock: azf0endpoint4_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint5_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint6_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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|
|
// addressBlock: azf0endpoint7_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0inputendpoint0_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint1_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint2_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint3_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint4_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint5_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint6_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint7_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: f2codecind
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// base address: 0x0
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#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
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#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
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#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
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#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
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#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
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#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
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#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
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#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
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#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
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#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
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#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
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#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
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#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
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#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
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#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
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#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
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#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
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#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
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#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
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#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
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#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
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// addressBlock: descriptorind
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// base address: 0x0
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#define ixAUDIO_DESCRIPTOR0 0x0001
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#define ixAUDIO_DESCRIPTOR1 0x0002
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#define ixAUDIO_DESCRIPTOR2 0x0003
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#define ixAUDIO_DESCRIPTOR3 0x0004
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#define ixAUDIO_DESCRIPTOR4 0x0005
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#define ixAUDIO_DESCRIPTOR5 0x0006
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#define ixAUDIO_DESCRIPTOR6 0x0007
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#define ixAUDIO_DESCRIPTOR7 0x0008
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#define ixAUDIO_DESCRIPTOR8 0x0009
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#define ixAUDIO_DESCRIPTOR9 0x000a
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#define ixAUDIO_DESCRIPTOR10 0x000b
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#define ixAUDIO_DESCRIPTOR11 0x000c
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#define ixAUDIO_DESCRIPTOR12 0x000d
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#define ixAUDIO_DESCRIPTOR13 0x000e
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// addressBlock: sinkinfoind
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// base address: 0x0
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
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#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
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#define ixSINK_DESCRIPTION0 0x0005
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#define ixSINK_DESCRIPTION1 0x0006
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#define ixSINK_DESCRIPTION2 0x0007
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#define ixSINK_DESCRIPTION3 0x0008
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#define ixSINK_DESCRIPTION4 0x0009
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#define ixSINK_DESCRIPTION5 0x000a
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#define ixSINK_DESCRIPTION6 0x000b
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#define ixSINK_DESCRIPTION7 0x000c
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#define ixSINK_DESCRIPTION8 0x000d
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#define ixSINK_DESCRIPTION9 0x000e
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#define ixSINK_DESCRIPTION10 0x000f
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#define ixSINK_DESCRIPTION11 0x0010
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#define ixSINK_DESCRIPTION12 0x0011
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#define ixSINK_DESCRIPTION13 0x0012
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#define ixSINK_DESCRIPTION14 0x0013
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#define ixSINK_DESCRIPTION15 0x0014
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#define ixSINK_DESCRIPTION16 0x0015
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#define ixSINK_DESCRIPTION17 0x0016
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// addressBlock: azinputcrc0resultind
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// base address: 0x0
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#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
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#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
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#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
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#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
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#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
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#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
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#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
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#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
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// addressBlock: azinputcrc1resultind
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// base address: 0x0
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#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
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#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
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#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
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#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
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#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
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#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
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#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
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#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
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// addressBlock: azcrc0resultind
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// base address: 0x0
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#define ixAZALIA_CRC0_CHANNEL0 0x0000
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#define ixAZALIA_CRC0_CHANNEL1 0x0001
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#define ixAZALIA_CRC0_CHANNEL2 0x0002
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#define ixAZALIA_CRC0_CHANNEL3 0x0003
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#define ixAZALIA_CRC0_CHANNEL4 0x0004
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#define ixAZALIA_CRC0_CHANNEL5 0x0005
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#define ixAZALIA_CRC0_CHANNEL6 0x0006
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#define ixAZALIA_CRC0_CHANNEL7 0x0007
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// addressBlock: azcrc1resultind
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// base address: 0x0
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#define ixAZALIA_CRC1_CHANNEL0 0x0000
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#define ixAZALIA_CRC1_CHANNEL1 0x0001
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#define ixAZALIA_CRC1_CHANNEL2 0x0002
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#define ixAZALIA_CRC1_CHANNEL3 0x0003
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#define ixAZALIA_CRC1_CHANNEL4 0x0004
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#define ixAZALIA_CRC1_CHANNEL5 0x0005
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#define ixAZALIA_CRC1_CHANNEL6 0x0006
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#define ixAZALIA_CRC1_CHANNEL7 0x0007
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// addressBlock: vgaseqind
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// base address: 0x0
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#define ixSEQ00 0x0000
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#define ixSEQ01 0x0001
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#define ixSEQ02 0x0002
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#define ixSEQ03 0x0003
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#define ixSEQ04 0x0004
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// addressBlock: vgacrtind
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// base address: 0x0
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#define ixCRT00 0x0000
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#define ixCRT01 0x0001
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#define ixCRT02 0x0002
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#define ixCRT03 0x0003
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#define ixCRT04 0x0004
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#define ixCRT05 0x0005
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#define ixCRT06 0x0006
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#define ixCRT07 0x0007
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#define ixCRT08 0x0008
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#define ixCRT09 0x0009
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#define ixCRT0A 0x000a
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#define ixCRT0B 0x000b
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#define ixCRT0C 0x000c
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#define ixCRT0D 0x000d
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#define ixCRT0E 0x000e
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#define ixCRT0F 0x000f
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#define ixCRT10 0x0010
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#define ixCRT11 0x0011
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#define ixCRT12 0x0012
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#define ixCRT13 0x0013
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#define ixCRT14 0x0014
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#define ixCRT15 0x0015
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#define ixCRT16 0x0016
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#define ixCRT17 0x0017
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#define ixCRT18 0x0018
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#define ixCRT1E 0x001e
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#define ixCRT1F 0x001f
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#define ixCRT22 0x0022
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// addressBlock: vgagrphind
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// base address: 0x0
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#define ixGRA00 0x0000
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#define ixGRA01 0x0001
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#define ixGRA02 0x0002
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#define ixGRA03 0x0003
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#define ixGRA04 0x0004
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#define ixGRA05 0x0005
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#define ixGRA06 0x0006
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#define ixGRA07 0x0007
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#define ixGRA08 0x0008
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// addressBlock: vgaattrind
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// base address: 0x0
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#define ixATTR00 0x0000
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#define ixATTR01 0x0001
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#define ixATTR02 0x0002
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#define ixATTR03 0x0003
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#define ixATTR04 0x0004
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#define ixATTR05 0x0005
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#define ixATTR06 0x0006
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#define ixATTR07 0x0007
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#define ixATTR08 0x0008
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#define ixATTR09 0x0009
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#define ixATTR0A 0x000a
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#define ixATTR0B 0x000b
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#define ixATTR0C 0x000c
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#define ixATTR0D 0x000d
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#define ixATTR0E 0x000e
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#define ixATTR0F 0x000f
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#define ixATTR10 0x0010
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#define ixATTR11 0x0011
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#define ixATTR12 0x0012
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#define ixATTR13 0x0013
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#define ixATTR14 0x0014
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#endif
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