/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_LINK_SERVICE_TYPES_H__
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#define __DAL_LINK_SERVICE_TYPES_H__
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#include "grph_object_id.h"
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#include "dal_types.h"
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#include "irq_types.h"
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/*struct mst_mgr_callback_object;*/
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struct ddc;
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struct irq_manager;
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enum {
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MAX_CONTROLLER_NUM = 6
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};
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enum dp_power_state {
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DP_POWER_STATE_D0 = 1,
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DP_POWER_STATE_D3
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};
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enum edp_revision {
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/* eDP version 1.1 or lower */
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EDP_REVISION_11 = 0x00,
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/* eDP version 1.2 */
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EDP_REVISION_12 = 0x01,
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/* eDP version 1.3 */
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EDP_REVISION_13 = 0x02
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};
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enum {
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LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
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};
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enum link_training_result {
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LINK_TRAINING_SUCCESS,
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LINK_TRAINING_CR_FAIL_LANE0,
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LINK_TRAINING_CR_FAIL_LANE1,
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LINK_TRAINING_CR_FAIL_LANE23,
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/* CR DONE bit is cleared during EQ step */
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LINK_TRAINING_EQ_FAIL_CR,
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/* other failure during EQ step */
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LINK_TRAINING_EQ_FAIL_EQ,
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LINK_TRAINING_LQA_FAIL,
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/* one of the CR,EQ or symbol lock is dropped */
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LINK_TRAINING_LINK_LOSS,
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};
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struct link_training_settings {
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struct dc_link_settings link_settings;
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struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
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enum dc_voltage_swing *voltage_swing;
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enum dc_pre_emphasis *pre_emphasis;
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enum dc_post_cursor2 *post_cursor2;
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uint16_t cr_pattern_time;
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uint16_t eq_pattern_time;
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enum dc_dp_training_pattern pattern_for_cr;
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enum dc_dp_training_pattern pattern_for_eq;
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bool enhanced_framing;
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bool allow_invalid_msa_timing_param;
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};
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/*TODO: Move this enum test harness*/
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/* Test patterns*/
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enum dp_test_pattern {
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/* Input data is pass through Scrambler
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* and 8b10b Encoder straight to output*/
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DP_TEST_PATTERN_VIDEO_MODE = 0,
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/* phy test patterns*/
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DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
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DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
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DP_TEST_PATTERN_SYMBOL_ERROR,
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DP_TEST_PATTERN_PRBS7,
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DP_TEST_PATTERN_80BIT_CUSTOM,
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DP_TEST_PATTERN_CP2520_1,
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DP_TEST_PATTERN_CP2520_2,
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DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
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DP_TEST_PATTERN_CP2520_3,
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/* Link Training Patterns */
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DP_TEST_PATTERN_TRAINING_PATTERN1,
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DP_TEST_PATTERN_TRAINING_PATTERN2,
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DP_TEST_PATTERN_TRAINING_PATTERN3,
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DP_TEST_PATTERN_TRAINING_PATTERN4,
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DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
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/* link test patterns*/
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DP_TEST_PATTERN_COLOR_SQUARES,
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DP_TEST_PATTERN_COLOR_SQUARES_CEA,
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DP_TEST_PATTERN_VERTICAL_BARS,
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DP_TEST_PATTERN_HORIZONTAL_BARS,
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DP_TEST_PATTERN_COLOR_RAMP,
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/* audio test patterns*/
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DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
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DP_TEST_PATTERN_AUDIO_SAWTOOTH,
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DP_TEST_PATTERN_UNSUPPORTED
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};
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enum dp_test_pattern_color_space {
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DP_TEST_PATTERN_COLOR_SPACE_RGB,
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DP_TEST_PATTERN_COLOR_SPACE_YCBCR601,
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DP_TEST_PATTERN_COLOR_SPACE_YCBCR709,
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DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
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};
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enum dp_panel_mode {
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/* not required */
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DP_PANEL_MODE_DEFAULT,
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/* standard mode for eDP */
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DP_PANEL_MODE_EDP,
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/* external chips specific settings */
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DP_PANEL_MODE_SPECIAL
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};
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/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
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union dpcd_training_lane_set {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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uint8_t VOLTAGE_SWING_SET:2;
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uint8_t MAX_SWING_REACHED:1;
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uint8_t PRE_EMPHASIS_SET:2;
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uint8_t MAX_PRE_EMPHASIS_REACHED:1;
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/* following is reserved in DP 1.1 */
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uint8_t POST_CURSOR2_SET:2;
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#elif defined(BIGENDIAN_CPU)
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uint8_t POST_CURSOR2_SET:2;
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uint8_t MAX_PRE_EMPHASIS_REACHED:1;
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uint8_t PRE_EMPHASIS_SET:2;
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uint8_t MAX_SWING_REACHED:1;
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uint8_t VOLTAGE_SWING_SET:2;
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#else
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#error ARCH not defined!
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#endif
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} bits;
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uint8_t raw;
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};
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/* DP MST stream allocation (payload bandwidth number) */
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struct dp_mst_stream_allocation {
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uint8_t vcp_id;
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/* number of slots required for the DP stream in
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* transport packet */
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uint8_t slot_count;
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};
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/* DP MST stream allocation table */
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struct dp_mst_stream_allocation_table {
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/* number of DP video streams */
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int stream_count;
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/* array of stream allocations */
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struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
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};
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#endif /*__DAL_LINK_SERVICE_TYPES_H__*/
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