/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_HDCP_TYPES_H__
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#define __DC_HDCP_TYPES_H__
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enum hdcp_message_id {
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HDCP_MESSAGE_ID_INVALID = -1,
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/* HDCP 1.4 */
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HDCP_MESSAGE_ID_READ_BKSV = 0,
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/* HDMI is called Ri', DP is called R0' */
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HDCP_MESSAGE_ID_READ_RI_R0,
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HDCP_MESSAGE_ID_READ_PJ,
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HDCP_MESSAGE_ID_WRITE_AKSV,
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HDCP_MESSAGE_ID_WRITE_AINFO,
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HDCP_MESSAGE_ID_WRITE_AN,
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HDCP_MESSAGE_ID_READ_VH_X,
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HDCP_MESSAGE_ID_READ_VH_0,
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HDCP_MESSAGE_ID_READ_VH_1,
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HDCP_MESSAGE_ID_READ_VH_2,
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HDCP_MESSAGE_ID_READ_VH_3,
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HDCP_MESSAGE_ID_READ_VH_4,
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HDCP_MESSAGE_ID_READ_BCAPS,
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HDCP_MESSAGE_ID_READ_BSTATUS,
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HDCP_MESSAGE_ID_READ_KSV_FIFO,
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HDCP_MESSAGE_ID_READ_BINFO,
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/* HDCP 2.2 */
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HDCP_MESSAGE_ID_HDCP2VERSION,
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HDCP_MESSAGE_ID_RX_CAPS,
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HDCP_MESSAGE_ID_WRITE_AKE_INIT,
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HDCP_MESSAGE_ID_READ_AKE_SEND_CERT,
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HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM,
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HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM,
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HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME,
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HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO,
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HDCP_MESSAGE_ID_WRITE_LC_INIT,
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HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME,
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HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS,
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HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST,
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HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK,
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HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE,
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HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY,
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HDCP_MESSAGE_ID_READ_RXSTATUS,
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HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE,
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HDCP_MESSAGE_ID_MAX
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};
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enum hdcp_version {
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HDCP_Unknown = 0,
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HDCP_VERSION_14,
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HDCP_VERSION_22,
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};
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enum hdcp_link {
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HDCP_LINK_PRIMARY,
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HDCP_LINK_SECONDARY
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};
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enum hdcp_message_status {
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HDCP_MESSAGE_SUCCESS,
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HDCP_MESSAGE_FAILURE,
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HDCP_MESSAGE_UNSUPPORTED
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};
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struct hdcp_protection_message {
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enum hdcp_version version;
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/* relevant only for DVI */
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enum hdcp_link link;
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enum hdcp_message_id msg_id;
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uint32_t length;
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uint8_t max_retries;
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uint8_t *data;
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enum hdcp_message_status status;
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};
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#endif
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