/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_BIOS_PARSER_TYPES_H__
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#define __DAL_BIOS_PARSER_TYPES_H__
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#include "dm_services.h"
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#include "include/signal_types.h"
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#include "include/grph_object_ctrl_defs.h"
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#include "include/gpio_types.h"
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#include "include/link_service_types.h"
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/* TODO: include signal_types.h and remove this enum */
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enum as_signal_type {
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AS_SIGNAL_TYPE_NONE = 0L, /* no signal */
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AS_SIGNAL_TYPE_DVI,
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AS_SIGNAL_TYPE_HDMI,
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AS_SIGNAL_TYPE_LVDS,
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AS_SIGNAL_TYPE_DISPLAY_PORT,
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AS_SIGNAL_TYPE_GPU_PLL,
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AS_SIGNAL_TYPE_XGMI,
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AS_SIGNAL_TYPE_UNKNOWN
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};
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enum bp_result {
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BP_RESULT_OK = 0, /* There was no error */
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BP_RESULT_BADINPUT, /*Bad input parameter */
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BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
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BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
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BP_RESULT_NORECORD, /* Record can't be found */
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BP_RESULT_FAILURE
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};
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enum bp_encoder_control_action {
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/* direct VBIOS translation! Just to simplify the translation */
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ENCODER_CONTROL_DISABLE = 0,
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ENCODER_CONTROL_ENABLE,
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ENCODER_CONTROL_SETUP,
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ENCODER_CONTROL_INIT
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};
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enum bp_transmitter_control_action {
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/* direct VBIOS translation! Just to simplify the translation */
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TRANSMITTER_CONTROL_DISABLE = 0,
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TRANSMITTER_CONTROL_ENABLE,
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TRANSMITTER_CONTROL_BACKLIGHT_OFF,
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TRANSMITTER_CONTROL_BACKLIGHT_ON,
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TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
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TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
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TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
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TRANSMITTER_CONTROL_INIT,
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TRANSMITTER_CONTROL_DEACTIVATE,
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TRANSMITTER_CONTROL_ACTIAVATE,
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TRANSMITTER_CONTROL_SETUP,
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TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
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/* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only
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* (power up the panel)
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*/
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TRANSMITTER_CONTROL_POWER_ON,
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/* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only
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* (power down the panel)
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*/
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TRANSMITTER_CONTROL_POWER_OFF
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};
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enum bp_external_encoder_control_action {
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EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
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EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
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EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
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EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
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EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
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EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
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};
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enum bp_pipe_control_action {
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ASIC_PIPE_DISABLE = 0,
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ASIC_PIPE_ENABLE,
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ASIC_PIPE_INIT
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};
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enum bp_lvtma_control_action {
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LVTMA_CONTROL_LCD_BLOFF = 2,
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LVTMA_CONTROL_LCD_BLON = 3,
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LVTMA_CONTROL_POWER_ON = 12,
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LVTMA_CONTROL_POWER_OFF = 13
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};
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struct bp_encoder_control {
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enum bp_encoder_control_action action;
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enum engine_id engine_id;
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enum transmitter transmitter;
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enum signal_type signal;
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enum dc_lane_count lanes_number;
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enum dc_color_depth color_depth;
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bool enable_dp_audio;
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uint32_t pixel_clock; /* khz */
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};
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struct bp_external_encoder_control {
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enum bp_external_encoder_control_action action;
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enum engine_id engine_id;
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enum dc_link_rate link_rate;
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enum dc_lane_count lanes_number;
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enum signal_type signal;
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enum dc_color_depth color_depth;
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bool coherent;
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struct graphics_object_id encoder_id;
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struct graphics_object_id connector_obj_id;
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uint32_t pixel_clock; /* in KHz */
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};
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struct bp_crtc_source_select {
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enum engine_id engine_id;
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enum controller_id controller_id;
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/* from GPU Tx aka asic_signal */
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enum signal_type signal;
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/* sink_signal may differ from asicSignal if Translator encoder */
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enum signal_type sink_signal;
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enum display_output_bit_depth display_output_bit_depth;
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bool enable_dp_audio;
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};
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struct bp_transmitter_control {
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enum bp_transmitter_control_action action;
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enum engine_id engine_id;
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enum transmitter transmitter; /* PhyId */
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enum dc_lane_count lanes_number;
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enum clock_source_id pll_id; /* needed for DCE 4.0 */
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enum signal_type signal;
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enum dc_color_depth color_depth; /* not used for DCE6.0 */
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enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
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struct graphics_object_id connector_obj_id;
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/* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
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* be pixel clock * deep_color_ratio (in KHz)
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*/
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uint32_t pixel_clock;
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uint32_t lane_select;
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uint32_t lane_settings;
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bool coherent;
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bool multi_path;
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bool single_pll_mode;
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};
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struct bp_hw_crtc_timing_parameters {
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enum controller_id controller_id;
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/* horizontal part */
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uint32_t h_total;
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uint32_t h_addressable;
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uint32_t h_overscan_left;
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uint32_t h_overscan_right;
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uint32_t h_sync_start;
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uint32_t h_sync_width;
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/* vertical part */
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uint32_t v_total;
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uint32_t v_addressable;
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uint32_t v_overscan_top;
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uint32_t v_overscan_bottom;
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uint32_t v_sync_start;
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uint32_t v_sync_width;
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struct timing_flags {
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uint32_t INTERLACE:1;
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uint32_t PIXEL_REPETITION:4;
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uint32_t HSYNC_POSITIVE_POLARITY:1;
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uint32_t VSYNC_POSITIVE_POLARITY:1;
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uint32_t HORZ_COUNT_BY_TWO:1;
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} flags;
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};
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struct bp_adjust_pixel_clock_parameters {
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/* Input: Signal Type - to be converted to Encoder mode */
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enum signal_type signal_type;
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/* Input: Encoder object id */
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struct graphics_object_id encoder_object_id;
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/* Input: Pixel Clock (requested Pixel clock based on Video timing
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* standard used) in KHz
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*/
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uint32_t pixel_clock;
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/* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
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uint32_t adjusted_pixel_clock;
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/* Output: If non-zero, this refDiv value should be used to calculate
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* other ppll params */
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uint32_t reference_divider;
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/* Output: If non-zero, this postDiv value should be used to calculate
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* other ppll params */
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uint32_t pixel_clock_post_divider;
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/* Input: Enable spread spectrum */
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bool ss_enable;
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};
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struct bp_pixel_clock_parameters {
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enum controller_id controller_id; /* (Which CRTC uses this PLL) */
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enum clock_source_id pll_id; /* Clock Source Id */
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/* signal_type -> Encoder Mode - needed by VBIOS Exec table */
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enum signal_type signal_type;
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/* Adjusted Pixel Clock (after VBIOS exec table)
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* that becomes Target Pixel Clock (100 Hz units) */
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uint32_t target_pixel_clock_100hz;
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/* Calculated Reference divider of Display PLL */
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uint32_t reference_divider;
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/* Calculated Feedback divider of Display PLL */
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uint32_t feedback_divider;
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/* Calculated Fractional Feedback divider of Display PLL */
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uint32_t fractional_feedback_divider;
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/* Calculated Pixel Clock Post divider of Display PLL */
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uint32_t pixel_clock_post_divider;
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struct graphics_object_id encoder_object_id; /* Encoder object id */
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/* VBIOS returns a fixed display clock when DFS-bypass feature
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* is enabled (KHz) */
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uint32_t dfs_bypass_display_clock;
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/* color depth to support HDMI deep color */
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enum transmitter_color_depth color_depth;
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struct program_pixel_clock_flags {
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uint32_t FORCE_PROGRAMMING_OF_PLL:1;
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/* Use Engine Clock as source for Display Clock when
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* programming PLL */
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uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
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/* Use external reference clock (refDivSrc for PLL) */
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uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
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/* Use DFS bypass for Display clock. */
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uint32_t SET_DISPCLK_DFS_BYPASS:1;
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/* Force program PHY PLL only */
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uint32_t PROGRAM_PHY_PLL_ONLY:1;
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/* Support for YUV420 */
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uint32_t SUPPORT_YUV_420:1;
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/* Use XTALIN reference clock source */
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uint32_t SET_XTALIN_REF_SRC:1;
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/* Use GENLK reference clock source */
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uint32_t SET_GENLOCK_REF_DIV_SRC:1;
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} flags;
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};
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enum bp_dce_clock_type {
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DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
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DCECLOCK_TYPE_DPREFCLK = 1
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};
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/* DCE Clock Parameters structure for SetDceClock Exec command table */
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struct bp_set_dce_clock_parameters {
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enum clock_source_id pll_id; /* Clock Source Id */
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/* Display clock or DPREFCLK value */
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uint32_t target_clock_frequency;
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/* Clock to set: =0: DISPCLK =1: DPREFCLK =2: PIXCLK */
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enum bp_dce_clock_type clock_type;
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struct set_dce_clock_flags {
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uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
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/* Use XTALIN reference clock source */
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uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
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/* Use PCIE reference clock source */
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uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
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/* Use GENLK reference clock source */
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uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
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} flags;
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};
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struct spread_spectrum_flags {
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/* 1 = Center Spread; 0 = down spread */
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uint32_t CENTER_SPREAD:1;
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/* 1 = external; 0 = internal */
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uint32_t EXTERNAL_SS:1;
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/* 1 = delta-sigma type parameter; 0 = ver1 */
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uint32_t DS_TYPE:1;
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};
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struct bp_spread_spectrum_parameters {
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enum clock_source_id pll_id;
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uint32_t percentage;
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uint32_t ds_frac_amount;
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union {
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struct {
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uint32_t step;
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uint32_t delay;
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uint32_t range; /* In Hz unit */
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} ver1;
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struct {
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uint32_t feedback_amount;
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uint32_t nfrac_amount;
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uint32_t ds_frac_size;
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} ds;
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};
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struct spread_spectrum_flags flags;
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};
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struct bp_encoder_cap_info {
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uint32_t DP_HBR2_CAP:1;
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uint32_t DP_HBR2_EN:1;
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uint32_t DP_HBR3_EN:1;
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uint32_t HDMI_6GB_EN:1;
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uint32_t DP_IS_USB_C:1;
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uint32_t RESERVED:27;
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};
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struct bp_soc_bb_info {
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uint32_t dram_clock_change_latency_100ns;
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uint32_t dram_sr_exit_latency_100ns;
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uint32_t dram_sr_enter_exit_latency_100ns;
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};
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#endif /*__DAL_BIOS_PARSER_TYPES_H__ */
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