/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DC_DP_TYPES_H
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#define DC_DP_TYPES_H
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#include "os_types.h"
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enum dc_lane_count {
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LANE_COUNT_UNKNOWN = 0,
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LANE_COUNT_ONE = 1,
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LANE_COUNT_TWO = 2,
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LANE_COUNT_FOUR = 4,
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LANE_COUNT_EIGHT = 8,
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LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
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};
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/* This is actually a reference clock (27MHz) multiplier
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* 162MBps bandwidth for 1.62GHz like rate,
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* 270MBps for 2.70GHz,
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* 324MBps for 3.24Ghz,
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* 540MBps for 5.40GHz
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* 810MBps for 8.10GHz
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*/
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enum dc_link_rate {
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LINK_RATE_UNKNOWN = 0,
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LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
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LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
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LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
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LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
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LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane
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LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
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LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane
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LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane
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};
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enum dc_link_spread {
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LINK_SPREAD_DISABLED = 0x00,
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/* 0.5 % downspread 30 kHz */
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LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
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/* 0.5 % downspread 33 kHz */
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LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
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};
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enum dc_voltage_swing {
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VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */
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VOLTAGE_SWING_LEVEL1,
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VOLTAGE_SWING_LEVEL2,
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VOLTAGE_SWING_LEVEL3,
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VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
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};
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enum dc_pre_emphasis {
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PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */
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PRE_EMPHASIS_LEVEL1,
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PRE_EMPHASIS_LEVEL2,
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PRE_EMPHASIS_LEVEL3,
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PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
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};
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/* Post Cursor 2 is optional for transmitter
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* and it applies only to the main link operating at HBR2
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*/
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enum dc_post_cursor2 {
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POST_CURSOR2_DISABLED = 0, /* direct HW translation! */
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POST_CURSOR2_LEVEL1,
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POST_CURSOR2_LEVEL2,
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POST_CURSOR2_LEVEL3,
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POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
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};
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enum dc_dp_training_pattern {
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DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
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DP_TRAINING_PATTERN_SEQUENCE_2,
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DP_TRAINING_PATTERN_SEQUENCE_3,
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DP_TRAINING_PATTERN_SEQUENCE_4,
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};
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struct dc_link_settings {
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enum dc_lane_count lane_count;
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enum dc_link_rate link_rate;
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enum dc_link_spread link_spread;
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bool use_link_rate_set;
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uint8_t link_rate_set;
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};
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struct dc_lane_settings {
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enum dc_voltage_swing VOLTAGE_SWING;
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enum dc_pre_emphasis PRE_EMPHASIS;
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enum dc_post_cursor2 POST_CURSOR2;
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};
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struct dc_link_training_settings {
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struct dc_link_settings link;
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struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
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};
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struct dc_link_training_overrides {
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enum dc_voltage_swing *voltage_swing;
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enum dc_pre_emphasis *pre_emphasis;
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enum dc_post_cursor2 *post_cursor2;
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uint16_t *cr_pattern_time;
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uint16_t *eq_pattern_time;
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enum dc_dp_training_pattern *pattern_for_cr;
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enum dc_dp_training_pattern *pattern_for_eq;
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enum dc_link_spread *downspread;
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bool *alternate_scrambler_reset;
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bool *enhanced_framing;
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bool *mst_enable;
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bool *fec_enable;
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};
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union dpcd_rev {
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struct {
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uint8_t MINOR:4;
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uint8_t MAJOR:4;
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} bits;
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uint8_t raw;
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};
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union max_lane_count {
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struct {
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uint8_t MAX_LANE_COUNT:5;
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uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
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uint8_t TPS3_SUPPORTED:1;
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uint8_t ENHANCED_FRAME_CAP:1;
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} bits;
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uint8_t raw;
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};
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union max_down_spread {
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struct {
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uint8_t MAX_DOWN_SPREAD:1;
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uint8_t RESERVED:5;
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uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
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uint8_t TPS4_SUPPORTED:1;
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} bits;
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uint8_t raw;
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};
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union mstm_cap {
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struct {
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uint8_t MST_CAP:1;
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uint8_t RESERVED:7;
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} bits;
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uint8_t raw;
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};
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union lane_count_set {
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struct {
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uint8_t LANE_COUNT_SET:5;
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uint8_t POST_LT_ADJ_REQ_GRANTED:1;
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uint8_t RESERVED:1;
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uint8_t ENHANCED_FRAMING:1;
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} bits;
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uint8_t raw;
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};
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union lane_status {
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struct {
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uint8_t CR_DONE_0:1;
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uint8_t CHANNEL_EQ_DONE_0:1;
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uint8_t SYMBOL_LOCKED_0:1;
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uint8_t RESERVED0:1;
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uint8_t CR_DONE_1:1;
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uint8_t CHANNEL_EQ_DONE_1:1;
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uint8_t SYMBOL_LOCKED_1:1;
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uint8_t RESERVED_1:1;
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} bits;
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uint8_t raw;
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};
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union device_service_irq {
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struct {
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uint8_t REMOTE_CONTROL_CMD_PENDING:1;
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uint8_t AUTOMATED_TEST:1;
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uint8_t CP_IRQ:1;
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uint8_t MCCS_IRQ:1;
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uint8_t DOWN_REP_MSG_RDY:1;
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uint8_t UP_REQ_MSG_RDY:1;
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uint8_t SINK_SPECIFIC:1;
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uint8_t reserved:1;
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} bits;
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uint8_t raw;
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};
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union sink_count {
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struct {
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uint8_t SINK_COUNT:6;
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uint8_t CPREADY:1;
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uint8_t RESERVED:1;
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} bits;
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uint8_t raw;
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};
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union lane_align_status_updated {
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struct {
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uint8_t INTERLANE_ALIGN_DONE:1;
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uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
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uint8_t RESERVED:4;
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uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
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uint8_t LINK_STATUS_UPDATED:1;
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} bits;
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uint8_t raw;
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};
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union lane_adjust {
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struct {
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uint8_t VOLTAGE_SWING_LANE:2;
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uint8_t PRE_EMPHASIS_LANE:2;
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uint8_t RESERVED:4;
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} bits;
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uint8_t raw;
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};
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union dpcd_training_pattern {
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struct {
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uint8_t TRAINING_PATTERN_SET:4;
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uint8_t RECOVERED_CLOCK_OUT_EN:1;
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uint8_t SCRAMBLING_DISABLE:1;
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uint8_t SYMBOL_ERROR_COUNT_SEL:2;
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} v1_4;
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struct {
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uint8_t TRAINING_PATTERN_SET:2;
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uint8_t LINK_QUAL_PATTERN_SET:2;
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uint8_t RESERVED:4;
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} v1_3;
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uint8_t raw;
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};
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/* Training Lane is used to configure downstream DP device's voltage swing
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and pre-emphasis levels*/
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/* The DPCD addresses are from 0x103 to 0x106*/
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union dpcd_training_lane {
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struct {
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uint8_t VOLTAGE_SWING_SET:2;
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uint8_t MAX_SWING_REACHED:1;
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uint8_t PRE_EMPHASIS_SET:2;
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uint8_t MAX_PRE_EMPHASIS_REACHED:1;
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uint8_t RESERVED:2;
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} bits;
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uint8_t raw;
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};
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/* TMDS-converter related */
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union dwnstream_port_caps_byte0 {
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struct {
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uint8_t DWN_STRM_PORTX_TYPE:3;
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uint8_t DWN_STRM_PORTX_HPD:1;
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uint8_t RESERVERD:4;
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} bits;
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uint8_t raw;
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};
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/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
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enum dpcd_downstream_port_detailed_type {
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DOWN_STREAM_DETAILED_DP = 0,
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DOWN_STREAM_DETAILED_VGA,
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DOWN_STREAM_DETAILED_DVI,
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DOWN_STREAM_DETAILED_HDMI,
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DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
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DOWN_STREAM_DETAILED_DP_PLUS_PLUS
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};
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union dwnstream_port_caps_byte2 {
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struct {
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uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
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uint8_t RESERVED:6;
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} bits;
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uint8_t raw;
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};
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union dp_downstream_port_present {
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uint8_t byte;
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struct {
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uint8_t PORT_PRESENT:1;
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uint8_t PORT_TYPE:2;
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uint8_t FMT_CONVERSION:1;
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uint8_t DETAILED_CAPS:1;
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uint8_t RESERVED:3;
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} fields;
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};
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union dwnstream_port_caps_byte3_dvi {
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struct {
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uint8_t RESERVED1:1;
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uint8_t DUAL_LINK:1;
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uint8_t HIGH_COLOR_DEPTH:1;
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uint8_t RESERVED2:5;
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} bits;
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uint8_t raw;
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};
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union dwnstream_port_caps_byte3_hdmi {
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struct {
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uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
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uint8_t YCrCr422_PASS_THROUGH:1;
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uint8_t YCrCr420_PASS_THROUGH:1;
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uint8_t YCrCr422_CONVERSION:1;
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uint8_t YCrCr420_CONVERSION:1;
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uint8_t RESERVED:3;
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} bits;
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uint8_t raw;
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};
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/*4-byte structure for detailed capabilities of a down-stream port
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(DP-to-TMDS converter).*/
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union dwnstream_portxcaps {
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struct {
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union dwnstream_port_caps_byte0 byte0;
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unsigned char max_TMDS_clock; //byte1
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union dwnstream_port_caps_byte2 byte2;
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union {
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union dwnstream_port_caps_byte3_dvi byteDVI;
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union dwnstream_port_caps_byte3_hdmi byteHDMI;
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} byte3;
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} bytes;
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unsigned char raw[4];
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};
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union downstream_port {
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struct {
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unsigned char present:1;
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unsigned char type:2;
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unsigned char format_conv:1;
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unsigned char detailed_caps:1;
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unsigned char reserved:3;
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} bits;
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unsigned char raw;
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};
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union sink_status {
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struct {
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uint8_t RX_PORT0_STATUS:1;
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uint8_t RX_PORT1_STATUS:1;
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uint8_t RESERVED:6;
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} bits;
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uint8_t raw;
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};
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/*6-byte structure corresponding to 6 registers (200h-205h)
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read during handling of HPD-IRQ*/
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union hpd_irq_data {
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struct {
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union sink_count sink_cnt;/* 200h */
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union device_service_irq device_service_irq;/* 201h */
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union lane_status lane01_status;/* 202h */
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union lane_status lane23_status;/* 203h */
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union lane_align_status_updated lane_status_updated;/* 204h */
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union sink_status sink_status;
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} bytes;
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uint8_t raw[6];
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};
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union down_stream_port_count {
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struct {
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uint8_t DOWN_STR_PORT_COUNT:4;
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uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
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/*Bit 6 = MSA_TIMING_PAR_IGNORED
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0 = Sink device requires the MSA timing parameters
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1 = Sink device is capable of rendering incoming video
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stream without MSA timing parameters*/
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uint8_t IGNORE_MSA_TIMING_PARAM:1;
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/*Bit 7 = OUI Support
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0 = OUI not supported
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1 = OUI supported
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(OUI and Device Identification mandatory for DP 1.2)*/
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uint8_t OUI_SUPPORT:1;
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} bits;
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uint8_t raw;
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};
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union down_spread_ctrl {
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struct {
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uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
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/* Bits 4 = SPREAD_AMP. Spreading amplitude
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0 = Main link signal is not downspread
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1 = Main link signal is downspread <= 0.5%
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with frequency in the range of 30kHz ~ 33kHz*/
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uint8_t SPREAD_AMP:1;
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uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
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/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
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0 = Source device will send valid data for the MSA Timing Params
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1 = Source device may send invalid data for these MSA Timing Params*/
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uint8_t IGNORE_MSA_TIMING_PARAM:1;
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} bits;
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uint8_t raw;
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};
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union dpcd_edp_config {
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struct {
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uint8_t PANEL_MODE_EDP:1;
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uint8_t FRAMING_CHANGE_ENABLE:1;
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uint8_t RESERVED:5;
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uint8_t PANEL_SELF_TEST_ENABLE:1;
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} bits;
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uint8_t raw;
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};
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struct dp_device_vendor_id {
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uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
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uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
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};
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struct dp_sink_hw_fw_revision {
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uint8_t ieee_hw_rev;
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uint8_t ieee_fw_rev[2];
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};
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struct dpcd_vendor_signature {
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bool is_valid;
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union dpcd_ieee_vendor_signature {
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struct {
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uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
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uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
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uint8_t ieee_hw_rev;
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uint8_t ieee_fw_rev[2];
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};
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uint8_t raw[12];
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} data;
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};
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struct dpcd_amd_signature {
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uint8_t AMD_IEEE_TxSignature_byte1;
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uint8_t AMD_IEEE_TxSignature_byte2;
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uint8_t AMD_IEEE_TxSignature_byte3;
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uint8_t device_id_byte1;
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uint8_t device_id_byte2;
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uint8_t zero[4];
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uint8_t dce_version;
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uint8_t dal_version_byte1;
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uint8_t dal_version_byte2;
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};
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struct dpcd_source_backlight_set {
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struct {
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uint8_t byte0;
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uint8_t byte1;
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uint8_t byte2;
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uint8_t byte3;
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} backlight_level_millinits;
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struct {
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uint8_t byte0;
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uint8_t byte1;
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} backlight_transition_time_ms;
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};
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union dpcd_source_backlight_get {
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struct {
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uint32_t backlight_millinits_peak; /* 326h */
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uint32_t backlight_millinits_avg; /* 32Ah */
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} bytes;
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uint8_t raw[8];
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};
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/*DPCD register of DP receiver capability field bits-*/
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union edp_configuration_cap {
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struct {
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uint8_t ALT_SCRAMBLER_RESET:1;
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uint8_t FRAMING_CHANGE:1;
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uint8_t RESERVED:1;
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uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
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uint8_t RESERVED2:4;
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} bits;
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uint8_t raw;
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};
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union dprx_feature {
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struct {
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uint8_t GTC_CAP:1; // bit 0: DP 1.3+
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uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4
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uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+
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uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+
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uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4
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uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
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uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4
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uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4
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} bits;
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uint8_t raw;
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};
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union training_aux_rd_interval {
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struct {
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uint8_t TRAINIG_AUX_RD_INTERVAL:7;
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uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
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} bits;
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uint8_t raw;
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};
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/* Automated test structures */
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union test_request {
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struct {
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uint8_t LINK_TRAINING :1;
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uint8_t LINK_TEST_PATTRN :1;
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uint8_t EDID_READ :1;
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uint8_t PHY_TEST_PATTERN :1;
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uint8_t RESERVED :1;
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uint8_t AUDIO_TEST_PATTERN :1;
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uint8_t TEST_AUDIO_DISABLED_VIDEO :1;
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} bits;
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uint8_t raw;
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};
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union test_response {
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struct {
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uint8_t ACK :1;
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uint8_t NO_ACK :1;
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uint8_t EDID_CHECKSUM_WRITE:1;
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uint8_t RESERVED :5;
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} bits;
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uint8_t raw;
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};
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union phy_test_pattern {
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struct {
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/* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
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* and 3 bits for DP1.2.
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*/
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uint8_t PATTERN :3;
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/* BY speci, bit7:2 is 0 for DP1.1. */
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uint8_t RESERVED :5;
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} bits;
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uint8_t raw;
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};
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/* States of Compliance Test Specification (CTS DP1.2). */
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union compliance_test_state {
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struct {
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unsigned char STEREO_3D_RUNNING : 1;
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unsigned char RESERVED : 7;
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} bits;
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unsigned char raw;
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};
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union link_test_pattern {
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struct {
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/* dpcd_link_test_patterns */
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unsigned char PATTERN :2;
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unsigned char RESERVED:6;
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} bits;
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unsigned char raw;
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};
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union test_misc {
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struct dpcd_test_misc_bits {
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unsigned char SYNC_CLOCK :1;
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/* dpcd_test_color_format */
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unsigned char CLR_FORMAT :2;
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/* dpcd_test_dyn_range */
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unsigned char DYN_RANGE :1;
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unsigned char YCBCR_COEFS :1;
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/* dpcd_test_bit_depth */
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unsigned char BPC :3;
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} bits;
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unsigned char raw;
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};
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union audio_test_mode {
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struct {
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unsigned char sampling_rate :4;
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unsigned char channel_count :4;
|
} bits;
|
unsigned char raw;
|
};
|
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union audio_test_pattern_period {
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struct {
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unsigned char pattern_period :4;
|
unsigned char reserved :4;
|
} bits;
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unsigned char raw;
|
};
|
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struct audio_test_pattern_type {
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unsigned char value;
|
};
|
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struct dp_audio_test_data_flags {
|
uint8_t test_requested :1;
|
uint8_t disable_video :1;
|
};
|
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struct dp_audio_test_data {
|
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struct dp_audio_test_data_flags flags;
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uint8_t sampling_rate;
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uint8_t channel_count;
|
uint8_t pattern_type;
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uint8_t pattern_period[8];
|
};
|
|
/* FEC capability DPCD register field bits-*/
|
union dpcd_fec_capability {
|
struct {
|
uint8_t FEC_CAPABLE:1;
|
uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
|
uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
|
uint8_t BIT_ERROR_COUNT_CAPABLE:1;
|
uint8_t RESERVED:4;
|
} bits;
|
uint8_t raw;
|
};
|
|
/* DSC capability DPCD register field bits-*/
|
struct dpcd_dsc_support {
|
uint8_t DSC_SUPPORT :1;
|
uint8_t DSC_PASSTHROUGH_SUPPORT :1;
|
uint8_t RESERVED :6;
|
};
|
|
struct dpcd_dsc_algorithm_revision {
|
uint8_t DSC_VERSION_MAJOR :4;
|
uint8_t DSC_VERSION_MINOR :4;
|
};
|
|
struct dpcd_dsc_rc_buffer_block_size {
|
uint8_t RC_BLOCK_BUFFER_SIZE :2;
|
uint8_t RESERVED :6;
|
};
|
|
struct dpcd_dsc_slice_capability1 {
|
uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1;
|
uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1;
|
uint8_t RESERVED :1;
|
uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1;
|
uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1;
|
uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1;
|
uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1;
|
uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1;
|
};
|
|
struct dpcd_dsc_line_buffer_bit_depth {
|
uint8_t LINE_BUFFER_BIT_DEPTH :4;
|
uint8_t RESERVED :4;
|
};
|
|
struct dpcd_dsc_block_prediction_support {
|
uint8_t BLOCK_PREDICTION_SUPPORT:1;
|
uint8_t RESERVED :7;
|
};
|
|
struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
|
uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7;
|
uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7;
|
uint8_t RESERVED :2;
|
};
|
|
struct dpcd_dsc_decoder_color_format_capabilities {
|
uint8_t RGB_SUPPORT :1;
|
uint8_t Y_CB_CR_444_SUPPORT :1;
|
uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1;
|
uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1;
|
uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1;
|
uint8_t RESERVED :3;
|
};
|
|
struct dpcd_dsc_decoder_color_depth_capabilities {
|
uint8_t RESERVED0 :1;
|
uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1;
|
uint8_t TEN_BITS_PER_COLOR_SUPPORT :1;
|
uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1;
|
uint8_t RESERVED1 :4;
|
};
|
|
struct dpcd_peak_dsc_throughput_dsc_sink {
|
uint8_t THROUGHPUT_MODE_0:4;
|
uint8_t THROUGHPUT_MODE_1:4;
|
};
|
|
struct dpcd_dsc_slice_capabilities_2 {
|
uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1;
|
uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1;
|
uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1;
|
uint8_t RESERVED :5;
|
};
|
|
struct dpcd_bits_per_pixel_increment{
|
uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3;
|
uint8_t RESERVED :5;
|
};
|
union dpcd_dsc_basic_capabilities {
|
struct {
|
struct dpcd_dsc_support dsc_support;
|
struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
|
struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
|
uint8_t dsc_rc_buffer_size;
|
struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
|
struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
|
struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
|
struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
|
struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
|
struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
|
struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
|
uint8_t dsc_maximum_slice_width;
|
struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
|
uint8_t reserved;
|
struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
|
} fields;
|
uint8_t raw[16];
|
};
|
|
union dpcd_dsc_branch_decoder_capabilities {
|
struct {
|
uint8_t BRANCH_OVERALL_THROUGHPUT_0;
|
uint8_t BRANCH_OVERALL_THROUGHPUT_1;
|
uint8_t BRANCH_MAX_LINE_WIDTH;
|
} fields;
|
uint8_t raw[3];
|
};
|
|
struct dpcd_dsc_capabilities {
|
union dpcd_dsc_basic_capabilities dsc_basic_caps;
|
union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps;
|
};
|
|
/* These parameters are from PSR capabilities reported by Sink DPCD */
|
struct psr_caps {
|
unsigned char psr_version;
|
unsigned int psr_rfb_setup_time;
|
bool psr_exit_link_training_required;
|
};
|
|
#endif /* DC_DP_TYPES_H */
|
