/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "dm_services.h"
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#include "basics/dc_common.h"
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#include "dc.h"
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#include "core_types.h"
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#include "resource.h"
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#include "ipp.h"
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#include "timing_generator.h"
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#define DC_LOGGER dc->ctx->logger
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/*******************************************************************************
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* Private functions
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******************************************************************************/
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void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
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{
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if (sink->sink_signal == SIGNAL_TYPE_NONE)
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stream->signal = stream->link->connector_signal;
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else
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stream->signal = sink->sink_signal;
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if (dc_is_dvi_signal(stream->signal)) {
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if (stream->ctx->dc->caps.dual_link_dvi &&
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(stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
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sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
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stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
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else
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stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
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}
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}
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static bool dc_stream_construct(struct dc_stream_state *stream,
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struct dc_sink *dc_sink_data)
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{
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uint32_t i = 0;
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stream->sink = dc_sink_data;
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dc_sink_retain(dc_sink_data);
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stream->ctx = dc_sink_data->ctx;
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stream->link = dc_sink_data->link;
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stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
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stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
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stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
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stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
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/* Copy audio modes */
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/* TODO - Remove this translation */
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for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
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{
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stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
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stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
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stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
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stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
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}
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stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
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stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
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stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
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memmove(
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stream->audio_info.display_name,
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dc_sink_data->edid_caps.display_name,
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AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
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stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
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stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
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stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
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if (dc_sink_data->dc_container_id != NULL) {
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struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
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stream->audio_info.port_id[0] = dc_container_id->portId[0];
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stream->audio_info.port_id[1] = dc_container_id->portId[1];
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} else {
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/* TODO - WindowDM has implemented,
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other DMs need Unhardcode port_id */
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stream->audio_info.port_id[0] = 0x5558859e;
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stream->audio_info.port_id[1] = 0xd989449;
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}
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/* EDID CAP translation for HDMI 2.0 */
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stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
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memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
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stream->timing.dsc_cfg.num_slices_h = 0;
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stream->timing.dsc_cfg.num_slices_v = 0;
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stream->timing.dsc_cfg.bits_per_pixel = 128;
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stream->timing.dsc_cfg.block_pred_enable = 1;
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stream->timing.dsc_cfg.linebuf_depth = 9;
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stream->timing.dsc_cfg.version_minor = 2;
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stream->timing.dsc_cfg.ycbcr422_simple = 0;
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update_stream_signal(stream, dc_sink_data);
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stream->out_transfer_func = dc_create_transfer_func();
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if (stream->out_transfer_func == NULL) {
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dc_sink_release(dc_sink_data);
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return false;
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}
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stream->out_transfer_func->type = TF_TYPE_BYPASS;
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stream->stream_id = stream->ctx->dc_stream_id_count;
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stream->ctx->dc_stream_id_count++;
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return true;
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}
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static void dc_stream_destruct(struct dc_stream_state *stream)
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{
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dc_sink_release(stream->sink);
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if (stream->out_transfer_func != NULL) {
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dc_transfer_func_release(stream->out_transfer_func);
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stream->out_transfer_func = NULL;
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}
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}
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void dc_stream_retain(struct dc_stream_state *stream)
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{
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kref_get(&stream->refcount);
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}
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static void dc_stream_free(struct kref *kref)
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{
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struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
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dc_stream_destruct(stream);
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kfree(stream);
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}
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void dc_stream_release(struct dc_stream_state *stream)
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{
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if (stream != NULL) {
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kref_put(&stream->refcount, dc_stream_free);
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}
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}
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struct dc_stream_state *dc_create_stream_for_sink(
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struct dc_sink *sink)
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{
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struct dc_stream_state *stream;
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if (sink == NULL)
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return NULL;
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stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
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if (stream == NULL)
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goto alloc_fail;
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if (dc_stream_construct(stream, sink) == false)
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goto construct_fail;
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kref_init(&stream->refcount);
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return stream;
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construct_fail:
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kfree(stream);
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alloc_fail:
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return NULL;
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}
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struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
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{
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struct dc_stream_state *new_stream;
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new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL);
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if (!new_stream)
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return NULL;
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if (new_stream->sink)
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dc_sink_retain(new_stream->sink);
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if (new_stream->out_transfer_func)
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dc_transfer_func_retain(new_stream->out_transfer_func);
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new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
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new_stream->ctx->dc_stream_id_count++;
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kref_init(&new_stream->refcount);
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return new_stream;
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}
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/**
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* dc_stream_get_status_from_state - Get stream status from given dc state
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* @state: DC state to find the stream status in
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* @stream: The stream to get the stream status for
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*
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* The given stream is expected to exist in the given dc state. Otherwise, NULL
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* will be returned.
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*/
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struct dc_stream_status *dc_stream_get_status_from_state(
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struct dc_state *state,
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struct dc_stream_state *stream)
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{
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uint8_t i;
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for (i = 0; i < state->stream_count; i++) {
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if (stream == state->streams[i])
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return &state->stream_status[i];
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}
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return NULL;
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}
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/**
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* dc_stream_get_status() - Get current stream status of the given stream state
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* @stream: The stream to get the stream status for.
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*
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* The given stream is expected to exist in dc->current_state. Otherwise, NULL
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* will be returned.
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*/
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struct dc_stream_status *dc_stream_get_status(
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struct dc_stream_state *stream)
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{
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struct dc *dc = stream->ctx->dc;
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return dc_stream_get_status_from_state(dc->current_state, stream);
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}
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#ifndef TRIM_FSFT
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/**
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* dc_optimize_timing_for_fsft() - dc to optimize timing
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*/
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bool dc_optimize_timing_for_fsft(
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struct dc_stream_state *pStream,
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unsigned int max_input_rate_in_khz)
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{
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struct dc *dc;
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dc = pStream->ctx->dc;
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return (dc->hwss.optimize_timing_for_fsft &&
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dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz));
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}
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#endif
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/**
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* dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
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*/
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bool dc_stream_set_cursor_attributes(
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struct dc_stream_state *stream,
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const struct dc_cursor_attributes *attributes)
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{
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int i;
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struct dc *dc;
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struct resource_context *res_ctx;
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struct pipe_ctx *pipe_to_program = NULL;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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bool reset_idle_optimizations = false;
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#endif
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if (NULL == stream) {
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dm_error("DC: dc_stream is NULL!\n");
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return false;
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}
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if (NULL == attributes) {
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dm_error("DC: attributes is NULL!\n");
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return false;
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}
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if (attributes->address.quad_part == 0) {
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dm_output_to_console("DC: Cursor address is 0!\n");
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return false;
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}
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dc = stream->ctx->dc;
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res_ctx = &dc->current_state->res_ctx;
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stream->cursor_attributes = *attributes;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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/* disable idle optimizations while updating cursor */
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if (dc->idle_optimizations_allowed) {
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dc_allow_idle_optimizations(dc, false);
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reset_idle_optimizations = true;
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}
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#endif
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for (i = 0; i < MAX_PIPES; i++) {
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struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
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if (pipe_ctx->stream != stream)
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continue;
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if (!pipe_to_program) {
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pipe_to_program = pipe_ctx;
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dc->hwss.cursor_lock(dc, pipe_to_program, true);
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}
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dc->hwss.set_cursor_attribute(pipe_ctx);
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if (dc->hwss.set_cursor_sdr_white_level)
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dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
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}
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if (pipe_to_program)
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dc->hwss.cursor_lock(dc, pipe_to_program, false);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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/* re-enable idle optimizations if necessary */
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if (reset_idle_optimizations)
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dc_allow_idle_optimizations(dc, true);
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#endif
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return true;
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}
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bool dc_stream_set_cursor_position(
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struct dc_stream_state *stream,
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const struct dc_cursor_position *position)
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{
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int i;
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struct dc *dc;
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struct resource_context *res_ctx;
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struct pipe_ctx *pipe_to_program = NULL;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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bool reset_idle_optimizations = false;
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#endif
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if (NULL == stream) {
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dm_error("DC: dc_stream is NULL!\n");
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return false;
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}
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if (NULL == position) {
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dm_error("DC: cursor position is NULL!\n");
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return false;
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}
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dc = stream->ctx->dc;
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res_ctx = &dc->current_state->res_ctx;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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/* disable idle optimizations if enabling cursor */
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if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
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dc_allow_idle_optimizations(dc, false);
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reset_idle_optimizations = true;
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}
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#endif
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stream->cursor_position = *position;
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for (i = 0; i < MAX_PIPES; i++) {
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struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
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if (pipe_ctx->stream != stream ||
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(!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) ||
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!pipe_ctx->plane_state ||
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(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
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(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
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continue;
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if (!pipe_to_program) {
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pipe_to_program = pipe_ctx;
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dc->hwss.cursor_lock(dc, pipe_to_program, true);
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}
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dc->hwss.set_cursor_position(pipe_ctx);
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}
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if (pipe_to_program)
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dc->hwss.cursor_lock(dc, pipe_to_program, false);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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/* re-enable idle optimizations if necessary */
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if (reset_idle_optimizations)
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dc_allow_idle_optimizations(dc, true);
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#endif
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return true;
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}
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bool dc_stream_add_writeback(struct dc *dc,
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struct dc_stream_state *stream,
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struct dc_writeback_info *wb_info)
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{
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bool isDrc = false;
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int i = 0;
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struct dwbc *dwb;
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if (stream == NULL) {
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dm_error("DC: dc_stream is NULL!\n");
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return false;
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}
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if (wb_info == NULL) {
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dm_error("DC: dc_writeback_info is NULL!\n");
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return false;
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}
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if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
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dm_error("DC: writeback pipe is invalid!\n");
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return false;
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}
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wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
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dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
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dwb->dwb_is_drc = false;
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/* recalculate and apply DML parameters */
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for (i = 0; i < stream->num_wb_info; i++) {
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/*dynamic update*/
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if (stream->writeback_info[i].wb_enabled &&
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stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
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stream->writeback_info[i] = *wb_info;
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isDrc = true;
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}
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}
|
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if (!isDrc) {
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stream->writeback_info[stream->num_wb_info++] = *wb_info;
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}
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if (dc->hwss.enable_writeback) {
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struct dc_stream_status *stream_status = dc_stream_get_status(stream);
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struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
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dwb->otg_inst = stream_status->primary_otg_inst;
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}
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if (IS_DIAG_DC(dc->ctx->dce_environment)) {
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if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
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dm_error("DC: update_bandwidth failed!\n");
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return false;
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}
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/* enable writeback */
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if (dc->hwss.enable_writeback) {
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struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
|
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if (dwb->funcs->is_enabled(dwb)) {
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/* writeback pipe already enabled, only need to update */
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dc->hwss.update_writeback(dc, wb_info, dc->current_state);
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} else {
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/* Enable writeback pipe from scratch*/
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dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
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}
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}
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}
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return true;
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}
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bool dc_stream_remove_writeback(struct dc *dc,
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struct dc_stream_state *stream,
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uint32_t dwb_pipe_inst)
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{
|
int i = 0, j = 0;
|
if (stream == NULL) {
|
dm_error("DC: dc_stream is NULL!\n");
|
return false;
|
}
|
|
if (dwb_pipe_inst >= MAX_DWB_PIPES) {
|
dm_error("DC: writeback pipe is invalid!\n");
|
return false;
|
}
|
|
// stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
|
for (i = 0; i < stream->num_wb_info; i++) {
|
/*dynamic update*/
|
if (stream->writeback_info[i].wb_enabled &&
|
stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {
|
stream->writeback_info[i].wb_enabled = false;
|
}
|
}
|
|
/* remove writeback info for disabled writeback pipes from stream */
|
for (i = 0, j = 0; i < stream->num_wb_info; i++) {
|
if (stream->writeback_info[i].wb_enabled) {
|
if (i != j)
|
/* trim the array */
|
stream->writeback_info[j] = stream->writeback_info[i];
|
j++;
|
}
|
}
|
stream->num_wb_info = j;
|
|
if (IS_DIAG_DC(dc->ctx->dce_environment)) {
|
/* recalculate and apply DML parameters */
|
if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
|
dm_error("DC: update_bandwidth failed!\n");
|
return false;
|
}
|
|
/* disable writeback */
|
if (dc->hwss.disable_writeback)
|
dc->hwss.disable_writeback(dc, dwb_pipe_inst);
|
}
|
return true;
|
}
|
|
bool dc_stream_warmup_writeback(struct dc *dc,
|
int num_dwb,
|
struct dc_writeback_info *wb_info)
|
{
|
if (dc->hwss.mmhubbub_warmup)
|
return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
|
else
|
return false;
|
}
|
uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
|
{
|
uint8_t i;
|
struct dc *dc = stream->ctx->dc;
|
struct resource_context *res_ctx =
|
&dc->current_state->res_ctx;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
|
|
if (res_ctx->pipe_ctx[i].stream != stream)
|
continue;
|
|
return tg->funcs->get_frame_count(tg);
|
}
|
|
return 0;
|
}
|
|
bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
|
const uint8_t *custom_sdp_message,
|
unsigned int sdp_message_size)
|
{
|
int i;
|
struct dc *dc;
|
struct resource_context *res_ctx;
|
|
if (stream == NULL) {
|
dm_error("DC: dc_stream is NULL!\n");
|
return false;
|
}
|
|
dc = stream->ctx->dc;
|
res_ctx = &dc->current_state->res_ctx;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
|
|
if (pipe_ctx->stream != stream)
|
continue;
|
|
if (dc->hwss.send_immediate_sdp_message != NULL)
|
dc->hwss.send_immediate_sdp_message(pipe_ctx,
|
custom_sdp_message,
|
sdp_message_size);
|
else
|
DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n",
|
__func__);
|
|
}
|
|
return true;
|
}
|
|
bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
|
uint32_t *v_blank_start,
|
uint32_t *v_blank_end,
|
uint32_t *h_position,
|
uint32_t *v_position)
|
{
|
uint8_t i;
|
bool ret = false;
|
struct dc *dc = stream->ctx->dc;
|
struct resource_context *res_ctx =
|
&dc->current_state->res_ctx;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
|
|
if (res_ctx->pipe_ctx[i].stream != stream)
|
continue;
|
|
tg->funcs->get_scanoutpos(tg,
|
v_blank_start,
|
v_blank_end,
|
h_position,
|
v_position);
|
|
ret = true;
|
break;
|
}
|
|
return ret;
|
}
|
|
bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
|
{
|
struct pipe_ctx *pipe = NULL;
|
int i;
|
|
if (!dc->hwss.dmdata_status_done)
|
return false;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
|
if (pipe->stream == stream)
|
break;
|
}
|
/* Stream not found, by default we'll assume HUBP fetched dm data */
|
if (i == MAX_PIPES)
|
return true;
|
|
return dc->hwss.dmdata_status_done(pipe);
|
}
|
|
bool dc_stream_set_dynamic_metadata(struct dc *dc,
|
struct dc_stream_state *stream,
|
struct dc_dmdata_attributes *attr)
|
{
|
struct pipe_ctx *pipe_ctx = NULL;
|
struct hubp *hubp;
|
int i;
|
|
/* Dynamic metadata is only supported on HDMI or DP */
|
if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
|
return false;
|
|
/* Check hardware support */
|
if (!dc->hwss.program_dmdata_engine)
|
return false;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
|
if (pipe_ctx->stream == stream)
|
break;
|
}
|
|
if (i == MAX_PIPES)
|
return false;
|
|
hubp = pipe_ctx->plane_res.hubp;
|
if (hubp == NULL)
|
return false;
|
|
pipe_ctx->stream->dmdata_address = attr->address;
|
|
dc->hwss.program_dmdata_engine(pipe_ctx);
|
|
if (hubp->funcs->dmdata_set_attributes != NULL &&
|
pipe_ctx->stream->dmdata_address.quad_part != 0) {
|
hubp->funcs->dmdata_set_attributes(hubp, attr);
|
}
|
|
return true;
|
}
|
|
enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
|
struct dc_state *state,
|
struct dc_stream_state *stream)
|
{
|
if (dc->res_pool->funcs->add_dsc_to_stream_resource) {
|
return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream);
|
} else {
|
return DC_NO_DSC_RESOURCE;
|
}
|
}
|
|
void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
|
{
|
DC_LOG_DC(
|
"core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
|
stream,
|
stream->src.x,
|
stream->src.y,
|
stream->src.width,
|
stream->src.height,
|
stream->dst.x,
|
stream->dst.y,
|
stream->dst.width,
|
stream->dst.height,
|
stream->output_color_space);
|
DC_LOG_DC(
|
"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
|
stream->timing.pix_clk_100hz / 10,
|
stream->timing.h_total,
|
stream->timing.v_total,
|
stream->timing.pixel_encoding,
|
stream->timing.display_color_depth);
|
DC_LOG_DC(
|
"\tlink: %d\n",
|
stream->link->link_index);
|
}
|
