/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/slab.h>
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#include "dm_services.h"
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#include "atomfirmware.h"
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#include "dm_helpers.h"
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#include "dc.h"
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#include "grph_object_id.h"
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#include "gpio_service_interface.h"
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#include "core_status.h"
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#include "dc_link_dp.h"
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#include "dc_link_ddc.h"
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#include "link_hwss.h"
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#include "opp.h"
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#include "link_encoder.h"
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#include "hw_sequencer.h"
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#include "resource.h"
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#include "abm.h"
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#include "fixed31_32.h"
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#include "dpcd_defs.h"
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#include "dmcu.h"
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#include "hw/clk_mgr.h"
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#include "dce/dmub_psr.h"
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#include "dmub/dmub_srv.h"
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#include "inc/hw/panel_cntl.h"
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#define DC_LOGGER_INIT(logger)
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#define LINK_INFO(...) \
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DC_LOG_HW_HOTPLUG( \
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__VA_ARGS__)
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#define RETIMER_REDRIVER_INFO(...) \
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DC_LOG_RETIMER_REDRIVER( \
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__VA_ARGS__)
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/*******************************************************************************
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* Private structures
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******************************************************************************/
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enum {
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PEAK_FACTOR_X1000 = 1006,
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/*
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* Some receivers fail to train on first try and are good
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* on subsequent tries. 2 retries should be plenty. If we
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* don't have a successful training then we don't expect to
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* ever get one.
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*/
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LINK_TRAINING_MAX_VERIFY_RETRY = 2
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};
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/*******************************************************************************
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* Private functions
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******************************************************************************/
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static void dc_link_destruct(struct dc_link *link)
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{
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int i;
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if (link->hpd_gpio) {
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dal_gpio_destroy_irq(&link->hpd_gpio);
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link->hpd_gpio = NULL;
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}
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if (link->ddc)
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dal_ddc_service_destroy(&link->ddc);
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if (link->panel_cntl)
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link->panel_cntl->funcs->destroy(&link->panel_cntl);
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if (link->link_enc)
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link->link_enc->funcs->destroy(&link->link_enc);
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if (link->local_sink)
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dc_sink_release(link->local_sink);
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for (i = 0; i < link->sink_count; ++i)
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dc_sink_release(link->remote_sinks[i]);
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}
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struct gpio *get_hpd_gpio(struct dc_bios *dcb,
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struct graphics_object_id link_id,
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struct gpio_service *gpio_service)
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{
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enum bp_result bp_result;
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struct graphics_object_hpd_info hpd_info;
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struct gpio_pin_info pin_info;
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if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
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return NULL;
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bp_result = dcb->funcs->get_gpio_pin_info(dcb,
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hpd_info.hpd_int_gpio_uid, &pin_info);
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if (bp_result != BP_RESULT_OK) {
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ASSERT(bp_result == BP_RESULT_NORECORD);
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return NULL;
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}
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return dal_gpio_service_create_irq(gpio_service,
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pin_info.offset,
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pin_info.mask);
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}
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/*
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* Function: program_hpd_filter
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*
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* @brief
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* Programs HPD filter on associated HPD line
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*
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* @param [in] delay_on_connect_in_ms: Connect filter timeout
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* @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
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*
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* @return
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* true on success, false otherwise
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*/
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static bool program_hpd_filter(const struct dc_link *link)
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{
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bool result = false;
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struct gpio *hpd;
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int delay_on_connect_in_ms = 0;
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int delay_on_disconnect_in_ms = 0;
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if (link->is_hpd_filter_disabled)
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return false;
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/* Verify feature is supported */
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switch (link->connector_signal) {
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case SIGNAL_TYPE_DVI_SINGLE_LINK:
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case SIGNAL_TYPE_DVI_DUAL_LINK:
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case SIGNAL_TYPE_HDMI_TYPE_A:
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/* Program hpd filter */
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delay_on_connect_in_ms = 500;
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delay_on_disconnect_in_ms = 100;
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break;
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case SIGNAL_TYPE_DISPLAY_PORT:
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case SIGNAL_TYPE_DISPLAY_PORT_MST:
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/* Program hpd filter to allow DP signal to settle */
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/* 500: not able to detect MST <-> SST switch as HPD is low for
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* only 100ms on DELL U2413
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* 0: some passive dongle still show aux mode instead of i2c
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* 20-50: not enough to hide bouncing HPD with passive dongle.
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* also see intermittent i2c read issues.
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*/
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delay_on_connect_in_ms = 80;
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delay_on_disconnect_in_ms = 0;
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break;
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case SIGNAL_TYPE_LVDS:
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case SIGNAL_TYPE_EDP:
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default:
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/* Don't program hpd filter */
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return false;
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}
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/* Obtain HPD handle */
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hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
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link->ctx->gpio_service);
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if (!hpd)
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return result;
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/* Setup HPD filtering */
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if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
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struct gpio_hpd_config config;
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config.delay_on_connect = delay_on_connect_in_ms;
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config.delay_on_disconnect = delay_on_disconnect_in_ms;
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dal_irq_setup_hpd_filter(hpd, &config);
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dal_gpio_close(hpd);
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result = true;
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} else {
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ASSERT_CRITICAL(false);
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}
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/* Release HPD handle */
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dal_gpio_destroy_irq(&hpd);
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return result;
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}
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/**
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* dc_link_detect_sink() - Determine if there is a sink connected
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*
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* @type: Returned connection type
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* Does not detect downstream devices, such as MST sinks
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* or display connected through active dongles
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*/
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bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
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{
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uint32_t is_hpd_high = 0;
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struct gpio *hpd_pin;
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if (link->connector_signal == SIGNAL_TYPE_LVDS) {
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*type = dc_connection_single;
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return true;
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}
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if (link->connector_signal == SIGNAL_TYPE_EDP) {
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/*in case it is not on*/
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link->dc->hwss.edp_power_control(link, true);
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link->dc->hwss.edp_wait_for_hpd_ready(link, true);
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}
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/* todo: may need to lock gpio access */
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hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
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link->ctx->gpio_service);
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if (!hpd_pin)
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goto hpd_gpio_failure;
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dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
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dal_gpio_get_value(hpd_pin, &is_hpd_high);
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dal_gpio_close(hpd_pin);
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dal_gpio_destroy_irq(&hpd_pin);
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if (is_hpd_high) {
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*type = dc_connection_single;
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/* TODO: need to do the actual detection */
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} else {
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*type = dc_connection_none;
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}
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return true;
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hpd_gpio_failure:
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return false;
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}
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static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
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{
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enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
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switch (sink_signal) {
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case SIGNAL_TYPE_DVI_SINGLE_LINK:
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case SIGNAL_TYPE_DVI_DUAL_LINK:
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case SIGNAL_TYPE_HDMI_TYPE_A:
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case SIGNAL_TYPE_LVDS:
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case SIGNAL_TYPE_RGB:
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transaction_type = DDC_TRANSACTION_TYPE_I2C;
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break;
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case SIGNAL_TYPE_DISPLAY_PORT:
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case SIGNAL_TYPE_EDP:
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transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
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break;
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case SIGNAL_TYPE_DISPLAY_PORT_MST:
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/* MST does not use I2COverAux, but there is the
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* SPECIAL use case for "immediate dwnstrm device
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* access" (EPR#370830).
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*/
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transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
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break;
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default:
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break;
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}
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return transaction_type;
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}
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static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
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struct graphics_object_id downstream)
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{
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if (downstream.type == OBJECT_TYPE_CONNECTOR) {
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switch (downstream.id) {
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case CONNECTOR_ID_SINGLE_LINK_DVII:
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switch (encoder.id) {
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case ENCODER_ID_INTERNAL_DAC1:
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case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
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case ENCODER_ID_INTERNAL_DAC2:
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case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
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return SIGNAL_TYPE_RGB;
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default:
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return SIGNAL_TYPE_DVI_SINGLE_LINK;
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}
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break;
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case CONNECTOR_ID_DUAL_LINK_DVII:
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{
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switch (encoder.id) {
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case ENCODER_ID_INTERNAL_DAC1:
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case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
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case ENCODER_ID_INTERNAL_DAC2:
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case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
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return SIGNAL_TYPE_RGB;
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default:
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return SIGNAL_TYPE_DVI_DUAL_LINK;
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}
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}
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break;
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case CONNECTOR_ID_SINGLE_LINK_DVID:
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return SIGNAL_TYPE_DVI_SINGLE_LINK;
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case CONNECTOR_ID_DUAL_LINK_DVID:
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return SIGNAL_TYPE_DVI_DUAL_LINK;
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case CONNECTOR_ID_VGA:
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return SIGNAL_TYPE_RGB;
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case CONNECTOR_ID_HDMI_TYPE_A:
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return SIGNAL_TYPE_HDMI_TYPE_A;
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case CONNECTOR_ID_LVDS:
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return SIGNAL_TYPE_LVDS;
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case CONNECTOR_ID_DISPLAY_PORT:
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return SIGNAL_TYPE_DISPLAY_PORT;
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case CONNECTOR_ID_EDP:
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return SIGNAL_TYPE_EDP;
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default:
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return SIGNAL_TYPE_NONE;
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}
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} else if (downstream.type == OBJECT_TYPE_ENCODER) {
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switch (downstream.id) {
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case ENCODER_ID_EXTERNAL_NUTMEG:
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case ENCODER_ID_EXTERNAL_TRAVIS:
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return SIGNAL_TYPE_DISPLAY_PORT;
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default:
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return SIGNAL_TYPE_NONE;
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}
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}
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return SIGNAL_TYPE_NONE;
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}
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/**
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* dc_link_is_dp_sink_present() - Check if there is a native DP
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* or passive DP-HDMI dongle connected
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*/
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bool dc_link_is_dp_sink_present(struct dc_link *link)
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{
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enum gpio_result gpio_result;
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uint32_t clock_pin = 0;
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uint8_t retry = 0;
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struct ddc *ddc;
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enum connector_id connector_id =
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dal_graphics_object_id_get_connector_id(link->link_id);
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bool present =
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((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
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(connector_id == CONNECTOR_ID_EDP));
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ddc = dal_ddc_service_get_ddc_pin(link->ddc);
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if (!ddc) {
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BREAK_TO_DEBUGGER();
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return present;
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}
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/* Open GPIO and set it to I2C mode */
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/* Note: this GpioMode_Input will be converted
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* to GpioConfigType_I2cAuxDualMode in GPIO component,
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* which indicates we need additional delay
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*/
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if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
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GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
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dal_ddc_close(ddc);
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return present;
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}
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/*
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* Read GPIO: DP sink is present if both clock and data pins are zero
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*
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* [W/A] plug-unplug DP cable, sometimes customer board has
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* one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
|
* then monitor can't br light up. Add retry 3 times
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* But in real passive dongle, it need additional 3ms to detect
|
*/
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do {
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gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
|
ASSERT(gpio_result == GPIO_RESULT_OK);
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if (clock_pin)
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udelay(1000);
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else
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break;
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} while (retry++ < 3);
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present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
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dal_ddc_close(ddc);
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return present;
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}
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/*
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* @brief
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* Detect output sink type
|
*/
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static enum signal_type link_detect_sink(struct dc_link *link,
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enum dc_detect_reason reason)
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{
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enum signal_type result = get_basic_signal_type(link->link_enc->id,
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link->link_id);
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/* Internal digital encoder will detect only dongles
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* that require digital signal
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*/
|
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/* Detection mechanism is different
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* for different native connectors.
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* LVDS connector supports only LVDS signal;
|
* PCIE is a bus slot, the actual connector needs to be detected first;
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* eDP connector supports only eDP signal;
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* HDMI should check straps for audio
|
*/
|
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/* PCIE detects the actual connector on add-on board */
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if (link->link_id.id == CONNECTOR_ID_PCIE) {
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/* ZAZTODO implement PCIE add-on card detection */
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}
|
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switch (link->link_id.id) {
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case CONNECTOR_ID_HDMI_TYPE_A: {
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/* check audio support:
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* if native HDMI is not supported, switch to DVI
|
*/
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struct audio_support *aud_support =
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&link->dc->res_pool->audio_support;
|
|
if (!aud_support->hdmi_audio_native)
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if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
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result = SIGNAL_TYPE_DVI_SINGLE_LINK;
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}
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break;
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case CONNECTOR_ID_DISPLAY_PORT: {
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/* DP HPD short pulse. Passive DP dongle will not
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* have short pulse
|
*/
|
if (reason != DETECT_REASON_HPDRX) {
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/* Check whether DP signal detected: if not -
|
* we assume signal is DVI; it could be corrected
|
* to HDMI after dongle detection
|
*/
|
if (!dm_helpers_is_dp_sink_present(link))
|
result = SIGNAL_TYPE_DVI_SINGLE_LINK;
|
}
|
}
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break;
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default:
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break;
|
}
|
|
return result;
|
}
|
|
static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
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struct audio_support *audio_support)
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{
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enum signal_type signal = SIGNAL_TYPE_NONE;
|
|
switch (dongle_type) {
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case DISPLAY_DONGLE_DP_HDMI_DONGLE:
|
if (audio_support->hdmi_audio_on_dongle)
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signal = SIGNAL_TYPE_HDMI_TYPE_A;
|
else
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signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
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break;
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case DISPLAY_DONGLE_DP_DVI_DONGLE:
|
signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
|
break;
|
case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
|
if (audio_support->hdmi_audio_native)
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signal = SIGNAL_TYPE_HDMI_TYPE_A;
|
else
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signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
|
break;
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default:
|
signal = SIGNAL_TYPE_NONE;
|
break;
|
}
|
|
return signal;
|
}
|
|
static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
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struct display_sink_capability *sink_cap,
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struct audio_support *audio_support)
|
{
|
dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
|
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return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
|
audio_support);
|
}
|
|
static void link_disconnect_sink(struct dc_link *link)
|
{
|
if (link->local_sink) {
|
dc_sink_release(link->local_sink);
|
link->local_sink = NULL;
|
}
|
|
link->dpcd_sink_count = 0;
|
}
|
|
static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
|
{
|
dc_sink_release(link->local_sink);
|
link->local_sink = prev_sink;
|
}
|
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
|
{
|
bool ret = false;
|
|
switch (signal) {
|
case SIGNAL_TYPE_DISPLAY_PORT:
|
case SIGNAL_TYPE_DISPLAY_PORT_MST:
|
ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
|
break;
|
case SIGNAL_TYPE_DVI_SINGLE_LINK:
|
case SIGNAL_TYPE_DVI_DUAL_LINK:
|
case SIGNAL_TYPE_HDMI_TYPE_A:
|
/* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
|
* we can poll for bksv but some displays have an issue with this. Since its so rare
|
* for a display to not be 1.4 capable, this assumtion is ok
|
*/
|
ret = true;
|
break;
|
default:
|
break;
|
}
|
return ret;
|
}
|
|
bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
|
{
|
bool ret = false;
|
|
switch (signal) {
|
case SIGNAL_TYPE_DISPLAY_PORT:
|
case SIGNAL_TYPE_DISPLAY_PORT_MST:
|
ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
|
link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
|
(link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
|
break;
|
case SIGNAL_TYPE_DVI_SINGLE_LINK:
|
case SIGNAL_TYPE_DVI_DUAL_LINK:
|
case SIGNAL_TYPE_HDMI_TYPE_A:
|
ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
|
break;
|
default:
|
break;
|
}
|
|
return ret;
|
}
|
|
static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
|
{
|
struct hdcp_protection_message msg22;
|
struct hdcp_protection_message msg14;
|
|
memset(&msg22, 0, sizeof(struct hdcp_protection_message));
|
memset(&msg14, 0, sizeof(struct hdcp_protection_message));
|
memset(link->hdcp_caps.rx_caps.raw, 0,
|
sizeof(link->hdcp_caps.rx_caps.raw));
|
|
if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
|
link->ddc->transaction_type ==
|
DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
|
link->connector_signal == SIGNAL_TYPE_EDP) {
|
msg22.data = link->hdcp_caps.rx_caps.raw;
|
msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
|
msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
|
} else {
|
msg22.data = &link->hdcp_caps.rx_caps.fields.version;
|
msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
|
msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
|
}
|
msg22.version = HDCP_VERSION_22;
|
msg22.link = HDCP_LINK_PRIMARY;
|
msg22.max_retries = 5;
|
dc_process_hdcp_msg(signal, link, &msg22);
|
|
if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
|
enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED;
|
|
msg14.data = &link->hdcp_caps.bcaps.raw;
|
msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
|
msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
|
msg14.version = HDCP_VERSION_14;
|
msg14.link = HDCP_LINK_PRIMARY;
|
msg14.max_retries = 5;
|
|
status = dc_process_hdcp_msg(signal, link, &msg14);
|
}
|
|
}
|
#endif
|
|
static void read_current_link_settings_on_detect(struct dc_link *link)
|
{
|
union lane_count_set lane_count_set = { {0} };
|
uint8_t link_bw_set;
|
uint8_t link_rate_set;
|
uint32_t read_dpcd_retry_cnt = 10;
|
enum dc_status status = DC_ERROR_UNEXPECTED;
|
int i;
|
union max_down_spread max_down_spread = { {0} };
|
|
// Read DPCD 00101h to find out the number of lanes currently set
|
for (i = 0; i < read_dpcd_retry_cnt; i++) {
|
status = core_link_read_dpcd(link,
|
DP_LANE_COUNT_SET,
|
&lane_count_set.raw,
|
sizeof(lane_count_set));
|
/* First DPCD read after VDD ON can fail if the particular board
|
* does not have HPD pin wired correctly. So if DPCD read fails,
|
* which it should never happen, retry a few times. Target worst
|
* case scenario of 80 ms.
|
*/
|
if (status == DC_OK) {
|
link->cur_link_settings.lane_count =
|
lane_count_set.bits.LANE_COUNT_SET;
|
break;
|
}
|
|
msleep(8);
|
}
|
|
// Read DPCD 00100h to find if standard link rates are set
|
core_link_read_dpcd(link, DP_LINK_BW_SET,
|
&link_bw_set, sizeof(link_bw_set));
|
|
if (link_bw_set == 0) {
|
if (link->connector_signal == SIGNAL_TYPE_EDP) {
|
/* If standard link rates are not being used,
|
* Read DPCD 00115h to find the edp link rate set used
|
*/
|
core_link_read_dpcd(link, DP_LINK_RATE_SET,
|
&link_rate_set, sizeof(link_rate_set));
|
|
// edp_supported_link_rates_count = 0 for DP
|
if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
|
link->cur_link_settings.link_rate =
|
link->dpcd_caps.edp_supported_link_rates[link_rate_set];
|
link->cur_link_settings.link_rate_set = link_rate_set;
|
link->cur_link_settings.use_link_rate_set = true;
|
}
|
} else {
|
// Link Rate not found. Seamless boot may not work.
|
ASSERT(false);
|
}
|
} else {
|
link->cur_link_settings.link_rate = link_bw_set;
|
link->cur_link_settings.use_link_rate_set = false;
|
}
|
// Read DPCD 00003h to find the max down spread.
|
core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
|
&max_down_spread.raw, sizeof(max_down_spread));
|
link->cur_link_settings.link_spread =
|
max_down_spread.bits.MAX_DOWN_SPREAD ?
|
LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
|
}
|
|
static bool detect_dp(struct dc_link *link,
|
struct display_sink_capability *sink_caps,
|
bool *converter_disable_audio,
|
struct audio_support *audio_support,
|
enum dc_detect_reason reason)
|
{
|
bool boot = false;
|
|
sink_caps->signal = link_detect_sink(link, reason);
|
sink_caps->transaction_type =
|
get_ddc_transaction_type(sink_caps->signal);
|
|
if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
|
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
|
if (!detect_dp_sink_caps(link))
|
return false;
|
if (is_mst_supported(link)) {
|
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
|
link->type = dc_connection_mst_branch;
|
|
dal_ddc_service_set_transaction_type(link->ddc,
|
sink_caps->transaction_type);
|
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
/* In case of fallback to SST when topology discovery below fails
|
* HDCP caps will be querried again later by the upper layer (caller
|
* of this function). */
|
query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
|
#endif
|
/*
|
* This call will initiate MST topology discovery. Which
|
* will detect MST ports and add new DRM connector DRM
|
* framework. Then read EDID via remote i2c over aux. In
|
* the end, will notify DRM detect result and save EDID
|
* into DRM framework.
|
*
|
* .detect is called by .fill_modes.
|
* .fill_modes is called by user mode ioctl
|
* DRM_IOCTL_MODE_GETCONNECTOR.
|
*
|
* .get_modes is called by .fill_modes.
|
*
|
* call .get_modes, AMDGPU DM implementation will create
|
* new dc_sink and add to dc_link. For long HPD plug
|
* in/out, MST has its own handle.
|
*
|
* Therefore, just after dc_create, link->sink is not
|
* created for MST until user mode app calls
|
* DRM_IOCTL_MODE_GETCONNECTOR.
|
*
|
* Need check ->sink usages in case ->sink = NULL
|
* TODO: s3 resume check
|
*/
|
if (reason == DETECT_REASON_BOOT)
|
boot = true;
|
|
dm_helpers_dp_update_branch_info(link->ctx, link);
|
|
if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
|
link, boot)) {
|
/* MST not supported */
|
link->type = dc_connection_single;
|
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
|
}
|
}
|
|
if (link->type != dc_connection_mst_branch &&
|
is_dp_active_dongle(link)) {
|
/* DP active dongles */
|
link->type = dc_connection_active_dongle;
|
if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
|
/*
|
* active dongle unplug processing for short irq
|
*/
|
link_disconnect_sink(link);
|
return true;
|
}
|
|
if (link->dpcd_caps.dongle_type !=
|
DISPLAY_DONGLE_DP_HDMI_CONVERTER)
|
*converter_disable_audio = true;
|
}
|
} else {
|
/* DP passive dongles */
|
sink_caps->signal = dp_passive_dongle_detection(link->ddc,
|
sink_caps,
|
audio_support);
|
link->dpcd_caps.dongle_type = sink_caps->dongle_type;
|
}
|
|
return true;
|
}
|
|
static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
|
{
|
if (old_edid->length != new_edid->length)
|
return false;
|
|
if (new_edid->length == 0)
|
return false;
|
|
return (memcmp(old_edid->raw_edid,
|
new_edid->raw_edid, new_edid->length) == 0);
|
}
|
|
static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
|
{
|
/**
|
* something is terribly wrong if time out is > 200ms. (5Hz)
|
* 500 microseconds * 400 tries us 200 ms
|
**/
|
unsigned int sleep_time_in_microseconds = 500;
|
unsigned int tries_allowed = 400;
|
bool is_in_alt_mode;
|
unsigned long long enter_timestamp;
|
unsigned long long finish_timestamp;
|
unsigned long long time_taken_in_ns;
|
int tries_taken;
|
|
DC_LOGGER_INIT(link->ctx->logger);
|
|
if (!link->link_enc->funcs->is_in_alt_mode)
|
return true;
|
|
is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
|
DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
|
|
if (is_in_alt_mode)
|
return true;
|
|
enter_timestamp = dm_get_timestamp(link->ctx);
|
|
for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
|
udelay(sleep_time_in_microseconds);
|
/* ask the link if alt mode is enabled, if so return ok */
|
if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
|
finish_timestamp = dm_get_timestamp(link->ctx);
|
time_taken_in_ns =
|
dm_get_elapse_time_in_ns(link->ctx,
|
finish_timestamp,
|
enter_timestamp);
|
DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
|
div_u64(time_taken_in_ns, 1000000));
|
return true;
|
}
|
}
|
finish_timestamp = dm_get_timestamp(link->ctx);
|
time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
|
enter_timestamp);
|
DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
|
div_u64(time_taken_in_ns, 1000000));
|
return false;
|
}
|
|
/**
|
* dc_link_detect() - Detect if a sink is attached to a given link
|
*
|
* link->local_sink is created or destroyed as needed.
|
*
|
* This does not create remote sinks but will trigger DM
|
* to start MST detection if a branch is detected.
|
*/
|
static bool dc_link_detect_helper(struct dc_link *link,
|
enum dc_detect_reason reason)
|
{
|
struct dc_sink_init_data sink_init_data = { 0 };
|
struct display_sink_capability sink_caps = { 0 };
|
uint8_t i;
|
bool converter_disable_audio = false;
|
struct audio_support *aud_support = &link->dc->res_pool->audio_support;
|
bool same_edid = false;
|
enum dc_edid_status edid_status;
|
struct dc_context *dc_ctx = link->ctx;
|
struct dc_sink *sink = NULL;
|
struct dc_sink *prev_sink = NULL;
|
struct dpcd_caps prev_dpcd_caps;
|
bool same_dpcd = true;
|
enum dc_connection_type new_connection_type = dc_connection_none;
|
bool perform_dp_seamless_boot = false;
|
const uint32_t post_oui_delay = 30; // 30ms
|
|
DC_LOGGER_INIT(link->ctx->logger);
|
|
if (dc_is_virtual_signal(link->connector_signal))
|
return false;
|
|
if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
|
link->connector_signal == SIGNAL_TYPE_EDP) &&
|
link->local_sink) {
|
// need to re-write OUI and brightness in resume case
|
if (link->connector_signal == SIGNAL_TYPE_EDP) {
|
dpcd_set_source_specific_data(link);
|
msleep(post_oui_delay);
|
dc_link_set_default_brightness_aux(link);
|
//TODO: use cached
|
}
|
|
return true;
|
}
|
|
if (!dc_link_detect_sink(link, &new_connection_type)) {
|
BREAK_TO_DEBUGGER();
|
return false;
|
}
|
|
prev_sink = link->local_sink;
|
if (prev_sink) {
|
dc_sink_retain(prev_sink);
|
memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
|
}
|
|
link_disconnect_sink(link);
|
if (new_connection_type != dc_connection_none) {
|
link->type = new_connection_type;
|
link->link_state_valid = false;
|
|
/* From Disconnected-to-Connected. */
|
switch (link->connector_signal) {
|
case SIGNAL_TYPE_HDMI_TYPE_A: {
|
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
|
if (aud_support->hdmi_audio_native)
|
sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
|
else
|
sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
|
break;
|
}
|
|
case SIGNAL_TYPE_DVI_SINGLE_LINK: {
|
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
|
sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
|
break;
|
}
|
|
case SIGNAL_TYPE_DVI_DUAL_LINK: {
|
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
|
sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
|
break;
|
}
|
|
case SIGNAL_TYPE_LVDS: {
|
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
|
sink_caps.signal = SIGNAL_TYPE_LVDS;
|
break;
|
}
|
|
case SIGNAL_TYPE_EDP: {
|
read_current_link_settings_on_detect(link);
|
|
detect_edp_sink_caps(link);
|
read_current_link_settings_on_detect(link);
|
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
|
sink_caps.signal = SIGNAL_TYPE_EDP;
|
break;
|
}
|
|
case SIGNAL_TYPE_DISPLAY_PORT: {
|
/* wa HPD high coming too early*/
|
if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
|
/* if alt mode times out, return false */
|
if (!wait_for_entering_dp_alt_mode(link))
|
return false;
|
}
|
|
if (!detect_dp(link, &sink_caps,
|
&converter_disable_audio,
|
aud_support, reason)) {
|
if (prev_sink)
|
dc_sink_release(prev_sink);
|
return false;
|
}
|
|
// Check if dpcp block is the same
|
if (prev_sink) {
|
if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
|
sizeof(struct dpcd_caps)))
|
same_dpcd = false;
|
}
|
/* Active dongle downstream unplug*/
|
if (link->type == dc_connection_active_dongle &&
|
link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
|
if (prev_sink)
|
/* Downstream unplug */
|
dc_sink_release(prev_sink);
|
return true;
|
}
|
|
if (link->type == dc_connection_mst_branch) {
|
LINK_INFO("link=%d, mst branch is now Connected\n",
|
link->link_index);
|
/* Need to setup mst link_cap struct here
|
* otherwise dc_link_detect() will leave mst link_cap
|
* empty which leads to allocate_mst_payload() has "0"
|
* pbn_per_slot value leading to exception on dc_fixpt_div()
|
*/
|
dp_verify_mst_link_cap(link);
|
|
if (prev_sink)
|
dc_sink_release(prev_sink);
|
return false;
|
}
|
|
// For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
|
if (reason == DETECT_REASON_BOOT &&
|
!dc_ctx->dc->config.power_down_display_on_boot &&
|
link->link_status.link_active)
|
perform_dp_seamless_boot = true;
|
|
if (perform_dp_seamless_boot) {
|
read_current_link_settings_on_detect(link);
|
link->verified_link_cap = link->reported_link_cap;
|
}
|
|
break;
|
}
|
|
default:
|
DC_ERROR("Invalid connector type! signal:%d\n",
|
link->connector_signal);
|
if (prev_sink)
|
dc_sink_release(prev_sink);
|
return false;
|
} /* switch() */
|
|
if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
|
link->dpcd_sink_count =
|
link->dpcd_caps.sink_count.bits.SINK_COUNT;
|
else
|
link->dpcd_sink_count = 1;
|
|
dal_ddc_service_set_transaction_type(link->ddc,
|
sink_caps.transaction_type);
|
|
link->aux_mode =
|
dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
|
|
sink_init_data.link = link;
|
sink_init_data.sink_signal = sink_caps.signal;
|
|
sink = dc_sink_create(&sink_init_data);
|
if (!sink) {
|
DC_ERROR("Failed to create sink!\n");
|
if (prev_sink)
|
dc_sink_release(prev_sink);
|
return false;
|
}
|
|
sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
|
sink->converter_disable_audio = converter_disable_audio;
|
|
/* dc_sink_create returns a new reference */
|
link->local_sink = sink;
|
|
edid_status = dm_helpers_read_local_edid(link->ctx,
|
link, sink);
|
|
switch (edid_status) {
|
case EDID_BAD_CHECKSUM:
|
DC_LOG_ERROR("EDID checksum invalid.\n");
|
break;
|
case EDID_NO_RESPONSE:
|
DC_LOG_ERROR("No EDID read.\n");
|
/*
|
* Abort detection for non-DP connectors if we have
|
* no EDID
|
*
|
* DP needs to report as connected if HDP is high
|
* even if we have no EDID in order to go to
|
* fail-safe mode
|
*/
|
if (dc_is_hdmi_signal(link->connector_signal) ||
|
dc_is_dvi_signal(link->connector_signal)) {
|
if (prev_sink)
|
dc_sink_release(prev_sink);
|
link_disconnect_sink(link);
|
|
return false;
|
}
|
/*
|
* Abort detection for DP connectors if we have
|
* no EDID and connector is active converter
|
* as there are no display downstream
|
*
|
*/
|
if (dc_is_dp_sst_signal(link->connector_signal) &&
|
(link->dpcd_caps.dongle_type ==
|
DISPLAY_DONGLE_DP_VGA_CONVERTER ||
|
link->dpcd_caps.dongle_type ==
|
DISPLAY_DONGLE_DP_DVI_CONVERTER)) {
|
if (prev_sink)
|
dc_sink_release(prev_sink);
|
link_disconnect_sink(link);
|
|
return false;
|
}
|
default:
|
break;
|
}
|
|
if (link->local_sink->edid_caps.panel_patch.disable_fec)
|
link->ctx->dc->debug.disable_fec = true;
|
|
// Check if edid is the same
|
if ((prev_sink) &&
|
(edid_status == EDID_THE_SAME || edid_status == EDID_OK))
|
same_edid = is_same_edid(&prev_sink->dc_edid,
|
&sink->dc_edid);
|
|
if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
|
link->ctx->dc->debug.hdmi20_disable = true;
|
|
if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
|
sink_caps.transaction_type ==
|
DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
|
/*
|
* TODO debug why Dell 2413 doesn't like
|
* two link trainings
|
*/
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
query_hdcp_capability(sink->sink_signal, link);
|
#endif
|
|
// verify link cap for SST non-seamless boot
|
if (!perform_dp_seamless_boot)
|
dp_verify_link_cap_with_retries(link,
|
&link->reported_link_cap,
|
LINK_TRAINING_MAX_VERIFY_RETRY);
|
} else {
|
// If edid is the same, then discard new sink and revert back to original sink
|
if (same_edid) {
|
link_disconnect_remap(prev_sink, link);
|
sink = prev_sink;
|
prev_sink = NULL;
|
}
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
query_hdcp_capability(sink->sink_signal, link);
|
#endif
|
}
|
|
/* HDMI-DVI Dongle */
|
if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
|
!sink->edid_caps.edid_hdmi)
|
sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
|
|
/* Connectivity log: detection */
|
for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
|
CONN_DATA_DETECT(link,
|
&sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
|
DC_EDID_BLOCK_SIZE,
|
"%s: [Block %d] ", sink->edid_caps.display_name, i);
|
}
|
|
DC_LOG_DETECTION_EDID_PARSER("%s: "
|
"manufacturer_id = %X, "
|
"product_id = %X, "
|
"serial_number = %X, "
|
"manufacture_week = %d, "
|
"manufacture_year = %d, "
|
"display_name = %s, "
|
"speaker_flag = %d, "
|
"audio_mode_count = %d\n",
|
__func__,
|
sink->edid_caps.manufacturer_id,
|
sink->edid_caps.product_id,
|
sink->edid_caps.serial_number,
|
sink->edid_caps.manufacture_week,
|
sink->edid_caps.manufacture_year,
|
sink->edid_caps.display_name,
|
sink->edid_caps.speaker_flags,
|
sink->edid_caps.audio_mode_count);
|
|
for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
|
DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
|
"format_code = %d, "
|
"channel_count = %d, "
|
"sample_rate = %d, "
|
"sample_size = %d\n",
|
__func__,
|
i,
|
sink->edid_caps.audio_modes[i].format_code,
|
sink->edid_caps.audio_modes[i].channel_count,
|
sink->edid_caps.audio_modes[i].sample_rate,
|
sink->edid_caps.audio_modes[i].sample_size);
|
}
|
} else {
|
/* From Connected-to-Disconnected. */
|
if (link->type == dc_connection_mst_branch) {
|
LINK_INFO("link=%d, mst branch is now Disconnected\n",
|
link->link_index);
|
|
dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
|
|
link->mst_stream_alloc_table.stream_count = 0;
|
memset(link->mst_stream_alloc_table.stream_allocations,
|
0,
|
sizeof(link->mst_stream_alloc_table.stream_allocations));
|
}
|
|
link->type = dc_connection_none;
|
sink_caps.signal = SIGNAL_TYPE_NONE;
|
/* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
|
* is not cleared. If we emulate a DP signal on this connection, it thinks
|
* the dongle is still there and limits the number of modes we can emulate.
|
* Clear dongle_max_pix_clk on disconnect to fix this
|
*/
|
link->dongle_max_pix_clk = 0;
|
}
|
|
LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
|
link->link_index, sink,
|
(sink_caps.signal ==
|
SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
|
prev_sink, same_dpcd, same_edid);
|
|
if (prev_sink)
|
dc_sink_release(prev_sink);
|
|
return true;
|
}
|
|
bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
|
{
|
const struct dc *dc = link->dc;
|
bool ret;
|
|
/* get out of low power state */
|
clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
|
|
ret = dc_link_detect_helper(link, reason);
|
|
/* Go back to power optimized state */
|
clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
|
|
return ret;
|
}
|
|
bool dc_link_get_hpd_state(struct dc_link *dc_link)
|
{
|
uint32_t state;
|
|
dal_gpio_lock_pin(dc_link->hpd_gpio);
|
dal_gpio_get_value(dc_link->hpd_gpio, &state);
|
dal_gpio_unlock_pin(dc_link->hpd_gpio);
|
|
return state;
|
}
|
|
static enum hpd_source_id get_hpd_line(struct dc_link *link)
|
{
|
struct gpio *hpd;
|
enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
|
|
hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
|
link->ctx->gpio_service);
|
|
if (hpd) {
|
switch (dal_irq_get_source(hpd)) {
|
case DC_IRQ_SOURCE_HPD1:
|
hpd_id = HPD_SOURCEID1;
|
break;
|
case DC_IRQ_SOURCE_HPD2:
|
hpd_id = HPD_SOURCEID2;
|
break;
|
case DC_IRQ_SOURCE_HPD3:
|
hpd_id = HPD_SOURCEID3;
|
break;
|
case DC_IRQ_SOURCE_HPD4:
|
hpd_id = HPD_SOURCEID4;
|
break;
|
case DC_IRQ_SOURCE_HPD5:
|
hpd_id = HPD_SOURCEID5;
|
break;
|
case DC_IRQ_SOURCE_HPD6:
|
hpd_id = HPD_SOURCEID6;
|
break;
|
default:
|
BREAK_TO_DEBUGGER();
|
break;
|
}
|
|
dal_gpio_destroy_irq(&hpd);
|
}
|
|
return hpd_id;
|
}
|
|
static enum channel_id get_ddc_line(struct dc_link *link)
|
{
|
struct ddc *ddc;
|
enum channel_id channel = CHANNEL_ID_UNKNOWN;
|
|
ddc = dal_ddc_service_get_ddc_pin(link->ddc);
|
|
if (ddc) {
|
switch (dal_ddc_get_line(ddc)) {
|
case GPIO_DDC_LINE_DDC1:
|
channel = CHANNEL_ID_DDC1;
|
break;
|
case GPIO_DDC_LINE_DDC2:
|
channel = CHANNEL_ID_DDC2;
|
break;
|
case GPIO_DDC_LINE_DDC3:
|
channel = CHANNEL_ID_DDC3;
|
break;
|
case GPIO_DDC_LINE_DDC4:
|
channel = CHANNEL_ID_DDC4;
|
break;
|
case GPIO_DDC_LINE_DDC5:
|
channel = CHANNEL_ID_DDC5;
|
break;
|
case GPIO_DDC_LINE_DDC6:
|
channel = CHANNEL_ID_DDC6;
|
break;
|
case GPIO_DDC_LINE_DDC_VGA:
|
channel = CHANNEL_ID_DDC_VGA;
|
break;
|
case GPIO_DDC_LINE_I2C_PAD:
|
channel = CHANNEL_ID_I2C_PAD;
|
break;
|
default:
|
BREAK_TO_DEBUGGER();
|
break;
|
}
|
}
|
|
return channel;
|
}
|
|
static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
|
{
|
switch (encoder.id) {
|
case ENCODER_ID_INTERNAL_UNIPHY:
|
switch (encoder.enum_id) {
|
case ENUM_ID_1:
|
return TRANSMITTER_UNIPHY_A;
|
case ENUM_ID_2:
|
return TRANSMITTER_UNIPHY_B;
|
default:
|
return TRANSMITTER_UNKNOWN;
|
}
|
break;
|
case ENCODER_ID_INTERNAL_UNIPHY1:
|
switch (encoder.enum_id) {
|
case ENUM_ID_1:
|
return TRANSMITTER_UNIPHY_C;
|
case ENUM_ID_2:
|
return TRANSMITTER_UNIPHY_D;
|
default:
|
return TRANSMITTER_UNKNOWN;
|
}
|
break;
|
case ENCODER_ID_INTERNAL_UNIPHY2:
|
switch (encoder.enum_id) {
|
case ENUM_ID_1:
|
return TRANSMITTER_UNIPHY_E;
|
case ENUM_ID_2:
|
return TRANSMITTER_UNIPHY_F;
|
default:
|
return TRANSMITTER_UNKNOWN;
|
}
|
break;
|
case ENCODER_ID_INTERNAL_UNIPHY3:
|
switch (encoder.enum_id) {
|
case ENUM_ID_1:
|
return TRANSMITTER_UNIPHY_G;
|
default:
|
return TRANSMITTER_UNKNOWN;
|
}
|
break;
|
case ENCODER_ID_EXTERNAL_NUTMEG:
|
switch (encoder.enum_id) {
|
case ENUM_ID_1:
|
return TRANSMITTER_NUTMEG_CRT;
|
default:
|
return TRANSMITTER_UNKNOWN;
|
}
|
break;
|
case ENCODER_ID_EXTERNAL_TRAVIS:
|
switch (encoder.enum_id) {
|
case ENUM_ID_1:
|
return TRANSMITTER_TRAVIS_CRT;
|
case ENUM_ID_2:
|
return TRANSMITTER_TRAVIS_LCD;
|
default:
|
return TRANSMITTER_UNKNOWN;
|
}
|
break;
|
default:
|
return TRANSMITTER_UNKNOWN;
|
}
|
}
|
|
static bool dc_link_construct(struct dc_link *link,
|
const struct link_init_data *init_params)
|
{
|
uint8_t i;
|
struct ddc_service_init_data ddc_service_init_data = { { 0 } };
|
struct dc_context *dc_ctx = init_params->ctx;
|
struct encoder_init_data enc_init_data = { 0 };
|
struct panel_cntl_init_data panel_cntl_init_data = { 0 };
|
struct integrated_info info = {{{ 0 }}};
|
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
|
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
|
|
DC_LOGGER_INIT(dc_ctx->logger);
|
|
link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
|
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
|
|
link->link_status.dpcd_caps = &link->dpcd_caps;
|
|
link->dc = init_params->dc;
|
link->ctx = dc_ctx;
|
link->link_index = init_params->link_index;
|
|
memset(&link->preferred_training_settings, 0,
|
sizeof(struct dc_link_training_overrides));
|
memset(&link->preferred_link_setting, 0,
|
sizeof(struct dc_link_settings));
|
|
link->link_id =
|
bios->funcs->get_connector_id(bios, init_params->connector_index);
|
|
if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
|
dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
|
__func__, init_params->connector_index,
|
link->link_id.type, OBJECT_TYPE_CONNECTOR);
|
goto create_fail;
|
}
|
|
if (link->dc->res_pool->funcs->link_init)
|
link->dc->res_pool->funcs->link_init(link);
|
|
link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
|
link->ctx->gpio_service);
|
if (link->hpd_gpio) {
|
dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
|
dal_gpio_unlock_pin(link->hpd_gpio);
|
link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
|
}
|
|
switch (link->link_id.id) {
|
case CONNECTOR_ID_HDMI_TYPE_A:
|
link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
|
|
break;
|
case CONNECTOR_ID_SINGLE_LINK_DVID:
|
case CONNECTOR_ID_SINGLE_LINK_DVII:
|
link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
|
break;
|
case CONNECTOR_ID_DUAL_LINK_DVID:
|
case CONNECTOR_ID_DUAL_LINK_DVII:
|
link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
|
break;
|
case CONNECTOR_ID_DISPLAY_PORT:
|
link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
|
|
if (link->hpd_gpio)
|
link->irq_source_hpd_rx =
|
dal_irq_get_rx_source(link->hpd_gpio);
|
|
break;
|
case CONNECTOR_ID_EDP:
|
link->connector_signal = SIGNAL_TYPE_EDP;
|
|
if (link->hpd_gpio) {
|
link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
|
link->irq_source_hpd_rx =
|
dal_irq_get_rx_source(link->hpd_gpio);
|
}
|
|
break;
|
case CONNECTOR_ID_LVDS:
|
link->connector_signal = SIGNAL_TYPE_LVDS;
|
break;
|
default:
|
DC_LOG_WARNING("Unsupported Connector type:%d!\n",
|
link->link_id.id);
|
goto create_fail;
|
}
|
|
/* TODO: #DAL3 Implement id to str function.*/
|
LINK_INFO("Connector[%d] description:"
|
"signal %d\n",
|
init_params->connector_index,
|
link->connector_signal);
|
|
ddc_service_init_data.ctx = link->ctx;
|
ddc_service_init_data.id = link->link_id;
|
ddc_service_init_data.link = link;
|
link->ddc = dal_ddc_service_create(&ddc_service_init_data);
|
|
if (!link->ddc) {
|
DC_ERROR("Failed to create ddc_service!\n");
|
goto ddc_create_fail;
|
}
|
|
if (!link->ddc->ddc_pin) {
|
DC_ERROR("Failed to get I2C info for connector!\n");
|
goto ddc_create_fail;
|
}
|
|
link->ddc_hw_inst =
|
dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
|
|
|
if (link->dc->res_pool->funcs->panel_cntl_create &&
|
(link->link_id.id == CONNECTOR_ID_EDP ||
|
link->link_id.id == CONNECTOR_ID_LVDS)) {
|
panel_cntl_init_data.ctx = dc_ctx;
|
panel_cntl_init_data.inst = 0;
|
link->panel_cntl =
|
link->dc->res_pool->funcs->panel_cntl_create(
|
&panel_cntl_init_data);
|
|
if (link->panel_cntl == NULL) {
|
DC_ERROR("Failed to create link panel_cntl!\n");
|
goto panel_cntl_create_fail;
|
}
|
}
|
|
enc_init_data.ctx = dc_ctx;
|
bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
|
&enc_init_data.encoder);
|
enc_init_data.connector = link->link_id;
|
enc_init_data.channel = get_ddc_line(link);
|
enc_init_data.hpd_source = get_hpd_line(link);
|
|
link->hpd_src = enc_init_data.hpd_source;
|
|
enc_init_data.transmitter =
|
translate_encoder_to_transmitter(enc_init_data.encoder);
|
link->link_enc =
|
link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
|
|
if (!link->link_enc) {
|
DC_ERROR("Failed to create link encoder!\n");
|
goto link_enc_create_fail;
|
}
|
|
link->link_enc_hw_inst = link->link_enc->transmitter;
|
|
for (i = 0; i < 4; i++) {
|
if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
|
link->link_id, i,
|
&link->device_tag) != BP_RESULT_OK) {
|
DC_ERROR("Failed to find device tag!\n");
|
goto device_tag_fail;
|
}
|
|
/* Look for device tag that matches connector signal,
|
* CRT for rgb, LCD for other supported signal tyes
|
*/
|
if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
|
link->device_tag.dev_id))
|
continue;
|
if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
|
link->connector_signal != SIGNAL_TYPE_RGB)
|
continue;
|
if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
|
link->connector_signal == SIGNAL_TYPE_RGB)
|
continue;
|
break;
|
}
|
|
if (bios->integrated_info)
|
info = *bios->integrated_info;
|
|
/* Look for channel mapping corresponding to connector and device tag */
|
for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
|
struct external_display_path *path =
|
&info.ext_disp_conn_info.path[i];
|
|
if (path->device_connector_id.enum_id == link->link_id.enum_id &&
|
path->device_connector_id.id == link->link_id.id &&
|
path->device_connector_id.type == link->link_id.type) {
|
if (link->device_tag.acpi_device != 0 &&
|
path->device_acpi_enum == link->device_tag.acpi_device) {
|
link->ddi_channel_mapping = path->channel_mapping;
|
link->chip_caps = path->caps;
|
} else if (path->device_tag ==
|
link->device_tag.dev_id.raw_device_tag) {
|
link->ddi_channel_mapping = path->channel_mapping;
|
link->chip_caps = path->caps;
|
}
|
break;
|
}
|
}
|
|
if (bios->funcs->get_atom_dc_golden_table)
|
bios->funcs->get_atom_dc_golden_table(bios);
|
|
/*
|
* TODO check if GPIO programmed correctly
|
*
|
* If GPIO isn't programmed correctly HPD might not rise or drain
|
* fast enough, leading to bounces.
|
*/
|
program_hpd_filter(link);
|
|
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
|
|
return true;
|
device_tag_fail:
|
link->link_enc->funcs->destroy(&link->link_enc);
|
link_enc_create_fail:
|
if (link->panel_cntl != NULL)
|
link->panel_cntl->funcs->destroy(&link->panel_cntl);
|
panel_cntl_create_fail:
|
dal_ddc_service_destroy(&link->ddc);
|
ddc_create_fail:
|
create_fail:
|
|
if (link->hpd_gpio) {
|
dal_gpio_destroy_irq(&link->hpd_gpio);
|
link->hpd_gpio = NULL;
|
}
|
|
return false;
|
}
|
|
/*******************************************************************************
|
* Public functions
|
******************************************************************************/
|
struct dc_link *link_create(const struct link_init_data *init_params)
|
{
|
struct dc_link *link =
|
kzalloc(sizeof(*link), GFP_KERNEL);
|
|
if (NULL == link)
|
goto alloc_fail;
|
|
if (false == dc_link_construct(link, init_params))
|
goto construct_fail;
|
|
return link;
|
|
construct_fail:
|
kfree(link);
|
|
alloc_fail:
|
return NULL;
|
}
|
|
void link_destroy(struct dc_link **link)
|
{
|
dc_link_destruct(*link);
|
kfree(*link);
|
*link = NULL;
|
}
|
|
static void enable_stream_features(struct pipe_ctx *pipe_ctx)
|
{
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
struct dc_link *link = stream->link;
|
union down_spread_ctrl old_downspread;
|
union down_spread_ctrl new_downspread;
|
|
core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
|
&old_downspread.raw, sizeof(old_downspread));
|
|
new_downspread.raw = old_downspread.raw;
|
|
new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
|
(stream->ignore_msa_timing_param) ? 1 : 0;
|
|
if (new_downspread.raw != old_downspread.raw) {
|
core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
|
&new_downspread.raw, sizeof(new_downspread));
|
}
|
}
|
|
static enum dc_status enable_link_dp(struct dc_state *state,
|
struct pipe_ctx *pipe_ctx)
|
{
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
enum dc_status status;
|
bool skip_video_pattern;
|
struct dc_link *link = stream->link;
|
struct dc_link_settings link_settings = {0};
|
bool fec_enable;
|
int i;
|
bool apply_seamless_boot_optimization = false;
|
uint32_t bl_oled_enable_delay = 50; // in ms
|
const uint32_t post_oui_delay = 30; // 30ms
|
|
// check for seamless boot
|
for (i = 0; i < state->stream_count; i++) {
|
if (state->streams[i]->apply_seamless_boot_optimization) {
|
apply_seamless_boot_optimization = true;
|
break;
|
}
|
}
|
|
/* get link settings for video mode timing */
|
decide_link_settings(stream, &link_settings);
|
|
if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
|
/*in case it is not on*/
|
link->dc->hwss.edp_power_control(link, true);
|
link->dc->hwss.edp_wait_for_hpd_ready(link, true);
|
}
|
|
pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
|
link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
|
if (state->clk_mgr && !apply_seamless_boot_optimization)
|
state->clk_mgr->funcs->update_clocks(state->clk_mgr,
|
state, false);
|
|
// during mode switch we do DP_SET_POWER off then on, and OUI is lost
|
dpcd_set_source_specific_data(link);
|
if (link->dpcd_sink_ext_caps.raw != 0)
|
msleep(post_oui_delay);
|
|
skip_video_pattern = true;
|
|
if (link_settings.link_rate == LINK_RATE_LOW)
|
skip_video_pattern = false;
|
|
if (perform_link_training_with_retries(&link_settings,
|
skip_video_pattern,
|
LINK_TRAINING_ATTEMPTS,
|
pipe_ctx,
|
pipe_ctx->stream->signal)) {
|
link->cur_link_settings = link_settings;
|
status = DC_OK;
|
} else {
|
status = DC_FAIL_DP_LINK_TRAINING;
|
}
|
|
if (link->preferred_training_settings.fec_enable)
|
fec_enable = *link->preferred_training_settings.fec_enable;
|
else
|
fec_enable = true;
|
|
dp_set_fec_enable(link, fec_enable);
|
|
// during mode set we do DP_SET_POWER off then on, aux writes are lost
|
if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
|
link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
|
link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
|
dc_link_set_default_brightness_aux(link); // TODO: use cached if known
|
if (link->dpcd_sink_ext_caps.bits.oled == 1)
|
msleep(bl_oled_enable_delay);
|
dc_link_backlight_enable_aux(link, true);
|
}
|
|
return status;
|
}
|
|
static enum dc_status enable_link_edp(
|
struct dc_state *state,
|
struct pipe_ctx *pipe_ctx)
|
{
|
enum dc_status status;
|
|
status = enable_link_dp(state, pipe_ctx);
|
|
return status;
|
}
|
|
static enum dc_status enable_link_dp_mst(
|
struct dc_state *state,
|
struct pipe_ctx *pipe_ctx)
|
{
|
struct dc_link *link = pipe_ctx->stream->link;
|
|
/* sink signal type after MST branch is MST. Multiple MST sinks
|
* share one link. Link DP PHY is enable or training only once.
|
*/
|
if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
|
return DC_OK;
|
|
/* clear payload table */
|
dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
|
|
/* to make sure the pending down rep can be processed
|
* before enabling the link
|
*/
|
dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
|
|
/* set the sink to MST mode before enabling the link */
|
dp_enable_mst_on_sink(link, true);
|
|
return enable_link_dp(state, pipe_ctx);
|
}
|
|
static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
|
enum engine_id eng_id,
|
struct ext_hdmi_settings *settings)
|
{
|
bool result = false;
|
int i = 0;
|
struct integrated_info *integrated_info =
|
pipe_ctx->stream->ctx->dc_bios->integrated_info;
|
|
if (integrated_info == NULL)
|
return false;
|
|
/*
|
* Get retimer settings from sbios for passing SI eye test for DCE11
|
* The setting values are varied based on board revision and port id
|
* Therefore the setting values of each ports is passed by sbios.
|
*/
|
|
// Check if current bios contains ext Hdmi settings
|
if (integrated_info->gpu_cap_info & 0x20) {
|
switch (eng_id) {
|
case ENGINE_ID_DIGA:
|
settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
|
settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
|
settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
|
memmove(settings->reg_settings,
|
integrated_info->dp0_ext_hdmi_reg_settings,
|
sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
|
memmove(settings->reg_settings_6g,
|
integrated_info->dp0_ext_hdmi_6g_reg_settings,
|
sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
|
result = true;
|
break;
|
case ENGINE_ID_DIGB:
|
settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
|
settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
|
settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
|
memmove(settings->reg_settings,
|
integrated_info->dp1_ext_hdmi_reg_settings,
|
sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
|
memmove(settings->reg_settings_6g,
|
integrated_info->dp1_ext_hdmi_6g_reg_settings,
|
sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
|
result = true;
|
break;
|
case ENGINE_ID_DIGC:
|
settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
|
settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
|
settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
|
memmove(settings->reg_settings,
|
integrated_info->dp2_ext_hdmi_reg_settings,
|
sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
|
memmove(settings->reg_settings_6g,
|
integrated_info->dp2_ext_hdmi_6g_reg_settings,
|
sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
|
result = true;
|
break;
|
case ENGINE_ID_DIGD:
|
settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
|
settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
|
settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
|
memmove(settings->reg_settings,
|
integrated_info->dp3_ext_hdmi_reg_settings,
|
sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
|
memmove(settings->reg_settings_6g,
|
integrated_info->dp3_ext_hdmi_6g_reg_settings,
|
sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
|
result = true;
|
break;
|
default:
|
break;
|
}
|
|
if (result == true) {
|
// Validate settings from bios integrated info table
|
if (settings->slv_addr == 0)
|
return false;
|
if (settings->reg_num > 9)
|
return false;
|
if (settings->reg_num_6g > 3)
|
return false;
|
|
for (i = 0; i < settings->reg_num; i++) {
|
if (settings->reg_settings[i].i2c_reg_index > 0x20)
|
return false;
|
}
|
|
for (i = 0; i < settings->reg_num_6g; i++) {
|
if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
|
return false;
|
}
|
}
|
}
|
|
return result;
|
}
|
|
static bool i2c_write(struct pipe_ctx *pipe_ctx,
|
uint8_t address, uint8_t *buffer, uint32_t length)
|
{
|
struct i2c_command cmd = {0};
|
struct i2c_payload payload = {0};
|
|
memset(&payload, 0, sizeof(payload));
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.number_of_payloads = 1;
|
cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
|
cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
|
|
payload.address = address;
|
payload.data = buffer;
|
payload.length = length;
|
payload.write = true;
|
cmd.payloads = &payload;
|
|
if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
|
pipe_ctx->stream->link, &cmd))
|
return true;
|
|
return false;
|
}
|
|
static void write_i2c_retimer_setting(
|
struct pipe_ctx *pipe_ctx,
|
bool is_vga_mode,
|
bool is_over_340mhz,
|
struct ext_hdmi_settings *settings)
|
{
|
uint8_t slave_address = (settings->slv_addr >> 1);
|
uint8_t buffer[2];
|
const uint8_t apply_rx_tx_change = 0x4;
|
uint8_t offset = 0xA;
|
uint8_t value = 0;
|
int i = 0;
|
bool i2c_success = false;
|
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
|
|
memset(&buffer, 0, sizeof(buffer));
|
|
/* Start Ext-Hdmi programming*/
|
|
for (i = 0; i < settings->reg_num; i++) {
|
/* Apply 3G settings */
|
if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
|
|
buffer[0] = settings->reg_settings[i].i2c_reg_index;
|
buffer[1] = settings->reg_settings[i].i2c_reg_val;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
|
offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
|
* needs to be set to 1 on every 0xA-0xC write.
|
*/
|
if (settings->reg_settings[i].i2c_reg_index == 0xA ||
|
settings->reg_settings[i].i2c_reg_index == 0xB ||
|
settings->reg_settings[i].i2c_reg_index == 0xC) {
|
|
/* Query current value from offset 0xA */
|
if (settings->reg_settings[i].i2c_reg_index == 0xA)
|
value = settings->reg_settings[i].i2c_reg_val;
|
else {
|
i2c_success =
|
dal_ddc_service_query_ddc_data(
|
pipe_ctx->stream->link->ddc,
|
slave_address, &offset, 1, &value, 1);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
}
|
|
buffer[0] = offset;
|
/* Set APPLY_RX_TX_CHANGE bit to 1 */
|
buffer[1] = value | apply_rx_tx_change;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
}
|
}
|
}
|
|
/* Apply 3G settings */
|
if (is_over_340mhz) {
|
for (i = 0; i < settings->reg_num_6g; i++) {
|
/* Apply 3G settings */
|
if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
|
|
buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
|
buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
|
* needs to be set to 1 on every 0xA-0xC write.
|
*/
|
if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
|
settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
|
settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
|
|
/* Query current value from offset 0xA */
|
if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
|
value = settings->reg_settings_6g[i].i2c_reg_val;
|
else {
|
i2c_success =
|
dal_ddc_service_query_ddc_data(
|
pipe_ctx->stream->link->ddc,
|
slave_address, &offset, 1, &value, 1);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
}
|
|
buffer[0] = offset;
|
/* Set APPLY_RX_TX_CHANGE bit to 1 */
|
buffer[1] = value | apply_rx_tx_change;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
}
|
}
|
}
|
}
|
|
if (is_vga_mode) {
|
/* Program additional settings if using 640x480 resolution */
|
|
/* Write offset 0xFF to 0x01 */
|
buffer[0] = 0xff;
|
buffer[1] = 0x01;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0x00 to 0x23 */
|
buffer[0] = 0x00;
|
buffer[1] = 0x23;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0xff to 0x00 */
|
buffer[0] = 0xff;
|
buffer[1] = 0x00;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
}
|
|
return;
|
|
i2c_write_fail:
|
DC_LOG_DEBUG("Set retimer failed");
|
}
|
|
static void write_i2c_default_retimer_setting(
|
struct pipe_ctx *pipe_ctx,
|
bool is_vga_mode,
|
bool is_over_340mhz)
|
{
|
uint8_t slave_address = (0xBA >> 1);
|
uint8_t buffer[2];
|
bool i2c_success = false;
|
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
|
|
memset(&buffer, 0, sizeof(buffer));
|
|
/* Program Slave Address for tuning single integrity */
|
/* Write offset 0x0A to 0x13 */
|
buffer[0] = 0x0A;
|
buffer[1] = 0x13;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0x0A to 0x17 */
|
buffer[0] = 0x0A;
|
buffer[1] = 0x17;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0x0B to 0xDA or 0xD8 */
|
buffer[0] = 0x0B;
|
buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0x0A to 0x17 */
|
buffer[0] = 0x0A;
|
buffer[1] = 0x17;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
|
offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0x0C to 0x1D or 0x91 */
|
buffer[0] = 0x0C;
|
buffer[1] = is_over_340mhz ? 0x1D : 0x91;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0x0A to 0x17 */
|
buffer[0] = 0x0A;
|
buffer[1] = 0x17;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
|
if (is_vga_mode) {
|
/* Program additional settings if using 640x480 resolution */
|
|
/* Write offset 0xFF to 0x01 */
|
buffer[0] = 0xff;
|
buffer[1] = 0x01;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
|
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0x00 to 0x23 */
|
buffer[0] = 0x00;
|
buffer[1] = 0x23;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
|
offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
|
/* Write offset 0xff to 0x00 */
|
buffer[0] = 0xff;
|
buffer[1] = 0x00;
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
|
offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
|
slave_address, buffer[0], buffer[1], i2c_success?1:0);
|
if (!i2c_success)
|
goto i2c_write_fail;
|
}
|
|
return;
|
|
i2c_write_fail:
|
DC_LOG_DEBUG("Set default retimer failed");
|
}
|
|
static void write_i2c_redriver_setting(
|
struct pipe_ctx *pipe_ctx,
|
bool is_over_340mhz)
|
{
|
uint8_t slave_address = (0xF0 >> 1);
|
uint8_t buffer[16];
|
bool i2c_success = false;
|
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
|
|
memset(&buffer, 0, sizeof(buffer));
|
|
// Program Slave Address for tuning single integrity
|
buffer[3] = 0x4E;
|
buffer[4] = 0x4E;
|
buffer[5] = 0x4E;
|
buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
|
|
i2c_success = i2c_write(pipe_ctx, slave_address,
|
buffer, sizeof(buffer));
|
RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
|
\t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
|
offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
|
i2c_success = %d\n",
|
slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
|
|
if (!i2c_success)
|
DC_LOG_DEBUG("Set redriver failed");
|
}
|
|
static void disable_link(struct dc_link *link, enum signal_type signal)
|
{
|
/*
|
* TODO: implement call for dp_set_hw_test_pattern
|
* it is needed for compliance testing
|
*/
|
|
/* Here we need to specify that encoder output settings
|
* need to be calculated as for the set mode,
|
* it will lead to querying dynamic link capabilities
|
* which should be done before enable output
|
*/
|
|
if (dc_is_dp_signal(signal)) {
|
/* SST DP, eDP */
|
if (dc_is_dp_sst_signal(signal))
|
dp_disable_link_phy(link, signal);
|
else
|
dp_disable_link_phy_mst(link, signal);
|
|
if (dc_is_dp_sst_signal(signal) ||
|
link->mst_stream_alloc_table.stream_count == 0) {
|
dp_set_fec_enable(link, false);
|
dp_set_fec_ready(link, false);
|
}
|
} else {
|
if (signal != SIGNAL_TYPE_VIRTUAL)
|
link->link_enc->funcs->disable_output(link->link_enc, signal);
|
}
|
|
if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
|
/* MST disable link only when no stream use the link */
|
if (link->mst_stream_alloc_table.stream_count <= 0)
|
link->link_status.link_active = false;
|
} else {
|
link->link_status.link_active = false;
|
}
|
}
|
|
static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
|
{
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
struct dc_link *link = stream->link;
|
enum dc_color_depth display_color_depth;
|
enum engine_id eng_id;
|
struct ext_hdmi_settings settings = {0};
|
bool is_over_340mhz = false;
|
bool is_vga_mode = (stream->timing.h_addressable == 640)
|
&& (stream->timing.v_addressable == 480);
|
|
if (stream->phy_pix_clk == 0)
|
stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
|
if (stream->phy_pix_clk > 340000)
|
is_over_340mhz = true;
|
|
if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
|
unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
|
EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
|
if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
|
/* DP159, Retimer settings */
|
eng_id = pipe_ctx->stream_res.stream_enc->id;
|
|
if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
|
write_i2c_retimer_setting(pipe_ctx,
|
is_vga_mode, is_over_340mhz, &settings);
|
} else {
|
write_i2c_default_retimer_setting(pipe_ctx,
|
is_vga_mode, is_over_340mhz);
|
}
|
} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
|
/* PI3EQX1204, Redriver settings */
|
write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
|
}
|
}
|
|
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
|
dal_ddc_service_write_scdc_data(
|
stream->link->ddc,
|
stream->phy_pix_clk,
|
stream->timing.flags.LTE_340MCSC_SCRAMBLE);
|
|
memset(&stream->link->cur_link_settings, 0,
|
sizeof(struct dc_link_settings));
|
|
display_color_depth = stream->timing.display_color_depth;
|
if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
|
display_color_depth = COLOR_DEPTH_888;
|
|
link->link_enc->funcs->enable_tmds_output(
|
link->link_enc,
|
pipe_ctx->clock_source->id,
|
display_color_depth,
|
pipe_ctx->stream->signal,
|
stream->phy_pix_clk);
|
|
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
|
dal_ddc_service_read_scdc_data(link->ddc);
|
}
|
|
static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
|
{
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
struct dc_link *link = stream->link;
|
|
if (stream->phy_pix_clk == 0)
|
stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
|
|
memset(&stream->link->cur_link_settings, 0,
|
sizeof(struct dc_link_settings));
|
|
link->link_enc->funcs->enable_lvds_output(
|
link->link_enc,
|
pipe_ctx->clock_source->id,
|
stream->phy_pix_clk);
|
|
}
|
|
/****************************enable_link***********************************/
|
static enum dc_status enable_link(
|
struct dc_state *state,
|
struct pipe_ctx *pipe_ctx)
|
{
|
enum dc_status status = DC_ERROR_UNEXPECTED;
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
struct dc_link *link = stream->link;
|
|
/* There's some scenarios where driver is unloaded with display
|
* still enabled. When driver is reloaded, it may cause a display
|
* to not light up if there is a mismatch between old and new
|
* link settings. Need to call disable first before enabling at
|
* new link settings.
|
*/
|
if (link->link_status.link_active) {
|
disable_link(link, pipe_ctx->stream->signal);
|
}
|
|
switch (pipe_ctx->stream->signal) {
|
case SIGNAL_TYPE_DISPLAY_PORT:
|
status = enable_link_dp(state, pipe_ctx);
|
break;
|
case SIGNAL_TYPE_EDP:
|
status = enable_link_edp(state, pipe_ctx);
|
break;
|
case SIGNAL_TYPE_DISPLAY_PORT_MST:
|
status = enable_link_dp_mst(state, pipe_ctx);
|
msleep(200);
|
break;
|
case SIGNAL_TYPE_DVI_SINGLE_LINK:
|
case SIGNAL_TYPE_DVI_DUAL_LINK:
|
case SIGNAL_TYPE_HDMI_TYPE_A:
|
enable_link_hdmi(pipe_ctx);
|
status = DC_OK;
|
break;
|
case SIGNAL_TYPE_LVDS:
|
enable_link_lvds(pipe_ctx);
|
status = DC_OK;
|
break;
|
case SIGNAL_TYPE_VIRTUAL:
|
status = DC_OK;
|
break;
|
default:
|
break;
|
}
|
|
if (status == DC_OK)
|
pipe_ctx->stream->link->link_status.link_active = true;
|
|
return status;
|
}
|
|
static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
|
{
|
|
uint32_t pxl_clk = timing->pix_clk_100hz;
|
|
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
|
pxl_clk /= 2;
|
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
|
pxl_clk = pxl_clk * 2 / 3;
|
|
if (timing->display_color_depth == COLOR_DEPTH_101010)
|
pxl_clk = pxl_clk * 10 / 8;
|
else if (timing->display_color_depth == COLOR_DEPTH_121212)
|
pxl_clk = pxl_clk * 12 / 8;
|
|
return pxl_clk;
|
}
|
|
static bool dp_active_dongle_validate_timing(
|
const struct dc_crtc_timing *timing,
|
const struct dpcd_caps *dpcd_caps)
|
{
|
const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
|
|
switch (dpcd_caps->dongle_type) {
|
case DISPLAY_DONGLE_DP_VGA_CONVERTER:
|
case DISPLAY_DONGLE_DP_DVI_CONVERTER:
|
case DISPLAY_DONGLE_DP_DVI_DONGLE:
|
if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
|
return true;
|
else
|
return false;
|
default:
|
break;
|
}
|
|
if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
|
dongle_caps->extendedCapValid == false)
|
return true;
|
|
/* Check Pixel Encoding */
|
switch (timing->pixel_encoding) {
|
case PIXEL_ENCODING_RGB:
|
case PIXEL_ENCODING_YCBCR444:
|
break;
|
case PIXEL_ENCODING_YCBCR422:
|
if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
|
return false;
|
break;
|
case PIXEL_ENCODING_YCBCR420:
|
if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
|
return false;
|
break;
|
default:
|
/* Invalid Pixel Encoding*/
|
return false;
|
}
|
|
switch (timing->display_color_depth) {
|
case COLOR_DEPTH_666:
|
case COLOR_DEPTH_888:
|
/*888 and 666 should always be supported*/
|
break;
|
case COLOR_DEPTH_101010:
|
if (dongle_caps->dp_hdmi_max_bpc < 10)
|
return false;
|
break;
|
case COLOR_DEPTH_121212:
|
if (dongle_caps->dp_hdmi_max_bpc < 12)
|
return false;
|
break;
|
case COLOR_DEPTH_141414:
|
case COLOR_DEPTH_161616:
|
default:
|
/* These color depths are currently not supported */
|
return false;
|
}
|
|
if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
|
return false;
|
|
return true;
|
}
|
|
enum dc_status dc_link_validate_mode_timing(
|
const struct dc_stream_state *stream,
|
struct dc_link *link,
|
const struct dc_crtc_timing *timing)
|
{
|
uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
|
struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
|
|
/* A hack to avoid failing any modes for EDID override feature on
|
* topology change such as lower quality cable for DP or different dongle
|
*/
|
if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
|
return DC_OK;
|
|
/* Passive Dongle */
|
if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
|
return DC_EXCEED_DONGLE_CAP;
|
|
/* Active Dongle*/
|
if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
|
return DC_EXCEED_DONGLE_CAP;
|
|
switch (stream->signal) {
|
case SIGNAL_TYPE_EDP:
|
case SIGNAL_TYPE_DISPLAY_PORT:
|
if (!dp_validate_mode_timing(
|
link,
|
timing))
|
return DC_NO_DP_LINK_BANDWIDTH;
|
break;
|
|
default:
|
break;
|
}
|
|
return DC_OK;
|
}
|
|
static struct abm *get_abm_from_stream_res(const struct dc_link *link)
|
{
|
int i;
|
struct dc *dc = NULL;
|
struct abm *abm = NULL;
|
|
if (!link || !link->ctx)
|
return NULL;
|
|
dc = link->ctx->dc;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
|
struct dc_stream_state *stream = pipe_ctx.stream;
|
|
if (stream && stream->link == link) {
|
abm = pipe_ctx.stream_res.abm;
|
break;
|
}
|
}
|
return abm;
|
}
|
|
int dc_link_get_backlight_level(const struct dc_link *link)
|
{
|
|
struct abm *abm = get_abm_from_stream_res(link);
|
|
if (abm == NULL || abm->funcs->get_current_backlight == NULL)
|
return DC_ERROR_UNEXPECTED;
|
|
return (int) abm->funcs->get_current_backlight(abm);
|
}
|
|
int dc_link_get_target_backlight_pwm(const struct dc_link *link)
|
{
|
struct abm *abm = get_abm_from_stream_res(link);
|
|
if (abm == NULL || abm->funcs->get_target_backlight == NULL)
|
return DC_ERROR_UNEXPECTED;
|
|
return (int) abm->funcs->get_target_backlight(abm);
|
}
|
|
static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
|
{
|
int i;
|
struct dc *dc = link->ctx->dc;
|
struct pipe_ctx *pipe_ctx = NULL;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
|
if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
|
pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
|
break;
|
}
|
}
|
}
|
|
return pipe_ctx;
|
}
|
|
bool dc_link_set_backlight_level(const struct dc_link *link,
|
uint32_t backlight_pwm_u16_16,
|
uint32_t frame_ramp)
|
{
|
struct dc *dc = link->ctx->dc;
|
|
DC_LOGGER_INIT(link->ctx->logger);
|
DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
|
backlight_pwm_u16_16, backlight_pwm_u16_16);
|
|
if (dc_is_embedded_signal(link->connector_signal)) {
|
struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
|
|
if (pipe_ctx) {
|
/* Disable brightness ramping when the display is blanked
|
* as it can hang the DMCU
|
*/
|
if (pipe_ctx->plane_state == NULL)
|
frame_ramp = 0;
|
} else {
|
return false;
|
}
|
|
dc->hwss.set_backlight_level(
|
pipe_ctx,
|
backlight_pwm_u16_16,
|
frame_ramp);
|
}
|
return true;
|
}
|
|
bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
|
{
|
struct dc *dc = link->ctx->dc;
|
struct dmcu *dmcu = dc->res_pool->dmcu;
|
struct dmub_psr *psr = dc->res_pool->psr;
|
|
link->psr_settings.psr_allow_active = allow_active;
|
|
if (psr != NULL && link->psr_settings.psr_feature_enabled)
|
psr->funcs->psr_enable(psr, allow_active, wait);
|
else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
|
dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
|
else
|
return false;
|
|
return true;
|
}
|
|
bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
|
{
|
struct dc *dc = link->ctx->dc;
|
struct dmcu *dmcu = dc->res_pool->dmcu;
|
struct dmub_psr *psr = dc->res_pool->psr;
|
|
if (psr != NULL && link->psr_settings.psr_feature_enabled)
|
psr->funcs->psr_get_state(psr, psr_state);
|
else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
|
dmcu->funcs->get_psr_state(dmcu, psr_state);
|
|
return true;
|
}
|
|
static inline enum physical_phy_id
|
transmitter_to_phy_id(enum transmitter transmitter_value)
|
{
|
switch (transmitter_value) {
|
case TRANSMITTER_UNIPHY_A:
|
return PHYLD_0;
|
case TRANSMITTER_UNIPHY_B:
|
return PHYLD_1;
|
case TRANSMITTER_UNIPHY_C:
|
return PHYLD_2;
|
case TRANSMITTER_UNIPHY_D:
|
return PHYLD_3;
|
case TRANSMITTER_UNIPHY_E:
|
return PHYLD_4;
|
case TRANSMITTER_UNIPHY_F:
|
return PHYLD_5;
|
case TRANSMITTER_NUTMEG_CRT:
|
return PHYLD_6;
|
case TRANSMITTER_TRAVIS_CRT:
|
return PHYLD_7;
|
case TRANSMITTER_TRAVIS_LCD:
|
return PHYLD_8;
|
case TRANSMITTER_UNIPHY_G:
|
return PHYLD_9;
|
case TRANSMITTER_COUNT:
|
return PHYLD_COUNT;
|
case TRANSMITTER_UNKNOWN:
|
return PHYLD_UNKNOWN;
|
default:
|
WARN_ONCE(1, "Unknown transmitter value %d\n",
|
transmitter_value);
|
return PHYLD_UNKNOWN;
|
}
|
}
|
|
bool dc_link_setup_psr(struct dc_link *link,
|
const struct dc_stream_state *stream, struct psr_config *psr_config,
|
struct psr_context *psr_context)
|
{
|
struct dc *dc;
|
struct dmcu *dmcu;
|
struct dmub_psr *psr;
|
int i;
|
/* updateSinkPsrDpcdConfig*/
|
union dpcd_psr_configuration psr_configuration;
|
|
psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
|
|
if (!link)
|
return false;
|
|
dc = link->ctx->dc;
|
dmcu = dc->res_pool->dmcu;
|
psr = dc->res_pool->psr;
|
|
if (!dmcu && !psr)
|
return false;
|
|
|
memset(&psr_configuration, 0, sizeof(psr_configuration));
|
|
psr_configuration.bits.ENABLE = 1;
|
psr_configuration.bits.CRC_VERIFICATION = 1;
|
psr_configuration.bits.FRAME_CAPTURE_INDICATION =
|
psr_config->psr_frame_capture_indication_req;
|
|
/* Check for PSR v2*/
|
if (psr_config->psr_version == 0x2) {
|
/* For PSR v2 selective update.
|
* Indicates whether sink should start capturing
|
* immediately following active scan line,
|
* or starting with the 2nd active scan line.
|
*/
|
psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
|
/*For PSR v2, determines whether Sink should generate
|
* IRQ_HPD when CRC mismatch is detected.
|
*/
|
psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
|
}
|
|
dm_helpers_dp_write_dpcd(
|
link->ctx,
|
link,
|
368,
|
&psr_configuration.raw,
|
sizeof(psr_configuration.raw));
|
|
psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
|
psr_context->transmitterId = link->link_enc->transmitter;
|
psr_context->engineId = link->link_enc->preferred_engine;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
if (dc->current_state->res_ctx.pipe_ctx[i].stream
|
== stream) {
|
/* dmcu -1 for all controller id values,
|
* therefore +1 here
|
*/
|
psr_context->controllerId =
|
dc->current_state->res_ctx.
|
pipe_ctx[i].stream_res.tg->inst + 1;
|
break;
|
}
|
}
|
|
/* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
|
psr_context->phyType = PHY_TYPE_UNIPHY;
|
/*PhyId is associated with the transmitter id*/
|
psr_context->smuPhyId =
|
transmitter_to_phy_id(link->link_enc->transmitter);
|
|
psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
|
psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
|
timing.pix_clk_100hz * 100),
|
stream->timing.v_total),
|
stream->timing.h_total);
|
|
psr_context->psrSupportedDisplayConfig = true;
|
psr_context->psrExitLinkTrainingRequired =
|
psr_config->psr_exit_link_training_required;
|
psr_context->sdpTransmitLineNumDeadline =
|
psr_config->psr_sdp_transmit_line_num_deadline;
|
psr_context->psrFrameCaptureIndicationReq =
|
psr_config->psr_frame_capture_indication_req;
|
|
psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
|
|
psr_context->numberOfControllers =
|
link->dc->res_pool->timing_generator_count;
|
|
psr_context->rfb_update_auto_en = true;
|
|
/* 2 frames before enter PSR. */
|
psr_context->timehyst_frames = 2;
|
/* half a frame
|
* (units in 100 lines, i.e. a value of 1 represents 100 lines)
|
*/
|
psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
|
psr_context->aux_repeats = 10;
|
|
psr_context->psr_level.u32all = 0;
|
|
#if defined(CONFIG_DRM_AMD_DC_DCN)
|
/*skip power down the single pipe since it blocks the cstate*/
|
if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
|
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
|
#endif
|
|
/* SMU will perform additional powerdown sequence.
|
* For unsupported ASICs, set psr_level flag to skip PSR
|
* static screen notification to SMU.
|
* (Always set for DAL2, did not check ASIC)
|
*/
|
psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
|
|
/* Complete PSR entry before aborting to prevent intermittent
|
* freezes on certain eDPs
|
*/
|
psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
|
|
/* Controls additional delay after remote frame capture before
|
* continuing power down, default = 0
|
*/
|
psr_context->frame_delay = 0;
|
|
if (psr)
|
link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
|
else
|
link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
|
|
/* psr_enabled == 0 indicates setup_psr did not succeed, but this
|
* should not happen since firmware should be running at this point
|
*/
|
if (link->psr_settings.psr_feature_enabled == 0)
|
ASSERT(0);
|
|
return true;
|
|
}
|
|
const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
|
{
|
return &link->link_status;
|
}
|
|
void core_link_resume(struct dc_link *link)
|
{
|
if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
|
program_hpd_filter(link);
|
}
|
|
static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
|
{
|
struct fixed31_32 mbytes_per_sec;
|
uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
|
&stream->link->cur_link_settings);
|
link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
|
|
mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
|
|
return dc_fixpt_div_int(mbytes_per_sec, 54);
|
}
|
|
static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
|
{
|
uint64_t kbps;
|
struct fixed31_32 peak_kbps;
|
uint32_t numerator;
|
uint32_t denominator;
|
|
kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
|
|
/*
|
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
|
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
|
* common multiplier to render an integer PBN for all link rate/lane
|
* counts combinations
|
* calculate
|
* peak_kbps *= (1006/1000)
|
* peak_kbps *= (64/54)
|
* peak_kbps *= 8 convert to bytes
|
*/
|
|
numerator = 64 * PEAK_FACTOR_X1000;
|
denominator = 54 * 8 * 1000 * 1000;
|
kbps *= numerator;
|
peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
|
|
return peak_kbps;
|
}
|
|
static void update_mst_stream_alloc_table(
|
struct dc_link *link,
|
struct stream_encoder *stream_enc,
|
const struct dp_mst_stream_allocation_table *proposed_table)
|
{
|
struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
|
{ 0 } };
|
struct link_mst_stream_allocation *dc_alloc;
|
|
int i;
|
int j;
|
|
/* if DRM proposed_table has more than one new payload */
|
ASSERT(proposed_table->stream_count -
|
link->mst_stream_alloc_table.stream_count < 2);
|
|
/* copy proposed_table to link, add stream encoder */
|
for (i = 0; i < proposed_table->stream_count; i++) {
|
|
for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
|
dc_alloc =
|
&link->mst_stream_alloc_table.stream_allocations[j];
|
|
if (dc_alloc->vcp_id ==
|
proposed_table->stream_allocations[i].vcp_id) {
|
|
work_table[i] = *dc_alloc;
|
break; /* exit j loop */
|
}
|
}
|
|
/* new vcp_id */
|
if (j == link->mst_stream_alloc_table.stream_count) {
|
work_table[i].vcp_id =
|
proposed_table->stream_allocations[i].vcp_id;
|
work_table[i].slot_count =
|
proposed_table->stream_allocations[i].slot_count;
|
work_table[i].stream_enc = stream_enc;
|
}
|
}
|
|
/* update link->mst_stream_alloc_table with work_table */
|
link->mst_stream_alloc_table.stream_count =
|
proposed_table->stream_count;
|
for (i = 0; i < MAX_CONTROLLER_NUM; i++)
|
link->mst_stream_alloc_table.stream_allocations[i] =
|
work_table[i];
|
}
|
|
/* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
|
* because stream_encoder is not exposed to dm
|
*/
|
enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
|
{
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
struct dc_link *link = stream->link;
|
struct link_encoder *link_encoder = link->link_enc;
|
struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
|
struct dp_mst_stream_allocation_table proposed_table = {0};
|
struct fixed31_32 avg_time_slots_per_mtp;
|
struct fixed31_32 pbn;
|
struct fixed31_32 pbn_per_slot;
|
uint8_t i;
|
enum act_return_status ret;
|
DC_LOGGER_INIT(link->ctx->logger);
|
|
/* enable_link_dp_mst already check link->enabled_stream_count
|
* and stream is in link->stream[]. This is called during set mode,
|
* stream_enc is available.
|
*/
|
|
/* get calculate VC payload for stream: stream_alloc */
|
if (dm_helpers_dp_mst_write_payload_allocation_table(
|
stream->ctx,
|
stream,
|
&proposed_table,
|
true)) {
|
update_mst_stream_alloc_table(
|
link, pipe_ctx->stream_res.stream_enc, &proposed_table);
|
}
|
else
|
DC_LOG_WARNING("Failed to update"
|
"MST allocation table for"
|
"pipe idx:%d\n",
|
pipe_ctx->pipe_idx);
|
|
DC_LOG_MST("%s "
|
"stream_count: %d: \n ",
|
__func__,
|
link->mst_stream_alloc_table.stream_count);
|
|
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
|
DC_LOG_MST("stream_enc[%d]: %p "
|
"stream[%d].vcp_id: %d "
|
"stream[%d].slot_count: %d\n",
|
i,
|
(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
|
i,
|
link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
|
i,
|
link->mst_stream_alloc_table.stream_allocations[i].slot_count);
|
}
|
|
ASSERT(proposed_table.stream_count > 0);
|
|
/* program DP source TX for payload */
|
link_encoder->funcs->update_mst_stream_allocation_table(
|
link_encoder,
|
&link->mst_stream_alloc_table);
|
|
/* send down message */
|
ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
|
stream->ctx,
|
stream);
|
|
if (ret != ACT_LINK_LOST) {
|
dm_helpers_dp_mst_send_payload_allocation(
|
stream->ctx,
|
stream,
|
true);
|
}
|
|
/* slot X.Y for only current stream */
|
pbn_per_slot = get_pbn_per_slot(stream);
|
pbn = get_pbn_from_timing(pipe_ctx);
|
avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
|
|
stream_encoder->funcs->set_throttled_vcp_size(
|
stream_encoder,
|
avg_time_slots_per_mtp);
|
|
return DC_OK;
|
|
}
|
|
static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
|
{
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
struct dc_link *link = stream->link;
|
struct link_encoder *link_encoder = link->link_enc;
|
struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
|
struct dp_mst_stream_allocation_table proposed_table = {0};
|
struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
|
uint8_t i;
|
bool mst_mode = (link->type == dc_connection_mst_branch);
|
DC_LOGGER_INIT(link->ctx->logger);
|
|
/* deallocate_mst_payload is called before disable link. When mode or
|
* disable/enable monitor, new stream is created which is not in link
|
* stream[] yet. For this, payload is not allocated yet, so de-alloc
|
* should not done. For new mode set, map_resources will get engine
|
* for new stream, so stream_enc->id should be validated until here.
|
*/
|
|
/* slot X.Y */
|
stream_encoder->funcs->set_throttled_vcp_size(
|
stream_encoder,
|
avg_time_slots_per_mtp);
|
|
/* TODO: which component is responsible for remove payload table? */
|
if (mst_mode) {
|
if (dm_helpers_dp_mst_write_payload_allocation_table(
|
stream->ctx,
|
stream,
|
&proposed_table,
|
false)) {
|
|
update_mst_stream_alloc_table(
|
link, pipe_ctx->stream_res.stream_enc, &proposed_table);
|
}
|
else {
|
DC_LOG_WARNING("Failed to update"
|
"MST allocation table for"
|
"pipe idx:%d\n",
|
pipe_ctx->pipe_idx);
|
}
|
}
|
|
DC_LOG_MST("%s"
|
"stream_count: %d: ",
|
__func__,
|
link->mst_stream_alloc_table.stream_count);
|
|
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
|
DC_LOG_MST("stream_enc[%d]: %p "
|
"stream[%d].vcp_id: %d "
|
"stream[%d].slot_count: %d\n",
|
i,
|
(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
|
i,
|
link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
|
i,
|
link->mst_stream_alloc_table.stream_allocations[i].slot_count);
|
}
|
|
link_encoder->funcs->update_mst_stream_allocation_table(
|
link_encoder,
|
&link->mst_stream_alloc_table);
|
|
if (mst_mode) {
|
dm_helpers_dp_mst_poll_for_allocation_change_trigger(
|
stream->ctx,
|
stream);
|
|
dm_helpers_dp_mst_send_payload_allocation(
|
stream->ctx,
|
stream,
|
false);
|
}
|
|
return DC_OK;
|
}
|
|
enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link)
|
{
|
int i;
|
struct pipe_ctx *pipe_ctx;
|
|
// Clear all of MST payload then reallocate
|
for (i = 0; i < MAX_PIPES; i++) {
|
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
|
|
/* driver enable split pipe for external monitors
|
* we have to check pipe_ctx is split pipe or not
|
* If it's split pipe, driver using top pipe to
|
* reaallocate.
|
*/
|
if (!pipe_ctx || pipe_ctx->top_pipe)
|
continue;
|
|
if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
|
pipe_ctx->stream->dpms_off == false &&
|
pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
|
deallocate_mst_payload(pipe_ctx);
|
}
|
}
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
|
|
if (!pipe_ctx || pipe_ctx->top_pipe)
|
continue;
|
|
if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
|
pipe_ctx->stream->dpms_off == false &&
|
pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
|
/* enable/disable PHY will clear connection between BE and FE
|
* need to restore it.
|
*/
|
link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
|
pipe_ctx->stream_res.stream_enc->id, true);
|
dc_link_allocate_mst_payload(pipe_ctx);
|
}
|
}
|
|
return DC_OK;
|
}
|
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
|
{
|
struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
|
if (cp_psp && cp_psp->funcs.update_stream_config) {
|
struct cp_psp_stream_config config;
|
|
memset(&config, 0, sizeof(config));
|
|
config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
|
/*stream_enc_inst*/
|
config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
|
config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
|
config.dpms_off = dpms_off;
|
config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
|
config.mst_supported = (pipe_ctx->stream->signal ==
|
SIGNAL_TYPE_DISPLAY_PORT_MST);
|
cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
|
}
|
}
|
#endif
|
|
void core_link_enable_stream(
|
struct dc_state *state,
|
struct pipe_ctx *pipe_ctx)
|
{
|
struct dc *dc = pipe_ctx->stream->ctx->dc;
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
enum dc_status status;
|
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
|
#endif
|
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
|
|
if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
|
dc_is_virtual_signal(pipe_ctx->stream->signal))
|
return;
|
|
if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
|
stream->link->link_enc->funcs->setup(
|
stream->link->link_enc,
|
pipe_ctx->stream->signal);
|
pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
|
pipe_ctx->stream_res.stream_enc,
|
pipe_ctx->stream_res.tg->inst,
|
stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
|
}
|
|
if (dc_is_dp_signal(pipe_ctx->stream->signal))
|
pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
|
pipe_ctx->stream_res.stream_enc,
|
&stream->timing,
|
stream->output_color_space,
|
stream->use_vsc_sdp_for_colorimetry,
|
stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
|
|
if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
|
pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
|
pipe_ctx->stream_res.stream_enc,
|
&stream->timing,
|
stream->phy_pix_clk,
|
pipe_ctx->stream_res.audio != NULL);
|
|
pipe_ctx->stream->link->link_state_valid = true;
|
|
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
|
pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
|
#endif
|
|
if (dc_is_dvi_signal(pipe_ctx->stream->signal))
|
pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
|
pipe_ctx->stream_res.stream_enc,
|
&stream->timing,
|
(pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
|
true : false);
|
|
if (dc_is_lvds_signal(pipe_ctx->stream->signal))
|
pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
|
pipe_ctx->stream_res.stream_enc,
|
&stream->timing);
|
|
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
|
bool apply_edp_fast_boot_optimization =
|
pipe_ctx->stream->apply_edp_fast_boot_optimization;
|
|
pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
|
|
resource_build_info_frame(pipe_ctx);
|
dc->hwss.update_info_frame(pipe_ctx);
|
|
/* Do not touch link on seamless boot optimization. */
|
if (pipe_ctx->stream->apply_seamless_boot_optimization) {
|
pipe_ctx->stream->dpms_off = false;
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
update_psp_stream_config(pipe_ctx, false);
|
#endif
|
return;
|
}
|
|
/* eDP lit up by bios already, no need to enable again. */
|
if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
|
apply_edp_fast_boot_optimization) {
|
pipe_ctx->stream->dpms_off = false;
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
update_psp_stream_config(pipe_ctx, false);
|
#endif
|
return;
|
}
|
|
if (pipe_ctx->stream->dpms_off)
|
return;
|
|
/* Have to setup DSC before DIG FE and BE are connected (which happens before the
|
* link training). This is to make sure the bandwidth sent to DIG BE won't be
|
* bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
|
* will be automatically set at a later time when the video is enabled
|
* (DP_VID_STREAM_EN = 1).
|
*/
|
if (pipe_ctx->stream->timing.flags.DSC) {
|
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
|
dc_is_virtual_signal(pipe_ctx->stream->signal))
|
dp_set_dsc_enable(pipe_ctx, true);
|
}
|
|
status = enable_link(state, pipe_ctx);
|
|
if (status != DC_OK) {
|
DC_LOG_WARNING("enabling link %u failed: %d\n",
|
pipe_ctx->stream->link->link_index,
|
status);
|
|
/* Abort stream enable *unless* the failure was due to
|
* DP link training - some DP monitors will recover and
|
* show the stream anyway. But MST displays can't proceed
|
* without link training.
|
*/
|
if (status != DC_FAIL_DP_LINK_TRAINING ||
|
pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
|
BREAK_TO_DEBUGGER();
|
return;
|
}
|
}
|
|
dc->hwss.enable_audio_stream(pipe_ctx);
|
|
/* turn off otg test pattern if enable */
|
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
|
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
|
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
|
COLOR_DEPTH_UNDEFINED);
|
|
/* This second call is needed to reconfigure the DIG
|
* as a workaround for the incorrect value being applied
|
* from transmitter control.
|
*/
|
if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
|
stream->link->link_enc->funcs->setup(
|
stream->link->link_enc,
|
pipe_ctx->stream->signal);
|
|
dc->hwss.enable_stream(pipe_ctx);
|
|
/* Set DPS PPS SDP (AKA "info frames") */
|
if (pipe_ctx->stream->timing.flags.DSC) {
|
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
|
dc_is_virtual_signal(pipe_ctx->stream->signal))
|
dp_set_dsc_pps_sdp(pipe_ctx, true);
|
}
|
|
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
|
dc_link_allocate_mst_payload(pipe_ctx);
|
|
dc->hwss.unblank_stream(pipe_ctx,
|
&pipe_ctx->stream->link->cur_link_settings);
|
|
if (stream->sink_patches.delay_ignore_msa > 0)
|
msleep(stream->sink_patches.delay_ignore_msa);
|
|
if (dc_is_dp_signal(pipe_ctx->stream->signal))
|
enable_stream_features(pipe_ctx);
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
update_psp_stream_config(pipe_ctx, false);
|
#endif
|
} else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
|
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
|
dc_is_virtual_signal(pipe_ctx->stream->signal))
|
dp_set_dsc_enable(pipe_ctx, true);
|
|
}
|
|
if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
|
core_link_set_avmute(pipe_ctx, false);
|
}
|
}
|
|
void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
|
{
|
struct dc *dc = pipe_ctx->stream->ctx->dc;
|
struct dc_stream_state *stream = pipe_ctx->stream;
|
struct dc_link *link = stream->sink->link;
|
|
if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
|
dc_is_virtual_signal(pipe_ctx->stream->signal))
|
return;
|
|
if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
|
core_link_set_avmute(pipe_ctx, true);
|
}
|
|
#if defined(CONFIG_DRM_AMD_DC_HDCP)
|
update_psp_stream_config(pipe_ctx, true);
|
#endif
|
dc->hwss.blank_stream(pipe_ctx);
|
|
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
|
deallocate_mst_payload(pipe_ctx);
|
|
if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
|
struct ext_hdmi_settings settings = {0};
|
enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
|
|
unsigned short masked_chip_caps = link->chip_caps &
|
EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
|
//Need to inform that sink is going to use legacy HDMI mode.
|
dal_ddc_service_write_scdc_data(
|
link->ddc,
|
165000,//vbios only handles 165Mhz.
|
false);
|
if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
|
/* DP159, Retimer settings */
|
if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
|
write_i2c_retimer_setting(pipe_ctx,
|
false, false, &settings);
|
else
|
write_i2c_default_retimer_setting(pipe_ctx,
|
false, false);
|
} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
|
/* PI3EQX1204, Redriver settings */
|
write_i2c_redriver_setting(pipe_ctx, false);
|
}
|
}
|
|
disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
|
|
dc->hwss.disable_stream(pipe_ctx);
|
|
if (pipe_ctx->stream->timing.flags.DSC) {
|
if (dc_is_dp_signal(pipe_ctx->stream->signal))
|
dp_set_dsc_enable(pipe_ctx, false);
|
}
|
}
|
|
void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
|
{
|
struct dc *dc = pipe_ctx->stream->ctx->dc;
|
|
if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
|
return;
|
|
dc->hwss.set_avmute(pipe_ctx, enable);
|
}
|
|
/**
|
*****************************************************************************
|
* Function: dc_link_enable_hpd_filter
|
*
|
* @brief
|
* If enable is true, programs HPD filter on associated HPD line using
|
* delay_on_disconnect/delay_on_connect values dependent on
|
* link->connector_signal
|
*
|
* If enable is false, programs HPD filter on associated HPD line with no
|
* delays on connect or disconnect
|
*
|
* @param [in] link: pointer to the dc link
|
* @param [in] enable: boolean specifying whether to enable hbd
|
*****************************************************************************
|
*/
|
void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
|
{
|
struct gpio *hpd;
|
|
if (enable) {
|
link->is_hpd_filter_disabled = false;
|
program_hpd_filter(link);
|
} else {
|
link->is_hpd_filter_disabled = true;
|
/* Obtain HPD handle */
|
hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
|
|
if (!hpd)
|
return;
|
|
/* Setup HPD filtering */
|
if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
|
struct gpio_hpd_config config;
|
|
config.delay_on_connect = 0;
|
config.delay_on_disconnect = 0;
|
|
dal_irq_setup_hpd_filter(hpd, &config);
|
|
dal_gpio_close(hpd);
|
} else {
|
ASSERT_CRITICAL(false);
|
}
|
/* Release HPD handle */
|
dal_gpio_destroy_irq(&hpd);
|
}
|
}
|
|
uint32_t dc_bandwidth_in_kbps_from_timing(
|
const struct dc_crtc_timing *timing)
|
{
|
uint32_t bits_per_channel = 0;
|
uint32_t kbps;
|
struct fixed31_32 link_bw_kbps;
|
|
if (timing->flags.DSC) {
|
link_bw_kbps = dc_fixpt_from_int(timing->pix_clk_100hz);
|
link_bw_kbps = dc_fixpt_div_int(link_bw_kbps, 160);
|
link_bw_kbps = dc_fixpt_mul_int(link_bw_kbps, timing->dsc_cfg.bits_per_pixel);
|
kbps = dc_fixpt_ceil(link_bw_kbps);
|
return kbps;
|
}
|
|
switch (timing->display_color_depth) {
|
case COLOR_DEPTH_666:
|
bits_per_channel = 6;
|
break;
|
case COLOR_DEPTH_888:
|
bits_per_channel = 8;
|
break;
|
case COLOR_DEPTH_101010:
|
bits_per_channel = 10;
|
break;
|
case COLOR_DEPTH_121212:
|
bits_per_channel = 12;
|
break;
|
case COLOR_DEPTH_141414:
|
bits_per_channel = 14;
|
break;
|
case COLOR_DEPTH_161616:
|
bits_per_channel = 16;
|
break;
|
default:
|
break;
|
}
|
|
ASSERT(bits_per_channel != 0);
|
|
kbps = timing->pix_clk_100hz / 10;
|
kbps *= bits_per_channel;
|
|
if (timing->flags.Y_ONLY != 1) {
|
/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
|
kbps *= 3;
|
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
|
kbps /= 2;
|
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
|
kbps = kbps * 2 / 3;
|
}
|
|
return kbps;
|
|
}
|
|
void dc_link_set_drive_settings(struct dc *dc,
|
struct link_training_settings *lt_settings,
|
const struct dc_link *link)
|
{
|
|
int i;
|
|
for (i = 0; i < dc->link_count; i++) {
|
if (dc->links[i] == link)
|
break;
|
}
|
|
if (i >= dc->link_count)
|
ASSERT_CRITICAL(false);
|
|
dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
|
}
|
|
void dc_link_perform_link_training(struct dc *dc,
|
struct dc_link_settings *link_setting,
|
bool skip_video_pattern)
|
{
|
int i;
|
|
for (i = 0; i < dc->link_count; i++)
|
dc_link_dp_perform_link_training(
|
dc->links[i],
|
link_setting,
|
skip_video_pattern);
|
}
|
|
void dc_link_set_preferred_link_settings(struct dc *dc,
|
struct dc_link_settings *link_setting,
|
struct dc_link *link)
|
{
|
int i;
|
struct pipe_ctx *pipe;
|
struct dc_stream_state *link_stream;
|
struct dc_link_settings store_settings = *link_setting;
|
|
link->preferred_link_setting = store_settings;
|
|
/* Retrain with preferred link settings only relevant for
|
* DP signal type
|
* Check for non-DP signal or if passive dongle present
|
*/
|
if (!dc_is_dp_signal(link->connector_signal) ||
|
link->dongle_max_pix_clk > 0)
|
return;
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
|
if (pipe->stream && pipe->stream->link) {
|
if (pipe->stream->link == link) {
|
link_stream = pipe->stream;
|
break;
|
}
|
}
|
}
|
|
/* Stream not found */
|
if (i == MAX_PIPES)
|
return;
|
|
/* Cannot retrain link if backend is off */
|
if (link_stream->dpms_off)
|
return;
|
|
decide_link_settings(link_stream, &store_settings);
|
|
if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
|
(store_settings.link_rate != LINK_RATE_UNKNOWN))
|
dp_retrain_link_dp_test(link, &store_settings, false);
|
}
|
|
void dc_link_set_preferred_training_settings(struct dc *dc,
|
struct dc_link_settings *link_setting,
|
struct dc_link_training_overrides *lt_overrides,
|
struct dc_link *link,
|
bool skip_immediate_retrain)
|
{
|
if (lt_overrides != NULL)
|
link->preferred_training_settings = *lt_overrides;
|
else
|
memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
|
|
if (link_setting != NULL) {
|
link->preferred_link_setting = *link_setting;
|
} else {
|
link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
|
link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
|
}
|
|
/* Retrain now, or wait until next stream update to apply */
|
if (skip_immediate_retrain == false)
|
dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
|
}
|
|
void dc_link_enable_hpd(const struct dc_link *link)
|
{
|
dc_link_dp_enable_hpd(link);
|
}
|
|
void dc_link_disable_hpd(const struct dc_link *link)
|
{
|
dc_link_dp_disable_hpd(link);
|
}
|
|
void dc_link_set_test_pattern(struct dc_link *link,
|
enum dp_test_pattern test_pattern,
|
enum dp_test_pattern_color_space test_pattern_color_space,
|
const struct link_training_settings *p_link_settings,
|
const unsigned char *p_custom_pattern,
|
unsigned int cust_pattern_size)
|
{
|
if (link != NULL)
|
dc_link_dp_set_test_pattern(
|
link,
|
test_pattern,
|
test_pattern_color_space,
|
p_link_settings,
|
p_custom_pattern,
|
cust_pattern_size);
|
}
|
|
uint32_t dc_link_bandwidth_kbps(
|
const struct dc_link *link,
|
const struct dc_link_settings *link_setting)
|
{
|
uint32_t link_bw_kbps =
|
link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
|
|
link_bw_kbps *= 8; /* 8 bits per byte*/
|
link_bw_kbps *= link_setting->lane_count;
|
|
if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
|
/* Account for FEC overhead.
|
* We have to do it based on caps,
|
* and not based on FEC being set ready,
|
* because FEC is set ready too late in
|
* the process to correctly be picked up
|
* by mode enumeration.
|
*
|
* There's enough zeros at the end of 'kbps'
|
* that make the below operation 100% precise
|
* for our purposes.
|
* 'long long' makes it work even for HDMI 2.1
|
* max bandwidth (and much, much bigger bandwidths
|
* than that, actually).
|
*
|
* NOTE: Reducing link BW by 3% may not be precise
|
* because it may be a stream BT that increases by 3%, and so
|
* 1/1.03 = 0.970873 factor should have been used instead,
|
* but the difference is minimal and is in a safe direction,
|
* which all works well around potential ambiguity of DP 1.4a spec.
|
*/
|
link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
|
link_bw_kbps, 32);
|
}
|
|
return link_bw_kbps;
|
|
}
|
|
const struct dc_link_settings *dc_link_get_link_cap(
|
const struct dc_link *link)
|
{
|
if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
|
link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
|
return &link->preferred_link_setting;
|
return &link->verified_link_cap;
|
}
|
|
void dc_link_overwrite_extended_receiver_cap(
|
struct dc_link *link)
|
{
|
dp_overwrite_extended_receiver_cap(link);
|
}
|
|
bool dc_link_is_fec_supported(const struct dc_link *link)
|
{
|
return (dc_is_dp_signal(link->connector_signal) &&
|
link->link_enc->features.fec_supported &&
|
link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
|
!IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
|
}
|
