/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_DM_IRQ_H__
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#define __AMDGPU_DM_IRQ_H__
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#include "irq_types.h" /* DAL irq definitions */
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/*
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* Display Manager IRQ-related interfaces (for use by DAL).
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*/
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/**
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* amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'.
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*
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* This function should be called exactly once - during DM initialization.
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*
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* Returns:
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* 0 - success
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* non-zero - error
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*/
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int amdgpu_dm_irq_init(struct amdgpu_device *adev);
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/**
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* amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'.
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*
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* This function should be called exactly once - during DM destruction.
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*
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*/
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void amdgpu_dm_irq_fini(struct amdgpu_device *adev);
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/**
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* amdgpu_dm_irq_register_interrupt - register irq handler for Display block.
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*
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* @adev: AMD DRM device
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* @int_params: parameters for the irq
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* @ih: pointer to the irq hander function
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* @handler_args: arguments which will be passed to ih
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*
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* Returns:
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* IRQ Handler Index on success.
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* NULL on failure.
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*
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* Cannot be called from an interrupt handler.
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*/
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void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
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struct dc_interrupt_params *int_params,
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void (*ih)(void *),
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void *handler_args);
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/**
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* amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered
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* by amdgpu_dm_irq_register_interrupt().
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*
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* @adev: AMD DRM device.
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* @ih_index: irq handler index which was returned by
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* amdgpu_dm_irq_register_interrupt
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*/
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void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
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enum dc_irq_source irq_source,
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void *ih_index);
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void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
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void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
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void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
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/**
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* amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.
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*
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*/
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int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
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/**
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* amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume.
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* amdgpu_dm_irq_resume - enable ASIC interrupt during resume.
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*
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*/
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int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);
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int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);
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#endif /* __AMDGPU_DM_IRQ_H__ */
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