/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services_types.h"
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#include "dc.h"
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#include "amdgpu.h"
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#include "amdgpu_dm.h"
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#include "amdgpu_dm_irq.h"
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/**
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* DOC: overview
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*
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* DM provides another layer of IRQ management on top of what the base driver
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* already provides. This is something that could be cleaned up, and is a
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* future TODO item.
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*
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* The base driver provides IRQ source registration with DRM, handler
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* registration into the base driver's IRQ table, and a handler callback
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* amdgpu_irq_handler(), with which DRM calls on interrupts. This generic
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* handler looks up the IRQ table, and calls the respective
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* &amdgpu_irq_src_funcs.process hookups.
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*
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* What DM provides on top are two IRQ tables specifically for top-half and
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* bottom-half IRQ handling, with the bottom-half implementing workqueues:
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*
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* - &amdgpu_display_manager.irq_handler_list_high_tab
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* - &amdgpu_display_manager.irq_handler_list_low_tab
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*
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* They override the base driver's IRQ table, and the effect can be seen
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* in the hooks that DM provides for &amdgpu_irq_src_funcs.process. They
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* are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up
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* DM's IRQ tables. However, in order for base driver to recognize this hook, DM
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* still needs to register the IRQ with the base driver. See
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* dce110_register_irq_handlers() and dcn10_register_irq_handlers().
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*
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* To expose DC's hardware interrupt toggle to the base driver, DM implements
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* &amdgpu_irq_src_funcs.set hooks. Base driver calls it through
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* amdgpu_irq_update() to enable or disable the interrupt.
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*/
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/******************************************************************************
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* Private declarations.
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*****************************************************************************/
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/**
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* struct amdgpu_dm_irq_handler_data - Data for DM interrupt handlers.
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*
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* @list: Linked list entry referencing the next/previous handler
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* @handler: Handler function
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* @handler_arg: Argument passed to the handler when triggered
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* @dm: DM which this handler belongs to
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* @irq_source: DC interrupt source that this handler is registered for
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*/
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struct amdgpu_dm_irq_handler_data {
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struct list_head list;
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interrupt_handler handler;
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void *handler_arg;
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struct amdgpu_display_manager *dm;
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/* DAL irq source which registered for this interrupt. */
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enum dc_irq_source irq_source;
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struct work_struct work;
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};
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#define DM_IRQ_TABLE_LOCK(adev, flags) \
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spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
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#define DM_IRQ_TABLE_UNLOCK(adev, flags) \
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spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
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/******************************************************************************
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* Private functions.
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*****************************************************************************/
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static void init_handler_common_data(struct amdgpu_dm_irq_handler_data *hcd,
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void (*ih)(void *),
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void *args,
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struct amdgpu_display_manager *dm)
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{
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hcd->handler = ih;
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hcd->handler_arg = args;
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hcd->dm = dm;
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}
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/**
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* dm_irq_work_func() - Handle an IRQ outside of the interrupt handler proper.
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*
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* @work: work struct
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*/
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static void dm_irq_work_func(struct work_struct *work)
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{
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struct amdgpu_dm_irq_handler_data *handler_data =
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container_of(work, struct amdgpu_dm_irq_handler_data, work);
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handler_data->handler(handler_data->handler_arg);
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/* Call a DAL subcomponent which registered for interrupt notification
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* at INTERRUPT_LOW_IRQ_CONTEXT.
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* (The most common use is HPD interrupt) */
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}
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/*
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* Remove a handler and return a pointer to handler list from which the
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* handler was removed.
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*/
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static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
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void *ih,
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const struct dc_interrupt_params *int_params)
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{
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struct list_head *hnd_list;
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struct list_head *entry, *tmp;
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struct amdgpu_dm_irq_handler_data *handler;
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unsigned long irq_table_flags;
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bool handler_removed = false;
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enum dc_irq_source irq_source;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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irq_source = int_params->irq_source;
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switch (int_params->int_context) {
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case INTERRUPT_HIGH_IRQ_CONTEXT:
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hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
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break;
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case INTERRUPT_LOW_IRQ_CONTEXT:
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default:
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hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source];
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break;
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}
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list_for_each_safe(entry, tmp, hnd_list) {
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handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
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list);
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if (ih == handler) {
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/* Found our handler. Remove it from the list. */
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list_del(&handler->list);
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handler_removed = true;
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break;
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}
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}
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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if (handler_removed == false) {
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/* Not necessarily an error - caller may not
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* know the context. */
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return NULL;
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}
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kfree(handler);
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DRM_DEBUG_KMS(
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"DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
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ih, int_params->irq_source, int_params->int_context);
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return hnd_list;
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}
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static bool
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validate_irq_registration_params(struct dc_interrupt_params *int_params,
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void (*ih)(void *))
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{
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if (NULL == int_params || NULL == ih) {
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DRM_ERROR("DM_IRQ: invalid input!\n");
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return false;
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}
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if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
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DRM_ERROR("DM_IRQ: invalid context: %d!\n",
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int_params->int_context);
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return false;
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}
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if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
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DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
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int_params->irq_source);
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return false;
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}
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return true;
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}
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static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
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irq_handler_idx handler_idx)
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{
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if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
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DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
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return false;
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}
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if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
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DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
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return false;
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}
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return true;
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}
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/******************************************************************************
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* Public functions.
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*
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* Note: caller is responsible for input validation.
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*****************************************************************************/
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/**
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* amdgpu_dm_irq_register_interrupt() - Register a handler within DM.
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* @adev: The base driver device containing the DM device.
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* @int_params: Interrupt parameters containing the source, and handler context
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* @ih: Function pointer to the interrupt handler to register
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* @handler_args: Arguments passed to the handler when the interrupt occurs
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*
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* Register an interrupt handler for the given IRQ source, under the given
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* context. The context can either be high or low. High context handlers are
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* executed directly within ISR context, while low context is executed within a
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* workqueue, thereby allowing operations that sleep.
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*
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* Registered handlers are called in a FIFO manner, i.e. the most recently
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* registered handler will be called first.
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*
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* Return: Handler data &struct amdgpu_dm_irq_handler_data containing the IRQ
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* source, handler function, and args
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*/
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void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
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struct dc_interrupt_params *int_params,
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void (*ih)(void *),
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void *handler_args)
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{
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struct list_head *hnd_list;
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struct amdgpu_dm_irq_handler_data *handler_data;
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unsigned long irq_table_flags;
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enum dc_irq_source irq_source;
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if (false == validate_irq_registration_params(int_params, ih))
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return DAL_INVALID_IRQ_HANDLER_IDX;
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handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
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if (!handler_data) {
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DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
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return DAL_INVALID_IRQ_HANDLER_IDX;
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}
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init_handler_common_data(handler_data, ih, handler_args, &adev->dm);
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irq_source = int_params->irq_source;
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handler_data->irq_source = irq_source;
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/* Lock the list, add the handler. */
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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switch (int_params->int_context) {
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case INTERRUPT_HIGH_IRQ_CONTEXT:
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hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
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break;
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case INTERRUPT_LOW_IRQ_CONTEXT:
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default:
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hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source];
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INIT_WORK(&handler_data->work, dm_irq_work_func);
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break;
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}
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list_add_tail(&handler_data->list, hnd_list);
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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/* This pointer will be stored by code which requested interrupt
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* registration.
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* The same pointer will be needed in order to unregister the
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* interrupt. */
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DRM_DEBUG_KMS(
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"DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
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handler_data,
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irq_source,
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int_params->int_context);
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return handler_data;
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}
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/**
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* amdgpu_dm_irq_unregister_interrupt() - Remove a handler from the DM IRQ table
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* @adev: The base driver device containing the DM device
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* @irq_source: IRQ source to remove the given handler from
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* @ih: Function pointer to the interrupt handler to unregister
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*
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* Go through both low and high context IRQ tables, and find the given handler
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* for the given irq source. If found, remove it. Otherwise, do nothing.
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*/
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void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
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enum dc_irq_source irq_source,
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void *ih)
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{
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struct list_head *handler_list;
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struct dc_interrupt_params int_params;
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int i;
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if (false == validate_irq_unregistration_params(irq_source, ih))
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return;
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memset(&int_params, 0, sizeof(int_params));
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int_params.irq_source = irq_source;
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for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
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int_params.int_context = i;
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handler_list = remove_irq_handler(adev, ih, &int_params);
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if (handler_list != NULL)
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break;
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}
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if (handler_list == NULL) {
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/* If we got here, it means we searched all irq contexts
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* for this irq source, but the handler was not found. */
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DRM_ERROR(
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"DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
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ih, irq_source);
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}
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}
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/**
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* amdgpu_dm_irq_init() - Initialize DM IRQ management
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* @adev: The base driver device containing the DM device
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*
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* Initialize DM's high and low context IRQ tables.
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*
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* The N by M table contains N IRQ sources, with M
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* &struct amdgpu_dm_irq_handler_data hooked together in a linked list. The
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* list_heads are initialized here. When an interrupt n is triggered, all m
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* handlers are called in sequence, FIFO according to registration order.
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*
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* The low context table requires special steps to initialize, since handlers
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* will be deferred to a workqueue. See &struct irq_list_head.
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*/
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int amdgpu_dm_irq_init(struct amdgpu_device *adev)
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{
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int src;
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struct list_head *lh;
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DRM_DEBUG_KMS("DM_IRQ\n");
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spin_lock_init(&adev->dm.irq_handler_list_table_lock);
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for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
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/* low context handler list init */
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lh = &adev->dm.irq_handler_list_low_tab[src];
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INIT_LIST_HEAD(lh);
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/* high context handler init */
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INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
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}
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return 0;
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}
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/**
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* amdgpu_dm_irq_fini() - Tear down DM IRQ management
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* @adev: The base driver device containing the DM device
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*
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* Flush all work within the low context IRQ table.
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*/
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void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
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{
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int src;
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struct list_head *lh;
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struct list_head *entry, *tmp;
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struct amdgpu_dm_irq_handler_data *handler;
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unsigned long irq_table_flags;
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DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
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for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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/* The handler was removed from the table,
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* it means it is safe to flush all the 'work'
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* (because no code can schedule a new one). */
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lh = &adev->dm.irq_handler_list_low_tab[src];
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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if (!list_empty(lh)) {
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list_for_each_safe(entry, tmp, lh) {
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handler = list_entry(
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entry,
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struct amdgpu_dm_irq_handler_data,
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list);
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flush_work(&handler->work);
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}
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}
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}
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}
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int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
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{
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int src;
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struct list_head *hnd_list_h;
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struct list_head *hnd_list_l;
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unsigned long irq_table_flags;
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struct list_head *entry, *tmp;
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struct amdgpu_dm_irq_handler_data *handler;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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DRM_DEBUG_KMS("DM_IRQ: suspend\n");
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/**
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* Disable HW interrupt for HPD and HPDRX only since FLIP and VBLANK
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* will be disabled from manage_dm_interrupts on disable CRTC.
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*/
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for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
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hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
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hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
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if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
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dc_interrupt_set(adev->dm.dc, src, false);
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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if (!list_empty(hnd_list_l)) {
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list_for_each_safe (entry, tmp, hnd_list_l) {
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handler = list_entry(
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entry,
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struct amdgpu_dm_irq_handler_data,
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list);
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flush_work(&handler->work);
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}
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}
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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}
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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return 0;
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}
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int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
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{
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int src;
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struct list_head *hnd_list_h, *hnd_list_l;
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unsigned long irq_table_flags;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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DRM_DEBUG_KMS("DM_IRQ: early resume\n");
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/* re-enable short pulse interrupts HW interrupt */
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for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
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hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
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hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
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if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
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dc_interrupt_set(adev->dm.dc, src, true);
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}
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
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return 0;
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}
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int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
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{
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int src;
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struct list_head *hnd_list_h, *hnd_list_l;
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unsigned long irq_table_flags;
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DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
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DRM_DEBUG_KMS("DM_IRQ: resume\n");
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/**
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* Renable HW interrupt for HPD and only since FLIP and VBLANK
|
* will be enabled from manage_dm_interrupts on enable CRTC.
|
*/
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for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {
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hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
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hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
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if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
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dc_interrupt_set(adev->dm.dc, src, true);
|
}
|
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DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
|
return 0;
|
}
|
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/*
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* amdgpu_dm_irq_schedule_work - schedule all work items registered for the
|
* "irq_source".
|
*/
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static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
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enum dc_irq_source irq_source)
|
{
|
struct list_head *handler_list = &adev->dm.irq_handler_list_low_tab[irq_source];
|
struct amdgpu_dm_irq_handler_data *handler_data;
|
bool work_queued = false;
|
|
if (list_empty(handler_list))
|
return;
|
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list_for_each_entry (handler_data, handler_list, list) {
|
if (!queue_work(system_highpri_wq, &handler_data->work)) {
|
continue;
|
} else {
|
work_queued = true;
|
break;
|
}
|
}
|
|
if (!work_queued) {
|
struct amdgpu_dm_irq_handler_data *handler_data_add;
|
/*get the amdgpu_dm_irq_handler_data of first item pointed by handler_list*/
|
handler_data = container_of(handler_list->next, struct amdgpu_dm_irq_handler_data, list);
|
|
/*allocate a new amdgpu_dm_irq_handler_data*/
|
handler_data_add = kzalloc(sizeof(*handler_data), GFP_ATOMIC);
|
if (!handler_data_add) {
|
DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
|
return;
|
}
|
|
/*copy new amdgpu_dm_irq_handler_data members from handler_data*/
|
handler_data_add->handler = handler_data->handler;
|
handler_data_add->handler_arg = handler_data->handler_arg;
|
handler_data_add->dm = handler_data->dm;
|
handler_data_add->irq_source = irq_source;
|
|
list_add_tail(&handler_data_add->list, handler_list);
|
|
INIT_WORK(&handler_data_add->work, dm_irq_work_func);
|
|
if (queue_work(system_highpri_wq, &handler_data_add->work))
|
DRM_DEBUG("Queued work for handling interrupt from "
|
"display for IRQ source %d\n",
|
irq_source);
|
else
|
DRM_ERROR("Failed to queue work for handling interrupt "
|
"from display for IRQ source %d\n",
|
irq_source);
|
}
|
}
|
|
/*
|
* amdgpu_dm_irq_immediate_work
|
* Callback high irq work immediately, don't send to work queue
|
*/
|
static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
|
enum dc_irq_source irq_source)
|
{
|
struct amdgpu_dm_irq_handler_data *handler_data;
|
unsigned long irq_table_flags;
|
|
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
|
|
list_for_each_entry(handler_data,
|
&adev->dm.irq_handler_list_high_tab[irq_source],
|
list) {
|
/* Call a subcomponent which registered for immediate
|
* interrupt notification */
|
handler_data->handler(handler_data->handler_arg);
|
}
|
|
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
|
}
|
|
/**
|
* amdgpu_dm_irq_handler - Generic DM IRQ handler
|
* @adev: amdgpu base driver device containing the DM device
|
* @source: Unused
|
* @entry: Data about the triggered interrupt
|
*
|
* Calls all registered high irq work immediately, and schedules work for low
|
* irq. The DM IRQ table is used to find the corresponding handlers.
|
*/
|
static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
struct amdgpu_iv_entry *entry)
|
{
|
|
enum dc_irq_source src =
|
dc_interrupt_to_irq_source(
|
adev->dm.dc,
|
entry->src_id,
|
entry->src_data[0]);
|
|
dc_interrupt_ack(adev->dm.dc, src);
|
|
/* Call high irq work immediately */
|
amdgpu_dm_irq_immediate_work(adev, src);
|
/*Schedule low_irq work */
|
amdgpu_dm_irq_schedule_work(adev, src);
|
|
return 0;
|
}
|
|
static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
|
{
|
switch (type) {
|
case AMDGPU_HPD_1:
|
return DC_IRQ_SOURCE_HPD1;
|
case AMDGPU_HPD_2:
|
return DC_IRQ_SOURCE_HPD2;
|
case AMDGPU_HPD_3:
|
return DC_IRQ_SOURCE_HPD3;
|
case AMDGPU_HPD_4:
|
return DC_IRQ_SOURCE_HPD4;
|
case AMDGPU_HPD_5:
|
return DC_IRQ_SOURCE_HPD5;
|
case AMDGPU_HPD_6:
|
return DC_IRQ_SOURCE_HPD6;
|
default:
|
return DC_IRQ_SOURCE_INVALID;
|
}
|
}
|
|
static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
unsigned type,
|
enum amdgpu_interrupt_state state)
|
{
|
enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
|
bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
|
|
dc_interrupt_set(adev->dm.dc, src, st);
|
return 0;
|
}
|
|
static inline int dm_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
unsigned crtc_id,
|
enum amdgpu_interrupt_state state,
|
const enum irq_type dal_irq_type,
|
const char *func)
|
{
|
bool st;
|
enum dc_irq_source irq_source;
|
|
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
|
|
if (!acrtc) {
|
DRM_ERROR(
|
"%s: crtc is NULL at id :%d\n",
|
func,
|
crtc_id);
|
return 0;
|
}
|
|
if (acrtc->otg_inst == -1)
|
return 0;
|
|
irq_source = dal_irq_type + acrtc->otg_inst;
|
|
st = (state == AMDGPU_IRQ_STATE_ENABLE);
|
|
dc_interrupt_set(adev->dm.dc, irq_source, st);
|
return 0;
|
}
|
|
static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
unsigned crtc_id,
|
enum amdgpu_interrupt_state state)
|
{
|
return dm_irq_state(
|
adev,
|
source,
|
crtc_id,
|
state,
|
IRQ_TYPE_PFLIP,
|
__func__);
|
}
|
|
static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
unsigned crtc_id,
|
enum amdgpu_interrupt_state state)
|
{
|
return dm_irq_state(
|
adev,
|
source,
|
crtc_id,
|
state,
|
IRQ_TYPE_VBLANK,
|
__func__);
|
}
|
|
static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev,
|
struct amdgpu_irq_src *source,
|
unsigned int crtc_id,
|
enum amdgpu_interrupt_state state)
|
{
|
return dm_irq_state(
|
adev,
|
source,
|
crtc_id,
|
state,
|
IRQ_TYPE_VUPDATE,
|
__func__);
|
}
|
|
static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
|
.set = amdgpu_dm_set_crtc_irq_state,
|
.process = amdgpu_dm_irq_handler,
|
};
|
|
static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = {
|
.set = amdgpu_dm_set_vupdate_irq_state,
|
.process = amdgpu_dm_irq_handler,
|
};
|
|
static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
|
.set = amdgpu_dm_set_pflip_irq_state,
|
.process = amdgpu_dm_irq_handler,
|
};
|
|
static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
|
.set = amdgpu_dm_set_hpd_irq_state,
|
.process = amdgpu_dm_irq_handler,
|
};
|
|
void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
|
{
|
|
adev->crtc_irq.num_types = adev->mode_info.num_crtc;
|
adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
|
|
adev->vupdate_irq.num_types = adev->mode_info.num_crtc;
|
adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs;
|
|
adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
|
adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
|
|
adev->hpd_irq.num_types = adev->mode_info.num_hpd;
|
adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
|
}
|
|
/**
|
* amdgpu_dm_hpd_init - hpd setup callback.
|
*
|
* @adev: amdgpu_device pointer
|
*
|
* Setup the hpd pins used by the card (evergreen+).
|
* Enable the pin, set the polarity, and enable the hpd interrupts.
|
*/
|
void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
|
{
|
struct drm_device *dev = adev_to_drm(adev);
|
struct drm_connector *connector;
|
struct drm_connector_list_iter iter;
|
|
drm_connector_list_iter_begin(dev, &iter);
|
drm_for_each_connector_iter(connector, &iter) {
|
struct amdgpu_dm_connector *amdgpu_dm_connector =
|
to_amdgpu_dm_connector(connector);
|
|
const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
|
|
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
|
dc_interrupt_set(adev->dm.dc,
|
dc_link->irq_source_hpd,
|
true);
|
}
|
|
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
|
dc_interrupt_set(adev->dm.dc,
|
dc_link->irq_source_hpd_rx,
|
true);
|
}
|
}
|
drm_connector_list_iter_end(&iter);
|
}
|
|
/**
|
* amdgpu_dm_hpd_fini - hpd tear down callback.
|
*
|
* @adev: amdgpu_device pointer
|
*
|
* Tear down the hpd pins used by the card (evergreen+).
|
* Disable the hpd interrupts.
|
*/
|
void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
|
{
|
struct drm_device *dev = adev_to_drm(adev);
|
struct drm_connector *connector;
|
struct drm_connector_list_iter iter;
|
|
drm_connector_list_iter_begin(dev, &iter);
|
drm_for_each_connector_iter(connector, &iter) {
|
struct amdgpu_dm_connector *amdgpu_dm_connector =
|
to_amdgpu_dm_connector(connector);
|
const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
|
|
dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
|
|
if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
|
dc_interrupt_set(adev->dm.dc,
|
dc_link->irq_source_hpd_rx,
|
false);
|
}
|
}
|
drm_connector_list_iter_end(&iter);
|
}
|
